DC to 28 GHz, GaAs, pHEMT,
MMIC, Low Noise Amplifier
HMC8401
Data Sheet
FEATURES
GENERAL DESCRIPTION
Output power for 1 dB compression (P1dB): 16.5 dBm typical
Saturated output power (PSAT): 19 dBm typical
Gain: 14.5 dB typical
Noise figure: 1.5 dB
Output third order intercept (IP3): 26 dBm typical
Supply voltage: 7.5 V at 60 mA
50 Ω matched input/output
Die size: 2.55 mm x 1.62 mm x 0.05 mm
The HMC8401 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transistor (pHEMT), monolithic microwave
integrated circuit (MMIC). The HMC8401 is a wideband low
noise amplifier which operates between dc and 28 GHz. The
amplifier provides 14.5 dB of gain, 1.5 dB noise figure, 26 dBm
output IP3 and 16.5 dBm of output power at 1 dB gain compression
while requiring 60 mA from a 7.5 V supply. The HMC8401 also
has a gain control option, VGG2. The HMC8401 amplifier input/
outputs are internally matched to 50 Ω facilitating integration
into multichip modules (MCMs). All data is taken with the chip
connected via two 0.025 mm (1 mil) wire bonds of minimal
length 0.31 mm (12 mils).
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military and space
Telecommunications infrastructure
Fiber optics
FUNCTIONAL BLOCK DIAGRAM
VDD
4
ACG
3
HMC8401
RFOUT
7
6
13850-001
8
ACG
RFIN
VGG1
1
5
VGG2
ACG
2
Figure 1.
Rev. B
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HMC8401
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................7
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................8
General Description ......................................................................... 1
Theory of Operation ...................................................................... 14
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 15
Revision History ............................................................................... 2
Biasing Procedures ..................................................................... 15
Specifications..................................................................................... 3
0.01 GHz to 3 GHz Frequency Range........................................ 3
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs ......................................................................................... 15
3 GHz to 26 GHz Frequency Range ........................................... 3
Typical Application Circuit ....................................................... 16
26 GHz to 28 GHz Frequency Range......................................... 4
Assembly Diagram ..................................................................... 16
Absolute Maximum Ratings............................................................ 5
Outline Dimensions ....................................................................... 17
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 17
Pin Configuration and Function Descriptions ............................. 6
REVISION HISTORY
4/2018—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
9/2017—Rev. 0 to Rev. A
Changes to Supply Voltage Parameter, Table 1 ............................. 3
Changes to Supply Voltage Parameter, Table 2 ............................. 3
Changes to Supply Voltage Parameter, Table 3 ............................. 4
Changes to Thermal Resistance, θJC (Channel to Die Bottom)
Parameter Heading, Table 4 ............................................................ 5
Changes to Table 5 ............................................................................ 6
Changes to Figure 7 .......................................................................... 7
Added Figure 41; Renumbered Sequentially .............................. 13
7/2016—Revision 0: Initial Version
Rev. B | Page 2 of 17
Data Sheet
HMC8401
SPECIFICATIONS
0.01 GHz TO 3 GHz FREQUENCY RANGE
TA = 25°C, VDD = 7.5 V, IDQ = 60 mA, VGG2 = open, unless otherwise stated. 1 When using VGG2, it is recommended to limit VGG2 from −2 V
to +2.6 V.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third Order Intercept
NOISE FIGURE
SUPPLY CURRENT
Total Supply Current
SUPPLY VOLTAGE
1
Symbol
P1dB
PSAT
IP3
NF
Test Conditions/Comments
Min
0.01
13
14.5
Measurement taken at POUT/tone = 10 dBm
IDQ
VDD
4.5
Typ
Max
3
15
0.005
Unit
GHz
dB
dB/°C
14
19
dB
dB
17
19
27
2.5
4.5
dBm
dBm
dBm
dB
60
7.5
8.5
mA
V
Adjust the VGG1 supply voltage between −2 V and 0 V to achieve IDQ = 60 mA typical.
3 GHz TO 26 GHz FREQUENCY RANGE
TA = 25°C, VDD = 7.5 V, IDQ = 60 mA, VGG2 = open, unless otherwise stated. 1 When using VGG2, it is recommended to limit VGG2 from −2 V
to +2.6 V.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third Order Intercept
NOISE FIGURE
SUPPLY CURRENT
Total Supply Current
SUPPLY VOLTAGE
1
Symbol
P1dB
PSAT
IP3
NF
Test Conditions/Comments
Min
3
12.5
14
Measurement taken at POUT/tone = 10 dBm
IDQ
VDD
4.5
Adjust the VGG1 supply voltage between −2 V and 0 V to achieve IDQ= 60 mA typical.
Rev. B | Page 3 of 17
Typ
14.5
0.007
Unit
GHz
dB
dB/°C
16
17
dB
dB
16.5
19
26
1.5
4.5
dBm
dBm
dBm
dB
8.5
mA
V
60
7.5
Max
26
HMC8401
Data Sheet
26 GHz TO 28 GHz FREQUENCY RANGE
TA = 25°C, VDD = 7.5 V, IDQ = 60 mA, VGG2 = open, unless otherwise stated. 1 When using VGG2, it is recommended to limit VGG2 from −2 V
to +2.6 V.
Table 3.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third Order Intercept
NOISE FIGURE
SUPPLY CURRENT
Total Supply Current
SUPPLY VOLTAGE
1
Symbol
P1dB
PSAT
IP3
NF
Test Conditions/Comments
Min
26
12.5
11.5
Measurement taken at POUT/tone = 10 dBm
IDQ
VDD
4.5
Adjust the VGG1 supply voltage between −2 V and 0 V to achieve IDQ = 60 mA typical.
Rev. B | Page 4 of 17
Typ
Max
28
14.5
0.009
Unit
GHz
dB
dB/°C
15
17
dB
dB
14
17
24
2
4
dBm
dBm
dBm
dB
60
7.5
8.5
mA
V
Data Sheet
HMC8401
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Drain Bias Voltage (VDD)
Second Gate Bias Voltage (VGG2)
RF Input Power (RFIN)
Channel Temperature
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 18.3 mW/°C Above 85°C)
Thermal Resistance, θJC (Channel to
Die Bottom)
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity, Human Body Model (HBM)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rating
+10 V
−2.6 V to +3.6V
20 dBm
175°C
1.67W
54°C/W
ESD CAUTION
−65°C to +150°C
−55°C to +85°C
Class 1A, 250 V
Rev. B | Page 5 of 17
HMC8401
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC8401
3
4
5
2
ADI2014
8
7
6
13850-002
1
Figure 2. Pad Configuration
Table 5. Pad Function Descriptions
Pad No.
1
2
Mnemonic
RFIN
VGG2
3
VDD
4, 6, 7
ACG
5
8
RFOUT
VGG1
Die Bottom
GND
Description
Radio Frequency (RF) Input. This pad is dc coupled and matched to 50 Ω. See Figure 3 for the interface schematic.
Gain Control. This pad is dc-coupled and accomplishes gain control by bringing this voltage lower and
becoming more negative. Attach bypass capacitors to this pad as shown in Figure 44. See Figure 4 for the
interface schematic.
Power Supply Voltage for the Amplifier. Connect a dc bias to provide drain current (IDD). Attach bypass
capacitors to this pad as shown in Figure 44. See Figure 5 for the interface schematic.
Low Frequency Termination. Attach bypass capacitors to this pad as shown in Figure 44. See Figure 6 for
the interface schematic.
Radio Frequency (RF) Output. This pad is dc coupled and matched to 50 Ω. See Figure 3 for the interface schematic.
Gate Control for the Amplifier. Adjust VGG1 to achieve the recommended bias current. Attach bypass
capacitors to this pad as shown in Figure 44. See Figure 8 for the interface schematic.
Die Bottom. The die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic.
Rev. B | Page 6 of 17
Data Sheet
HMC8401
INTERFACE SCHEMATICS
RFOUT
13850-007
13850-003
RFIN
Figure 7. RFOUT Interface Schematic
Figure 3. RFIN Interface Schematic
13850-004
VGG1
13850-008
VGG2
Figure 8. VGG1 Interface Schematic
Figure 4. VGG2 Interface Schematic
VDD
13850-005
13850-009
GND
Figure 9. GND Interface Schematic
ACG
13850-006
Figure 5. VDD Interface Schematic
Figure 6. ACG Interface Schematic
Rev. B | Page 7 of 17
HMC8401
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
17
20
16
15
14
GAIN (dB)
0
–10
–20
13
12
11
10
9
S11
S21
S22
–40
0
5
10
15
20
25
30
FREQUENCY (GHz)
7
0
10
15
20
25
30
Figure 13. Gain vs. Frequency at Various Temperatures
0
0
–4
–6
–6
RETURN LOSS (dB)
–4
–8
–10
–12
–14
–8
–10
–12
–14
–16
–16
–18
–18
5
10
15
20
25
30
FREQUENCY (GHz)
–20
13850-011
–20
0
+85°C
+25°C
–55°C
–2
Figure 11. Input Return Loss vs. Frequency at Various Temperatures
0
5
10
15
20
25
30
FREQUENCY (GHz)
13850-014
+85°C
+25°C
–55°C
–2
Figure 14. Output Return Loss vs. Frequency at Various Temperatures
6
6
+85°C
+25°C
–55°C
6.5V
7.5V
8.5V
5
NOISE FIGURE (dB)
5
4
3
2
1
4
3
2
0
0
5
10
15
20
25
30
FREQUENCY (GHz)
13850-012
1
Figure 12. Noise Figure vs. Frequency at Various Temperatures
0
0
5
10
15
20
25
30
FREQUENCY (GHz)
Figure 15. Noise Figure vs. Frequency at Various Supply Voltages
Rev. B | Page 8 of 17
13850-015
RETURN LOSS (dB)
5
FREQUENCY (GHz)
Figure 10. Response Gain and Return Loss vs. Frequency
NOISE FIGURE (dB)
+85°C
+25°C
–55°C
8
13850-013
–30
13850-010
GAIN AND RETURN LOSS (dB)
10
Data Sheet
HMC8401
22
22
+85°C
+25°C
–55°C
20
16
14
16
14
12
12
10
10
8
0
5
10
15
20
25
30
FREQUENCY (GHz)
8
0
5
10
15
20
25
30
FREQUENCY (GHz)
Figure 16. P1dB vs. Frequency at Various Temperatures
13850-019
PSAT (dBm)
18
13850-016
Figure 19. PSAT vs. Frequency at Various Temperatures
22
22
6.5V
7.5V
8.5V
20
20
18
PSAT (dBm)
18
16
14
16
14
12
12
10
10
0
5
10
15
20
25
30
FREQUENCY (GHz)
8
13850-017
8
6.5V
7.5V
8.5V
0
5
10
15
20
25
30
FREQUENCY (GHz)
13850-020
P1dB (dBm)
18
P1dB (dBm)
+85°C
+25°C
–55°C
20
Figure 20. PSAT vs. Frequency at Various Supply Voltages
Figure 17. P1dB vs. Frequency at Various Supply Voltages
55
30
+85°C
+25°C
–55°C
50
26
40
35
3GHz
7GHz
11GHz
17GHz
21GHz
25GHz
27GHz
18
30
14
0
5
10
15
20
25
30
FREQUENCY (GHz)
Figure 18. Output IP3 vs. Frequency for Various Temperatures at
POUT = 0 dBm/Tone
25
0
1
2
3
4
5
POUT /TONE (dBm)
6
7
8
13850-021
IM3 (dBc)
22
13850-018
IP3 (dBm)
45
Figure 21. Output Third Order Intermodulation (IM3) vs. POUT/Tone for
Various Frequencies at VDD = 6.5 V
Rev. B | Page 9 of 17
Data Sheet
55
50
50
45
45
IM3 (dBc)
55
35
3GHz
7GHz
11GHz
17GHz
21GHz
25GHz
27GHz
30
25
0
3
2
1
4
5
6
7
8
POUT /TONE (dBm)
25
Figure 22. Output IM3 vs. POUT/Tone for Various Frequencies at VDD = 7.5 V
0
–20
–30
–40
–50
–60
3
4
5
6
7
20
100
18
96
16
92
14
88
12
84
10
80
8
76
6
72
4
–70
5
10
15
20
25
30
FREQUENCY (GHz)
64
60
0
–9
13850-023
0
68
POUT
GAIN
PAE
IDD
2
–80
8
Figure 25. Output IM3 vs. POUT/Tone for Various Frequencies at VDD = 8.5 V
POUT (dBm), GAIN (dB), PAE (%)
–10
2
POUT /TONE (dBm)
0
+85°C
+25°C
–55°C
1
–7
–5
–3
–1
1
3
5
13850-026
30
3GHz
7GHz
11GHz
17GHz
21GHz
25GHz
27GHz
IDD (mA)
35
REVERSE ISOLATION (dB)
40
13850-025
40
13850-022
IM3 (dBc)
HMC8401
7
INPUT POWER (dBm)
Figure 26. Power Compression at 15 GHz
Figure 23. Reverse Isolation vs. Frequency at Various Temperatures
17
0.70
16
15
14
GAIN (dB)
0.60
0.55
0.50
12
11
–8
–6
–4
–2
0
2
INPUT POWER (dBm)
4
6
5V
6.5V
7.5V
8.5V
9
8
8
Figure 24. Power Dissipation vs. Input Power at Various Frequencies, TA = 85°C
Rev. B | Page 10 of 17
7
0
5
10
15
20
25
FREQUENCY (GHz)
Figure 27. Gain vs. Frequency at Various Supply Voltages
30
13850-027
0.45
0.40
–10
13
10
3GHz
9GHz
15GHz
23GHz
28GHz
13850-024
POWER DISSIPATION (W)
0.65
Data Sheet
HMC8401
0
5V
6.5V
7.5V
8.5V
–2
–4
RETURN LOSS (dB)
–6
–8
–10
–12
–14
–14
–18
5
10
15
20
25
30
FREQUENCY (GHz)
–20
0
5
10
15
20
25
30
FREQUENCY (GHz)
Figure 31. Input Return Loss vs. Frequency at Various VGG2 Voltages
Figure 28. Input Return Loss vs. Frequency at Various Supply Voltages
0
5V
6.5V
7.5V
8.5V
–2
–4
–4
RETURN LOSS (dB)
–6
–8
–10
–12
–14
–8
–10
–12
–14
–16
–18
–18
5
10
15
20
25
30
FREQUENCY (GHz)
–20
13850-029
–20
Figure 29. Output Return Loss vs. Frequency at Various Supply Voltages
0
10
15
20
25
30
Figure 32. Output Return Loss vs. Frequency at Various VGG2 Voltages
16
17
15
16
14
15
13
14
GAIN (dB)
18
11
5
FREQUENCY (GHz)
17
12
0V
+0.8V
+1.6V
+2.4V
–6
–16
0
–2V
–1.6V
–1.2V
–0.8V
–2
13850-032
0
13
12
11
10
–2V
–1.6V
–1.2V
–0.8V
8
10
0V
+0.8V
+1.6V
+2.4V
9
7
0
5
10
15
20
25
FREQUENCY (GHz)
30
13850-030
9
Figure 30. Gain vs. Frequency at Various VGG2 Voltages
8
2.4
2.0
1.6
1.2
0.8
0.4
0
–0.4 –0.8 –1.2 –1.6 –2.0
VGG2 (V)
Figure 33. Gain vs. VGG2 at 14 GHz
Rev. B | Page 11 of 17
13850-033
RETURN LOSS (dB)
–12
–18
0
GAIN (dB)
–8
–10
–16
–20
0V
+0.8V
+1.6V
+2.4V
–6
–16
13850-028
RETURN LOSS (dB)
–4
–2V
–1.6V
–1.2V
–0.8V
–2
13850-031
0
HMC8401
Data Sheet
17
30
16
27
15
13
24
IP3 (dBm)
GAIN (dB)
14
12
11
21
10
18
9
25mA
35mA
45mA
7
0
5
10
15
20
25
30
FREQUENCY (GHz)
15
2.4
1.6
1.2
0.8
0.4
0
–0.4 –0.8 –1.2 –1.6 –2.0
VGG2 (V)
Figure 36. Output IP3 vs. VGG2 at 16 GHz
Figure 34. Gain vs. Frequency at Various IDQ Currents
0
25mA
35mA
45mA
–2
55mA
60mA
65mA
–4
–6
–6
RETURN LOSS (dB)
–4
–8
–10
–12
–14
–10
–12
–14
–18
5
10
15
20
25
30
FREQUENCY (GHz)
13850-035
–16
–18
–20
Figure 35. Input Return Loss vs. Frequency at Various IDQ Currents
55mA
60mA
65mA
–8
–16
0
25mA
35mA
45mA
–2
–20
0
5
10
15
20
25
30
FREQUENCY (GHz)
Figure 37. Output Return Loss vs. Frequency at Various IDQ Currents
Rev. B | Page 12 of 17
13850-037
0
RETURN LOSS (dB)
2.0
13850-036
55mA
60mA
65mA
13850-034
8
HMC8401
30
24
25
20
20
16
PSAT (dBm)
15
12
8
10
–2V
–1.8V
–1.6V
–1.4V
–1.2
0
2
6
10
14
18
22
26
–2V
–1.8V
–1.6V
–1.4V
4
30
FREQUENCY (GHz)
–1.2
–1V
+2V
0
13850-038
5
–1V
0V
+1V
+2V
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
Figure 38. Output IP3 vs Frequency at Various VGG2 Voltages
13850-040
IP3 (dBm)
Data Sheet
Figure 40. PSAT vs. Frequency at Various VGG2 Voltages
24
35
–2V
–1.8V
–1.6V
–1.4V
20
–1.2
–1V
+2V
30
IP2 (dBm)
12
25
20
8
0
2
6
10
14
18
22
26
FREQUENCY (GHz)
30
10
0
3
6
9
12
15
18
21
FREQUENCY (GHz)
Figure 41. OIP2 vs. Frequency at Various RF Pout
Figure 39. P1dB vs. Frequency at Various VGG2 Voltages
Rev. B | Page 13 of 17
24
13850-045
0dBm
2dBm
4dBm
6dBm
8dBm
15
4
13850-039
P1dB (dBm)
16
HMC8401
Data Sheet
THEORY OF OPERATION
The HMC8401 is a GaAs, pHEMT, MMIC low noise amplifier.
Its basic architecture is that of a cascode distributed amplifier
with an integrated resistor for the drain. The cascode distributed
architecture uses a fundamental cell consisting of a stack of two
field effect transistors (FETs) with the source of the upper FET
connected to drain of the lower FET. The fundamental cell is then
duplicated several times with an RFIN transmission line interconnecting the gates of the lower FETs and an RFOUT transmission
line interconnecting the drains of the upper FETs.
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth and noise figure. The major
benefit of this architecture is that a low noise figure is maintained
across a bandwidth far greater than what a single instance of the
fundamental cell provides. A simplified schematic of this
architecture is shown in Figure 42.
VDD
Though the gate bias voltages of the upper FETs are set internally
by a resistive voltage divider tapped off of VDD, the VGG2 pad is
provided to allow the user an optional means of changing the
gate bias of the upper FETs. Adjustment of the VGG2 voltage
across the range from −2 V through +2.4 V changes the gate bias of
the upper FETs, thus affecting gain changes of approximately 4 dB,
depending on frequency. Increasing the voltage applied to VGG2
increases the gain, while decreasing the voltage decreases the
gain. For the nominal VDD = 7.5 V, the resulting VGG2 open
circuit voltage is approximately 2.06 V.
A voltage applied to the VGG1 pad sets the gate bias of the lower
FETs, providing control of the drain current. Unlike the upper
FETs, a gate bias voltage for the lower FETs is not generated
internally. For this reason, the application of a bias voltage to the
VGG1 pad is required and not optional.
To operate the HMC8401 at voltages lower than the nominal 7.5 V,
use a bias tee to apply 5.25 V to the drain via the RFOUT pad.
ACG
T-LINE
RFOUT
When using this alternate bias configuration, leave the VDD pad
open and adjust VGG1 to obtain a nominal quiescent IDD = 60 mA.
Though data taken using the alternate bias configuration is not
presented on this data sheet, the resulting performance differs only
slightly from that obtained using the typical bias configuration. The
small signal gain is a few tenths of dB greater, the compression
characteristics are slightly harder, and the noise figure characteristics
remain mostly unchanged.
VGG2
T-LINE
VGG1 ACG ACG
13850-041
RFIN
For additional information regarding this alternate bias
configuration, contact Analog Devices Applications.
Figure 42. Architecture and Simplified Schematic
Rev. B | Page 14 of 17
Data Sheet
HMC8401
APPLICATIONS INFORMATION
BIASING PROCEDURES
0.05mm (0.002") THICK GaAs MMIC
Capacitive bypassing is required for VDD and VGG1, as shown in
the typical application circuit in Figure 44. Gain control is
possible through the application of a dc voltage to VGG2. If gain
control is used, then VGG2 must be bypassed by 100 pF, 0.1 µF, and
4.7 µF capacitors. If gain control is not used, then VGG2 can be
either left open or capacitively bypassed as described.
WIRE BOND
0.076mm
(0.003")
1.
2.
3.
4.
5.
Set VGG1 to −2.0 V to pinch off the channels of the lower
FETs.
Set VDD to 7.5 V. Because the lower FETs are pinched off,
IDQ remains very low upon application of VDD.
Adjust VGG1 to be more positive until the desired quiescent
drain current is obtained.
Apply the RF input signal.
If the gain control function is to be used, apply to VGG2 a
voltage within the range of −2.0 V to +2.4 V until the
desired gain is achieved.
0.150mm
(0.005”) THICK
MOLY TAB
Figure 43. Routing RF Signals with Molytab
To minimize bond wire length, place microstrip substrates as
close to the die as possible. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
Handling Precautions
To avoid permanent damage, adhere to the following precautions:
•
Use of the VGG2 (the gain control function) affects the drain
current.
The recommended bias sequence during power-down is as follows:
1.
2.
3.
4.
5.
Turn off the RF input signal.
Remove the VGG2 voltage or set it to 0 V.
Set VGG1 to −2.0 V to pinch off the channels of the lower
FETs.
Set VDD to 0 V.
Set VGG1 to 0 V.
•
•
•
•
Power-up and power-down sequences may differ from the ones
described, though care must always be taken to ensure adherence
to the values shown in the Absolute Maximum Ratings.
Unless otherwise noted, all measurements and data shown
were taken using the typical application circuit (see Figure 44),
configured as shown on the assembly diagram (see Figure 45)
and biased per the conditions in this section. The bias conditions
shown in this section are the operating points recommended to
optimize the overall performance. Operation using other bias
conditions may provide performance that differs from what is
shown in this data sheet. To obtain the best performance while
not damaging the device, follow the recommended biasing
sequence outlined in this section.
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICs
Attach the die directly to the ground plane eutectically or with
conductive epoxy. To bring RF to and from the chip, use 50 Ω
microstrip transmission lines on 0.127 mm (5 mil) thick alumina
thin film substrates (see Figure 43).
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
13850-042
RF GROUND PLANE
The recommended bias sequence during power-up is as follows:
All bare die ship in either waffle or gel-based ESD protective
containers, sealed in an ESD protective bag. After the sealed
ESD protective bag is opened, store all die in a dry nitrogen
environment.
Handle the chips in a clean environment. Never use liquid
cleaning systems to clean the chip.
Follow ESD precautions to protect against ESD strikes.
While bias is applied, suppress instrument and bias supply
transients. To minimize inductive pickup, use shielded
signal and bias cables.
Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
may have fragile air bridges and must not be touched with
vacuum collet, tweezers, or fingers.
Mounting
The chip is back metallized and can be die mounted with gold/tin
(AuSn) eutectic preforms or with electrically conductive epoxy.
The mounting surface must be clean and flat.
Eutectic Die Attach
It is best to use an 80% gold/20% tin preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When
hot 90% nitrogen/10% hydrogen gas is applied, maintain tool tip
temperature at 290°C. Do not expose the chip to a temperature
greater than 320°C for more than 20 sec. No more than 3 sec of
scrubbing is required for attachment.
Epoxy Die Attach
ABLETHERM 2600BT is recommended for die attachment.
Apply a minimum amount of epoxy to the mounting surface so
that a thin epoxy fillet is observed around the perimeter of the
chip after placing it into position. Cure the epoxy per the schedule
provided by the manufacturer.
Rev. B | Page 15 of 17
HMC8401
Data Sheet
Wire Bonding
Create ball bonds with a force of 40 g to 50 g and wedge bonds
with a force of 18 g to 22 g. Create all bonds with a nominal stage
temperature of 150°C. Apply a minimum amount of ultrasonic
energy to achieve reliable bonds. Keep all bonds as short as
possible, less than 12 mil (0.31 mm).
RF bonds made with 0.003 in. × 0.0005 in. gold ribbon are recommended for the RF ports. These bonds must be thermosonically
bonded with a force of 40 g to 60 g. DC bonds of 1 mil (0.025 mm)
diameter, thermosonically bonded, are recommended.
TYPICAL APPLICATION CIRCUIT
VDD
4.7µF
0.1µF
100pF
VGG2
3
2
0.1µF
4
100pF
RFOUT
5
6
7
RFIN
1
8
100pF
0.1µF
VGG1
4.7µF
0.1µF
4.7µF
100pF
13850-043
4.7µF
Figure 44. Typical Application Circuit
ASSEMBLY DIAGRAM
+
–
–
ALL BOND WIRES ARE
1mil DIAMETER
+
4.7µF
4.7µF
TO VDD SUPPLY
0.1µF
TO VGG2 SUPPLY
3mil NOMINAL GAP
100pF
0.1µF
100pF
100pF
50Ω
TRANSMISSION
LINE
TO VGG1 SUPPLY
100pF
0.1µF
0.1µF
4.7µF
+
–
–
Figure 45. Assembly Diagram
Rev. B | Page 16 of 17
+
13850-044
4.7µF
Data Sheet
HMC8401
OUTLINE DIMENSIONS
2.549
0.050
0.013
0.127
3
4
0.536
0.187
5
0.187
2
0.158
1.615
0.187
1
0.799
0.187
0.449
8
K8801
7
6
0.146
TOP VIEW
1.891
0.009
0.152
0.118
0.131
SIDE VIEW
03-20-2018-B
0.136
0.010
Figure 46. 8-Pad Bare Die [CHIP]
(C-8-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
HMC8401
HMC8401-SX
1
2
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
8-Pad Bare Die [CHIP]
8-Pad Bare Die [CHIP]
The HMC8401-SX is a sample order of two devices.
All models are RoHS compliant parts.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13850-0-4/18(B)
Rev. B | Page 17 of 17
Package Option
C-8-8
C-8-8
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