LT1970
500mA Power Op Amp with
Adjustable Precision Current Limit
Features
Description
± 500mA Minimum Output Current
n Independent Adjustment of Source and
Sink Current Limits
n 2% Current Limit Accuracy
n Operates with Single or Split Supplies
n Shutdown/Enable Control Input
n Open Collector Status Flags:
Sink Current Limit
Source Current Limit
Thermal Shutdown
n Fail Safe Current Limit and Thermal Shutdown
n 1.6V/µs Slew Rate
n 3.6MHz Gain Bandwidth Product
n Fast Current Limit Response: 2MHz Bandwidth
n Specified Temperature Range: –40°C to 85°C
n Available in a 20-Lead TSSOP Package
The LT®1970 is a ± 500mA power op amp with precise
externally controlled current limiting. Separate control
voltages program the sourcing and sinking current limit
sense thresholds with 2% accuracy. Output current may
be boosted by adding external power transistors.
n
The circuit operates with single or split power supplies
from 5V to 36V total supply voltage. In normal operation,
the input stage supplies and the output stage supplies are
connected (VCC to V+ and VEE to V–). To reduce power
dissipation it is possible to power the output stage (V+,
V–) from independent, lower voltage rails. The amplifier is
unity-gain stable with a 3.6MHz gain bandwidth product
and slews at 1.6V/µs. The current limit circuits operate
with a 2MHz response between the VCSRC or VCSNK control
inputs and the amplifier output.
Open collector status flags signal current limit circuit
activation, as well as thermal shutdown of the amplifier.
An enable logic input puts the amplifier into a low power,
high impedance output state when pulled low. Thermal
shutdown and a ±800mA fixed current limit protect the
chip under fault conditions.
Applications
n
n
n
n
Automatic Test Equipment
Laboratory Power Supplies
Motor Drivers
Thermoelectric Cooler Driver
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LT1970 is packaged in a 20-lead TSSOP package with
a thermally conductive copper bottom plate to facilitate
heat sinking.
Typical Application
AV = 2 Amplifier with Adjustable ± 500mA Full-Scale
Current Limit and Fault Indication
VLIMIT
0V TO 5V
V
IOUT(LIMIT) = ± LIMIT
10 • RCS
VIN
15V
VCC
+IN
Current Limited Sinewave Into 10Ω Load
15V
4V
3k
2V
V+
EN
VCSRC
VCSNK
ISNK
ISRC
TSD
LT1970
OUT
SENSE+
–
SENSE
V–
–IN
VEE
COMMON
–15V
VLOAD 0V
IOUT
–2V
RCS
1Ω
1/4W
R1
10k
LOAD
VCSRC = 4V
VCSNK = 2V
RCS = 1Ω
20µs/DIV
1970 TA02
R2
10k
1970 TA01
1970fe
For more information www.linear.com/LT1970
1
LT1970
Absolute Maximum Ratings
Pin Configuration
(Note 1)
TOP VIEW
Supply Voltage (VCC to VEE)...................................... 36V
Positive High Current Supply (V+).................... V – to VCC
Negative High Current Supply(V –).....................VEE to V+
Amplifier Output (OUT)...................................... V – to V+
Current Sense Pins
(SENSE+, SENSE–, FILTER)............................ V – to V+
Logic Outputs (ISRC, ISNK, TSD)........ COMMON to VCC
Input Voltage (–IN, +IN)............. VEE – 0.3V to VEE + 36V
Input Current.......................................................... 10mA
Current Control Inputs
(VCSRC, VCSNK)............... COMMON to COMMON + 7V
Enable Logic Input............................... COMMON to VCC
COMMON........................................................ VEE to VCC
Output Short-Circuit Duration.......................... Indefinite
Operating Temperature Range (Note 2)....–40°C to 85°C
Specified Temperature Range (Note 3)..... –40°C to 85°C
Maximum Junction Temperature.......................... 150°C
Storage Temperature Range.................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
VEE
1
V–
2
20 VEE
21
19 V+
OUT
3
18 TSD
SENSE+
4
17 ISNK
FILTER
5
SENSE–
6
VCC
7
14 COMMON
–IN
8
13 VCSRC
+IN
9
12 VCSNK
– +
VEE 10
16 ISRC
15 ENABLE
11 VEE
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 40°C/W (NOTE 8)
EXPOSED PAD (PIN 21) IS CONNECTED TO VEE
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LT1970CFE#PBF
LT1970CFE#TRPBF
LT1970CFE
20-Lead Plastic TSSOP
0°C to 70°C
LT1970IFE#PBF
LT1970IFE#TRPBF
LT1970IFE
20-Lead Plastic TSSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. See Test Circuit for standard test conditions.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
200
600
1000
1300
µV
µV
µV
Power Op Amp Characteristics
VOS
Input Offset Voltage
0°C < TA < 70°C
–40°C < TA < 85°C
Input Offset Voltage Drift (Note 4)
l
l
l
–10
–4
10
µV/°C
100
nA
IOS
Input Offset Current
VCM = 0V
l
–100
IB
Input Bias Current
VCM = 0V
l
–600
Input Noise Voltage
0.1Hz to 10Hz
3
µVP-P
en
Input Noise Voltage Density
1kHz
15
nV/√Hz
in
Input Noise Current Density
1kHz
3
pA/√Hz
2
–160
nA
1970fe
For more information www.linear.com/LT1970
LT1970
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. See Test Circuit for standard test conditions.
SYMBOL
PARAMETER
CONDITIONS
MIN
RIN
Input Resistance
Common Mode
Differential Mode
CIN
Input Capacitance
Pin 8 and Pin 9 to Ground
VCM
Input Voltage Range
Typical
Guaranteed by CMRR Test
l
–14.5
–12.0
TYP
MAX
UNITS
500
100
kΩ
kΩ
6
pF
13.6
12.0
V
V
CMRR
Common Mode Rejection Ratio
–12V < VCM < 12V
l
92
105
dB
PSRR
Power Supply Rejection Ratio
VEE = V – = –5V, VCC = V+ = 3V to 30V
VEE = V – = –5V, VCC = 30V, V+ = 2.5V to 30V
VEE = V – = –3V to – 30V, VCC = V+ = 5V
VEE = –30V, V – = –2.5V to –30V, VCC = V+ = 5V
l
l
l
l
90
110
90
110
100
130
100
130
dB
dB
dB
dB
AVOL
Large-Signal Voltage Gain
RL = 1k, –12.5V < VOUT < 12.5V
100
75
150
l
V/mV
V/mV
80
40
120
l
V/mV
V/mV
20
5
45
l
V/mV
V/mV
RL = 100Ω, –12.5V < VOUT < 12.5V
RL = 10Ω, –5V < VOUT < 5V, V+ = – V – = 8V
VOL
VOH
Output Sat Voltage Low
Output Sat Voltage High
VOL = VOUT – V –
RL = 100, VCC = V+ = 15V, VEE = V – = –15V
RL = 10, VCC = – VEE = 15V, V+ = –V – = 5V
l
1.9
0.8
2.5
V
V
VOH = V+ – VOUT
RL = 100, VCC = V+ = 15V, VEE = V – = –15V
RL = 10, VCC = – VEE = 15V, V+ = –V – = 5V
l
1.7
1.0
2.3
V
V
1200
–500
ISC
Output Short-Circuit Current
Output Low, RSENSE = 0Ω
Output High, RSENSE = 0Ω
500
–1000
800
–800
SR
Slew Rate
–10V < VOUT < 10V, RL = 1k
0.7
1.6
V/µs
FPBW
Full Power Bandwidth
VOUT = 10VPEAK (Note 5)
11
GBW
Gain Bandwidth Product
f = 10kHz
3.6
MHz
tS
Settling Time
0.01%, VOUT = 0V to 10V, AV = –1, RL = 1k
mA
mA
kHz
8
µs
Current Sense Characteristics
VSENSE(MIN) Minimum Current Sense Voltage
VCSRC = VCSNK = 0V
0.1
0.1
4
l
7
10
mV
mV
VSENSE(4%) Current Sense Voltage 4% of Full Scale
VCSRC = VCSNK = 0.2V
l
15
20
25
mV
VSENSE(10%) Current Sense Voltage 10% of Full Scale
VCSRC = VCSNK = 0.5V
l
45
50
55
mV
l
490
480
500
500
510
520
mV
mV
–0.2
VSENSE(FS)
Current Sense Voltage 100% of Full Scale
VCSRC = VCSNK = 5V
IBI
Current Limit Control Input Bias Current
VCSRC, VCSNK Pins
l
–1
0.1
µA
ISENSE–
SENSE– Input Current
0V < (VCSRC, VCSNK) < 5V
l
–500
500
nA
IFILTER
FILTER Input Current
0V < (VCSRC, VCSNK) < 5V
l
–500
500
nA
ISENSE+
SENSE+ Input Current
VCSRC= VCSNK = 0V
VCSRC = 5V, VCSNK = 0V
VCSRC= 0V, VCSNK = 5V
VCSRC = VCSNK = 5V
l
l
l
l
–500
200
–300
–25
500
300
–200
25
nA
nA
nA
nA
Current Sense Change with Output Voltage VCSRC = VCSNK = 5V, –12.5V < VOUT < 12.5V
Current Sense Change with Supply Voltage
VCSRC = VCSNK = 5V, 6V < (VCC, V+) < 18V
2.5V < V+ < 18V, VCC = 18V
–18V < (VEE, V –) < –2.5V
–18V < V – < –2.5V, VEE = –18V
250
–250
±0.1
%
±0.05
±0.01
±0.05
±0.01
%
%
%
%
1970fe
For more information www.linear.com/LT1970
3
LT1970
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. See Test Circuit for standard test conditions.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
750
1000
Current Sense Bandwidth
RCSF
MAX
UNITS
2
Resistance FILTER to SENSE–
l
MHz
1250
Ω
1
µA
0.4
V
Logic I/O Characteristics
Logic Output Leakage ISRC, ISNK, TSD
V = 15V
l
Logic Low Output Level
I = 5mA (Note 6)
l
0.2
Logic Output Current Limit
VENABLE
Enable Logic Threshold
IENABLE
Enable Pin Bias Current
25
l
0.8
l
–1
mA
1.9
2.5
V
1
µA
ISUPPLY
Total Supply Current
ICC
VCC Supply Current
ICC(STBY)
Supply Current Disabled
VCC, V+ and V –, VEE Connected
VCC, V+ and V –, VEE Separate
VCC, V+ and V –, VEE Connected, VENABLE ≤ 0.8V
tON
Turn-On Delay
(Note 7)
10
µs
tOFF
Turn-Off Delay
(Note 7)
10
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The LT1970C is guaranteed functional over the operating temperature range of – 40°C and 85°C.
Note 3: The LT1970C is guaranteed to meet specified performance from
0°C to 70°C. The LT1970C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LT1970I is guaranteed to meet specified performance from –40°C to 85°C.
l
7
13
mA
l
3
7
mA
l
0.6
1.5
mA
Note 4: This parameter is not 100% tested.
Note 5: Full power bandwidth is calculated from slew rate measurements:
FPBW = SR/(2 • π • VP)
Note 6: The logic low output level of pin TSD is guaranteed by correlating
the output level of pin ISRC and pin ISNK over temperature.
Note 7: Turn-on and turn-off delay are measured from VENABLE crossing
1.6V to the OUT pin at 90% of normal output voltage.
Note 8: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
typical performance characteristics
Warm-Up Drift VIO vs Time
Total Supply Current
vs Supply Voltage
Input Bias Current vs VCM
–100
VS = ±15V
TIME (100ms/DIV)
1970 G01
–140
–160
–180
TOTAL SUPPLY CURRENT (mA)
0V
INPUT BIAS CURRENT (nA)
VOS • 1000 (50mV/DIV)
–120
–IBIAS
+IBIAS
–200
–220
–240
–260
–15 –12 –9 –6 –3 0 3 6 9 12 15
COMMON MODE INPUT VOLTAGE (V)
1970 G02
4
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
ICC + IV+
125°C
25°C
–55°C
IEE + IV–
–55°C
25°C
125°C
0
2
4
6
8 10 12 14
SUPPLY VOLTAGE (±V)
16
18
1970 G03
1970fe
For more information www.linear.com/LT1970
LT1970
Typical Performance Characteristics
Open-Loop Gain and Phase
vs Frequency
Supply Current vs Supply Voltage
IV+
IV–
IVCC
3.0
2.5
IVEE
2.0
1.5
1.0
TA = 25°C
VCC = V+ = –VEE = –V–
0.5
2
4
6
8 10 12 14 16
SUPPLY VOLTAGE (±V)
60
90
58
80
56
18
20
GAIN
40
PHASE
30
60
20
50
10
40
0
30
–10
20
–20
10
–30
100
1k
10k 100k
1M
FREQUENCY (Hz)
4
8 12 16 20 24 28 32
TOTAL SUPPLY VOLTAGE (V)
VS = ±15V
VS = ±5V
–20
100k
1M
FREQUENCY (Hz)
AV = 1
0.01
0.001
1k
100k
1M
FREQUENCY (Hz)
10M
100M
1970 G10
10nF
0nF
–20
100k
1M
FREQUENCY (Hz)
10M
1970 G09
Slew Rate vs Supply Voltage
1.8
VS = ±15V
VENABLE = 0.8V
1.7
FALLING
1.6
10k
1k
100
RISING
1.5
1.4
1.3
1.2
10
10k
30nF
1nF
–40
10k
10M
SLEW RATE (V/µs)
OUTPUT IMPEDANCE (Ω)
OUTPUT IMPEDANCE (Ω)
AV = 10
VS = ±15V
AV = 1
1970 G08
100k
1
Gain vs Frequency with CLOAD
–10
Disabled Output Impedance
AV = 100
36
–30
600k
10
8 12 16 20 24 28 32
TOTAL SUPPLY VOLTAGE (V)
0
–40
10k
36
VS = ±15V
4
0
1970 G06
AV = 1
–10
Output Impedance
0.1
46
10
1970 G07
100
48
42
–30
1
0
50
40
0
VOLTAGE GAIN (dB)
GAIN BANDWIDTH (MHz)
AV = 100
4
0
52
Gain vs Frequency
10
2
54
1970 G05
Gain Bandwidth vs Supply Voltage
3
AV = –1
RF = RG = 1k
TA = 25°C
VOUT = VS/2
44
0
100M
10M
1870 G04
5
70
VOLTAGE GAIN (dB)
0
60
50
OPEN-LOOP GAIN (dB)
3.5
100
PHASE MARGIN (DEG)
SUPPLY CURRENT (mA)
4.0
Phase Margin vs Supply Voltage
70
PHASE MARGIN (DEG)
4.5
1
1k
AV = –1
RF = RG = 1k
TA = 25°C
1.1
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1970 G11
1.0
4
6
14
8
12
10
SUPPLY VOLTAGE (±V)
16
18
1970 G12
1970fe
For more information www.linear.com/LT1970
5
LT1970
Typical Performance Characteristics
Large-Signal Response, AV = 1
Slew Rate vs Temperature
2.5
VS = ±15V
FALLING
2.0
10V
10V
1.5
5V/DIV
RISING
5V/DIV
SLEW RATE (V/µs)
Large-Signal Response, AV = – 1
0V
–10V
1.0
0V
–10V
0.5
RL = 1k
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
20µs/DIV
RL = 1k
CL = 1000pF
1970 G14
20µs/DIV
1970 G15
125
1970 G13
Small-Signal Response, AV = – 1
Output Overdriven
VOUT
0V
5V/DIV
20mV/DIV
20mV/DIV
Small-Signal Response, AV = 1
VIN
5V/DIV 0V
RL = 1k
500ns/DIV
RL = 1k
CL = 1000pF
1970 G16
AV = –1
20
10
100
1k
10k
CLOAD (pF)
1970 G19
300
SOURCING
CURRENT
200
20
15
100
0
–100
10
5
10
6
400
VSENSE (mV)
30
OUTPUT SWING (VP-P)
OVERSHOOT (%)
40
1970 G18
500
25
AV = 1
200µs/DIV
Full Range Current Sense
Transfer Curve
30
VS = ±15V
50
0
VS = ±5V
AV = 1
1970 G17
Undistorted Output Swing
vs Frequency
% Overshoot vs CLOAD
60
2µs/DIV
SINKING
CURRENT
–200
–300
VS = ±15V
AV = –5
1% THD
0
100
–400
1k
10k
FREQUENCY (Hz)
100k
1970 G20
–500
0
1
3
2
VCSNK = VCSRC (V)
4
5
1970 G21
1970fe
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LT1970
Typical Performance Characteristics
Low Level Current Sense
Transfer Curve
Logic Output Level
vs Sink Current (Output Low)
1.0 +
V = 15V
0.9 V– = –15V
25
20
0
–5
SINKING
CURRENT
–10
–15
0.7
0.6
25°C
0.5
125°C
0.4
0.3
–55°C
0.2
0
0.001
25 50 75 100 125 150 175 200 225 250
VCSNK = VCSRC (mV)
0.01
0.1
1
10
SINK CURRENT (mA)
100
8
OUTPUT STAGE CURRENT (mA)
800
600
400
200
5
400
0
25 50 75
–75 –50 –25 0
TEMPERATURE (°C)
IV+
6
25°C
4
–55°C
2
0
IV–
–2
–55°C
–4
25°C
–6
10 15 20 25 30
SUPPLY VOLTAGE (V)
35
–10
40
125°C
0
2
4
6
8 10 12 14
SUPPLY VOLTAGE (±V)
TOTAL SUPPLY CURRENT, ICC + IV+ (µA)
125°C
25°C
–55°C
3
2
1
0
IEE
–1
–55°C
–2
25°C
–3
125°C
–4
–5
0
2
4
6
8 10 12 14
SUPPLY VOLTAGE (±V)
16
18
Supply Current vs Supply Voltage
in Shutdown
800
ICC
16
1970 G26
Control Stage Quiescent Current
vs Supply Voltage
4
100 125
125°C
1970 G25
5
SINK
600
1970 G24
–8
0
800
10
IOUT AT 10% DUTY CYCLE
1000
0
SOURCE
1000
Output Stage Quiescent Current
vs Supply Voltage
Safe Operating Area
1200
1200
1970 G23
1970 G22
IOUT PEAK (mA)
0
V+ = 15V
V– = –15V
200
0.1
–20
SUPPLY CURRENT (mA)
VSENSE (mV)
5
1400
OUTPUT CURRENT (mA)
SOURCING
CURRENT
1600
0.8
LOGIC OUTPUT VOLTAGE (V)
15
10
–25
Maximum Output Current
vs Temperature
18
VENABLE = 0V
700
85°C
25°C
600
–55°C
500
400
300
200
100
0
0
2
1970 G27
4
8 10 12 14
6
SUPPLY VOLTAGE (V)
16
18
1970 G28
1970fe
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7
LT1970
Pin Functions
VEE (Pins 1, 10, 11, 20, Package Base): Minus Supply
Voltage. VEE connects to the substrate of the integrated
circuit die, and therefore must always be the most negative
voltage applied to the part. Decouple VEE to ground with
a low ESR capacitor. VEE may be a negative voltage or it
may equal ground potential. Any or all of the VEE pins may
be used. Unused VEE pins must remain open.
V– (Pin 2): Output Stage Negative Supply. V – may equal
VEE or may be smaller in magnitude. Only output stage
current flows out of V –, all other current flows out of VEE.
V – may be used to drive the base/gate of an external power
device to boost the amplifier’s output current to levels above
the rated 500mA of the on-chip output devices. Unless
used to drive boost transistors, V– should be decoupled
to ground with a low ESR capacitor.
OUT (Pin 3): Amplifier Output. The OUT pin provides the
force function as part of a Kelvin sensed load connection.
OUT is normally connected directly to an external load current sense resistor and the SENSE+ pin. Amplifier feedback
is directly connected to the load and the other end of the
current sense resistor. The load connection is also wired
directly to the SENSE– pin to monitor the load current.
The OUT pin is current limited to ±800mA typical. This
current limit protects the output transistor in the event
that connections to the external sense resistor are
opened or shorted which disables the precision current
limit function.
SENSE + (Pin 4): Positive Current Sense Pin. This lead is
normally connected to the driven end of the external sense
resistor. Sourcing current limit operation is activated when
the voltage VSENSE (VSENSE+ – VSENSE –) equals 1/10 of
the programming control voltage at VCSRC (Pin 13). Sinking current limit operation is activated when the voltage
VSENSE equals –1/10 of the programming control voltage
at VCSNK (Pin 12).
8
FILTER (Pin 5): Current Sense Filter Pin. This pin is
normally not used and should be left open or shorted to
the SENSE– pin. The FILTER pin can be used to adapt the
response time of the current sense amplifiers with a 1nF
to 100nF capacitor connected to the SENSE – input. An
internal 1k resistor sets the filter time constant.
SENSE– (Pin 6): Negative Current Sense Pin. This pin is
normally connected to the load end of the external sense
resistor. Sourcing current limit operation is activated when
the voltage VSENSE (VSENSE+ – VSENSE –) equals 1/10 of
the programming control voltage at VCSRC (Pin 13). Sinking current limit operation is activated when the voltage
VSENSE equals –1/10 of the programming control voltage
at VCSNK (Pin 12).
VCC (Pin 7): Positive Supply Voltage. All circuitry except
the output transistors draw power from VCC. Total supply voltage from VCC to VEE must be between 3.5V and
36V. VCC must always be greater than or equal to V+. VCC
should always be decoupled to ground with a low ESR
capacitor.
–IN (Pin 8): Inverting Input of Amplifier. –IN may be any
voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain
high impedance at all times to prevent current flow into
the inputs when current limit mode is active. Care must
be taken to insure that –IN or +IN can never go to a voltage below VEE – 0.3V even during transient conditions or
damage to the circuit may result. A Schottky diode from
VEE to –IN can provide clamping if other elements in the
circuit can allow –IN to go below VEE.
+IN (Pin 9): Noninverting Input of Amplifier. +IN may be any
voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain
high impedance at all times to prevent current flow into
the inputs when current limit mode is active. Care must
be taken to insure that –IN or +IN can never go to a voltage below VEE – 0.3V even during transient conditions or
damage to the circuit may result. A Schottky diode from
VEE to +IN can provide clamping if other elements in the
circuit can allow + IN to go below VEE.
1970fe
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LT1970
pin functions
VCSNK (Pin 12): Sink Current Limit Control Voltage Input. The current sink limit amplifier will activate when
the sense voltage between SENSE+ and SENSE– equals
–1.0 • VVCSNK/10. VCSNK may be set between VCOMMON
and VCOMMON + 6V. The transfer function between VCSNK
and VSENSE is linear except for very small input voltages
at VCSNK < 60mV. VSENSE limits at a minimum set point of
4mV typical to insure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero
output current, the ENABLE pin can be taken low.
VCSRC (Pin 13): Source Current Limit Control Voltage
Input. The current source limit amplifier will activate when
the sense voltage between SENSE+ and SENSE– equals
VVCSRC/10. VCSRC may be set between VCOMMON and
VCOMMON + 6V. The transfer function between VCSRC
and VSENSE is linear except for very small input voltages
at VCSRC < 60mV. VSENSE limits at a minimum set point
of 4mV typical to insure that the sink and source limit
amplifiers do not try to operate simultaneously. To force
zero output current, the ENABLE pin can be taken low.
COMMON (Pin 14): Control and ENABLE inputs and flag
outputs are referenced to the COMMON pin. COMMON may
be at any potential between VEE and VCC – 3V. In typical
applications, COMMON is connected to ground.
ENABLE (Pin 15): ENABLE Digital Input Control. When
taken low this TTL‑level digital input turns off the amplifier output and drops supply current to less than 1mA.
Use the ENABLE pin to force zero output current. Setting
VCSNK = VCSRC = 0V allows IOUT = ±4mV/RSENSE to flow
in or out of VOUT.
ISRC (Pin 16): Sourcing Current Limit Digital Output Flag.
ISRC is an open collector digital output. ISRC pulls low
whenever the sourcing current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISRC may be left open if
this function is not monitored.
ISNK (Pin 17): Sinking Current Limit Digital Output Flag.
ISNK is an open collector digital output. ISNK pulls low
whenever the sinking current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISNK may be left open if
this function is not monitored.
TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD
is an open collector digital output. TSD pulls low whenever
the internal thermal shutdown circuit activates, typically at
a die temperature of 160°C. This pin can sink up to 10mA
of output current. The TSD flag is off when the die temperature is within normal operating temperatures. ISRC,
ISNK and TSD may be wired “OR” together if desired. TSD
may be left open if this function is not monitored. Thermal
shutdown activation should prompt the user to evaluate
electrical loading or thermal environmental conditions.
V+ (Pin 19): Output Stage Positive Supply. V + may equal
VCC or may be smaller in magnitude. Only output stage
current flows through V+, all other current flows into VCC.
V+ may be used to drive the base/gate of an external power
device to boost the amplifier’s output current to levels above
the rated 500mA of the on-chip output devices. Unless
used to drive boost transistors, V+ should be decoupled
to ground with a low ESR capacitor.
Package Base: The exposed backside of the package is
electrically connected to the VEE pins on the IC die. The
package base should be soldered to a heat spreading pad
on the PC board that is electrically connected to VEE.
1970fe
For more information www.linear.com/LT1970
9
LT1970
Block Diagram and test circuit
RFB
1k
VCC
V+
9
10k
15V
16
18
15
5V
12
13
–
OUT
15V
3
ISNK
ISRC
D1
ISINK
TSD
ENABLE
VCSNK
VCSRC
ENABLE
VCSNK
+
–
+
–
D2
VSNK
SENSE+
FILTER
VSRC
SENSE–
RFIL
1k
ISRC
VCSRC
V–
+
14
19
Q2
–
10k
17
–IN
+
10k
Q1
1×
GM1
8
RG
1k
+
VIN
–
+
–
+IN
7
VEE
COMMON
1, 10, 11, 20
4
RCS
1Ω
5
6
RLOAD
1k
2
–15V
1970TC
applications information
The LT1970 power op amp with precision controllable
current limit is a flexible voltage and current source
module. The drawing on the front page of this data sheet
is representative of the basic application of the circuit,
however many alternate uses are possible with proper
understanding of the sub circuit capabilities.
Circuit Description
Main Operational Amplifier
Sub circuit block GM1, the 1X unity-gain current buffer
and output transistors Q1 and Q2 form a standard operational amplifier. This amplifier has ± 500mA current output
capability and a 3.6MHz gain bandwidth product. Most
applications of the LT1970 will use this op amp in the main
signal path. All conventional op amp circuit configurations
are supported. Inverting, noninverting, filter, summation
or nonlinear circuits may be implemented in a conventional manner. The output stage includes current limiting
at ±800mA to protect against fault conditions. The input
stage has high differential breakdown of 36V minimum
10
between –IN and +IN. No current will flow at the inputs
when differential input voltage is present. This feature is
important when the precision current sense amplifiers
“ISINK” and “ISRC” become active.
Current Limit Amplifiers
Amplifier stages “ISINK” and “ISRC” are very high transconductance amplifier stages with independently controlled
offset voltages. These amplifiers monitor the voltage between input pins SENSE+ and SENSE– which usually sense
the voltage across a small external current sense resistor.
The transconductance amplifiers outputs connect to the
same high impedance node as the main input stage GM1
amplifier. Small voltage differences between SENSE+ and
SENSE–, smaller than the user set VCSNK/10 and VCSRC /10
in magnitude, cause the current limit amplifiers to decouple
from the signal path. This is functionally indicated by diodes
D1 and D2 in the Block Diagram. When the voltage VSENSE
increases in magnitude sufficient to equal or overcome one
of the offset voltages VCSNK/10 or VCSRC /10, the appropriate current limit amplifier becomes active and because of
For more information www.linear.com/LT1970
1970fe
LT1970
applications information
its very high transconductance, takes control from the input
stage, GM1. The output current is regulated to a value of
IOUT = VSENSE/RSENSE = (VCSRC or VCSNK)/(10 • RSENSE).
The time required for the current limit amplifiers to take
control of the output is typically 4µs.
Linear operation of the current limit sense amplifier occurs
with the inputs SENSE+ and SENSE– ranging between VCC
– 1.5V and VEE + 1.5V. Most applications will connect pins
SENSE+ and OUT together, with the load on the opposite
side of the external sense resistor and pin SENSE–. Feedback to the inverting input of GM1 should be connected
from SENSE– to – IN. Ground side sensing of load current
may be employed by connecting the load between pins
OUT and SENSE+. Pin SENSE– would be connected to
ground in this instance. Load current would be regulated
in exactly the same way as the conventional connection.
However, voltage mode accuracy would be degraded in
this case due to the voltage across RSENSE.
Creative applications are possible where pins SENSE+ and
SENSE– monitor a parameter other than load current. The
operating principle that at most one of the current limit
stages may be active at one time, and that when active,
the current limit stages take control of the output from
GM1, can be used for many different signals.
The transfer function from VC to the associated VOS is
linear from about 0.1V to 5V in, or 10mV to 500mV at
the current limit amplifier inputs. An intentional nonlinearity is built into the transfer functions at low levels. This
nonlinearity insures that both the sink and source limit
amplifiers cannot become active simultaneously. Simultaneous activation of the limit amplifiers could result in
uncontrolled outputs. As shown in the Typical Performance
Characteristics curves, the control inputs have a “hockey
stick” shape, to keep the minimum limit threshold at 4mV
for each limit amplifier.
Figure 1 illustrates an interesting use of the current
sense input pins. Here the current limit control amplifiers are used to produce a symmetrically limited output
voltage swing. Instead of monitoring the output current,
the output voltage is divided down by a factor of 20 and
applied to the SENSE+ input, with the SENSE– input
grounded. When the threshold voltage between SENSE+
and SENSE– (VCLAMP/10) is reached, the current limit
stage takes control of the output and clamps it a level of
±2 • VCLAMP. With control inputs VCSRC and VCSNK tied
together, a single polarity input voltage sets the same +
and – output limit voltage for symmetrical limiting. In this
circuit the output will current limit at the built-in fail-safe
level of typically 800mA.
Current Limit Threshold Control Buffers
Input pins VCSNK and VCSRC are used to set the response
thresholds of current limit amplifiers “ISINK” and “ISRC”.
Each of these inputs may be independently driven by a
voltage of 0V to 5V above the COMMON reference pin.
The 0V to 5V input voltage is attenuated by a factor of 10
and applied as an offset to the appropriate current limit
amplifier. AC signals may be applied to these pins. The AC
bandwidth from a VC pin to the output is typically 2MHz.
For proper operation of the LT1970, these control inputs
cannot be left floating.
For low VCC supply applications it is important to keep
the maximum input control voltages, VCSRC and VCSNK,
at least 2.5V below the VCC potential. This ensures linear
control of the current limit threshold. Reducing the current
limit sense resistor value allows high output current from
a smaller control voltage which may be necessary if the
VCC supply is only 5V.
12V
VCLAMP
OV TO 5V
R3
3k
VCSRC
VCSNK
VIN
80mV
TO
10V
+IN
EN
VCC
V+
ISRC
ISNK
–80mV
TO
±CLAMP
–10V
REACHED
OUTPUT CLAMPS
AT 2× VCLAMP
TSD
OUT
SENSE+
–
SENSE
FILTER
V–
LT1970
–IN
COMMON
VEE
–12V
RG
RF
R1
21.5k
RL
R2
1.13k
1970 F01
Figure 1. Symmetrical Output Voltage Limiting
1970fe
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11
LT1970
Applications Information
ENABLE Control
The ENABLE input pin puts the LT1970 into a low supply current, high impedance output state. The ENABLE
pin responds to TTL threshold levels with respect to the
COMMON pin. Pulling the ENABLE pin low is the best
way to force zero current at the output. Setting VCSNK =
VCSRC = 0V allows the output current to remain as high
as ± 4mV/RSENSE.
In applications such as circuit testers (ATE), it may be
preferable to apply a predetermined test voltage with a
preset current limit to a test node simultaneously. The
ENABLE pin can be used to provide this gating action as
shown in Figure 2. While the LT1970 is disabled, the load
is essentially floating and the input voltage and current
limit control voltages can be set to produce the load test
levels. Enabling the LT1970 then drives the load. The
LT1970 enables and disables in just a few microseconds.
The actual enable and disable times at the load are a
function of the load reactance.
Operating Status Flags
The LT1970 has three digital output indicators; TSD, ISRC
and ISNK. These outputs are open collector drivers referred
to the COMMON pin. The outputs have 36V capabilities
and can sink in excess of 10mA. ISRC and ISNK indicate
5V
0V
activation of the associated current limit amplifier. The TSD
output indicates excessive die temperature has caused the
circuit to enter thermal shutdown. The three digital outputs
may be wire “OR’d” together, monitored individually or left
open. These outputs do not affect circuit operation, but
provide an indication of the present operational status of
the chip.
For slow varying output signals, the assertion of a low level
at the current limit output flags occurs when the current
limit threshold is reached. For fast moving signals where
the LT1970 output is moving at the slew limit, typically
1.6V/µs, the flag assertion can be somewhat premature
at typically 75% of the actual current limit value.
The operating status flags are designed to drive LEDs to
provide a visual indication of current limit and thermal
conditions. As such, the transition edges to and from
the active low state are not particularly sharp and may
exhibit some uncertainty. Adding some positive feedback
to the current limit control inputs helps to sharpen these
transitions.
With the values shown in Figure 3, the current limit threshold is reduced by approximately 0.5% when either current
limit status flag goes low. With sharp logic transitions, the
status outputs can be used in a system control loop to
ENABLE
VOUT
DISABLE
1V/DIV
0V
5V
12V
VCSRC
VCSNK
VIN
+IN
–IN
COMMON
RG
10k
EN
VCC
EN
10V/DIV
VIN = 0.5V
V+
ISRC
ISNK
TSD
OUT
LT1970
SENSE+
–
SENSE
FILTER
V–
VEE
–12V
0V
5µs/DIV
VIN = –0.5V
RS
1Ω
RF
10k
RL
10Ω
1970 F02
Figure 2. Using the ENABLE pin
12
1970fe
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LT1970
applications information
take protective measures when a current limit condition
is detected automatically.
initially sets a high value of current limit (500mA). The
circuit operates normally until the signal is large enough
to enter current limit. When either current limit flag goes
low, the current limit control voltage is reduced by a factor of 10. This then forces a low level of output current
(50mA) until the signal is reduced in magnitude. When
the load current drops below the lower level, the current
limit is then restored to the higher value. This action is
similar to a self resettable fuse that trips at dangerously
high current levels and resets only when conditions are
safe to do so.
The current limit status flag can also be used to produce
a dramatic change in the current limit value of the amplifier. Figure 4 illustrates a “snap-back” current limiting
characteristic. In this circuit, a simple resistor network
CURRENT
LIMIT
CONTROL
VOLTAGE
(0.1V TO 5V)
R1
100Ω
R3
20k
R2
100Ω
R4
20k
ISOURCE FLAG
ISINK FLAG
12V
VCSRC
VCSNK
+IN
VIN
EN
VCC
WHEN CURRENT LIMIT
IS FLAGGED, ILIMIT
TRESHOLD IS REDUCED
BY 0.5%
V+
ISRC
ISNK
Thermal Management
Minimizing Power Dissipation
RS
1Ω
TSD
OUT
SENSE+
–
SENSE
FILTER
V–
LT1970
–IN
COMMON
VEE
–12V
RG
RL
RF
1970 F03
Figure 3. Adding Positive Feedback to Sharpen the Transition
Edges of the Current Limit Status Flags
12V
R2
39.2k
R1
54.9k
VCSRC
VCSNK
VIN
+IN
–IN
COMMON
RG
10k
EN
VCC
R3
2.55k
The first concern for thermal management is minimizing
the heat which must be dissipated. The separate power
pins V+ and V– can be a great aid in minimizing on-chip
power. The output pin can swing to within 1.0V of V+ or
V– even under maximum output current conditions. Using
separate power supplies, or voltage regulators, to set V+
500mA
V+
ISRC
ISNK
TSD
OUT
LT1970
SENSE+
–
SENSE
FILTER
V–
VEE
–12V
The LT1970 can operate with up to 36V total supply voltage with output currents up to ± 500mA. The amount of
power dissipated in the chip could approach 18W under
worst-case conditions. This amount of power will cause
die temperature to rise until the circuit enters thermal
shutdown. While the thermal shutdown feature prevents
damage to the circuit, normal operation is impaired.
Thermal design of the LT1970 operating environment is
essential to getting maximum utility from the circuit.
RS
1Ω
IOUT
RL
IMAX
50mA
0
ILOW
–500mA
IMAX ≈
VCC • R2
(R1 + R2) • 10 • RS
ILOW ≈
VCC • (R2||R3)
[R1 + (R2||R3)] • 10 • RS
RF
10k
1970 F04
Figure 4. “Snap-Back” Current Limiting
1970fe
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13
LT1970
Applications Information
and V– to their minimum values for the required output
swing will minimize power dissipation. The supplies VCC
and VEE may also be reduced to a minimal value, but these
supply pins do not carry high currents, and the power
saving is much less. VCC and VEE must be greater than
the maximum output swing by 1.5V or more.
not very effective. Expanding the area on various layers
significantly reduces the overall thermal resistance. The
addition of vias (small 13 mil holes which fill during PCB
plating) connecting all layers of metal also helps reduce
the operating temperature of the LT1970. These are also
shown in Figure 5.
When V – and V+ are provided separately from VCC and VEE,
care must be taken to insure that V– and V+ are always less
than or equal to the main supplies in magnitude. Protection Schottky diodes may be required to insure this in all
cases, including power on/off transients.
It is important to note that the metal planes used for heat
sinking are connecting electrically to VEE. These planes
must be isolated from any other power planes used in
the PCB design.
Operation with reduced V+ and V– supplies does not affect
any performance parameters except maximum output
swing. All DC accuracy and AC performance specifications
guaranteed with VCC = V+ and VEE = V– are still valid with
the reduced output signal swing range.
Another effective way to control the power amplifier operating temperature is to use airflow over the board. Airflow
can significantly reduce the total thermal resistance as
also shown in Figure 5.
Driving Reactive Loads
Heat Sinking
Capacitive Loads
The power dissipated in the LT1970 die must have a path
to the environment. With 100°C/W thermal resistance in
free air with no heat sink, the package power dissipation
is limited to only 1W. The 20-pin TSSOP package with
exposed copper underside is an efficient heat conductor
if it is effectively mounted on a PC board. Thermal resistances as low as 40°C/W can be obtained by soldering the
bottom of the package to a large copper pattern on the PC
board. For operation at 85°C, this allows up to 1.625W of
power to be dissipated on the LT1970. At 25°C operation,
up to 3.125W of power dissipation can be achieved. The
PC board heat spreading copper area must be connected
to VEE.
The LT1970 is much more tolerant of capacitive loading
than most operational amplifiers. In a worst-case configuration as a voltage follower, the circuit is stable for
capacitive loads less than 2.5nF. Higher gain configurations
improve the CLOAD handling. If very large capacitive loads
are to be driven, a resistive decoupling of the amplifier
from the capacitive load is effective in maintaining stability
and reducing peaking. The current sense resistor, usually
connected between the output pin and the load can serve
as a part of the decoupling resistance.
Figure 5 shows examples of PCB metal being used for heat
spreading. These are provided as a reference for what might
be expected when using different combinations of metal
area on different layers of a PCB. These examples are with
a 4-layer board using 1oz copper on each layer. The most
effective layers for spreading heat are those closest to the
LT1970 junction. Soldering the exposed thermal pad of the
TSSOP package to the board produces a thermal resistance
from junction-to-case of approximately 3°C/W.
As a minimum, the area directly beneath the package on
all PCB layers can be used for heat spreading. However,
limiting the area to that of the metal heat sinking pad is
14
Inductive Loads
Load inductance is usually not a problem at the outputs
of operational amplifiers, but the LT1970 can be used as a
high output impedance current source. This condition may
be the main operating mode, or when the circuit enters
a protective current limit mode. Just as load capacitance
degrades the phase margin of normal op amps, load
inductance causes a peaking in the loop response of the
feedback controlled current source. The inductive load may
be caused by long lead lengths at the amplifier output. If
the amplifier will be driving inductive loads or long lead
lengths (greater than 4 inches) a 500pF capacitor from the
SENSE– pin to the ground plane will cancel the inductive
load and ensure stability.
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1970fe
LT1970
applications information
STILL AIR θJA
PACKAGE
TOP LAYER
2ND LAYER
3RD LAYER
BOTTOM LAYER
TSSOP
100°C/W
TSSOP
50°C/W
TSSOP
45°C/W
1970 F05a
Typical Reduction in θJA with
Laminar Airflow Over the Device
0
REDUCTION IN θJA (%)
–10
% REDUCTION RELATIVE
TO θJA IN STILL AIR
–20
–30
–40
–50
–60
0 100 200 300 400 500 600 700 800 900 1000
AIRFLOW (LINEAR FEET PER MINUTE, lfpm)
1970 F05b
Figure 5. Examples of PCB Metal Used for Heat Dissipation. Driver Package Mounted on Top
Layer. Heat Sink Pad Soldered to Top Layer Metal. Metal Areas Drawn to Scale of Package Size
1970fe
For more information www.linear.com/LT1970
15
LT1970
Applications Information
Figure 6 shows the LT1970 driving an inductive load with
a controlled amount of current. This load is shown as
a generic magnetic transducer, which could be used to
create and modulate a magnetic field. Driving the current
limit control inputs directly forces a current through the
load that could range up to 2MHz in modulation. Biasing
the input stage to the midpoint of the modulation signal
allows symmetrical bidirectional current flow through
the load. Clamp diodes are added to protect the LT1970
output from large inductive flyback potentials caused by
rapid di/dt changes.
Figure 7 shows the connection of these back-to-back
clamp diodes between the FILTER pin and the SENSE+ pin.
With this connection, the internal 1k resistor between the
SENSE– pin and the FILTER pin limits the diode current. The
BAV99 diodes are small SOT-23 packaged general purpose
silicon diodes. The maximum current limit sense voltage
is now the diode voltage drop, determined by the voltage
across the sense resistor and the 1k internal resistor. As
the diode begins to conduct current, with a voltage drop
of around 300mV, an error in the expected current limit
level at the high end of the control becomes apparent, as
Abrupt Load Short Protection
MAIN
AMPLIFIER
An abrupt short-circuit connection, often referred to as
screwdriver or crowbar short, to ground or other supply
potentials is the worst-case load condition for the LT1970.
The current limit sense amplifier normally operates with
an input voltage differential equal to the voltage across the
sense resistor, which is only 500mV maximum in a typical
application. During an abrupt load short to ground, the
load end of the sense resistor is immediately connected to
ground while the amplifier output remains at the normal
output voltage. This can impose a large differential voltage
to the sense amplifier inputs for a brief period. If this delta
V can be greater than ±2V, it is beneficial to add clamps
between the current limit sense amplifier inputs. These
clamps ensure a smooth transition from the main amplifier
control to the current limit amplifier control under all load
short conditions that may arise.
3
OUT
RSENSE
LOAD
CURRENT
LIMIT SENSE
AMPLIFIER
3
+
4
5
1k
–
6
SENSE+
FILTER
SENSE–
*OPTIONAL—SEE TEXT
BAV99
1
2
1nF TO 10nF
100Ω*
SENSE+
2N3904
FILTER
2N3904
1970 F07
HIGHER CLAMP VOLTAGE
ALTERNATIVE
Figure 7. Adding Protection for Abrupt Load Shorts
5V
VIN
12V
0V
VCSRC
VCSNK
+IN
EN
VCC
D1
1N4001
V+
ISRC
ISNK
12V
R1
95.3K
LT1634-2.5
2.5V
–IN
COMMON
TSD
OUT
LT1970
SENSE+
–
SENSE
FILTER
V–
VEE
–12V
C1
500pF
RS
1Ω
±500mA
MAGNETIC
TRANSDUCER
D2
1N4001
1970 F06
Figure 6. Current Modulation of a Magnetic Transducer
16
1970fe
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LT1970
applications information
VDIODE is less than the voltage across RSENSE. Adding an
optional external 100Ω resistor in parallel with the internal
1k resistor forces the diode voltage closer to the sensed
current limit voltage and reduces the current limit error.
Alternatively, the base-emitter junctions of back-to-back
2N3904 NPN transistors can provide this clamping action.
These diodes begin to conduct at a higher voltage level
nearer to 600mV. With a 500mV maximum current limit
threshold very little error will be noticed. Comparisons
of typical current limit error with three ways of adding
clamping protection are shown in Figure 8. Scaling the
current sense resistor and the current limit control voltage
down so that a 0V to 300mV current limit sense voltage
range also prevents these accuracy errors caused by the
abrupt-short clamping diodes.
Also shown in Figure 7 is a small filtering capacitor. This
too provides an extra measure of control under abrupt
load shorting conditions. A fast short-circuit makes apparent all parasitic interconnect lead inductances between
the LT1970 and the load. These distributed parasitic elements can cause significant transient voltage spikes in
the short time after the application or removal of a short
circuit. These uncontrolled voltage transients could actually couple back to the current limit amplifier and cause
polarity reversal from sourcing current limit to sinking or
vice versa. This can act as positive feedback and cause
CURRENT LIMIT ACCURACY (%)
25
20
BAV99 w 1kΩ
15
10
5
BAV99 w 100Ω
0
2N3904 w 1kΩ
–5
–10
50 100 150 200 250 300 350 400 450 500
±VCL SENSE (mV)
1970 F08
Figure 8. Current Limit Accuracy with Different Clamps
the current limit amplifier to go to the incorrect current
limit direction and hang up. Adding a small filter capacitor between the SENSE– and FILTER pins, 1nF to 10nF is
fairly typical, which charges through the clamp diodes
forces the correct current limit polarity at the instant of the
load short. This holds the amplifier in current limit until
the capacitor discharges through the internal 1k resistor,
eliminating transient induced behavior and creating a
smooth transition into current limit.
Supply Bypassing
The LT1970 can supply large currents from the power
supplies to a load at frequencies up to 4MHz. Power supply impedance must be kept low enough to deliver these
currents without causing supply rails to droop. Low ESR
capacitors, such as 0.1µF or 1µF ceramics, located close to
the pins are essential in all applications. When large, high
speed transient currents are present additional capacitance
may be needed near the chip. Check supply rails with a
scope and if signal related ripple is seen on the supply rail,
increase the decoupling capacitor as needed.
To ensure proper start-up biasing of the LT1970, it is recommended that the rate of change of the supply voltages
at turn-on be limited to be no faster than 6V/µs.
Application Circuit Ideas
The digitally controlled analog pin driver is shown in
Figure 9. All of the control signals are provided by an
LTC®1664 quad, 10-bit DAC by way of a 3-wire serial
interface. The LT1970 is configured as a simple difference amplifier with a gain of 3. This gain is required to
produce ±15V from the 0V to 5V outputs from DACs C
and D. To provide voltage headroom, the supplies for the
LT1970 are set to the maximum value of ±18V. As ±18V
is the absolute maximum rating of supply voltage for the
LT1970, care must be taken to not allow the supply voltage
to increase. DACs A and B separately control the sinking
and sourcing current limit to the load over the range of
± 4mA to ±500mA. An optional ON/OFF control for the pin
driver using the ENABLE input is shown. If always enabled
the ENABLE pin should be tied to VCC.
1970fe
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17
LT1970
Applications Information
OPTIONAL TEST PIN
ON/OFF CONTROL
APPLY LOAD
DRIVE
5V
Hi-Z
0V
5V
VOUT = 15V
VCC
CLR VREF
(
)
CODE C – CODE D
≈ ±15V
1024
ISOURCE(MAX) = 0.5 • CODE B ≈ –4mA TO –500mA
1024 • RS
DAC A
ISINK(MAX) = 0.5 • CODE A ≈ 4mA TO 500mA
1024 • RS
18V
3-WIRE
SERIAL
INTERFACE
R6
3k
+
10µF
0.1µF
DECODER
VCSRC
VCSNK
R1
3.4k
DAC C
+IN
EN
R2
10.2k
R3
3.4k
DAC D
–IN
COMMON
V+
ISRC
ISNK
RS
1Ω
TSD
OUT
LT1970
SENSE+
SENSE–
FILTER
V–
VEE
R4
10.2k
LTC1664
QUAD 10-BIT DAC
VCC
FORCE
TEST PIN
LOAD
SENSE
–18V
+
CS/LD
SCK
DI
R5
3k
DAC B
10µF
0.1µF
1970 F09
Figure 9. Digitally Controlled Analog Pin Driver
In some applications it may be necessary to know what
the current into the load is at any time. Figure 10 shows an
LT1787 high side current sense amplifier monitoring the
current through sense resistor RS. The LT1787 is biased
from the VEE supply to accommodate the common mode
input range of ±10V. The sense resistor is scaled down
to provide a 100mV maximum differential signal to the
current sense amplifier to preserve linearity. The LT1880
amplifier provides gain and level shifting to produce a 0V
to 5V output signal (2.5V DC ±5mV/mA) with up to 1kHz
full-scale bandwidth. An A/D converter could then digitize this instantaneous current reading to provide digital
feedback from the circuit.
18
The LT1970 is just as easy to use as a standard operational
amplifier. Basic amplification of a precision reference
voltage creates a very simple bench DC power supply as
shown in Figure 11. The built-in power stage produces an
adjustable 0V to 25V at 4mA to 100mA of output current.
Voltage and current adjustments are derived from the
LT1634-5 5V reference. The output current capability is
500mA, but this supply is restricted to 100mA for power
dissipation reasons. The worst-case output voltage for
maximum power dissipated in the LT1970 output stage
occurs if the output is shorted to ground or set to a voltage
near zero. Limiting the output current to 100mA sets the
maximum power dissipation to 3W. To allow the output to
1970fe
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LT1970
applications information
VCC
0V TO 1V
12V
VCSRC
VCSNK
+IN
–IN
COMMON
EN
VCC
V+
ISRC
ISNK
RS
0.2Ω
TSD
OUT
LT1970
SENSE+
–
SENSE
FILTER
V–
VEE
RLOAD
R4
255k
LT1787
RF
VS+
BIAS
–12V
R1
60.4k
20k
VEE
12V
–
R2
10k
+
VOUT
2.5V
±5mV/mA
LT1880
R3
20k
–12V
1kHz FULL CURRENT
BANDWIDTH
–12V
0V TO 5V
A/D
1970 F10
OPTIONAL DIGITAL FEEDBACK
Figure 10. Sensing Output Current
R2 40k
R3
10k
R4 10k
OUTPUT
VOLTAGE
ADJUST
30V DC
CURRENT LIMIT
ADJUST
VCSRC
VCSNK
+IN
LT1634-5
–IN
COMMON
R5
5.49k
LOAD
FAULT
EN
VCC
V+
ISRC
ISNK
RF
10.2k
+
VOUT
0V TO 25V
4mA TO 100mA
C3
10µF
GND
–5V
LTC1046
RG
2.55k
RS
1Ω
TSD
OUT
LT1970
SENSE+
–
SENSE
FILTER
V–
VEE
+
R1
2.1k
+
RG
VS–
–12V
C2
10µF
C1 10µF
Figure 11. Simple Bench Power Supply
For more information www.linear.com/LT1970
1970 F11
1970fe
19
LT1970
Applications Information
R6
18.2k
15V
VCSRC
VCSNK
R5
13k
–IN
+IN
COMMON
18V
R3
23.2k
LT1634-5
R4
10k
VCC
R8
3k
+OUT
CURRENT
LIMIT
THERMAL
FAULT
V+
ISRC
ISNK
+
10µF
+
R9
10k
1%
15V
R11
10k
1/2 LT1881
–
OPTIONAL SYMMETRY
ADJUST
100Ω
1/2 LT1881
+
R13
25.5k
+OUT
0V TO 12V
4mA TO 150mA
C2
10µF
C1
1µF
–15V
R12
10k
+
RS1
1Ω
TSD
OUT
LT1970
SENSE+
SENSE–
FILTER
V–
VEE
5V
REF
VOUT
ADJUST
R2
10k
CURRENT
LIMIT
ADJUST
0.1
–
R1
6.19k
EN
R7
3k
GROUND
–15V
15V
R15
3k
VCSRC
VCSNK
+IN
COMMON
EN
VCC
V+
ISRC
ISNK
TSD
OUT
LT1970
SENSE+
–
SENSE
FILTER
–
V
VEE
–15V
+
–IN
–OUT
CURRENT
LIMIT
10µF
RS2
1Ω
+
R14
10.7k
R10
10k
1%
TO TSD PIN
OF +OUT
C3
10µF
–OUT
0V TO –12V
4mA TO 150mA
1970 F12
0.1µF
Figure 12. Dual Tracking Bench Power Supply
20
1970fe
For more information www.linear.com/LT1970
LT1970
applications information
range all the way to 0V, an LTC1046 charge pump inverter
is used to develop a –5V supply. This produces a negative
rail for the LT1970 which has to sink only the quiescent
current of the amplifier, typically 7mA.
Using a second LT1970, a 0V to ±12V dual tracking power
supply is shown in Figure 12. The midpoint of two 10k
resistors connected between the + and – outputs is held
at 0V by the LT1881 dual op amp servo feedback loop. To
maintain 0V, both outputs must be equal and opposite in
polarity, thus they track each other. If one output reaches
current limit and drops in voltage, the other output follows to maintain a symmetrical + and – voltage across a
common load. Again, the output current limit is less than
the full capability of the LT1970 due to thermal reasons.
Separate current limit indicators are used on each LT1970
because one output only sources current and the other
only sinks current. Both devices can share the same
thermal shutdown indicator, as the output flags can be
ORed together.
OV TO 5V
TORQUE/STALL
CURRENT CONTROL
Another simple linear power amplifier circuit is shown in
Figure 13. This uses the LT1970 as a linear driver of a DC
motor with speed control. The ability to source and sink
the same amount of output current provides for bidirectional rotation of the motor. Speed control is managed by
sensing the output of a tachometer built on to the motor.
A typical feedback signal of 3V/1000rpm is compared
with the desired speed-set input voltage. Because the
LT1970 is unity-gain stable, it can be configured as an
integrator to force whatever voltage across the motor as
necessary to match the feedback speed signal with the
set input signal.
Additionally, the current limit of the amplifier can be adjusted to control the torque and stall current of the motor.
For reliability, a feedback scheme similar to that shown in
Figure 4 can be used. Assuming that a stalled rotor will
generate a current limit condition, the stall current limit
can be significantly reduced to prevent excessive power
dissipation in the motor windings.
15V
VCSRC
VCSNK
+IN
–IN
COMMON
EN
VCC
V+
ISRC
ISNK
TSD
OUT
LT1970
SENSE+
–
SENSE
FILTER
V–
VEE
RS
1Ω
12V DC
MOTOR
GND
15V
R1
1.2k
R2
10k
–15V
REVERSE
R4
49.9k
C1
1µF
R5
49.9k
TACH
FEEDBACK
3V/1000rpm
1970 F13
FORWARD
R3
1.2k
–15V
Figure 13. Simple Bidirectional DC Motor Speed Controller
1970fe
For more information www.linear.com/LT1970
21
LT1970
Applications Information
For motor speed control without using a tachometer, the
circuit in Figure 14 shows an approach. Using the enable feature of the LT1970, the drive to the motor can be
removed periodically. With no drive applied, the spinning
motor presents a back EMF voltage proportional to its
rotational speed. The LT1782 is a tiny rail-to-rail amplifier
with a shutdown pin. The amplifier is enabled during this
interval to sample the back EMF voltage across the motor.
This voltage is then buffered by one-half of an LT1638 dual
op amp and used to provide the feedback to the LT1970
integrator. When re-enabled the LT1970 will adjust the drive
to the motor until the speed feedback voltage, compared
to the speed-set input voltage, settles the output to a fixed
value. A 0V to 5V signal for the motor speed input controls
both rotational speed and direction.
The other half of the LT1638 is used as a simple pulse
oscillator to control the periodic sampling of the motor
back EMF.
Figure 15 shows how easy it is to boost the output current
of the LT1970. This ±5A power stage uses complementary
22
external N- and P‑channel MOSFETs to provide the additional current. The output stage power supply inputs,
V+ and V–, are used to provide gate drive as needed. With
higher output currents, the sense resistor RCS, is reduced
in value to maintain the same easy current limit control.
This Class B power stage is intended for DC and low
frequency,
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