LT1970CFE

LT1970 500mA Power Op Amp with Adjustable Precision Current Limit FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ ■ ■ ■ ■ ■ ± 500mA Minimum Output Current Independent Adjustment of Source and Sink Current Limits 2% Current Limit Accuracy Operates with Single or Split Supplies Shutdown/Enable Control Input Open Collector Status Flags: Sink Current Limit Source Current Limit Thermal Shutdown Fail Safe Current Limit and Thermal Shutdown 1.6V/µs Slew Rate 3.6MHz Gain Bandwidth Product Fast Current Limit Response: 2MHz Bandwidth Specified Temperature Range: – 40°C to 85°C Available in a 20-Lead TSSOP Package The LT®1970 is a ± 500mA power op amp with precise externally controlled current limiting. Separate control voltages program the sourcing and sinking current limit sense thresholds with 2% accuracy. Output current may be boosted by adding external power transistors. The circuit operates with single or split power supplies from 5V to 36V total supply voltage. In normal operation, the input stage supplies and the output stage supplies are connected (VCC to V+ and VEE to V–). To reduce power dissipation it is possible to power the output stage (V+, V–) from independent, lower voltage rails. The amplifier is unity-gain stable with a 3.6MHz gain bandwidth product and slews at 1.6V/µs. The current limit circuits operate with a 2MHz response between the VCSRC or VCSNK control inputs and the amplifier output. Open collector status flags signal current limit circuit activation, as well as thermal shutdown of the amplifier. An enable logic input puts the amplifier into a low power, high impedance output state when pulled low. Thermal shutdown and a ±800mA fixed current limit protect the chip under fault conditions. The LT1970 is packaged in a 20-lead TSSOP package with a thermally conductive copper bottom plate to facilitate heat sinking. APPLICATIO S ■ ■ ■ ■ Automatic Test Equipment Laboratory Power Supplies Motor Drivers Thermoelectric Cooler Driver , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO VLIMIT 0V TO 5V V IOUT(LIMIT) = ± LIMIT 10 • RCS VIN AV = 2 Amplifier with Adjustable ± 500mA Full-Scale Current Limit and Fault Indication 15V 15V 3k VCC V+ EN VCSRC +IN VCSNK ISNK ISRC TSD LT1970 OUT SENSE+ SENSE– V– –IN VEE COMMON Current Limited Sinewave Into 10Ω Load 4V VLOAD 2V 0V – 2V IOUT RCS 1Ω 1/4W R1 10k R2 10k 1970 TA01 LOAD –15V VCSRC = 4V VCSNK = 2V RCS = 1Ω U 20µs/DIV 1970 TA02 U U 1970fb 1 LT1970 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW VEE V– OUT SENSE+ FILTER SENSE– VCC –IN +IN 1 2 3 4 5 6 7 8 9 21 20 VEE 19 V+ 18 TSD 17 ISNK 16 ISRC VEE 10 FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 40°C/ W (NOTE 8) EXPOSED PAD (PIN 21) IS CONNECTED TO VEE Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VOS PARAMETER Input Offset Voltage Power Op Amp Characteristics The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions. CONDITIONS MIN TYP 200 0°C < TA < 70°C –40°C < TA < 85°C Input Offset Voltage Drift (Note 4) IOS IB en in RIN CIN VCM CMRR PSRR Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Input Resistance Input Capacitance Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio VCM = 0V VCM = 0V 0.1Hz to 10Hz 1kHz 1kHz Common Mode Differential Mode Pin 8 and Pin 9 to Ground Typical Guaranteed by CMRR Test –12V < VCM < 12V VEE CC VEE = V– = – 5V, VCC = 30V, V+ = 2.5V to 30V VEE = V– = – 3V to – 30V, VCC = V+ = 5V VEE = – 30V, V– = – 2.5V to –30V, VCC = V+ = 5V = V– = – 5V, V = V+ = 3V to 30V ● ● ● ● ● ● ● ● ● ● ● 2 +– Supply Voltage (VCC to VEE).................................... 36V Positive High Current Supply (V+) .................. V– to VCC Negative High Current Supply(V–) ................... VEE to V+ Amplifier Output (OUT) ..................................... V – to V+ Current Sense Pins (SENSE+, SENSE–, FILTER) .......................... V – to V+ Logic Outputs (ISRC, ISNK, TSD) ....... COMMON to VCC Input Voltage (–IN, +IN) .......... VEE – 0.3V to VEE + 36V Input Current ....................................................... 10mA Current Control Inputs (VCSRC, VCSNK) ............. COMMON to COMMON + 7V Enable Logic Input .............................. COMMON to VCC COMMON ..................................................... VEE to VCC Output Short-Circuit Duration ......................... Indefinite Operating Temperature Range (Note 2) .. – 40°C to 85°C Specified Temperature Range (Note 3) ... – 40°C to 85°C Maximum Junction Temperature ......................... 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LT1970CFE LT1970IFE 15 ENABLE 14 COMMON 13 VCSRC 12 VCSNK 11 VEE MAX 600 1000 1300 10 100 UNITS µV µV µV µV/°C nA nA µVP-P nV/√Hz pA/√Hz kΩ kΩ pF –10 –100 –600 –4 –160 3 15 3 500 100 6 –14.5 –12.0 92 90 110 90 110 105 100 130 100 130 13.6 12.0 U V V dB dB dB dB dB 1970fb W U U WW W LT1970 ELECTRICAL CHARACTERISTICS SYMBOL AVOL PARAMETER Large-Signal Voltage Gain The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions. CONDITIONS RL = 1k, –12.5V < VOUT < 12.5V ● MIN 100 75 80 40 20 5 TYP 150 120 45 MAX UNITS V/mV V/mV V/mV V/mV V/mV V/mV RL = 100Ω, –12.5V < VOUT < 12.5V ● RL = 10Ω, –5V < VOUT < 5V, V+ = – V– = 8V ● VOL Output Sat Voltage Low VOL = VOUT – V– RL = 100, VCC = V+ = 15V, VEE = V– = –15V RL = 10, VCC = – VEE = 15V, V+ = – V– = 5V VOH = V+ – VOUT RL = 100, VCC = V+ = 15V, VEE = V– = –15V RL = 10, VCC = – VEE = 15V, V+ = – V– = 5V Output Low, RSENSE = 0Ω Output High, RSENSE = 0Ω –10V < VOUT < 10V, RL = 1k VOUT = 10VPEAK (Note 5) f = 10kHz 0.01%, VOUT = 0V to 10V, AV = – 1, RL = 1k VCSRC = VCSNK = 0V ● 1.9 0.8 1.7 1.0 500 –1000 0.7 11 3.6 8 0.1 0.1 15 45 490 480 –1 – 500 – 500 –500 200 –300 –25 250 –250 ±0.1 ±0.05 ±0.01 ±0.05 ±0.01 2 4 20 50 500 500 –0.2 800 – 800 1.6 2.5 V V V V mA mA V/µs kHz MHz µs VOH Output Sat Voltage High ● 2.3 1200 – 500 ISC SR FPBW GBW tS VSENSE(MIN) VSENSE(4%) VSENSE(10%) VSENSE(FS) IBI ISENSE– IFILTER ISENSE+ Output Short-Circuit Current Slew Rate Full Power Bandwidth Gain Bandwidth Product Settling Time Minimum Current Sense Voltage Current Sense Voltage 4% of Full Scale Current Sense Voltage 10% of Full Scale Current Sense Voltage 100% of Full Scale Current Limit Control Input Bias Current SENSE– Input Current FILTER Input Current SENSE+ Input Current Current Sense Characteristics ● 7 10 25 55 510 520 0.1 500 500 500 300 –200 25 mV mV mV mV mV mV µA nA nA nA µA µA µA % % % % % MHz VCSRC = VCSNK = 0.2V VCSRC = VCSNK = 0.5V VCSRC = VCSNK = 5V ● ● ● VCSRC, VCSNK Pins 0V < (VCSRC, VCSNK) < 5V 0V < (VCSRC, VCSNK) < 5V VCSRC= VCSNK = 0V VCSRC = 5V, VCSNK = 0V VCSRC= 0V, VCSNK = 5V VCSRC = VCSNK = 5V ● ● ● ● ● ● ● Current Sense Change with Output Voltage VCSRC = VCSNK = 5V, –12.5V < VOUT < 12.5V Current Sense Change with Supply Voltage VCSRC = VCSNK = 5V, 6V < (VCC, V+) < 18V 2.5V < V+ < 18V, VCC = 18V –18V < (VEE, V–) < –2.5V –18V < V– < – 2.5V, VEE = – 18V Current Sense Bandwidth RCSF Resistance FILTER to SENSE– Logic Output Leakage ISRC, ISNK, TSD Logic Low Output Level Logic Output Current Limit VENABLE IENABLE Enable Logic Threshold Enable Pin Bias Current ● ● ● 750 1000 1250 1 Ω µA V mA V µA 1970fb Logic I/O Characteristics V = 15V I = 5mA (Note 6) ● ● 0.2 25 0.8 –1 1.9 0.4 2.5 1 3 LT1970 ELECTRICAL CHARACTERISTICS SYMBOL ISUPPLY ICC ICC(STBY) tON tOFF PARAMETER Total Supply Current VCC Supply Current Supply Current Disabled Turn-On Delay Turn-Off Delay VCC, V+ VCC, V+ VCC, V+ The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions. CONDITIONS and V–, VEE Connected and V–, VEE Separate and V–, VEE Connected, VENABLE ● ● MIN TYP 7 3 0.6 10 10 MAX 13 7 1.5 UNITS mA mA mA µs µs ≤ 0.8V ● (Note 7) (Note 7) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT1970C is guaranteed functional over the operating temperature range of – 40°C and 85°C. Note 3: The LT1970C is guaranteed to meet specified performance from 0°C to 70°C. The LT1970C is designed, characterized and expected to meet specified performance from – 40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1970I is guaranteed to meet specified performance from –40°C to 85°C. Note 4: This parameter is not 100% tested. Note 5: Full power bandwidth is calculated from slew rate measurements: FPBW = SR/(2 • π • VP) Note 6: The logic low output level of pin TSD is guaranteed by correlating the output level of pin ISRC and pin ISNK over temperature. Note 7: Turn-on and turn-off delay are measured from VENABLE crossing 1.6V to the OUT pin at 90% of normal output voltage. Note 8: Thermal resistance varies depending upon the amount of PC board metal attached to the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. TYPICAL PERFOR A CE CHARACTERISTICS Warm-Up Drift VIO vs Time –100 VOS • 1000 (50mV/DIV) TOTAL SUPPLY CURRENT (mA) INPUT BIAS CURRENT (nA) TIME (100ms/DIV) 4 UW 0V 1970 G01 Input Bias Current vs VCM VS = ±15V –120 –140 –IBIAS –160 +IBIAS –180 –200 – 220 –240 –260 –15 –12 –9 –6 –3 0 3 6 9 12 15 COMMON MODE INPUT VOLTAGE (V) 1970 G02 Total Supply Current vs Supply Voltage 14 12 10 8 6 4 2 0 –2 –4 –6 –8 –10 –12 –14 0 ICC + IV + 125°C 25°C –55°C IEE + IV – –55°C 25°C 125°C 2 4 6 8 10 12 14 SUPPLY VOLTAGE (± V) 16 18 1970 G03 1970fb LT1970 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 4.5 4.0 SUPPLY CURRENT (mA) 70 IV+ IV IVCC – OPEN-LOOP GAIN (dB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (± V) TA = 25°C VCC = V + = –VEE = –V – IVEE 40 30 20 10 0 –10 –20 70 60 50 40 30 20 10 1k 10k 100k 1M FREQUENCY (Hz) 10M 0 100M PHASE MARGIN (DEG) Gain Bandwidth vs Supply Voltage 5 AV = 100 10 4 GAIN BANDWIDTH (MHz) VOLTAGE GAIN (dB) 3 –10 VS = ±15V VS = ±5V VOLTAGE GAIN (dB) 2 1 0 0 4 8 12 16 20 24 28 32 TOTAL SUPPLY VOLTAGE (V) 36 Output Impedance 100 VS = ± 15V 600k 100k 10 OUTPUT IMPEDANCE (Ω) OUTPUT IMPEDANCE (Ω) SLEW RATE (V/µs) AV = 100 1 AV = 10 0.1 AV = 1 0.01 0.001 1k 10k 100k 1M FREQUENCY (Hz) UW 18 1870 G04 1970 G07 Open-Loop Gain and Phase vs Frequency 100 90 GAIN PHASE 80 Phase Margin vs Supply Voltage 60 58 56 PHASE MARGIN (DEG) 60 50 AV = –1 RF = RG = 1k TA = 25°C VOUT = VS/2 54 52 50 48 46 44 42 40 0 4 8 12 16 20 24 28 32 TOTAL SUPPLY VOLTAGE (V) 36 20 –30 100 1970 G05 1970 G06 Gain vs Frequency 10 AV = 1 0 Gain vs Frequency with CLOAD VS = ±15V AV = 1 30nF 10nF 1nF –10 0nF –20 0 –20 –30 –30 –40 10k 100k 1M FREQUENCY (Hz) 10M 1970 G08 –40 10k 1M 100k FREQUENCY (Hz) 10M 1970 G09 Disabled Output Impedance VS = ±15V VENABLE = 0.8V 1.8 1.7 Slew Rate vs Supply Voltage FALLING 1.6 10k 1k 100 10 1 1k RISING 1.5 1.4 1.3 1.2 1.1 AV = –1 RF = RG = 1k TA = 25°C 4 6 8 12 14 10 SUPPLY VOLTAGE (± V) 16 18 1970 G12 10M 100M 1970 G10 10k 100k 1M FREQUENCY (Hz) 10M 100M 1970 G11 1.0 1970fb 5 LT1970 TYPICAL PERFOR A CE CHARACTERISTICS Slew Rate vs Temperature 2.5 VS = ±15V FALLING 2.0 SLEW RATE (V/µs) RISING 5V/DIV 5V/DIV 1.5 1.0 0.5 0 –50 –25 50 25 0 75 TEMPERATURE (°C) Small-Signal Response, AV = 1 20mV/DIV 20mV/DIV RL = 1k 500ns/DIV % Overshoot vs CLOAD 60 50 OUTPUT SWING (VP-P) AV = 1 OVERSHOOT (%) VS = ± 15V 40 30 AV = – 1 20 10 0 10 100 CLOAD (pF) 1970 G19 VSENSE (mV) 1k 6 UW 100 1970 G13 Large-Signal Response, AV = 1 Large-Signal Response, AV = – 1 10V 10V 0V 0V –10V –10V RL = 1k 20µs/DIV 1970 G14 RL = 1k CL = 1000pF 20µs/DIV 1970 G15 125 Small-Signal Response, AV = – 1 VOUT 5V/DIV 0V Output Overdriven VIN 5V/DIV 0V 1970 G16 RL = 1k CL = 1000pF 2µs/DIV 1970 G17 VS = ±5V AV = 1 200µs/DIV 1970 G18 Undistorted Output Swing vs Frequency 30 25 20 15 10 5 VS = ±15V AV = –5 1% THD 1k 10k FREQUENCY (Hz) 100k 1970 G20 Full Range Current Sense Transfer Curve 500 400 300 200 100 0 –100 –200 –300 –400 –500 0 1 3 2 VCSNK = VCSRC (V) 4 5 1970 G21 SOURCING CURRENT SINKING CURRENT 10k 0 100 1970fb LT1970 TYPICAL PERFOR A CE CHARACTERISTICS Low Level Current Sense Transfer Curve 25 20 SOURCING CURRENT LOGIC OUTPUT VOLTAGE (V) 15 10 VSENSE (mV) OUTPUT CURRENT (mA) 5 0 –5 –10 –15 –20 –25 0 25 50 75 100 125 150 175 200 225 250 VCSNK = VCSRC (mV) 1970 G22 SINKING CURRENT Safe Operating Area 1200 1000 IOUT AT 10% DUTY CYCLE OUTPUT STAGE CURRENT (mA) 10 8 6 4 2 0 –2 –4 –6 –8 0 0 5 10 15 20 25 30 SUPPLY VOLTAGE (V) 35 40 –10 IOUT PEAK (mA) 800 600 400 200 Control Stage Quiescent Current vs Supply Voltage 5 4 3 SUPPLY CURRENT (mA) 2 1 0 –1 –2 –3 –4 –5 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (± V) 16 18 IEE 125°C 25°C –55°C TOTAL SUPPLY CURRENT, ICC + IV+ (µA) ICC UW Logic Output Level vs Sink Current (Output Low) 1.0 V + = 15V 0.9 V – = –15V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.001 0.01 0.1 1 10 SINK CURRENT (mA) 100 1970 G23 Maximum Output Current vs Temperature 1600 1400 1200 SOURCE 1000 800 600 400 200 0 25 50 75 –75 –50 –25 0 TEMPERATURE (°C) 100 125 1970 G24 V+ = 15V V – = –15V 25°C 125°C SINK –55°C Output Stage Quiescent Current vs Supply Voltage IV+ 125°C 25°C –55°C IV – –55°C 25°C 125°C 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (± V) 16 18 1970 G25 1970 G26 Supply Current vs Supply Voltage in Shutdown 800 700 600 500 400 300 200 100 0 0 2 4 8 10 12 14 6 SUPPLY VOLTAGE (V) 16 18 VENABLE = 0V 85°C 25°C –55°C –55°C 25°C 125°C 1970 G27 1970 G28 1970fb 7 LT1970 PI FU CTIO S VEE (Pins 1, 10, 11, 20, Package Base): Minus Supply Voltage. VEE connects to the substrate of the integrated circuit die, and therefore must always be the most negative voltage applied to the part. Decouple VEE to ground with a low ESR capacitor. VEE may be a negative voltage or it may equal ground potential. Any or all of the VEE pins may be used. Unused VEE pins must remain open. V– (Pin 2): Output Stage Negative Supply. V– may equal VEE or may be smaller in magnitude. Only output stage current flows out of V– , all other current flows out of VEE. V– may be used to drive the base/gate of an external power device to boost the amplifier’s output current to levels above the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V– should be decoupled to ground with a low ESR capacitor. OUT (Pin 3): Amplifier Output. The OUT pin provides the force function as part of a Kelvin sensed load connection. OUT is normally connected directly to an external load current sense resistor and the SENSE+ pin. Amplifier feedback is directly connected to the load and the other end of the current sense resistor. The load connection is also wired directly to the SENSE– pin to monitor the load current. The OUT pin is current limited to ± 800mA typical. This current limit protects the output transistor in the event that connections to the external sense resistor are opened or shorted which disables the precision current limit function. SENSE + (Pin 4): Positive Current Sense Pin. This lead is normally connected to the driven end of the external sense resistor. Sourcing current limit operation is activated when the voltage VSENSE (VSENSE + – VSENSE –) equals 1/ 10 of the programming control voltage at VCSRC (Pin 13). Sinking current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12). FILTER (Pin 5): Current Sense Filter Pin. This pin is normally not used and should be left open or shorted to the SENSE– pin. The FILTER pin can be used to adapt the response time of the current sense amplifiers with a 1nF to 100nF capacitor connected to the SENSE – input. An internal 1k resistor sets the filter time constant. SENSE – (Pin 6): Negative Current Sense Pin. This pin is normally connected to the load end of the external sense resistor. Sourcing current limit operation is activated when the voltage VSENSE (VSENSE + – VSENSE –) equals 1/ 10 of the programming control voltage at VCSRC (Pin 13). Sinking current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12). VCC (Pin 7): Positive Supply Voltage. All circuitry except the output transistors draw power from VCC. Total supply voltage from VCC to VEE must be between 3.5V and 36V. VCC must always be greater than or equal to V+. VCC should always be decoupled to ground with a low ESR capacitor. – IN (Pin 8): Inverting Input of Amplifier. – IN may be any voltage from VEE – 0.3V to VEE + 36V. – IN and + IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to insure that – IN or + IN can never go to a voltage below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to – IN can provide clamping if other elements in the circuit can allow – IN to go below VEE. + IN (Pin 9): Noninverting Input of Amplifier. + IN may be any voltage from VEE – 0.3V to VEE + 36V. – IN and + IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to insure that – IN or + IN can never go to a voltage below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to +IN can provide clamping if other elements in the circuit can allow + IN to go below VEE. 8 U U U 1970fb LT1970 PI FU CTIO S VCSNK (Pin 12): Sink Current Limit Control Voltage Input. The current sink limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals –1.0 • VVCSNK/10. VCSNK may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSNK and VSENSE is linear except for very small input voltages at VCSNK < 60mV. VSENSE limits at a minimum set point of 4mV typical to insure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low. VCSRC (Pin 13): Source Current Limit Control Voltage Input. The current source limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals VVCSRC/10. VCSRC may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSRC and VSENSE is linear except for very small input voltages at VCSRC < 60mV. VSENSE limits at a minimum set point of 4mV typical to insure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low. COMMON (Pin 14): Control and ENABLE inputs and flag outputs are referenced to the COMMON pin. COMMON may be at any potential between VEE and VCC – 3V. In typical applications, COMMON is connected to ground. ENABLE (Pin 15): ENABLE Digital Input Control. When taken low this TTL-level digital input turns off the amplifier output and drops supply current to less than 1mA. Use the ENABLE pin to force zero output current. Setting VCSNK = VCSRC = 0V allows IOUT = ± 4mV/RSENSE to flow in or out of VOUT. ISRC (Pin 16): Sourcing Current Limit Digital Output Flag. ISRC is an open collector digital output. ISRC pulls low whenever the sourcing current limit amplifier assumes control of the output. This pin can sink up to 10mA of current. The current limit flag is off when the source current limit is not active. ISRC, ISNK and TSD may be wired “OR” together if desired. ISRC may be left open if this function is not monitored. ISNK (Pin 17): Sinking Current Limit Digital Output Flag. ISNK is an open collector digital output. ISNK pulls low whenever the sinking current limit amplifier assumes control of the output. This pin can sink up to 10mA of current. The current limit flag is off when the source current limit is not active. ISRC, ISNK and TSD may be wired “OR” together if desired. ISNK may be left open if this function is not monitored. TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD is an open collector digital output. TSD pulls low whenever the internal thermal shutdown circuit activates, typically at a die temperature of 160°C. This pin can sink up to 10mA of output current. The TSD flag is off when the die temperature is within normal operating temperatures. ISRC, ISNK and TSD may be wired “OR” together if desired. ISNK may be left open if this function is not monitored. Thermal shutdown activation should prompt the user to evaluate electrical loading or thermal environmental conditions. V+ (Pin 19): Output Stage Positive Supply. V + may equal VCC or may be smaller in magnitude. Only output stage current flows through V +, all other current flows into VCC. V + may be used to drive the base/gate of an external power device to boost the amplifier’s output current to levels above the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V + should be decoupled to ground with a low ESR capacitor. Package Base: The exposed backside of the package is electrically connected to the VEE pins on the IC die. The package base should be soldered to a heat spreading pad on the PC board that is electrically connected to VEE. U U U 1970fb 9 LT1970 BLOCK DIAGRA RFB 1k 9 +IN + – RG 1k VIN 8 10k 17 16 10k 10k –IN ISNK D1 ISINK 15 5V 12 ENABLE VCSNK VCSRC ENABLE D2 13 VCSRC ISRC 14 COMMON APPLICATIO S I FOR ATIO The LT1970 power op amp with precision controllable current limit is a flexible voltage and current source module. The drawing on the front page of this data sheet is representative of the basic application of the circuit, however many alternate uses are possible with proper understanding of the subcircuit capabilities. CIRCUIT DESCRIPTION Main Operational Amplifier Subcircuit block GM1, the 1X unity-gain current buffer and output transistors Q1 and Q2 form a standard operational amplifier. This amplifier has ± 500mA current output capability and a 3.6MHz gain bandwidth product. Most applications of the LT1970 will use this op amp in the main signal path. All conventional op amp circuit configurations are supported. Inverting, noninverting, filter, summation or nonlinear circuits may be implemented in a conventional manner. The output stage includes current limiting at ± 800mA to protect against fault conditions. The input stage has high differential breakdown of 36V minimum between – IN and + IN. No current will flow at the inputs when differential input voltage is present. This feature is important when the precision current sense amplifiers “ISINK” and “ISRC” become active. Current Limit Amplifiers Amplifier stages “ISINK” and “ISRC” are very high transconductance amplifier stages with independently controlled offset voltages. These amplifiers monitor the voltage between input pins SENSE+ and SENSE– which usually sense the voltage across a small external current sense resistor. The transconductance amplifiers outputs connect to the same high impedance node as the main input stage GM1 amplifier. Small voltage differences between SENSE+ and SENSE– , smaller than the user set VCSNK/10 and VCSRC/10 in magnitude, cause the current limit amplifiers to decouple from the signal path. This is functionally indicated by diodes D1 and D2 in the Block Diagram. When the voltage VSENSE increases in magnitude sufficient to equal or overcome one of the offset voltages VCSNK/10 or VCSRC/10, the appropriate current limit amplifier becomes active and because of 1970fb 10 – VCSNK + 15V 18 TSD – ISRC + U W UW + – A D TEST CIRCUIT VCC V+ 19 Q1 GM1 1× Q2 OUT 3 15V 7 + – + – VSNK SENSE+ FILTER SENSE – RFIL 1k RCS 1Ω 4 5 6 RLOAD 1k VSRC V– 2 VEE 2, 10, 11, 20 –15V 1970TC UU LT1970 APPLICATIO S I FOR ATIO its very high transconductance, takes control from the input stage, GM1. The output current is regulated to a value of IOUT = VSENSE /RSENSE = (VCSRC or VCSNK)/(10 • RSENSE). The time required for the current limit amplifiers to take control of the output is typically 4µs. Linear operation of the current limit sense amplifier occurs with the inputs SENSE+ and SENSE– ranging between VCC – 1.5V and VEE + 1.5V. Most applications will connect pins SENSE+ and OUT together, with the load on the opposite side of the external sense resistor and pin SENSE–. Feedback to the inverting input of GM1 should be connected from SENSE– to – IN. Ground side sensing of load current may be employed by connecting the load between pins OUT and SENSE+. Pin SENSE– would be connected to ground in this instance. Load current would be regulated in exactly the same way as the conventional connection. However, voltage mode accuracy would be degraded in this case due to the voltage across RSENSE. Creative applications are possible where pins SENSE+ and SENSE– monitor a parameter other than load current. The operating principle that at most one of the current limit stages may be active at one time, and that when active, the current limit stages take control of the output from GM1, can be used for many different signals. Current Limit Threshold Control Buffers Input pins VCSNK and VCSRC are used to set the response thresholds of current limit amplifiers “ISINK” and “ISRC”. Each of these inputs may be independently driven by a voltage of 0V to 5V above the COMMON reference pin. The 0V to 5V input voltage is attenuated by a factor of 10 and applied as an offset to the appropriate current limit amplifier. AC signals may be applied to these pins. The AC bandwidth from a VC pin to the output is typically 2MHz. For proper operation of the LT1970, these control inputs cannot be left floating. For low VCC supply applications it is important to keep the maximum input control voltages, VCSRC and VCSNK, at least 2.5V below the VCC potential. This ensures linear control of the current limit threshold. Reducing the current limit sense resistor value allows high output current from a smaller control voltage which may be necessary if the VCC supply is only 5V. U The transfer function from VC to the associated VOS is linear from about 0.1V to 5V in, or 10mV to 500mV at the current limit amplifier inputs. An intentional nonlinearity is built into the transfer functions at low levels. This nonlinearity insures that both the sink and source limit amplifiers cannot become active simultaneously. Simultaneous activation of the limit amplifiers could result in uncontrolled outputs. As shown in the Typical Performance Characteristics curves, the control inputs have a “hockey stick” shape, to keep the minimum limit threshold at 4mV for each limit amplifier. Figure 1 illustrates an interesting use of the current sense input pins. Here the current limit control amplifiers are used to produce a symmetrically limited output voltage swing. Instead of monitoring the output current, the output voltage is divided down by a factor of 20 and applied to the SENSE+ input, with the SENSE– input grounded. When the threshold voltage between SENSE+ and SENSE– (VCLAMP/10) is reached, the current limit stage takes control of the output and clamps it a level of ±2 • VCLAMP. With control inputs VCSRC and VCSNK tied together, a single polarity input voltage sets the same + and – output limit voltage for symmetrical limiting. In this circuit the output will current limit at the built-in fail-safe level of typically 800mA. 12V VCLAMP OV TO 5V VCSRC VCSNK VIN +IN R3 3k 80mV TO 10V –80mV TO ± CLAMP –10V REACHED OUTPUT CLAMPS AT 2 × VCLAMP EN VCC V+ ISRC ISNK R1 21.5k R2 1.13k LT1970 –IN COMMON VEE TSD OUT SENSE+ – SENSE FILTER V– RL RG –12V RF 1970 F01 W UU Figure 1. Symmetrical Output Voltage Limiting 1970fb 11 LT1970 APPLICATIO S I FOR ATIO ENABLE Control The ENABLE input pin puts the LT1970 into a low supply current, high impedance output state. The ENABLE pin responds to TTL threshold levels with respect to the COMMON pin. Pulling the ENABLE pin low is the best way to force zero current at the output. Setting VCSNK = VCSRC = 0V allows the output current to remain as high as ± 4mV/RSENSE. In applications such as circuit testers (ATE), it may be preferable to apply a predetermined test voltage with a preset current limit to a test node simultaneously. The ENABLE pin can be used to provide this gating action as shown in Figure 2. While the LT1970 is disabled, the load is essentially floating and the input voltage and current limit control voltages can be set to produce the load test levels. Enabling the LT1970 then drives the load. The LT1970 enables and disables in just a few microseconds. The actual enable and disable times at the load are a function of the load reactance. Operating Status Flags The LT1970 has three digital output indicators; TSD, ISRC and ISNK. These outputs are open collector drivers referred to the COMMON pin. The outputs have 36V capabilities and can sink in excess of 10mA. ISRC and ISNK 5V 0V ENABLE DISABLE 5V 12V VCSRC VCSNK VIN +IN EN –IN COMMON TSD OUT LT1970 SENSE+ SENSE– FILTER V– VEE RG 10k Figure 2. Using the ENABLE pin 1970fb 12 U indicate activation of the associated current limit amplifier. The TSD output indicates excessive die temperature has caused the circuit to enter thermal shutdown. The three digital outputs may be wire “OR’d” together, monitored individually or left open. These outputs do not affect circuit operation, but provide an indication of the present operational status of the chip. For slow varying output signals, the assertion of a low level at the current limit output flags occurs when the current limit threshold is reached. For fast moving signals where the LT1970 output is moving at the slew limit, typically 1.6V/µs, the flag assertion can be somewhat premature at typically 75% of the actual current limit value. The operating status flags are designed to drive LEDs to provide a visual indication of current limit and thermal conditions. As such, the transition edges to and from the active low state are not particularly sharp and may exhibit some uncertainty. Adding some positive feedback to the current limit control inputs helps to sharpen these transitions. With the values shown in Figure 3, the current limit threshold is reduced by approximately 0.5% when either current limit status flag goes low. With sharp logic transitions, the status outputs can be used in a system control VOUT 1V/DIV 0V EN 10V/DIV 0V VIN = 0.5V V+ ISRC ISNK RS 1Ω RL 10Ω 5µs/DIV VIN = – 0.5V VCC –12V RF 10k 1970 F02 W UU LT1970 APPLICATIO S I FOR ATIO loop to take protective measures when a current limit condition is detected automatically. The current limit status flag can also be used to produce a dramatic change in the current limit value of the amplifier. Figure 4 illustrates a “snap-back” current limiting characteristic. In this circuit, a simple resistor network CURRENT LIMIT CONTROL VOLTAGE (0.1V TO 5V) R1 100Ω R2 100Ω R3 20k ISOURCE FLAG R4 20k ISINK FLAG 12V VCSRC VCSNK VIN +IN WHEN CURRENT LIMIT IS FLAGGED, ILIMIT TRESHOLD IS REDUCED BY 0.5% RS 1Ω EN VCC V+ ISRC ISNK –IN COMMON TSD OUT LT1970 SENSE+ SENSE– FILTER V– VEE RG –12V RF 1970 F03 Figure 3. Adding Positive Feedback to Sharpen the Transition Edges of the Current Limit Status Flags 12V R2 39.2k R1 54.9k R3 2.55k VCSRC VCSNK VIN +IN EN VCC V+ ISRC ISNK RS 1Ω IOUT 50mA 0 ILOW –IN COMMON TSD OUT LT1970 SENSE+ – SENSE FILTER V– VEE RG 10k –12V RF 10k 1970 F04 Figure 4. “Snap-Back” Current Limiting 1970fb U initially sets a high value of current limit (500mA). The circuit operates normally until the signal is large enough to enter current limit. When either current limit flag goes low, the current limit control voltage is reduced by a factor of 10. This then forces a low level of output current (50mA) until the signal is reduced in magnitude. When the load current drops below the lower level, the current limit is then restored to the higher value. This action is similar to a self resettable fuse that trips at dangerously high current levels and resets only when conditions are safe to do so. THERMAL MANAGEMENT Minimizing Power Dissipation The LT1970 can operate with up to 36V total supply voltage with output currents up to ± 500mA. The amount of power dissipated in the chip could approach 18W under worst-case conditions. This amount of power will cause die temperature to rise until the circuit enters thermal shutdown. While the thermal shutdown feature prevents damage to the circuit, normal operation is impaired. Thermal design of the LT1970 operating environment is essential to getting maximum utility from the circuit. The first concern for thermal management is minimizing the heat which must be dissipated. The separate power pins V+ and V– can be a great aid in minimizing on-chip power. The output pin can swing to within 1.0V of V+ or V– even under maximum output current conditions. Using separate power supplies, or voltage regulators, to set V+ RL W UU 500mA IMAX RL –500mA VCC • R2 (R1 + R2) • 10 • RS VCC • (R2||R3) [R1 + (R2||R3)] • 10 • RS IMAX ≈ ILOW ≈ 13 LT1970 APPLICATIO S I FOR ATIO and V– to their minimum values for the required output swing will minimize power dissipation. The supplies VCC and VEE may also be reduced to a minimal value, but these supply pins do not carry high currents, and the power saving is much less. VCC and VEE must be greater than the maximum output swing by 1.5V or more. When V – and V+ are provided separately from VCC and VEE, care must be taken to insure that V– and V+ are always less than or equal to the main supplies in magnitude. Protection Schottky diodes may be required to insure this in all cases, including power on/off transients. Operation with reduced V + and V – supplies does not affect any performance parameters except maximum output swing. All DC accuracy and AC performance specifications guaranteed with VCC = V + and VEE = V – are still valid with the reduced output signal swing range. Heat Sinking The power dissipated in the LT1970 die must have a path to the environment. With 100°C/W thermal resistance in free air with no heat sink, the package power dissipation is limited to only 1W. The 20-pin TSSOP package with exposed copper underside is an efficient heat conductor if it is effectively mounted on a PC board. Thermal resistances as low as 40°C/W can be obtained by soldering the bottom of the package to a large copper pattern on the PC board. For operation at 85°C, this allows up to 1.625W of power to be dissipated on the LT1970. At 25°C operation, up to 3.125W of power dissipation can be achieved. The PC board heat spreading copper area must be connected to VEE. Figure 5 shows examples of PCB metal being used for heat spreading. These are provided as a reference for what might be expected when using different combinations of metal area on different layers of a PCB. These examples are with a 4-layer board using 1oz copper on each layer. The most effective layers for spreading heat are those closest to the LT1970 junction. Soldering the exposed thermal pad of the TSSOP package to the board produces a thermal resistance from junction-to-case of approximately 3°C/W. As a minimum, the area directly beneath the package on all PCB layers can be used for heat spreading. However, limiting the area to that of the metal heat sinking pad is not 14 U very effective. Expanding the area on various layers significantly reduces the overall thermal resistance. The addition of vias (small 13 mil holes which fill during PCB plating) connecting all layers of metal also helps reduce the operating temperature of the LT1970. These are also shown in Figure 5. It is important to note that the metal planes used for heat sinking are connecting electrically to VEE. These planes must be isolated from any other power planes used in the PCB design. Another effective way to control the power amplifier operating temperature is to use airflow over the board. Airflow can significantly reduce the total thermal resistance as also shown in Figure 5. DRIVING REACTIVE LOADS Capacitive Loads The LT1970 is much more tolerant of capacitive loading than most operational amplifiers. In a worst-case configuration as a voltage follower, the circuit is stable for capacitive loads less than 2.5nF. Higher gain configurations improve the CLOAD handling. If very large capacitive loads are to be driven, a resistive decoupling of the amplifier from the capacitive load is effective in maintaining stability and reducing peaking. The current sense resistor, usually connected between the output pin and the load can serve as a part of the decoupling resistance. Inductive Loads Load inductance is usually not a problem at the outputs of operational amplifiers, but the LT1970 can be used as a high output impedance current source. This condition may be the main operating mode, or when the circuit enters a protective current limit mode. Just as load capacitance degrades the phase margin of normal op amps, load inductance causes a peaking in the loop response of the feedback controlled current source. The inductive load may be caused by long lead lengths at the amplifier output. If the amplifier will be driving inductive loads or long lead lengths (greater than 4 inches) a 500pF capacitor from the SENSE– pin to the ground plane will cancel the inductive load and ensure stability. 1970fb W UU LT1970 APPLICATIO S I FOR ATIO STILL AIR θJA TSSOP 100°C/W PACKAGE TOP LAYER TSSOP 50°C/W TSSOP 45°C/W Typical Reduction in θJA with Laminar Airflow Over the Device 0 –10 REDUCTION IN θJA (%) –20 –30 –40 –50 –60 0 100 200 300 400 500 600 700 800 900 1000 AIRFLOW (LINEAR FEET PER MINUTE, lfpm) 1970 F05b Figure 5. Examples of PCB Metal Used for Heat Dissipation. Driver Package Mounted on Top Layer. Heat Sink Pad Soldered to Top Layer Metal. Metal Areas Drawn to Scale of Package Size U 2ND LAYER 3RD LAYER BOTTOM LAYER 1970 F05a W UU % REDUCTION RELATIVE TO θJA IN STILL AIR 1970fb 15 LT1970 APPLICATIO S I FOR ATIO Figure 6 shows the LT1970 driving an inductive load with a controlled amount of current. This load is shown as a generic magnetic transducer, which could be used to create and modulate a magnetic field. Driving the current limit control inputs directly forces a current through the load that could range up to 2MHz in modulation. Biasing the input stage to the midpoint of the modulation signal allows symmetrical bidirectional current flow through the load. Clamp diodes are added to protect the LT1970 output from large inductive flyback potentials caused by rapid di/dt changes. Abrupt Load Short Protection An abrupt short-circuit connection, often referred to as screwdriver or crowbar short, to ground or other supply potentials is the worst-case load condition for the LT1970. The current limit sense amplifier normally operates with an input voltage differential equal to the voltage across the sense resistor, which is only 500mV maximum in a typical application. During an abrupt load short to ground, the load end of the sense resistor is immediately connected to ground while the amplifier output remains at the normal output voltage. This can impose a large differential voltage to the sense amplifier inputs for a brief period. If this delta V can be greater than ±2V, it is beneficial to add clamps between the current limit sense amplifier inputs. These clamps ensure a smooth transition from the main amplifier control to the current limit amplifier control under all load short conditions that may arise. 5V VIN 0V VCSRC VCSNK +IN 12V 12V R1 95.3K LT1634-2.5 2.5V –IN COMMON Figure 6. Current Modulation of a Magnetic Transducer 1970fb 16 U Figure 7 shows the connection of these back-to-back clamp diodes between the FILTER pin and the SENSE+ pin. With this connection, the internal 1k resistor between the SENSE– pin and the FILTER pin limits the diode current. The BAV99 diodes are small SOT-23 packaged general purpose silicon diodes. The maximum current limit sense voltage is now the diode voltage drop, determined by the voltage across the sense resistor and the 1k internal resistor. As the diode begins to conduct current, with a voltage drop of around 300mV, an error in the expected current limit level at the high end of the control becomes RSENSE LOAD MAIN AMPLIFIER 3 OUT CURRENT LIMIT SENSE AMPLIFIER 3 W UU + 1k 4 5 SENSE+ FILTER SENSE– 1 2 BAV99 1nF TO 10nF SENSE+ 100Ω* – 6 *OPTIONAL—SEE TEXT 2N3904 2N3904 FILTER HIGHER CLAMP VOLTAGE ALTERNATIVE 1970 F07 Figure 7. Adding Protection for Abrupt Load Shorts EN VCC V+ ISRC ISNK D1 1N4001 RS 1Ω ± 500mA TSD OUT LT1970 SENSE+ – SENSE FILTER V– VEE MAGNETIC TRANSDUCER D2 1N4001 1970 F06 –12V C1 500pF LT1970 APPLICATIO S I FOR ATIO apparent, as VDIODE is less than the voltage across RSENSE. Adding an optional external 100Ω resistor in parallel with the internal 1k resistor forces the diode voltage closer to the sensed current limit voltage and reduces the current limit error. Alternatively, the base-emitter junctions of back-to-back 2N3904 NPN transistors can provide this clamping action. These diodes begin to conduct at a higher voltage level nearer to 600mV. With a 500mV maximum current limit threshold very little error will be noticed. Comparisons of typical current limit error with three ways of adding clamping protection are shown in Figure 8. Scaling the current sense resistor and the current limit control voltage down so that a 0V to 300mV current limit sense voltage range also prevents these accuracy errors caused by the abrupt-short clamping diodes. Also shown in Figure 7 is a small filtering capacitor. This too provides an extra measure of control under abrupt load shorting conditions. A fast short-circuit makes apparent all parasitic interconnect lead inductances between the LT1970 and the load. These distributed parasitic elements can cause significant transient voltage spikes in the short time after the application or removal of a short circuit. These uncontrolled voltage transients could actually couple back to the current limit amplifier and cause polarity reversal from sourcing current limit to sinking or vice versa. This can act as positive feedback and cause the 25 20 BAV99 w 1kΩ 15 10 BAV99 w 100Ω 5 0 2N3904 w 1kΩ –5 –10 50 100 150 200 250 300 350 400 450 500 ± VCL SENSE (mV) 1970 F08 Figure 8. Current Limit Accuracy with Different Clamps CURRENT LIMIT ACCURACY (%) U current limit amplifier to go to the incorrect current limit direction and hang up. Adding a small filter capacitor between the SENSE– and FILTER pins, 1nF to 10nF is fairly typical, which charges through the clamp diodes forces the correct current limit polarity at the instant of the load short. This holds the amplifier in current limit until the capacitor discharges through the internal 1k resistor, eliminating transient induced behavior and creating a smooth transition into current limit. Supply Bypassing The LT1970 can supply large currents from the power supplies to a load at frequencies up to 4MHz. Power supply impedance must be kept low enough to deliver these currents without causing supply rails to droop. Low ESR capacitors, such as 0.1µF or 1µF ceramics, located close to the pins are essential in all applications. When large, high speed transient currents are present additional capacitance may be needed near the chip. Check supply rails with a scope and if signal related ripple is seen on the supply rail, increase the decoupling capacitor as needed. To ensure proper start-up biasing of the LT1970, it is recommended that the rate of change of the supply voltages at turn-on be limited to be no faster than 6V/µs. Application Circuit Ideas The digitally controlled analog pin driver is shown in Figure 9. All of the control signals are provided by an LTC®1664 quad, 10-bit DAC by way of a 3-wire serial interface. The LT1970 is configured as a simple difference amplifier with a gain of 3. This gain is required to produce ±15V from the 0V to 5V outputs from DACs C and D. To provide voltage headroom, the supplies for the LT1970 are set to the maximum value of ±18V. As ±18V is the absolute maximum rating of supply voltage for the LT1970, care must be taken to not allow the supply voltage to increase. DACs A and B separately control the sinking and sourcing current limit to the load over the range of ± 4mA to ± 500mA. An optional ON/OFF control for the pin driver using the ENABLE input is shown. If always enabled the ENABLE pin should be tied to VCC. 1970fb W UU 17 LT1970 APPLICATIO S I FOR ATIO OPTIONAL TEST PIN ON/OFF CONTROL APPLY LOAD DRIVE 5V Hi-Z 0V 5V VOUT = 15V VCC CLR VREF DAC A 3-WIRE SERIAL INTERFACE CS/LD SCK DI DECODER DAC B DAC C R2 10.2k DAC D –18V LTC1664 QUAD 10-BIT DAC R4 10.2k Figure 9. Digitally Controlled Analog Pin Driver In some applications it may be necessary to know what the current into the load is at any time. Figure 10 shows an LT1787 high side current sense amplifier monitoring the current through sense resistor RS. The LT1787 is biased from the VEE supply to accommodate the common mode input range of ±10V. The sense resistor is scaled down to provide a 100mV maximum differential signal to the current sense amplifier to preserve linearity. The LT1880 amplifier provides gain and level shifting to produce a 0V to 5V output signal (2.5V DC ±5mV/mA) with up to 1kHz full-scale bandwidth. An A/D converter could then digitize this instantaneous current reading to provide digital feedback from the circuit. The LT1970 is just as easy to use as a standard operational amplifier. Basic amplification of a precision reference voltage creates a very simple bench DC power supply as shown in Figure 11. The built-in power stage produces an adjustable 0V to 25V at 4mA to 100mA of output current. Voltage and current adjustments are derived from the LT1634-5 5V reference. The output current capability is 500mA, but this supply is restricted to 100mA for power dissipation reasons. The worst-case output voltage for maximum power dissipated in the LT1970 output stage occurs if the output is shorted to ground or set to a voltage near zero. Limiting the output current to 100mA sets the maximum power dissipation to 3W. To allow the output to 1970fb 18 + U W UU ( CODE C – CODE D ≈ ±15V 1024 ) ISOURCE(MAX) = 0.5 • CODE B ≈ – 4mA TO –500mA 1024 • RS ISINK(MAX) = 0.5 • CODE A ≈ 4mA TO 500mA 1024 • RS 18V R5 3k R6 3k + 10µF 0.1µF R1 3.4k VCSRC VCSNK +IN EN VCC V+ ISRC ISNK R3 3.4k –IN COMMON TSD OUT LT1970 SENSE+ – SENSE FILTER V– VEE RS 1Ω FORCE TEST PIN LOAD SENSE 10µF 0.1µF 1970 F09 LT1970 APPLICATIO S I FOR ATIO VCC 0V TO 1V 12V VCSRC VCSNK +IN EN VCC V+ ISRC ISNK –IN COMMON TSD OUT LT1970 SENSE+ SENSE– FILTER V– VEE RG RF –12V VEE –12V R3 20k Figure 10. Sensing Output Current 30V DC R1 2.1k R2 40k R3 10k R4 10k OUTPUT VOLTAGE ADJUST CURRENT LIMIT ADJUST R5 5.49k LOAD FAULT EN VCC VCSRC VCSNK +IN V+ ISRC ISNK LT1634-5 –IN COMMON TSD OUT LT1970 SENSE+ SENSE– FILTER V– VEE –5V LTC1046 RG 2.55k RF 10.2k C2 10µF C1 10µF Figure 11. Simple Bench Power Supply 1970fb + R2 10k – + + U RS 0.2Ω RLOAD LT1787 VS – V S+ 20k BIAS –12V R1 60.4k R4 255k 12V VOUT 2.5V ± 5mV/mA 1kHz FULL CURRENT BANDWIDTH LT1880 –12V 0V TO 5V A/D 1970 F10 W UU OPTIONAL DIGITAL FEEDBACK RS 1Ω + VOUT 0V TO 25V 4mA TO 100mA C3 10µF GND 1970 F11 19 LT1970 APPLICATIO S I FOR ATIO range all the way to 0V, an LTC1046 charge pump inverter is used to develop a –5V supply. This produces a negative rail for the LT1970 which has to sink only the quiescent current of the amplifier, typically 7mA. R5 13k 18V R1 6.19k R3 23.2k 5V REF VOUT ADJUST R2 10k LT1634-5 1/2 LT1881 R12 10k – R11 10k 1/2 LT1881 R13 25.5k 15V R15 3k –15V TO TSD PIN OF +OUT R14 10.7k VCSRC VCSNK –IN –OUT CURRENT LIMIT EN VCC V+ ISRC ISNK +IN COMMON 1970 F12 10µF 0.1µF –15V Figure 12. Dual Tracking Bench Power Supply 1970fb 20 + TSD OUT LT1970 SENSE+ – SENSE FILTER – V VEE RS2 1Ω C3 10µF – R4 10k CURRENT LIMIT ADJUST + + U Using a second LT1970, a 0V to ±12V dual tracking power supply is shown in Figure 12. The midpoint of two 10k resistors connected between the + and – outputs is held at 0V by the LT1881 dual op amp servo feedback loop. To R6 18.2k 15V R7 3k R8 3k W UU + 0.1 10µF VCSRC VCSNK –IN +OUT CURRENT LIMIT EN VCC V+ ISRC ISNK THERMAL FAULT +IN COMMON TSD OUT LT1970 SENSE+ – SENSE FILTER – V VEE RS1 1Ω + C2 10µF +OUT 0V TO 12V 4mA TO 150mA –15V C1 1µF R9 10k 1% + 15V OPTIONAL SYMMETRY ADJUST 100Ω GROUND R10 10k 1% –OUT 0V TO –12V 4mA TO 150mA LT1970 APPLICATIO S I FOR ATIO maintain 0V, both outputs must be equal and opposite in polarity, thus they track each other. If one output reaches current limit and drops in voltage, the other output follows to maintain a symmetrical + and – voltage across a common load. Again, the output current limit is less than the full capability of the LT1970 due to thermal reasons. Separate current limit indicators are used on each LT1970 because one output only sources current and the other only sinks current. Both devices can share the same thermal shutdown indicator, as the output flags can be OR’ed together. Another simple linear power amplifier circuit is shown in Figure 13. This uses the LT1970 as a linear driver of a DC motor with speed control. The ability to source and sink the same amount of output current provides for bidirectional rotation of the motor. Speed control is managed by sensing the output of a tachometer built on to the motor. A typical feedback signal of 3V/1000rpm is compared with OV TO 5V TORQUE/STALL CURRENT CONTROL VCSRC VCSNK +IN –IN COMMON 15V R1 1.2k REVERSE R4 49.9k FORWARD R3 1.2k –15V R2 10k Figure 13. Simple Bidirectional DC Motor Speed Controller U the desired speed-set input voltage. Because the LT1970 is unity-gain stable, it can be configured as an integrator to force whatever voltage across the motor as necessary to match the feedback speed signal with the set input signal. Additionally, the current limit of the amplifier can be adjusted to control the torque and stall current of the motor. For reliability, a feedback scheme similar to that shown in Figure 4 can be used. Assuming that a stalled rotor will generate a current limit condition, the stall current limit can be significantly reduced to prevent excessive power dissipation in the motor windings. For motor speed control without using a tachometer, the circuit in Figure 14 shows an approach. Using the enable feature of the LT1970, the drive to the motor can be removed periodically. With no drive applied, the spinning motor presents a back EMF voltage proportional to its rotational speed. The LT1782 is a tiny rail-to-rail amplifier 15V EN VCC V+ ISRC ISNK TSD OUT LT1970 SENSE+ – SENSE FILTER V– VEE RS 1Ω 12V DC MOTOR GND C1 1µF –15V R5 49.9k TACH FEEDBACK 3V/1000rpm 1970 F13 W UU 1970fb 21 LT1970 APPLICATIO S I FOR ATIO OV TO 5V TORQUE/STALL CURRENT CONTROL FWD MOTOR SPEED CONTROL 0V REV R1 10k R2 20k 5V VCSRC VCSNK +IN VCC V+ ISRC ISNK TSD OUT LT1970 SENSE+ – SENSE FILTER – V VEE C1 4.7µF R4 100k 12V R5 120k 12V STOP –IN EN COM R14 10k 1/2 LT1638 100Ω LT1782 C2 SHDN 0.01µF –12V –12V R7 10k R8 20k R13 10k 12V R12 10k 1/2 LT1638 D1 R10 82.5k 1N4148 D2 R11 9.09k 1N4148 –12V C3 0.1µF Figure 14. Simple Bidirectional DC Motor Speed Controller Without a Tachometer with a shutdown pin. The amplifier is enabled during this interval to sample the back EMF voltage across the motor. This voltage is then buffered by one-half of an LT1638 dual op amp and used to provide the feedback to the LT1970 integrator. When re-enabled the LT1970 will adjust the drive to the motor until the speed feedback voltage, compared to the speed-set input voltage, settles the output to a fixed value. A 0V to 5V signal for the motor speed input controls both rotational speed and direction. The other half of the LT1638 is used as a simple pulse oscillator to control the periodic sampling of the motor back EMF. 22 – + – + U 15V R3 2k FAULT/STALL RS 1Ω 12V DC MOTOR –15V W UU + – R9 20k 1970 F14 1970fb LT1970 PACKAGE DESCRIPTIO 4.95 (.195) 6.60 ± 0.10 4.50 ± 0.10 SEE NOTE 4 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663, Exposed Pad Variation CA) 6.40 – 6.60* (.252 – .260) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 2.74 (.108) 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 1.20 (.047) MAX 0° – 8° 6.40 2.74 (.252) (.108) BSC 0.25 REF 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 1970fb 23 LT1970 APPLICATIO S I FOR ATIO Figure 15 shows how easy it is to boost the output current of the LT1970. This ±5A power stage uses complementary external N- and P-channel MOSFETs to provide the additional current. The output stage power supply inputs, V+ and V–, are used to provide gate drive as needed. With higher output currents, the sense resistor RCS, is reduced in value to maintain the same easy current limit control. This Class B power stage is intended for DC and low frequency,