LT8228
Bidirectional Synchronous
100V Buck/Boost Controller with Reverse Supply,
Reverse Current and Fault Protection
FEATURES
DESCRIPTION
Bidirectional Voltage or Current Regulation
n Bidirectional Reverse Current Protection
n Input and Output Negative Voltage Protection to –60V
n Bidirectional Inrush Current Limit and Boost Output
Short Protection
n Switching MOSFET Short Detection and Protection
n 10V Gate Drive
n Wide Input and Output Voltage Range Up to 100V
n Feedback Voltage Tolerance: ±1.0% Over Temperature
n Bidirectional Programmable Current Regulation and
Monitoring
n Extensive Self-Test, Diagnostics and Fault Reporting
n Programmable Fixed or Synchronizable Switching
Frequency: 80kHz to 600kHz
n Programmable Soft-Start and Dynamic Current Limit
n Masterless, Fault Tolerant Current Sharing
The LT®8228 is a 100V bidirectional constant-current or
constant-voltage synchronous buck or boost controller
with independent compensation network. The direction of
the power flow is automatically determined by the LT8228
or externally controlled. The input and output protection MOSFETs protect against negative voltages, control
inrush currents and provide isolation between terminals
under fault conditions such as switching MOSFET shorts.
In buck mode, the protection MOSFETs at the V1 terminal prevents reverse current. In boost mode, the same
MOSFETs regulate the output inrush current and protects
itself with an adjustable timer circuit breaker.
n
The LT8228 offers bidirectional input and output current limit as well as independent current monitoring.
Masterless, fault tolerant current sharing allows any
LT8228 in parallel to be added or subtracted while maintaining current sharing accuracy. Internal and external
fault diagnostics and reporting are available via the FAULT
and REPORT pins. The LT8228 is available in a 38-lead
TSSOP package.
APPLICATIONS
Dual Battery Automotive and Industrial Systems
High Power System Backup and Supply Stabilization
n “N+1” Redundant, High Reliability Power Supplies
n Power Interrupt Protection System
n
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Simplified Bidirectional Battery Backup System
BOOST (48V AT 10A)
Buck and Boost Mode Transitions
2mΩ
V1
SUPPLY
24V TO
54V
IL
20A/DIV
10µH
DRVCC
SNS1P
TG BST
SW BG
SNS2P
V2
BATTERY
14V
DS2
DS1
DG2
50µs/DIV
8228 TA01b
µC VDD
LT8228
BIAS
IL
20A/DIV
FAULT
V2
DRVCC
DRXN
2V/DIV
SNS2N
V1D
DG1
V1
SNS1N
BUCK (14V AT 40A)
2mΩ
REPORT
GND
DRXN
8228 TA01a
µC I/O
DRXN
2V/DIV
100µs/DIV
8228 TA1c
Rev. 0
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1
LT8228
TABLE OF CONTENTS
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 3
Order Information........................................... 3
Pin Configuration........................................... 3
Electrical Characteristics.................................. 4
Typical Performance Characteristics.................... 9
Buck Efficiency and Operation................................... 9
Typical Performance Characteristics................... 11
Boost Efficiency and Operation................................ 11
ENABLE, Supply Current and VCC.................................... 13
SS Current, Frequency, Thresholds and Driver ....... 15
Protection MOSFET Controller................................. 15
Pin Functions............................................... 16
Block Diagram.............................................. 23
Operation................................................... 24
Overview.................................................................. 24
Buck Mode Operation.............................................. 24
Boost Mode Operation.............................................25
V1 Protection MOSFET Controller Operation ...........26
V2 Protection MOSFET Controller Operation ........... 28
Mode of Operation (DRXN)...................................... 28
Enable and Soft-Start (Enable and SS)....................29
Paralleling Multiple Controllers (ISHARE
and IGND)................................................................30
BIAS Supply and VCC Regulators............................. 31
Strong Gate Drivers................................................. 32
Frequency Selection, Spread Spectrum and PhaseLocked Loop (RT and SYNC)................................... 32
FAULT Monitoring and REPORT Feature................... 32
Applications Information................................. 33
Introduction.............................................................33
Programming the Switching Frequency...................33
Inductor Selection...................................................34
RSNS2 and RIN2 Selection for Peak Inductor
Current.....................................................................35
RSET2P Selection for V2 Output Current
Limit (Buck Mode) ..................................................36
RSET2N Selection for V2 Input Current
Limit (Boost Mode) ................................................. 37
RMON2 Selection for V2 Current Monitoring.............38
RSNS1 and RIN1 Selection.........................................38
RSET1P Selection for V1 Input Current
Limit (Buck Mode) .................................................. 39
RSET1N Selection for V1 Output Current
Limit (Boost Mode) .................................................40
RMON1 Selection for V1 Current Monitoring............. 41
Output Voltage, Input Undervoltage and Output
Overvoltage Programming....................................... 41
Power MOSFET Selection and Efficiency
Considerations......................................................... 42
Optional Schottky Diode (D2 and D3) Selection......45
Top MOSFET Driver Supply (CBST, DBST).................46
Power Path Capacitor Selection...............................46
Loop Compensation.................................................48
Inrush Current Control............................................. 49
Boost Output Short Protection and Timer...............50
FAULT Conditions..................................................... 52
Soft-Start.................................................................53
REPORT Feature.......................................................53
Paralleling Multiple LT8228s....................................56
BIAS, DRVCC, INTVCC and Power Dissipation.......... 57
Thermal Shutdown..................................................58
Pin Clearance/Creepage Consideration.................... 59
Efficiency Considerations........................................ 59
PC Board Layout Checklist...................................... 59
Design Example.......................................................60
Package Description...................................... 67
Typical Application........................................ 68
Related Parts............................................... 68
Rev. 0
2
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LT8228
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
DS1, DS2 ................................................... −60V to 100V
DG1 (Note 2) ............................ DS1 –0.3V to DS1 + 15V
DG2 (Note 3) ............................ DS2 –0.3V to DS2 + 15V
ENABLE, V1D, BIAS ................................................100V
SNS1P, SNS2P, SNS1N, SNS2N...............................100V
SNS1P – SNS1N, SNS2P – SNS2N.........................±0.3V
SW (Note 4)................................................. –5V to 100V
DRVCC (Note 5), BST – SW .......................................15V
TG, BG .............................................................. (Note 6)
INTVCC (Note 7)...........................................................4V
ISET1P, ISET1N, ISHARE ..................................... INTVCC
ISET2P, ISET2N ................................................... INTVCC
VC1, VC2, RT, SS, IMON1, IMON2 ....................... INTVCC
FB1, UV1, FB2, UV2...................................................5.5V
DRXN, SYNC, IGND, FAULT, REPORT........................5.5V
Operating Junction Temperature Range
LT8228E, I (Notes 8, 9)....................... –40°C to 125°C
LT8228H J (Notes 8, 9)....................... –40°C to 150°C
Storage Temperature Range................... –65°C to 175°C
SNS1P
1
38 DG1
SNS1N
2
37 DS1
UV1
3
36 V1D
FB1
4
35 DG2
IMON1
5
34 DS2
ISET1N
6
33 ENABLE
ISET2N
7
32 BST
VC1
8
31 TG
SS
9
VC2 10
ISET1P 11
30 SW
39
GND
29 BIAS
28 DRVCC
ISET2P 12
27 BG
IMON2 13
26 TMR
FB2 14
25 REPORT
UV2 15
24 FAULT
RT 16
23 SYNC
ISHARE 17
22 DRXN
SNS2P 18
21 INTVCC
SNS2N 19
20 IGND
FE PACKAGE
38-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 25°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8228EFE#PBF
LT8228EFE#TRPBF
LT8228FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT8228IFE#PBF
LT8228IFE#TRPBF
LT8228FE
38-Lead Plastic TSSOP
–40°C to 125°C
LT8228HFE#PBF
LT8228HFE#TRPBF
LT8228FE
38-Lead Plastic TSSOP
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
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3
LT8228
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DS1 = V1D = 48V, DS2 = BIAS = 14V, RIN1 = 1k, RIN2 = 1k, and ISHARE =
INTVCC unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
V1
V2
6
100
V
6
100
V
VBIAS
BIAS Operating Voltage Range
100
V
IQV1
DS1 Quiescent Current (Shutdown)
DS1 Quiescent Current (Not Switching)
ENABLE = 0V
ENABLE = 2V, VUV1 = VUV2 = 0V
l
10
200
45
350
µA
µA
IQV2
DS2 Quiescent Current (Shutdown)
DS2 Quiescent Current (Not Switching)
ENABLE = 0V
ENABLE = 2V, VUV1 = VUV2 = 0V
l
10
10
40
20
µA
µA
IQBIAS
BIAS Quiescent Current (Shutdown)
BIAS Quiescent Current (Not Switching)
ENABLE = 0V
ENABLE = 2V, VUV1 = VUV2 = 0V
l
4
3.7
10
5
µA
mA
ISS
Soft-Start Current (Note 10)
SS = 0V
l
9.5
10
10.5
µA
Buck Mode Input Voltage
l
Boost Mode Input Voltage
l
l
8
TYP
Threshold Voltages
ENTHRESH
ENABLE Threshold (Falling)
ENABLE Hysteresis
l
1.16
1.20
100
1.24
V
mV
UVV1
UV1 Voltage Threshold (Falling)
UV1 Hysteresis
l
1.18
1.20
100
1.22
V
mV
UVV2
UV2 Voltage Threshold (Falling)
UV2 Hysteresis
l
1.18
1.20
100
1.22
V
mV
OVV1
FB1 Over Voltage Threshold (Rising)
FB1 Over Voltage Hysteresis
l
1.28
1.30
100
1.32
V
mV
OVV2
FB2 Over Voltage Threshold (Rising)
FB2 Over Voltage Hysteresis
l
1.28
1.30
100
1.32
V
mV
DRXN
DRXN Logic Threshold (Rising)
DRXN Logic Threshold (Falling)
l
l
1.05
0.75
1.10
0.80
1.15
0.85
V
V
SYNC
SYNC Logic Threshold (Rising)
SYNC Logic Threshold (Falling)
l
l
0.65
0.95
0.80
1.10
V
V
ISHARETHRESH
ISHARE Disable Threshold (Rising)
ISHARE Disable Hysteresis
l
2.45
2.49
0.40
2.53
V
V
l
9.7
10
10.5
V
1.0
2.5
%
VCC Regulator
VDRVCC
DRVCC Regulation Voltage
12V < VBIAS < 100V
∆VDRVCC
DRVCC Load Regulation
IDRVCC = 0mA to 100mA
IDRVCCMAX
DRVCC Current Limit (Note 10)
VBIAS = 14V, VDRVCC = 8V
l
100
160
DRVCCUV
DRVCC Undervoltage Threshold (Falling)
DRVCC Undervoltage Hysteresis
l
6.1
6.35
300
6.6
V
mV
DRVCCOV
DRVCC Overvoltage Threshold (Rising)
DRVCC Overvoltage Hysteresis
l
14.6
15.1
1.0
15.6
V
V
VBIAS – VDRVCC DRVCC Dropout Voltage
VBIAS = 10V, IDRVCC = 100mA
mA
1.0
3.5
V
VINTVCC
INTVCC Regulation Voltage
l
3.8
4.0
4.3
V
INTVCCUV
INTVCC Undervoltage Threshold (Falling)
INTVCC Undervoltage Hysteresis
l
3.45
3.6
0.2
3.75
V
V
INTVCCOV
INTVCC Overvoltage Threshold (Rising)
INTVCC Overvoltage Hysteresis
l
4.50
4.7
0.5
4.85
V
V
l
Rev. 0
4
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LT8228
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DS1 = V1D = 48V, DS2 = BIAS = 14V, RIN1 = 1k, RIN2 = 1k, and ISHARE =
INTVCC unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
8.0
8.0
8.0
10
12.5
V
V
V
Protection MOSFET at V1 Terminal Controller
∆VDG1
DG1 Gate Drive
(DG1 – DS1)
VDS1 = 6V, VDS2 = 0V, BIAS = 8V
VDS1 = 0V, VDS2 = 0V, BIAS = 8V
l
l
l
IDG1UP
DG1 Pull-Up Current (Note 10)
VDG1 = VDS1 = 48V, VDG2 = VDS2 =14V
l
7
10
13
μA
IDG1DOWN
DG1 Pull-Down Current (Note 10)
VDG1 – VDS1 = 5V
l
–110
–80
–60
mA
V1NEGATIVE
Negative DS1 Voltage Threshold for DG1 Off
VDG1 = 0V, IDG1 = –1mA
l
–2.2
–1.7
IREVERSEV1
DS1 Reverse Leakage Current
VDS1 = –55V
0.6
mA
VSET1NMAX
ISET1N Boost Output Inrush limit in Boost
Mode (Note 11)
VDS1 = 8V, VDG1 – VDS1 = 2.5V, IDG1 = 0, DRXN l
= 0V, SS > 1.5V (Boost)
1.35
1.40
1.45
V
VDS2 = 14V, DRXN = 2V (Buck)
l
–5.0
–3.0
–1.0
mV
l
3.8
4.5
0.5
5.0
V
V
VDS1 = 0V, VDS2 = 6V, BIAS = 8V
VDS1 = 0V, VDS2 = 0V, BIAS = 8V
l
l
l
8.0
8.0
8.0
10
12.5
V
V
V
VSNS1P,1N(RCUR) Buck Mode Reverse Current Threshold for
DG1 Off (VSNS1P,SNSN1N)
VDG1UV
DG1 Undervoltage Threshold (Falling)
DG1 Undervoltage Hysteresis
V
Protection MOSFET at V2 Terminal Controller
∆VDG2
DG2 Gate Drive
(DG2 – DS2)
IDG2UP
DG2 Pull-Up Current (Note 10)
VDG1 = VDS1 = 48V, VDG2 = VDS2 = 14V
l
7
10
13
µA
IDG2DOWN
DG2 Pull-Down Current (Note 10)
VDG2 – VDS2 = 5V
l
–110
–80
–60
mA
V2NEGATIVE
Negative DS2 Voltage Threshold for DG2 Off
VDG2 = 0V, IDG2 = –1mA
l
–2.2
–1.7
IREVERSEV2
DS2 Reverse Leakage Current
VDS2 = –55V
0.6
mA
VDG2UV
DG2 Undervoltage Threshold (Falling)
DG2 Undervoltage Hysteresis
l
3.8
4.4
0.5
5.0
V
V
V
Current Sense Amplifiers (Note 12)
IB1
SNS1P, SNS1N Bias Current
2.5V < VCM1 < 100V
VCM1 = 0V
l
l
–105
35
–90
50
–70
70
µA
µA
IISET1P
ISET1P Output Current
2.5V < VCM1 < 100V
VRSNS1 = 1mV
VRSNS1 = 25mV
VRSNS1 = 50mV
VRSNS1 = 80mV
l
l
l
l
0.0
24.0
48.5
78.0
1.0
25.0
50.0
80.0
2.2
26.0
51.5
82.0
µA
µA
µA
µA
IISET1N
ISET1N Output Current
2.5V < VCM1 < 100V
VRSNS1 = –1mV
VRSNS1 = –25mV
VRSNS1 = –50mV
VRSNS1 = –80mV
l
l
l
l
0.0
24.0
48.5
78.0
1.0
25.0
50.0
80.0
2.2
26.0
51.5
82.0
µA
µA
µA
µA
IIMON1
IMON1 Output Current
2.5V < VCM1 < 100V
VRSNS1 = –80mV
VRSNS1 = –50mV
VRSNS1 = –25mV
VRSNS1 = –1mV
VRSNS1 = 1mV
VRSNS1 = 25mV
VRSNS1 = 50mV
VRSNS1 = 80mV
l
l
l
l
l
l
l
l
78.0
48.5
24.0
0.0
0.0
24.0
48.5
78.0
80
50.0
25.0
1.0
1.0
25.0
50.0
80.0
82.0
51.5
26.0
2.2
2.2
26.0
51.5
82.0
µA
µA
µA
µA
µA
µA
µA
µA
|VRSNS1| = 1mV
|VRSNS1| = 25mV
|VRSNS1| = 50mV
|VRSNS1| = 80mV
l
l
l
l
0.0
22.5
47.5
76.0
1.0
25.0
50.0
80.0
3.0
27.5
52.5
84.0
µA
µA
µA
µA
IISET1P, IISET1N, Output Current, VCM1 < 2.5V
IMON1
Rev. 0
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5
LT8228
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DS1 = V1D = 48V, DS2 = BIAS = 14V, RIN1 = 1k, RIN2 = 1k, and ISHARE =
INTVCC unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IB2
SNS2P, SNS2N Bias Current
2.5V < VCM2 < 100V
VCM2 = 0V
l
l
–105
35
–90
50
–70
70
µA
µA
IISET2P
ISET2P Output Current
2.5V < VCM2 < 100V
VRSNS2 = 1mV
VRSNS2 = 25mV
VRSNS2 = 50mV
VRSNS2 = 80mV
l
l
l
l
0.0
24.0
48.5
78.0
1.0
25.0
50.0
80.0
2.2
26.0
51.5
82.0
µA
µA
µA
µA
IISET2N
ISET2N Output Current
2.5V < VCM2 < 100V
VRSNS2 = –1mV
VRSNS2 = –25mV
VRSNS2 = –50mV
VRSNS2 = –80mV
l
l
l
l
0.0
24.0
48.5
78.0
1.0
25.0
50.0
80.0
2.2
26.0
51.5
82.0
µA
µA
µA
µA
IIMON2
IMON2 Output Current
2.5V < VCM2 < 100V
VRSNS2 = –80mV
VRSNS2 = –50mV
VRSNS2 = –25mV
VRSNS2 = –1mV
VRSNS2 = 1mV
VRSNS2 = 25mV
VRSNS2 = 50mV
VRSNS2 = 80mV
l
l
l
l
l
l
l
l
78.0
48.5
24.0
0.0
0.0
24.0
48.5
78.0
80.0
50.0
25.0
1.0
1.0
25.0
50.0
80.0
82.0
51.5
26.0
2.2
2.2
26.0
51.5
82.0
µA
µA
µA
µA
µA
µA
µA
µA
IISET2P, IISET2N,
IMON2,
Output Current, VCM1 < 2.5V
|VRSNS1| = 1mV
|VRSNS1| = 25mV
|VRSNS1| = 50mV
|VRSNS1| = 80mV
l
l
l
l
0.0
22.5
47.5
76.0
1.0
25.0
50.0
80.0
3.0
27.5
52.5
84.0
µA
µA
µA
µA
IISHARE
ISHARE Output Current, ISHARE = 0V
DRXN = 0V (Boost Mode),
2.5V < VCM1 < 100V
VRSNS1 = –1mV
VRSNS1 = –25mV
VRSNS1 = –50mV
VRSNS1 = –80mV
l
l
l
l
0.0
24.0
48.5
78.0
1.0
25.0
50.0
80.0
2.2
26.0
51.0
82.0
µA
µA
µA
µA
ISHARE Output Current, ISHARE = 0V
DRXN = 2V (Buck Mode),
2.5V < VCM1 < 100V
VRSNS2 = 1mV
VRSNS2 = 25mV
VRSNS2 = 50mV
VRSNS2 = 80mV
l
l
l
l
0.0
24.0
48.5
78.0
1.0
25.0
50.0
80.0
2.2
26.0
51.0
82.0
µA
µA
µA
µA
ISHARE Output Current, ISHARE = 0V
DRXN = 0V (Boost Mode),
VCM1 < 2.5V
VRSNS1 = –1mV
VRSNS1 = –25mV
VRSNS1 = –50mV
VRSNS1 = –80mV
l
l
l
l
0.0
22.5
47.5
76.0
1.0
25.0
50.0
80.0
3.0
27.5
52.5
84.0
µA
µA
µA
µA
ISHARE Output Current, ISHARE = 0V
DRXN = 2V (Buck Mode),
VCM2 < 2.5V
VRSNS2 = 1mV
VRSNS2 = 25mV
VRSNS2 = 50mV
VRSNS2 = 80mV
l
l
l
l
0.0
22.5
47.5
76.0
1.0
25.0
50.0
80.0
3.0
27.5
52.5
84.0
µA
µA
µA
µA
1.198
1.210
1.222
V
10
50
Buck Voltage and Current Regulation
VFB2
FB2 Regulation Voltage (Note 13)
l
l
IFB2
FB2 Pin Bias Current
gmFB1
V2 Error Amplifier Transconductance
VISET1P
ISET1P Regulation Voltage (Note 14)
gmISET1P
ISET1P Error Amplifier Transconductance
VISET2P
ISET2P Regulation Voltage (Note 14)
gmISET2P
ISET2P Error Amplifier Transconductance
RVC2
VC2 Output Impedance
∆ISET1P
Buck Mode Input Current (ISET1P) Regulation RSNS1 = 5Ω, RSET1P = 24.3k, VCM1 = 48V,
Error (Note 15)
DRXN = 2V (Buck Mode)
0.8
l
1.198
1.210
l
1.198
1.210
1.222
0.8
V
ms
1000
0
V
ms
1.222
0.8
l
nA
ms
kΩ
±2.5
%
Rev. 0
6
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LT8228
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DS1 = V1D = 48V, DS2 = BIAS = 14V, RIN1 = 1k, RIN2 = 1k, and ISHARE =
INTVCC unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
∆ISET2P
Buck Mode Output Current (ISET2P)
Regulation Error (Note 15)
RSNS2 = 5Ω, RSET2P = 24.3k, VCM2 = 14V,
DRXN = 2V (Buck Mode)
∆ISHAREBUCK
Buck Mode Output Current Sharing Error
(Note 16)
RSNS2 = 5Ω, RSET2P = 24.3K, VCM2 = 14V,
DRXN = 2V (Buck Mode), ISHARE = 0.605V
MIN
TYP
MAX
UNITS
l
0
±2.5
%
l
0
±4
%
1.210
1.222
V
10
50
nA
Boost Voltage and Current Regulation
VFB1
FB1 Regulation Voltage (Note 13)
l
IFB1
FB1 Pin Bias Current
l
gmFB1
V1 Error Amplifier Transconductance
VISET1N
ISET1N Regulation Voltage (Note 14)
gmISET1N
ISET1N Error Amplifier Transconductance
VISET2N
ISET2N Regulation Voltage (Note 14)
gmISET2N
ISET2N Error Amplifier Transconductance
1.198
0.8
l
1.198
1.210
ms
1.222
0.8
l
1.198
1.210
V
ms
1.222
0.8
V
ms
RVC1
VC1 Output Impedance
∆ISET1N
Boost Mode Output Current (ISET1N)
Regulation Error (Note 15)
RSNS1 = 5Ω, RSET1N = 24.3k, VCM1 = 48V,
DRXN = 2V (Buck Mode)
l
1000
0
±2.5
kΩ
%
∆ISET2N
Boost Mode Input Current (ISET2N)
Regulation Error (Note 15)
RSNS2 = 5Ω, RSET2N = 24.3k, VCM2 = 14V,
DRXN = 2V (Buck Mode)
l
0
±2.5
%
∆ISHAREBOOST
Boost Mode Output Current Sharing Error
(Note 16)
RSNS1 = 5Ω, RSET1N = 24.3k, VCM1 = 14V,
DRXN = 2V (Buck Mode), ISHARE = 0.605V
l
0
±4
%
Switching MOSFET Driver
RTG
Pull-Up On-Resistance
Pull-Down On-Resistance
2.5
1.0
Ω
Ω
RBG
Pull-Up On-Resistance
Pull-Down On-Resistance
2.5
1.0
Ω
Ω
tRTG
TG Rise Time
CLOAD = 6800pF (10% to 90%)
50
ns
tFTG
TG Fall Time
CLOAD = 6800pF (10% to 90%)
20
ns
tRBG
BG Rise Time
CLOAD = 6800pF (10% to 90%)
50
ns
tFBG
BG Fall Time
CLOAD = 6800pF (10% to 90%)
20
ns
tDTGBG
TG Off to BG On Delay
CLOAD = 6800pF Each Driver (50% to 50%)
50
ns
tDBGTG
BG Off to TG On Delay
CLOAD = 6800pF Each Driver (50% to 50%)
50
ns
tONBUCK
Min TG On-Time in Buck Mode
DRXN = 2V
150
ns
tONBOOST
Min BG On-Time in Boost Mode
DRXN = 0V
150
ns
tOFFBOOST
Min BG Off-Time in Boost Mode
DRXN = 0V
200
ns
tDTGBG,V1D = 48V TG Off to BG On Delay, V1D = 48V (Note 17)
60
ns
tDTGBG,V1D =100V TG Off to BG On Delay, V1D = 100V (Note 17)
60
ns
PLL and Oscillator
fPROG
Programmable Frequency
RRT = 124k
RRT = 100k
RRT = 14k
l
l
l
75
95
540
fSYNC
Synchronizable Frequency
l
fSPSC,MAX
Spread Spectrum Maximum Frequency
RRT = 100k, fPROG = 100kHz
l
82
fSPSC,MIN
Spread Spectrum Maximum Frequency
RRT = 100k, fPROG = 100kHz
l
65
80
100
600
85
105
660
700
kHz
130
145
kHz
80
kHz
kHz
kHz
kHz
Rev. 0
For more information www.analog.com
7
LT8228
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DS1 = V1D = 48V, DS2 = BIAS = 14V, RIN1 = 1k, RIN2 = 1k, and ISHARE =
INTVCC unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
VFAULT
FAULT Low Voltage
IFAULT = 2mA (Fault Condition)
TYP
MAX
UNITS
0.2
0.35
V
1
µA
0.2
0.35
V
1
µA
Logic
l
ILKGFAULT
FAULT Pin Leakage Current
VREPORT
REPORT Low Voltage
ILKGREPORT
REPORT Pin Leakage Current
IPULLDRXN
DRXN Pin Pull-Down Current (Boost Mode)
ILKGDRXN
DRXN Pin Leakage Current (Buck Mode)
l
RIGND
IGND Pin Resistance to GND (Sharing Enabled)
l
l
IREPORT = 2mA
l
l
UV1 = 0V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for an extended period may affect device
reliability and lifetime.
Note 2: An internal clamp limits the DG1 pin to a minimum of 10V above
DS1. Driving this pin to voltages beyond this clamp may damage the device.
Note 3: An internal clamp limits the DG2 pin to a minimum of 10V above
DS2. Driving this pin to voltages beyond this clamp may damage the device.
Note 4: Negative voltages on the SW pin are limited in an application by the
body diodes of the external NMOS device M3, or parallel Schottky diodes
when present. The SW pin is tolerant to these negative voltages in excess of
one diode drop below ground down to –5V, guaranteed by design.
Note 5: No external loading is allowed on this pin other than for charging
the boost capacitor, CBST.
Note 6: Do not apply a voltage or current sources to these pins. They must be
connected to capacitive loads only, otherwise permanent damage may occur.
Note 7: INTVCC cannot be externally driven. No external loading is allowed
on this pin other than connecting to the ISHARE pin and the pull-up
resistor for DRXN whose value should not be less than 50k.
Note 8: The LT8228 is tested and specified under pulse load conditions
such that TJ ≅ TA. The LT8228E is 100% production tested at TA = 25°C and
performance is guaranteed from 0°C to 125°C. Performance at –40°C to
125°C is assured by design, characterization and correlation with statistical
process controls. The LT8228I is guaranteed over the full –40°C to 125°C
operating junction temperature range. The LT8228H is guaranteed over the
full –40°C to 150°C operating junction temperature range.
Note 9: The LT8228 includes over-temperature protection that is intended
to protect the device during overload conditions. When the junction
temperature exceeds 150°C, overtemperature protection is activated.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability or permanently damage the device.
Note 10: Current convention. Positive current is defined as current flowing
out of the pin.
Note 11: There is a direct conduction path from V2 to V1D through V2
protection MOSFET M4 and the body diode of TG MOSFET M2. In Boost
mode, this specification limits the current into V1 from V1D through DG1.
l
100
120
120
µA
1
µA
200
Ω
Note 12: IB1 is defined as the average of the input bias current to the
SNS1P and SNS1N pins. Likewise, IB2 is defined as the average of the
input bias current to the SNS2P and SNS2N pins. The LT8228 is tested
and specified for these conditions with the voltages at the SNS1P, SNS1N,
SNS2P and SNS2N pins applied through 1k input gain resistors. VRSNS1
represents the voltage between the input gain resistors for the SNS1P and
SNS1N pins. Likewise, VRSNS2 represents the voltage between the input
gain resistors for the SNS2P and SNS2N pins. VCM1 and VCM2 are the
common mode voltages at the input gain resistors RIN1 and RIN2.
Note 13: The LT8228 is tested in a feedback loop that servos the output of
the error amplifier, VC, to the internal reference voltage by tying the FB pin
to the VC pin with all ISET pins tied to ground.
Note 14: The LT8228 is tested in a feedback loop that servos the output
of the error amplifier VC to the internal reference voltage by tying the ISET
pin under test to the VC pin with the FB and other ISET pins tied to ground.
Note 15: Current regulation error is the difference between the measured
current through the sense resistor and the programmed current set by:
(1) the sense resistor RSNS, (2) the input gain resistors RIN and (3) the
ISET resistor RSET. The LT8228 is tested in a feedback loop that regulates
a current through RSNS by tying the VC pin to the gate of a grounded
N-channel MOSFET whose drain is connected to RSNS. The error due to
the SNS pin bias current across RSNS is subtracted from this specification.
This specification is tested with no ripple voltage on RSNS.
Note 16: Current sharing error is the difference between the current
through the sense resistor RSNS and the average current defined by the
ISHARE pin. The voltage on ISHARE represents the average ISHARE
currents of multiple ideal LT8228s in parallel. The LT8228 is tested in a
feedback loop that regulates a current through RSNS by tying the VC pin
to the gate of a grounded N-channel MOSFET whose drain is connected
to RSNS. The current sharing loop servos the ISET1N pin voltage in boost
mode or the ISET2P pin voltage in buck mode to the ISHARE pin voltage
of 600mV. The error due to the SNS pin bias current across RSNS is
subtracted from this specification. This specification is tested with no
ripple voltage on RSNS.
Note 17: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels. Rise and fall times are assured by
design, characterization and correlation with statistical process controls.
Rev. 0
8
For more information www.analog.com
LT8228
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
BUCK EFFICIENCY AND OPERATION
90
100
EFFICIENCY
80
30
70
60
20
50
40
30
10
20
10
Efficiency vs V1 (Buck)
(V2 = 14V, IV2 = 20A)
Load Step (Buck)
LOAD
10A/DIV
98
POWER LOSS (W)
EFFICIENCY (%)
40
EFFICIENCY (%)
100
Efficiency vs V2 Current (Buck)
(V1 = 48V, V2 = 14V)
96
V2 (AC)
500mV/DIV
94
IL
10A/DIV
92
0
0.1
0
100
1
10
LOAD CURRENT (A)
90
24
28
32
36 40 44 48
INPUT VOLTAGE (V)
8228 G01
52
56
8228 G02
Inductor Current at Light Load
(Buck)
Start-Up at Prebiased Load
(Buck)
Soft Start-Up (Buck)
V2
5V/DIV
V2
5V/DIV
IL
500mA/DIV
IL
5A/DIV
SS
100mV/DIV
4µs/DIV
8228 G04
400µs/DIV
Output Higher Than Input, V2 > V1
(Reverse Current Protection, Buck)
8228 G05
400µs/DIV
Short-Circuit/Voltage and Current
Regulation Transition (Buck)
V2
5V/DIV
V1
10V/DIV
8228 G06
ISET2P and IMON2
Measurement Accuracy
12
DG1
10V/DIV
8228 G03
200µs/DIV
POWER LOSS
ISET2P
IMON2
10
8
V2
10V/DIV
IL
20A/DIV
ERROR (%)
IL
20A/DIV
ISET2P
1V/DIV
2ms/DIV
8228 G07
6
4
2
400µs/DIV
8228 G08
0
–2
0
10 20 30 40 50 60 70 80 90 100
VRSNS2 (mV)
8228 G09
Rev. 0
For more information www.analog.com
9
LT8228
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
BUCK EFFICIENCY AND OPERATION
ISET1P and IMON1
Measurement Accuracy
Peak Inductor Current vs V1
(Buck)
8
BG MOSFET Short in Regulation
(Buck)
60
ISET1P
IMON1
SW
25V/DIV
50
6
IL,PEAK
ERROR (%)
40
4
2
IL
50A/DIV
DG2
10V/DIV
30
V2
10V/DIV
20
0
–2
10
0
5
10
15
20
25
VRSNS1 (mV)
30
35
0
40
100µs/DIV
28
32
36
44
48
52
56
V1 (V)
8228 G10
TG MOSFET Short in Regulation
(Buck)
SW
25V/DIV
40
60
8228 G11
Reverse Battery Insertion at V2
(LT8228 Disabled)
Reverse Battery Insertion at V2
in Regulation
IL
20A/DIV
V2D
10V/DIV
DG2
10V/DIV
V2
10V/DIV
V2D
5V/DIV
DG2
5V/DIV
V2
5V/DIV
IL
50A/DIV
DG2
10V/DIV
8228 G12
V2
10V/DIV
100µs/DIV
8228 G13
8228 G14
100µs/DIV
Multiphase Operation (Buck)
Phase Turn-On
8228 G15
Multiphase Operation (Buck)
Phase Turn-Off
V2
5V/DIV
V2
5V/DIV
PHASE 1 IL
10A/DIV
PHASE 1 IL
10A/DIV
PHASE 2 IL
10A/DIV
PHASE 2 IL
10A/DIV
1ms/DIV
100µs/DIV
8228 G16
100µs/DIV
8228 G17
Rev. 0
10
For more information www.analog.com
LT8228
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
BOOST EFFICIENCY AND OPERATION
Efficiency vs V1 Current (Boost)
(V1 = 48V, V2 = 14V)
100
20
100
90
Load Step (Boost)
LOAD
4A/DIV
EFFICIENCY
98
80
60
10
50
40
30
POWER LOSS
20
EFFICIENCY (%)
70
POWER LOSS (W)
EFFICIENCY (%)
Efficiency vs V2 (Boost)
(V1 = 48V, IV1 = 5A)
96
V1 (AC)
5V/DIV
94
IL
10A/DIV
92
10
0
0.1
1
LOAD CURRENT (A)
10
0
90
8
8228 G18T
Inductor Current at Light Load
(Boost)
10
12
14
16
INPUT VOLTAGE, V2 (V)
18
20
8228 G19
Soft Start-Up (Boost)
Output Short (Boost, Start-Up)
V1D
10V/DIV
V1D
20V/DIV
V1
20V/DIV
SS
2A/DIV
IL
1000mA/DIV
ISET1N
1V/DIV
TMR
1V/DIV
IL
5A/DIV
4µs/DIV
8228 G21
10ms/DIV
Output Short-Circuit Transient
(Boost)/TMR Pin Operation
8228 G22
100ms/DIV
Voltage and Current Regulation
Transition (Boost)
V1
20V/DIV
FB1
1V/DIV
V1
20V/DIV
ISET2N
IMON2
10
8
ERROR (%)
ISET2N
1V/DIV
IL
20A/DIV
IL
25A/DIV
TMR
2V/DIV
8228 G23
ISET2N and IMON2
Measurement Accuracy
12
V1D
20V/DIV
8228 G20
1ms/DIV
6
4
2
100ms/DIV
8228 G24
1ms/DIV
8228 G25
0
–2
0
10 20 30 40 50 60 70 80 90 100
VRSNS2 (–mV)
8228 G26
Rev. 0
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11
LT8228
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
BOOST EFFICIENCY AND OPERATION
ISET1N and IMON1
Measurement Accuracy
8
Maximum Inductor Current
vs V2 (Boost)
60
ISET1N
IMON1
SW
25V/DIV
50
6
IL
60A/DIV
DG2
10V/DIV
40
4
IL,PEAK
ERROR (%)
BG MOSFET Short in Regulation
(Boost)
2
30
V2
10V/DIV
20
0
–2
10
0
4
8
12
VRSNS1 (–mV)
16
20
0
8
SW
25V/DIV
IL
60A/DIV
DG2
10V/DIV
V2
10V/DIV
10
12
14
16
18
V2 (V)
8228 G27
TG MOSFET Short in Regulation
(Boost)
100µs/DIV
100µs/DIV
20
8228 G28
Multiphase Operation Boost
Phase Turn-On
Multiphase Operation Boost
Phase Turn-Off
V2
20V/DIV
V1
20A/DIV
PHASE 1 IL
10A/DIV
PHASE 1 IL
10A/DIV
PHASE 2 IL
10A/DIV
PHASE 2 IL
10A/DIV
8228 G30
8228 G31
4ms/DIV
Auto DRXN: Buck to Boost
Transition (Input Undervoltage)
V1
20A/DIV
V2
10V/DIV
8228 G29
400µs/DIV
8228 G32
Auto DRXN: Buck to Boost
Transition (Output Overvoltage)
FAULT
2V/DIV
IL
20A/DIV
IL
50A/DIV
DRXN
3V/DIV
DRXN
3V/DIV
400µs/DIV
LT8228 G33
2ms/DIV
8228 G34
Rev. 0
12
For more information www.analog.com
LT8228
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
BOOST EFFICIENCY AND OPERATION
Auto DRXN: Boost to Buck
Transition (Output Overvoltage)
Auto DRXN: Boost to Buck
Transition (Input Undervoltage)
V1
10V/DIV
FAULT
2V/DIV
V2
5V/DIV
IL
25A/DIV
IL
25A/DIV
DRXN
3V/DIV
DRXN
3V/DIV
8228 G35
200µs/DIV
2ms/DIV
8228 G36
ENABLE, SUPPLY CURRENT AND VCC
Shutdown Current vs Temperature
(V1 = 48V, V2 = 14V, BIAS = 14V)
200
–40
25
125
150
180
24
16
8
8
DRVCC CURRENT LIMIT (mA)
32
DRVCC Current Limit vs BIAS
(Temperature = –40°C, 25°C, 150°C)
10
IQV1
IQV2
IQBIAS
QUISCENT CURRENT (μA)
QUISCENT CURRENT (μA)
40
Shutdown Current vs Input
Voltage (Input = V1, V2, BIAS)
IQV1
IQV2
IQBIAS
6
4
2
160
140
120
100
80
60
40
20
0
–50 –25
0
25
50
75
100 125 150
TEMPERATURE (°C)
8228 G37
0
0
20
40
60
80
100
0
0
10 20 30 40 50 60 70 80 90 100
BIAS (V)
INPUT VOLTAGE (V)
8228 G38
8228 G39
Rev. 0
For more information www.analog.com
13
LT8228
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
REGULATION AND CURRENT SENSE
CSA1/CSA2 Input Bias Current
vs Temperature
–80
100
IB1
IB2
–82
18
60
16
–86
40
14
–88
20
–92
0
–20
–94
–40
–96
–60
–98
–80
0
25
50
75
–100
100 125 150
IB (mA)
–90
12
2
0
0
–2
–20
10 20 30 40 50 60 70 80 90 100
VCM (V)
ERROR (%)
1
0
–1
1
1.5
2
2.5
2
2
1
1
0
RIN1 (kΩ)
2
1
1.5
2
2.5
RIN1 (kΩ)
ISET2N Gain Error vs RIN2
(VCM2 > 2.5V, Output: 10μA,
25μA and 50μA)
2
10μA
25μA
50μA
1
1.5
2
RIN2 (kΩ)
2.5
3
8228 G46
1.5
2
2.5
IMON2 Gain Error vs RIN2
(VCM2 > 2.5V, Output: 10μA,
25μA and 50μA)
3
8228 G45
2
1
0
–2
0.5
1
RIN1 (kΩ)
10μA
25μA
50μA
–1
–1
8228 G42
0
8228 G44
ERROR (%)
ERROR (%)
0
0
10μA (P)
25μA (P)
50μA (P)
10μA (N)
25μA (N)
50μA (N)
–2
0.5
3
1
1
–2
0.5
10μA
25μA
50μA
8228 G43
ISET2P Gain Error vs RIN2
(VCM2 > 2.5V, Output: 10μA,
25μA and 50μA)
–4
–1
–2
0.5
3
–8
IMON1 Gain Error vs RIN1
(VCM1 > 2.5V, Output: 10μA,
25μA and 50μA)
–1
–2
0.5
–12
VCM (V)
ISET1N Gain Error vs RIN1
(VCM1 > 2.5V, Output: 10μA,
25μA and 50μA)
10μA
25μA
50μA
–16
8228 G41
ERROR (%)
2
8
4
8228 G40
ISET1P Gain Error vs RIN1
(VCM1 > 2.5V, Output: 10μA,
25μA and 50μA)
10
6
TEMPERATURE (°C)
ERROR (%)
20
–84
–100
–50 –25
ERROR (%)
CSA1/CSA2 Input Bias Current vs
VCM (Reverse Battery Fault)
IB1
IB2
80
IB1, IB2 (μA)
IB1, IB2 (μA)
CSA1/CSA2 Input Bias Current
vs VCM
0
–1
1
1.5
2
RIN2 (kΩ)
2.5
3
8228 G47
–2
0.5
10μA (P)
25μA (P)
50μA (P)
10μA (N)
25μA (N)
50μA (N)
1
1.5
2
RIN2 (kΩ)
2.5
3
8228 G48
Rev. 0
14
For more information www.analog.com
LT8228
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
SS CURRENT, FREQUENCY, THRESHOLDS AND DRIVER
TG Pull-Up/Down Resistance vs
Temperature
4
BG Pull-Up/Down Resistance vs
Temperature
4
RPULL–DOWN
RPULL–UP
3
RESISTANCE (Ω)
RESISTANCE (Ω)
3
RPULL–DOWN
RPULL_UP
2
1
2
1
0
–50 –25
0
25
50
75
0
–50 –25
100 125 150
TEMPERATURE (°C)
0
25
50
75
100 125 150
TEMPERATURE (°C)
8228 G49
8228 G50
PROTECTION MOSFET CONTROLLER
DG1/DG2 Pull-Up Current vs BIAS
(DS1 = 0V, DS2 = 0V)
DG1/DG2 vs BIAS
(DS1 = 0V, DS2 = 0V)
12
14
11
13
DG1/DG2 Turn-Off Delay vs
Capacitance
1200
1000
10
IDG1UP, –40°C
IDG2UP, –40°C
IDG1UP, 25°C
IDG2UP, 25°C
IDG1UP, 125°C
IDG2UP, 125°C
8
0
10
10 20 30 40 50 60 70 80 90 100
VBIAS (V)
ITMR (μA)
1.40
1.35
50
75
0
100 125 150
0.32
100
TEMPERATURE (°C)
8228 G54
–40°C
25°C
125°C
0
10 20 30 40 50 60 70 80 90 100
VV1D, V1 (V)
8228 G55
8
12 16 20 24 28 32 36 40
8228 G53
DG1 Retry Duty Cycle vs
V (V1D, DS1)
200
150
4
CDG (nF)
0.40
0
0
8228 G52
250
50
25
200
TMR Current vs V (V1D, DS1)
1.45
0
600
400
10 20 30 40 50 60 70 80 90 100
VBIAS (V)
1.50
VSET1N,MAX (V)
0
8228 G51
ISET1N Inrush Regulation vs
Temperature
1.30
–50 –25
VDG1, –40°C
VDG2, –40°C
VDG1, 25°C
VDG2, 25°C
VDG1, 125°C
VDG2, 125°C
11
DUTY CYCLE (%)
9
12
DELAY (nS)
VDG (V)
IDGUP (μA)
800
0.24
0.16
0.08
0
0
10 20 30 40 50 60 70 80 90 100
VV1D, V1 (V)
8228 G56
Rev. 0
For more information www.analog.com
15
LT8228
PIN FUNCTIONS
SNS1P, SNS1N (Pins 1, 2): Positive and Negative Input
Terminals of the V1 Bidirectional Current Sense Amplifier
(CSA1 in the Block Diagram section). The pins allow current monitoring and regulation of the V1 input current in
buck mode and V1 output current in boost mode. Current
sense polarity is positive for current flowing out of V1 into
V2. Place input gain resistors RIN1 between the current
sense resistor RSNS1 and these pins. Typical bias current
into these pins is 90µA for common mode voltage above
2.5V. As common mode voltage decreases below 2.5V,
bias current decreases and reverses direction. Refer to
the curve of IB1 over VCM1 in the Typical Performance
Characteristics section.
CSA1 is connected in a negative feedback loop to make
SNS1N and SNS1P pin voltages equal. The voltage across
the current sense resistor and the input gain resistors
generates a difference in current flowing into the SNS1N
and SNS1P pins, ISNS1N and ISNS1P. The current flowing
through RSNS1, ISNS1, includes the V1 current, the input
bias current of CSA1’s negative feedback terminal and the
differential current given by Equation 1.
I
•R
ISNS1N – ISNS1P = SNS1 SNS1
RIN1
(1)
In buck mode, this current difference is generated out of
the ISET1P and IMON1 pins. In boost mode, it is generated out of the ISET1N, ISHARE and IMON1 pins. Limit
the difference between SNS1N and SNS1P pin currents
to ±100µA by choosing the values of RSNS1 and RIN1
appropriately. Refer to the RSNS1 and RIN1 Selection in
Applications Information section for more details.
UV1 (Pin 3): Undervoltage Detection Input for V1. It is
a high impedance pin with the undervoltage detection
threshold set at 1.2V typically. The undervoltage level is
set using a resistor divider connected between V1 node
and ground. If V1 needs reverse voltage protection, connect the resistor divider in series with a diode whose
anode is connected to V1. The status of the UV1 pin is
reported at the REPORT pin in buck mode.
If the DRXN pin is externally set high for buck mode operation and the UV1 pin voltage falls below its threshold
voltage, the FAULT and SS pins pull low and the LT8228
stops switching. If the DRXN pin is high but not externally
controlled, and the UV1 pin voltage falls below the threshold voltage, the regulation mode changes from buck to
boost and the DRXN pin is internally driven low. See the
Operation section for more information. Tie the pin to
INTVCC if not used.
FB1 (Pin 4): V1D Feedback Voltage and Overvoltage
Detection Input. This pin is one of the boost mode error
amplifier’s (EA1 in the Block Diagram section) inverting
terminals. It is a high impedance pin and senses the V1D
voltage through an external resistor divider network. The
pin is regulated to the typical internal reference voltage
of 1.21V in boost mode.
V1D overvoltage detection threshold is set at 1.3V typically. The status of V1D overvoltage is reported at the
REPORT pin in boost mode. If the DRXN pin is externally
set low for boost mode operation and the FB1 pin voltage
rises above its overvoltage threshold voltage, the FAULT
pin pulls low. If the DRXN pin is low but not externally
controlled, and the FB1 pin voltage rises above the overvoltage threshold voltage for a duration of 1024 switching
clock cycle, the regulation mode changes from boost to
buck and the DRXN pin is pulled high by the external pullup resistor. Tie the pin to ground if not used.
IMON1 (Pin 5): V1 Current Monitor Output. The current
out of this pin is equal to the absolute voltage across
the current sense resistor RSNS1 divided by the value of
the input sense resistor RIN1. This current represents
V1 input current in buck mode and V1 output current in
boost mode. Connecting a resistor RMON1, from IMON1
to ground generates a voltage VMON1 for monitoring by an
external ADC. The maximum dynamic range for IMON1 is
2.5V. To set RMON1, first determine the maximum monitor
voltage VMON1MAX based on ADC input dynamic range.
Next, calculate the value of RMON1 with Equation 2.
R MON1 =
RIN1
ISNS1MAX • R SNS1
• VMON1MAX
(2)
where ISNS1MAX is the maximum of the programmed V1
output current limit IV1N(LIM) in boost mode or the programmed V1 input current limit IV1P(LIM) in buck mode.
A filtering capacitor can be added to read the average
current at the ADC input. Refer to the RMON1 Selection for
V1 Current Monitoring in Applications Information section
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LT8228
PIN FUNCTIONS
for more detail on resistor and capacitor selection. Tie the
pin to ground if not used.
ISET1N (Pin 6): Boost Mode Output Current Limit
Programming. This pin sets the V1 output current limit in
boost mode by connecting a resistor RSET1N from ISET1N
to ground. The pin outputs a current equal to the negative
voltage across the current sense resistor RSNS1 divided by
the value of the input sense resistor RIN1. The voltage at
ISET1N is regulated to the lower of the SS pin voltage and
the typical internal reference voltage of 1.21V. Calculate
the value of RSET1N with Equation 3.
RISET1N =
RIN1
R SNS1 •I V1N(LIM)
• 1.21V
(3)
where IV1N(LIM) is the maximum programmed V1 output
current limit in boost mode.
In boost mode, at start-up when V1 is lower than V2 or V1
is shorted to GND, the output current cannot be limited
by the boost regulation loop. Under such conditions, the
LT8228 controls the output current by controlling M1, the
V1 protection MOSFET. The LT8228 controls DG1, the gate
of M1 by regulating ISET1N to 1.4V.
Current at this pin is discontinuous during switching.
Connect a filtering capacitor at this pin to regulate the
average current limit. The value of the filtering capacitor affects the current regulation loop stability. Refer to
the RSET1N Selection for V1 Output Current Limit (Boost
Mode) in Applications Information section for resistor
and capacitor selection. Tie the pin to ground if not used.
ISET2N (Pin 7): Boost Mode Input Current Limit
Programming. This pin sets the V2 input current limit in
boost mode by connecting a resistor RSET2N from ISET2N
to ground. The pin outputs a current equal to the negative
voltage across the current sense resistor RSNS2 divided by
the value of the input sense resistor RIN2. The voltage at
ISET2N is regulated to the lower of the SS pin voltage and
the typical internal reference voltage of 1.21V. Calculate
the value of RSET2N with Equation 4.
RISET2N =
RIN2
R SNS2 •I V2N(LIM)
• 1.21V
(4)
where IV2N(LIM) is the maximum programmed V2 input
current limit in boost mode. Connect a filtering capacitor
at this pin to regulate the average current limit. The value
of the filtering capacitor affects the current regulation
loop stability. Refer to the RSET2N Selection for V2 Input
Current Limit (Boost Mode) in Applications Information
section for resistor and capacitor selection. Tie the pin to
ground if not used.
VC1 (Pin 8): Boost Mode Error Amplifier (EA1 in the Block
Diagram section) Compensation. VC1 is the compensation pin for boost mode regulation of the V1D voltage, the
V1 output current and the V2 input current. EA1 servos
the higher of the FB1, ISET1N and ISET2N pin voltages
to the typical internal reference voltage of 1.21V. If the
SS pin voltage is lower than the typical internal reference
of 1.21V, EA1 regulates the current programming pins
ISET1N and ISET2N voltages to the SS pin voltage. Leave
the pin open if not used.
SS (Pin 9): Soft-Start Input. The LT8228 limits all the
ISET pin voltages to the SS pin voltage when the pin voltage is lower than the typical internal reference voltage of
1.21V. Connect a soft-start capacitor CSS between the
SS pin and ground. When the LT8228 is disabled, or a
fault is detected (refer to the Soft-Start in Applications
Information section for all the fault conditions), the SS
pin is actively pulled low by an internal MOSFET to reset
the soft-start. Select CSS for a soft-start time tSS according to Equation 5.
C SS =
10µA
•
1
1.21V t SS
(5)
Leave the pin open if not used.
VC2 (Pin 10): Buck Mode Error Amplifier (EA2 in the Block
Diagram section) Compensation. VC2 is the compensation pin for buck mode regulation of the V2D voltage, the
V2 output current and the V1 input current. EA2 servos
the higher of the FB2, ISET1P and ISET2P pin voltages
to the typical internal reference voltage of 1.21V. If the
SS pin voltage is lower than the typical internal reference
of 1.21V, EA2 regulates the current programming pins
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17
LT8228
PIN FUNCTIONS
ISET1P and ISET2P voltages to the SS pin voltage. Leave
the pin open if not used.
ISET1P (Pin 11): Buck Mode Input Current Limit
Programming. This pin sets the V1 input current limit in
buck mode by connecting a resistor RSET1P from ISET1P
to ground. The pin outputs a current equal to the positive
voltage across the current sense resistor RSNS1 divided by
the value of the input sense resistor RIN1. The voltage at
ISET1P is regulated to the lower of the SS pin voltage and
the typical internal reference voltage of 1.21V. Calculate
the value of RSET1P with Equation 6.
RISET1P =
RIN1
R SNS1 •I V1P(LIM)
• 1.21V
(6)
where IV1P(LIM) is the maximum programmed V1 input
current limit in buck mode. Connect a filtering capacitor
at this pin to regulate the average current limit. The value
of the filtering capacitor affects the current regulation loop
stability. Refer to the RSET1P Selection for V1 Input Current
Limit (Buck Mode) in Applications Information section for
resistor and capacitor selection. Tie the pin to ground if
not used.
ISET2P (Pin 12): Buck Mode Output Current Limit
Programming. This pin sets the V2 output current limit in
buck mode by connecting a resistor RSET2P from ISET2P
to ground. The pin outputs a current equal to the positive
voltage across the current sense resistor RSNS2 divided
by the value of the input sense resistor RIN2. The voltage
at ISET2P is regulated to the lower of the SS pin voltage and the typical internal reference voltage of 1.21V.
Calculate the value of RSET2P with Equation 7.
RISET2P =
RIN2
R SNS2 •I V2P(LIM)
• 1.21V
(7)
where IV2P(LIM) is the maximum programmed V2 output
current limit in buck mode. Connect a filtering capacitor
at this pin to regulate the average current limit. The value
of the filtering capacitor affects the current regulation
loop stability. Refer to the RSET2P Selection for V2 Output
Current Limit (Buck Mode) in Applications Information
section for resistor and capacitor selection. Tie the pin to
ground if not used.
IMON2 (Pins 13): V2 Current Monitor Output. The current out of this pin is equal to the absolute voltage across
the current sense resistor RSNS2 divided by the value of
the input sense resistor RIN2. This current represents V2
input current in boost mode and V2 output current in
buck mode. Connecting a resistor RMON2, from IMON2 to
ground generates a voltage VMON2 for monitoring by an
external ADC. The maximum dynamic range for IMON2 is
2.5V. To set RMON2, first determine the maximum monitor
voltage VMON2MAX based on ADC input dynamic range.
Next, calculate the value of RMON2 with Equation 8.
R MON2 =
RIN2
ISNS2MAX • R SNS2
• VMON2MAX
(8)
where ISNS2MAX is the maximum of the IV2N(LIM), programmed V2 input current limit in boost mode or IV2P(LIM),
the programmed V2 output current limit in buck mode. A
filtering capacitor can be added to read the average current at the ADC input. Refer to the RMON2 Selection for
V2 Current Monitoring in Applications Information section
for more detail on resistor and capacitor selection. Tie the
pin to ground if not used.
FB2 (Pin 14): V2D Feedback Voltage and Overvoltage
Detection Input. This pin is one of the buck mode error
amplifier’s (EA2 in the Block Diagram section) inverting
terminals. It is a high impedance pin and senses the V2D
voltage through an external resistor divider network. The
pin is regulated to the typical internal reference voltage
of 1.21V in buck mode.
V2D overvoltage detection threshold is set at 1.3V typically. The status of V2D overvoltage is reported at the
REPORT pin in boost mode. If the DRXN pin is externally
set high for buck mode operation and the FB2 pin voltage
rises above its overvoltage threshold voltage, the FAULT
pin pulls low. If the DRXN pin is high but not externally
controlled, and the FB2 pin voltage rises above the overvoltage threshold voltage for a duration of 1024 switching
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LT8228
PIN FUNCTIONS
clock cycle, the regulation mode changes from buck to
boost and the DRXN pin is actively pulled-low. Tie the pin
to ground if not used.
UV2 (Pin 15): Undervoltage Detection Input for V2 . It is
a high impedance pin with the undervoltage detection
threshold set at 1.2V typically. The undervoltage level is
set using a resistor divider connected between V2 node
and ground. If V2 needs reverse voltage protection, connect the resistor divider in series with a diode whose
anode is connected to V2 . The status of the UV2 pin is
reported at the REPORT pin in boost mode.
If the DRXN pin is externally set low for boost mode operation and the UV2 pin voltage falls below its threshold
voltage, the FAULT and SS pin pulls low and the LT8228
stops switching. If the DRXN pin is low but not externally
controlled, and the UV2 pin voltage falls below the threshold voltage, the regulation mode changes from boost to
buck and the DRXN pin is pulled high by the external pullup resistor. See the Operation section for more information. Tie the pin to INTVCC if not used.
RT (Pin 16): Switching Frequency Set Input. Place a resistor RRT from RT to ground to set the internal frequency.
The range of frequency is 80kHz to 600kHz. Set the RRT
resistance for a fixed frequency fPROG according to the
RRT resistance vs frequency curve in Typical Performance
Characteristics section. See the Programming the
Switching Frequency in Applications Information section
for more details on resistor selection. Do not tie this pin
to ground or leave it open.
ISHARE (Pin 17): Masterless Current Sharing Input for
Paralleling. Together with the IGND pin, this pin allows
equal output current sharing among multiple LT8228s
in parallel, enabling higher total load current, better heat
management and redundancy. Each LT8228 regulates to
the average output current eliminating the need for a master controller. When paralleling, tie the ISHARE pins of all
the LT8228s together. For each LT8228, connect a local
resistor RSHARE from the ISHARE pin to its own IGND pin.
In buck mode when DRXN is high, the ISHARE pin outputs
a current equal to the current out of the ISET2P pin which
represents V2 output current. In boost mode when DRXN
is low, the ISHARE pin outputs a current equal to the current out of the ISET1N pin which represents V1 output
current. Each LT8228 contributes this current into the
common ISHARE node. When all the RSHARE resistors are
equal, voltage at the ISHARE node represents the average
output current. When a controller is disabled or has a fault
condition, the ISHARE pin does not output any current.
In buck mode, V2 output current is regulated so that
ISET2P pin voltage is equal to the voltage on the ISHARE
pin. To regulate each LT8228’s V2 output current to the
average output current, make RSET2P and RSHARE equal. In
boost mode, V1 output current is regulated so that ISET1N
pin voltage is equal to the voltage on the ISHARE pin. To
regulate each LT8228’s V1 output current to the average
output current, make RSET1N and RSHARE equal. In order
to set different output current limits in buck and boost
modes, RSET2P and RSET1N can be set at different values
as long as the value of RSHARE is changed based on the
mode of operation defined by the DRXN pin.
Connect a filtering capacitor between the ISHARE pin and
ground for average current regulation. See the Paralleling
Multiple LT8228s in Applications Information section for
more details. Refer to the IGND pin function description
for fault tolerance and redundancy design. Tie the ISHARE
pin to INTVCC if not used.
SNS2P, SNS2N (Pins 18, 19): Positive and Negative Input
Terminals of the V2 Bidirectional Current Sense Amplifier
(CSA2 in the Block Diagram section) for current monitoring and regulation of the input current in boost mode and
output current in buck mode. Current sense polarity is
positive for current flowing out of V1 into V2 . Place input
gain resistors RIN2 between the current sense resistor
RSNS2 and these pins. Typical bias current into these pins
is 90µA for common mode voltage above 2.5V. As common mode voltage decreases below 2.5V, bias current
decreases and reverses direction. See the curve of IB2 over
VCM2 in the Typical Performance Characteristics section.
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LT8228
PIN FUNCTIONS
CSA2 is connected in a negative feedback loop to make
SNS2N and SNS2P pin voltages equal. The voltage across
the current sense resistor and the input gain resistors
generate a difference in current flowing into the SNS2N
and SNS2P pins, ISNS2N and ISNS2P. The current flowing
through RSNS2 , ISNS2, includes the V2 current, the input
bias current of CSA2’s negative feedback terminal and the
differential current given by Equation 9.
•R
I
ISNS2N – ISNS2P = SNS2 SNS2
RIN2
(9)
In buck mode, this current difference is generated out of
the ISET2P, ISHARE and IMON2 pins. In boost mode, it is
generated out of the ISET2N and IMON2 pins. Limit the
difference between SNS2N and SNS2P pin currents to
±100µA by choosing the values of RSNS2 and RIN2 appropriately. Refer to the RSNS2 and RIN2 Selection for Peak
Inductor Current in Applications Information section for
more details.
IGND (Pin 20): Current Sharing Ground. Connect a local
resistor RSHARE from the ISHARE pin to the IGND pin.
When the LT8228 is enabled and the internal diagnostic routine is passed, the IGND pin connects RSHARE to
ground through a 120Ω switch. During shutdown or a
faulted condition, ISHARE stops generating current and
the switch at the IGND pin is opened so that no current
flows through the current sharing resistor. This disconnects the RSHARE resistor from the common ISHARE node
so that the ISHARE node continues to represent the average output current of the remaining active LT8228’s in
parallel. With this scheme, any paralleled LT8228 can
be added or subtracted without affecting current sharing accuracy. The IGND pin along with the ISHARE pin
provides a current sharing that is masterless as well as
fault tolerant. Refer to the Paralleling Multiple LT8228s
in Applications Information section for more information.
Tie the pin to ground if not used.
INTVCC (Pin 21): Internal 4V VCC Supply. INTVCC is powered from DRVCC. Connect a minimum bypass capacitor
of 1µF from INTVCC to ground. Do not load this pin except
for pulling up the DRXN and FAULT pins.
DRXN (Pin 22): Buck or Boost Regulation Mode Select.
Pulling the pin high selects buck regulation mode and
pulling the pin low selects boost regulation mode. Drive
the DRXN pin with logic level input or with a pull-up resistor. Driving the DRXN pin higher than 1.1V selects buck
mode and lower than 0.8V selects boost mode. The pullup resistor allows the LT8228 to auto-select the regulation
mode based on the UV1, UV2, FB1 and FB2 pin voltages.
The DRXN pin is high impedance when the LT8228 is
in buck mode which pulls the DRXN pin high through
the pull-up resistor. A 100μA pull-down is enabled when
the LT8228 is in boost mode which pulls the DRXN pin
low. The typical value of the pull-up resistor is 100k and
should not be less than 40k when connected to INTVCC
to guarantee a low logic level.
When the LT8228 is enabled and the UV1 pin voltage is
higher than 1.2V, the part starts regulation in buck mode.
If the UV1 pin voltage is lower than 1.2V when enabled,
the LT8228 starts regulation in boost mode. If both UV1
and UV2 pin voltages are lower than 1.2V, the part is
in buck mode, the FAULT and SS pins pull low and the
LT8228 does not switch. If the LT8228 is in buck mode
and the UV1 pin voltage drops lower than 1.2V or the
FB2 pin voltage rises higher than 1.3V for 1024 switching clock cycles, the controller transitions to boost mode.
When in boost mode, if the UV2 pin voltage drops lower
than 1.2V or the FB1 pin voltage rises higher than 1.3V
for 1024 switching clock cycles, the controller transitions
to buck mode. If both the FB1 and FB2 pin voltages are
higher than 1.3V for 1024 switching clock cycles, the part
is in buck mode, the FAULT and SS pins pull low and the
LT8228 does not switch. Anytime DRVCC or INTVCC pin
voltages fall below their respective undervoltage threshold, the part goes to buck mode, the FAULT and SS pins
pull low and the LT8228 does not switch.
When multiple LT8228s are in parallel, tie all the DRXN
pins together to operate all LT8228s in the same regulation mode. Connect a single pull-up resistor between the
common DRXN node and an external voltage source. If
the external voltage source is not available, each LT8228
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LT8228
PIN FUNCTIONS
needs its own pull-up resistor in series with a diode whose
anode is connected to its INTVCC pin. This diode prevents
unintentional boost mode selection when one or more
channels are disabled. Refer to the Paralleling Multiple
LT8228s in Applications Information section for more
information. Do not leave this pin open.
Applications Information). When the TMR reaches 1.4V,
the LT8228 shorts DG1 to DS1 to turn-off M1. Upon M1
gate off, a cool down interval commences while the TMR
pin cycles 32 times between 0.4V and 1.4V with 2μA
charge and discharge currents. When TMR crosses 0.4V
the 32nd time, the DG1 pin pulls high, turning on M1.
SYNC (Pin 23): Synchronization or Spread Spectrum
Input. Synchronize to an external clock with pulses that
have duty cycles between 5% and 95% from 80kHz to
600kHz. The high level of the clock voltage needs to be
above 1V and the low level needs to be below 0.5V. To
enable spread spectrum of the internal frequency generator, connect this pin to INTVCC. Connect this pin to ground
to disable spread spectrum. Do not leave this pin open.
BG (Pin 27): Bottom Gate Drive. The BG pin drives the
gate of the low side N-channel synchronous switch
MOSFET M3. The BG voltage transitions between DRVCC
and ground.
FAULT (Pin 24): Fault Status Indicator. FAULT is an opendrain logic pin which flags fault conditions (refer to the
FAULT Conditions in Applications Information section
for more information). When the FAULT pin asserts, the
LT8228 stops switching and the SS pin pulls low. Pull-up
the pin with an LED in series with a resistor to a voltage
source to provide a visual status indicator. For a sink current of 2mA, the maximum voltage overtemperature at
the FAULT pin is 0.5V. Tie the pin to ground if not used.
BIAS (Pin 29): DRVCC and Control Circuitry Supply. This
pin supplies the DRVCC regulator as well as the internal
control circuitry. BIAS can be connected to V1 or V2 or
an external supply. No negative voltage is allowed at the
BIAS pin. Refer to the BIAS, DRVCC, INTVCC and Power
Dissipation in Applications Information section for more
details. Connect a minimum bypass capacitor of 10µF
from BIAS to ground.
REPORT (Pin 25): Diagnostic Status. This pin is an opendrain active low output that reports the state of the internal diagnostic monitors of critical safety features through
a digital logic bit stream synchronized to the frequency
of the SYNC pin. See the Report Feature in Applications
Information section for more details on the report function. Pull-up the pin with a series resistor to a microcontroller input logic voltage source. For a sink current
of 2mA, the maximum voltage overtemperature at the
REPORT pin is 0.5V. Tie the pin to ground if not used.
TMR (Pin 26): Timer Input for SOA Management of V1
Protection MOSFET (M1). Connect a capacitor between
this pin and ground to set the M1 turn-off and cool down
periods at excess power dissipation during output inrush
current in boost mode. In boost mode, when current regulation at ISET1N is 1.4V and voltage across M1 (V1D,
DS1) exceeds 500mV, the TMR pin voltage starts to
increase. The current charging up this pin increases with
the voltage difference between V1D and DS1 pins (see
DRVCC (Pin 28): 10V Gate Drive VCC Supply. DRVCC is
powered from BIAS. It provides power to the top gate (TG)
and bottom gate (BG) MOSFET drivers. Connect a minimum bypass capacitor of 2.2µF from DRVCC to ground.
SW (Pin 30): Switch Node. This pin connects to the
source of the top side MOSFET M2 and to the drain of
the bottom side MOSFET M3. This pin also connects to
the inductor and the bootstrap capacitor CBST.
TG (Pin 31): Top Gate Drive. The TG pin drives the gate
of the high side N-channel MOSFET M2. TG draws power
from the BST pin and returns to the SW pin, providing true
floating gate drive to the high side MOSFETs.
BST (Pin 32): Top Gate Driver Boosted Supply. The BST
pin supplies power to the floating TG driver for the high
side MOSFET (M2). Connect a low ESR capacitor from the
BST pin to the SW pin. Connect a fast recovery diode from
DRVCC to BST to supply this pin. The pin voltage swings
from a diode below DRVCC up to DRVCC + V1D.
ENABLE (PIN 33): Enable Input. Pull this pin above 1.3V
typically to enable the LT8228. When this pin is pulled
below the typical threshold voltage of 1.2V, the controller
stops switching, the protection MOSFETs are turned off,
and the DRVCC and INTVCC regulators are disabled. When
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21
LT8228
PIN FUNCTIONS
the ENABLE pin is pulled below 0.7V typically, the LT8228
turns off internal references and enters a low quiescent
current state of 10µA typically.
DS2 (Pin 34): Source Input of the V2 N-channel Protection
MOSFET and DG2 Drive Return. Connect the pin to the
sources of the V2 N-channel protection MOSFETs M4A
and M4B. If a single MOSFET M4 is used as the V2 protection MOSFET, DS2 pin connects to both the source of
M4 and the V2 terminal. Voltage sensed at the DS2 pin
is used for M4’s gate control. DS2 can sustain voltages
down to –40V. The LT8228 protects itself and the load
at V1 by turning off M4 when a supply is connected in
reverse at V2.
DG2 (Pin 35): V2 Protection MOSFET M4A and M4B’s
Gate. The DG2 pin controls the gate of the N-channel
MOSFETs M4A and M4B. After the LT8228 is enabled, The
DG2 pin pulls high with a 10µA pull-up current to a typical
value of 10V above DS2 to enhance M4A and M4B. When
the LT8228 is disabled, or in a fault condition, or if the
V2 voltage goes negative, the LT8228 shorts DG2 to DS2,
turning off M4A and M4B (refer to the FAULT Conditions in
the Applications Information section). This pin is designed
for capacitive load only. Connect a series capacitor CDG2
and a resistor RDG2 for inrush current control. Refer to
the Inrush Current Control in Applications Information
section for more details. Keep the pin open if not in use.
V1D (Pin 36): The Drain of V1 Protection MOSFET M1A.
The voltage sensed at this pin is used to control the DG1
voltage in boost mode. V1D is the regulated output in
boost mode. Connect a minimum bypass capacitor of
10µF from V1D to ground.
DS1 (Pin 37): Source Input of the V1 N-channel Protection
MOSFET and DG1 Drive Return. Connect the pin to the
sources of the V1 N-channel protection MOSFETs M1A
and M1B. If a single MOSFET M1 is used as the V1 protection MOSFET, DS1 pin connects to both the source of
M1 and the V1 terminal. Voltage sensed at the DS1 pin
is used for M1’s gate control. DS1 can sustain voltages
down to –40V. The LT8228 protects itself and the load
at V2 by turning off M1 when a supply is connected in
reverse at V1.
DG1 (Pin 38): V1 Protection MOSFET M1A and M1B’s
Gate. The DG1 pin controls the gate of the N-channel
MOSFETs M1A and M1B. After the LT8228 is enabled, The
DG1 pin pulls high with a 10µA pull-up current to a typical
value of 10V above DS1 to enhance M1A and M1B. When
the LT8228 is disabled, or in a fault condition, or if the
V1 voltage goes negative, the LT8228 shorts DG1 to DS1,
turning off M1A and M1B (refer to the FAULT Conditions
in the Applications Information section). Connect a series
capacitor CDG1 and a resistor RDG1 for inrush current control and boost output short current regulation. Refer to
the Inrush Current Control and boost short output current
in Applications Information section for more details. This
pin is designed for capacitive load only. Keep the pin open
if not in use.
In buck mode, when V1 falls within 500mV of V2 and
RSNS1 current passes negative threshold, the LT8228
detects reverse current and shorts DG1 to DS1, turning
off M1. Negative threshold for reverse current detection
in buck mode is given by Equation 10.
IRCUR,BUCK =
RIN
R SNS2
• 3µA
(10)
In boost mode, at start-up when V1 is lower than V2 or V1
is shorted to GND, the output current cannot be limited
by the boost regulation loop. Under such conditions, the
LT8228 controls the output current by controlling M1A,
the V1 protection MOSFET. The LT8228 controls DG1,
the gate of M1 by regulating ISET1N to 1.4V. Current
regulation at ISET1N and voltage across M1 (V1D, DS1)
exceeding 500mV triggers current at the TMR pin. The
current is proportional to the voltage across the drain
and source of M1. If the voltage at the TMR pin reaches
1.4V, the LT8228 turns of M1 and initiates a cool down
period. Programming the TMR pin with a capacitor (see
Application Information) keeps M1 always within its safe
operating area (SOA).
GND (Exposed Pad Pin 39): Ground. The exposed pad of the
TSSOP is an electrical connection to GND. Tie the exposed
pad directly to the other GND pin and the PCB ground to
ensure proper electrical and thermal performance.
Rev. 0
22
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LT8228
BLOCK DIAGRAM
D2
M1B
V1
RSNS1
M1A
CDM1
CV1
DV1
RDG1
L
M2
CBST
RIN1
SNS1P
M4A
SNS1N
TG
SW
RIN2
CDRVCC
BST
DRVCC
RDG2
RIN2
GND
BG
TG + BG DRIVER
SNS2P
DS1
BIAS
DS1
SNS2N
CHARGE
PUMP
DG1 CONTROLLER
(SEE FIGURE 1 + 2)
DS2
TMR
DG2 CONTROLLER
(SEE FIGURE 3)
SYNCHRONOUS
LOGIC
ISHARE
AMP 1
ISHARE
ISHARE
ISET2P
PWM
COMP
RREF1
1.21V
DG2
ISHARE
AMP 2
ISET1N
RFB1A
RREF2
RFB2A
1.21V
FB2
FB1
ISET1N
RFB1B
MAX
ISET2N
1.21V
ERROR AMPLIFIER 1
EA1
VC1
RC1
CC1
UV1
ERROR AMPLIFIER 2
EA2
RFB2B
ISET2P
1.21V
MIN
SS
VC2
1.3V
UV1
FB2
1.2V
RC2
CC2
SYSTEM
CONTROL
BIAS
INTVCC
µC VDD
1.2V
1.2V
REFERENCE
REPORT
INTERNAL DIAGNOSTICS
+ FAULT REPORTING
DRVCC
10V LDO
FAULT
3.3V LDO
SNS1P
CSA1
SYNC
RRT
SNS2P
SNS1N
DRXN
SNS2N
EN
CSA2
PLL +
OSCILLATOR
100µA
RUV2B
RREPORT
TO µC
µC VDD
RFAULT
INTVCC
CINTVCC
RT
RUV2A
UV2
1.3V
ENABLE
RUV1B
ISET1P
MAX
MIN
SS
RUV1A
DV2
TO CSA2
(CURRENT SENSE AMPLIFIER 2)
DS2
CTMR
V2
CDG2
TO CSA1
(CURRENT SENSE AMPLIFIER 1)
DG1
M4B
CV2
M3
D3
DBST
CDG1
V1D
V2D
CDM4
CDM2
RIN1
RSNS2
TO µC
RDRXN
TO DRXN
PINS FOR
PARALLELING
IGND
INTVCC
10µA
SS
VH
VL
IMON1
ISET1P
ISET1N
CSS
DRXN
ISHARE
ISET2P
ISET2N
IMON2
TO ISHARE
PINS FOR
PARALLELING
CMON1
RMON1
CSET1P
RSET1P
CSET1N
RSET1N
RSHARE
CSHARE
RSET2P
CSET2P
RSET2N
CSET2N
RMON2
CMON2
8228 BD
Rev. 0
For more information www.analog.com
23
LT8228
OPERATION
Refer to the Block Diagram section when reading the following sections about the operation of the LT8228.
OVERVIEW
The LT8228 is a 100V bidirectional peak current mode
synchronous controller with protection MOSFETs. The
controller provides a step-down output voltage V2 from an
input voltage V1 when in buck mode or a step-up output
voltage V1 from an input voltage V2 when in boost mode.
The input and output voltage can be set as high as 100V.
The mode of operation is externally controlled through
the DRXN pin or automatically selected. In addition, the
LT8228 has protection MOSFETs for the V1 and the V2
terminals. The protection MOSFETs provide negative voltage protection, isolation between the input and output
terminals during an internal or external fault, reverse current protection and inrush current control. In applications
such as battery backup systems, the bidirectional feature
allows the battery to be charged from either a higher or
lower voltage supply. When the supply is unavailable, the
battery boosts or bucks power back to the supply. To
optimize transient response, the LT8228 has two error
amplifiers: EA1 in boost mode and EA2 in buck mode
with separate compensation pins VC1 and VC2 respectively. The controller operates in discontinuous conduction mode when reverse inductor current is detected for
conditions such as light load operation.
The LT8228 provides input and output current limit programming in buck and boost mode operation using four
pins, ISET1P, ISET1N, ISET2P and ISET2N. The controller
also provides independent input and output current monitoring using the IMON1 and IMON2 pins. Current limit
programming and monitoring is functional for the entire
input and output voltage range of 0V to 100V. Dynamic
control of the input and output current limits is achieved
by modulating the ISET pins. These features allow maximum design flexibility for applications such as maintaining battery charging profiles. The LT8228 employs a masterless fault-tolerant current sharing scheme using the
ISHARE and the IGND pins allowing higher load current,
better heat management and redundancy.
The LT8228’s control circuitry and the 10V gate drive
are supplied from the BIAS pin. The BIAS pin is tied to
either V1 or V2 or to an independent source. Managing the
voltage at the BIAS pin lowers thermal dissipation. The
10V gate drive feature complements high voltage high
current switching MOSFETs, which tend to have higher
threshold tvoltages.
The LT8228 provides fixed switching frequency operation
from 80kHz to 600kHz programmed through the RT pin.
The SYNC pin is used to synchronize to an external clock
or enable the spread spectrum of the switching frequency
set by the RT pin.
The LT8228 has undervoltage protection for the input
and overvoltage protection for the output, over temperature protection and switching MOSFET fault detection
and protection that are all reported via the FAULT and the
REPORT pins. When the controller is enabled, an internal diagnostic routine checks for functionality of critical
circuits before switching starts. If any error is found, the
controller remains disabled and the error can be read
through the REPORT pin. Fault reporting and internal
diagnostics improve the reliability of the LT8228 from a
safety perspective.
BUCK MODE OPERATION
In buck mode, the LT8228 is a peak current mode stepdown controller where V1 is the input supply and V2 is
the output load. Two back-to-back N-channel MOSFETs
M1A and M1B are placed between the V1 terminal and
the input of the buck regulator V1D as shown in the Block
Diagram section. DS1 is the source and DG1 is the gate
of both M1A and M1B. V1D is the drain of M1A and V1
is the drain of M1B. M1A is used by the LT8228 V1 protection MOSFET controller to protect the regulator from
reverse current from V2 to V1 and negative voltages on
V1. M1B is used to control the inrush current from V1
to V1D and to isolate V1 and V2 during fault conditions.
Depending on the application requirement, either M1A
or M1B or both M1A and M1B are optional. In normal
operation when M1A and M1B are enhanced, the voltage
difference between V1 and V1D is equal to the total onresistance multiplied by the V1 input current.
Rev. 0
24
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LT8228
OPERATION
Two back-to-back N-channel MOSFETs M4A and M4B
are placed between the V2 terminal and the output of the
buck regulator, V2D as shown in the Block Diagram section. M4A is used by the LT8228's V2 protection MOSFET
controller to protect the regulator from negative voltages
on V2. M4B is used to control inrush current from V2
to V2D and to isolate V1 and V2 completely during fault
conditions. DS2 is the source and DG2 is the gate of both
M4A and M4B. V2D is the drain of M4A and V2 is the
drain of M4B. Depending on the application requirement,
either M4A or M4B or both M4A and M4B are optional.
In normal operation when M4A and M4B are enhanced,
the voltage difference between V2 and V2D is equal to the
total on-resistance multiplied by the V2 output current.
V2D is the node to be regulated by the buck regulator
through a resistor divider from V2D to the FB2 feedback
pin. The error amplifier regulates the FB2 pin to the typical
internal reference voltage of 1.21V. The compensation of
the buck regulator error amplifier output is at the VC2 pin.
The VC2 pin sets the inductor current which is modulated
to regulate the V2D voltage.
In a general implementation where V2D is regulated to a
constant voltage, EA2 senses the output voltage through
the FB2 pin and compares the signal to the typical internal
reference voltage of 1.21V. Low V2D voltage creates a
higher VC2 voltage to increase the current flow into the
V2D node and raises V2D to the steady state regulation target value. Conversely, higher V2D voltage creates a lower
VC2 voltage to reduce the current flow into the V2D node
and lowers V2D to the steady state target value.
In buck mode, the LT8228 provides input and output
current limiting using the ISET1P and the ISET2P pins
respectively. The controller additionally provides input
and output current monitoring using the IMON1 and
IMON2 pins respectively. The input current is measured
by the V1 current sense amplifier CSA1 which senses the
voltage across the current sense resistor RSNS1 and generates a current proportional to the sensed voltage. CSA1
outputs the current out of the IMON1 and ISET1P pins.
Similarly, the output current is measured by the V2 current
sense amplifier CSA2 which senses the voltage difference
across the current sense resistor RSNS2 and generates a
current proportional to the sensed voltage. CSA2 outputs
the current out of the IMON2 and ISET2P pins.
The voltages at the IMON1, IMON2, ISET1P and ISET2P
pins are set by connecting resistors from these pins to
ground. The buck regulator limits current when either
ISET1P or ISET2P reaches the typical internal reference
voltage of 1.21V. This current regulation feature is ideal
for many battery charging applications. During start-up
when the SS pin voltage is lower than the typical internal
reference voltage, ISET1P and ISET2P are regulated to
the SS pin voltage.
BOOST MODE OPERATION
In boost mode, the LT8228 is a peak current mode step-up
controller where V2 is the input supply and V1 is the output
load. Two back-to-back N-channel MOSFETs M1A and M1B
are placed between the V1 terminal and the output of the
boost regulator, V1D as shown in the Block Diagram section.
DS1 is the source and DG1 is the gate of both M1A and M1B.
V1D is the drain of M1A and V1 is the drain of M1B. M1A is
used by the LT8228 V1 protection MOSFET controller to protect the regulator from negative voltages on V1 and to control
the outrush current from V1D to V1. M1B is used to control
the inrush current from V1 to V1D and to isolate V1 and V2
during fault conditions. Depending on the application requirement, either M1A or M1B or both M1A and M1B are optional.
In normal operation when M1A and M1B are enhanced, the
voltage difference between V1 and V1D is equal to the total
on-resistance multiplied by the V1 output current.
Two back-to-back N-channel MOSFETs M4A and M4B
are placed between the V2 terminal and the output of the
buck regulator V2D as shown in the Block Diagram section. M4A is used by the LT8228 V2 protection MOSFET
controller to protect the regulator from negative voltages
on V2. M4B is used to control the inrush current from V2
to V2D and to isolate V1 and V2 during fault conditions.
DS2 is the source and DG2 is the gate of both M4A and
M4B. V2D is the drain of M4A and V2 is the drain of M4B.
Depending on the application requirement, either M4A
or M4B or both M4A and M4B are optional. In normal
operation when M4A and M4B are enhanced, the voltage
difference between V2 and V2D is equal to the total onresistance multiplied by the V2 output current.
Rev. 0
For more information www.analog.com
25
LT8228
OPERATION
V1D is the node to be regulated by the boost regulator
through a resistor divider from V1D to the FB1 feedback
pin. The error amplifier regulates the FB1 pin to the typical
internal reference voltage of 1.21V. The compensation of
the boost regulator error amplifier output is at the VC1
pin. The VC1 pin sets the inductor current which is modulated to regulate the V1D voltage.
In a general implementation where V1D is regulated to a
constant voltage, EA1 senses the output voltage through
the FB1 pin and compares the signal to the typical internal
reference voltage of 1.21V. Low V1D voltage would create
a higher VC1 voltage, and more current would flow into
the V1D node, raising V1D to the steady state regulation
target value. Conversely, higher V1D voltage would create
a lower VC1 voltage, thus reducing the current flowing
into the V1D node, lowering the V1D voltage closer to the
steady state target value.
In boost mode, the LT8228 provides input and output
current limiting using the ISET2N and the ISET1N pins
respectively. The controller additionally provides input
and output current monitoring using the IMON2 and
IMON1 pins respectively. The input current is measured
by the V2 current sense amplifier CSA2 which senses the
voltage across the current sense resistor RSNS2 and generates a current proportional to the sensed voltage. CSA2
outputs the current out of the IMON2 and ISET2P pins.
Similarly, the output current is measured by the V1 current
sense amplifier CSA1 which senses the voltage difference
across the current sense resistor RSNS1 and generates a
current proportional to the sensed voltage. CSA1 outputs
the current out of the IMON1 and ISET1N pins.
The voltages at the IMON1, IMON2, ISET1N and ISET2N
pins are set by connecting resistors from these pins to
ground. The boost regulator limits current when either
ISET1N or ISET2N reaches the typical internal reference
voltage of 1.21V. This current regulation feature is ideal
for many battery charging applications. During start-up
when the SS pin voltage is lower than the typical internal
reference voltage, ISET1P and ISET2P are regulated to
the SS pin voltage.
V1 PROTECTION MOSFET CONTROLLER OPERATION
The LT8228 provides protection functionality at the V1
terminal using two N-channel MOSFETs M1A and M1B
connected back-to-back in series or a single N-channel
MOSFET M1 as shown in Figure 1. In dual MOSFET backto-back configuration, DS1 is the source and DG1 is the
gate of both M1A and M1B. V1D is the drain of M1A and
V1 is the drain of M1B. In single MOSFET configuration,
the source of M1 is connected to DS1 and the V1 terminal,
DG1 is the gate and V1D is the drain. The advantages of
the dual MOSFET configuration are inrush current control and complete isolation of the V1 terminal in a fault
condition. In normal operation, the controller drives DG1
high with a typical 10µA pull-up current that enhances
the V1 protection MOSFETs to provide a low loss conduction path between V1 and V1D. The DG1 voltage is
clamped at a typical value of 10V above DS1. The DG1
controller shorts DG1 to DS1 thereby isolating V1 from
the rest of the circuit when (1) the LT8228 is disabled or
M1
V1
TERMINAL
RDG1
V1D
V1
TERMINAL
CDG1
DS1
M1A
V1D
OR
RDG1
DG1
DS1 DG1
CDG1
RSNS1
V1
TERMINAL
M1B
L
M2
RSNS2 M4
V2
M1
TG
DS1
DG1
V1D
RIN1
RIN1
SNS1P
SNS1N
BG
M3
DG2
LT8228
CHARGE
PUMP
10μA
MDG1
CSA1
DG1 OFF
CONTROL
LOGIC
3μA
V2
DS2
V1 –500mV
8228 F01
Figure 1. M1 Control in Buck Mode
Rev. 0
26
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LT8228
OPERATION
(2) DS1 drops below –1.7V typically or (3) the internal
temperature rises above the overtemperature threshold
or (4) Any of the switching MOSFET short conditions is
detected or (5) DRVCC pin voltage drops below its undervoltage threshold or rises above its overvoltage threshold
or (6) INTVCC pin voltage drops below its undervoltage
threshold or rises above its overvoltage threshold or (7)
the part fails the internal diagnostic tests. When M1 is
not enhanced in single MOSFET configuration, V1D is a
forward diode voltage away from V1 due to the M1 body
diode. In dual MOSFET configuration, V1D is fully isolated
from V1 when M1A and M1B are not enhanced.
The buck mode operation circuitry of the V1 protection
MOSFET controller is shown in Figure 1. Without protection MOSFETs, there is a direct conduction path from V2
to V1 through the body diode of the top MOSFET M2. If
V2 is higher than V1 by a forward diode voltage, uncontrolled reverse current flows from V2 to V1. Unlike other
buck controllers, the LT8228 provides protection from
this reverse current condition using the V1 protection
MOSFET. If V1 falls within 500mV of V2 and RSNS1 current
passes negative threshold, the LT8228 detects reverse
current. A fast pull-down circuit shorts DG1 and DS1,
turning off M1. This isolates V1 from V1D and stops any
reverse current. The reverse current detect threshold is
set by Equation 11.
IRCUR,BUCK =
RIN
R SNS2
• 3µA
(11)
This protection feature is useful for applications where V2
is prebiased with a load such as a battery.
In dual MOSFET configuration, inrush current to CDM1 and
CDM2 in buck mode is limited by controlling the DG1 pin
voltage slew rate. In this configuration, the compensation
resistor RDG1 and capacitor CDG1 are ground referenced
as shown in Figure 1. At start-up, a 10µA pull-up current
charges DG1, pulling up both MOSFET gates. M1B operates as a source follower (see Equation 12).
IINRUSH,BUCK =
10µA • (CDM1 + CDM2 )
CDG1
This feature is not available with single MOSFET due to
the M1 body diode connecting V1D to V1.
The boost mode operation circuitry of the protection
MOSFET controller at V1 is shown in Figure 2. Without protection MOSFETs, there is a direct conduction path from V2
to V1 through the body diode of the top MOSFET M2. If V2
is higher than V1 by a forward diode voltage, uncontrolled
current flows from V2 to V1. This condition is common to
most boost start-up events. Unlike other boost controllers,
the LT8228 provides protection from this uncontrolled
output current condition using the V1 protection MOSFET
M1A (M1 in single MOSFET configuration). This current
is limited in boost mode through DG1 by regulating the
ISET1N pin voltage to 1.4V. Further reduction in V2 output
current is possible by increasing the RSET1N resistance or
injecting current into the ISET1N pin.
In addition to output current control in boost mode, the
LT8228 includes an adjustable fault timer to protect M1A
(M1 in single MOSFET configuration) from excessive
power dissipation damage. If V1D is higher than V1 by
M1
V1
TERMINAL
DS1
RDG1
DG1
V1D
DS1 DG1
CDG3
RSNS1
V1D
V1
TERMINAL
M1A
OR
CDG2
RDG1
M1B
V1
TERMINAL
V1D
RSNS2
L
M2
M4
V2
M1
DS1
DG1
V1D
TG
RIN1
RIN1
SNS1P
SNS1N
M3
DG2
BG
CHARGE
PUMP
LT8228
CSA1
10μA
V1D V1
MDG1
V1D
–0.5V
GMDG1
INRUSH
AMP
DG1 OFF
CONTROL
LOGIC
V1
Gm =
1/500k +10μA
GMDG1
1.3V
TMR
CTRL
1.4V
ISET1N
TMR
8228 F02
(12)
CSET1N
RSET1N
CTMR
Figure 2. M1 Control in Boost Mode
Rev. 0
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27
LT8228
OPERATION
500mV and ISET1N is regulated to 1.4V, a current source
starts charging up the capacitor connected at the TMR pin
to ground. When TMR reaches 1.4V, the DG1 controller
shorts DG1 to DS1 and turns off M1. The timer allows
the LT8228 to increase the voltage at V1 while protecting the MOSFET from being damaged by long period of
high power dissipation. The TMR charging current varies
depending on the voltage drop between V1D and V1, corresponding to the MOSFET VDS. The on time is inversely
proportional to the voltage drop across the MOSFET. This
helps to keep the MOSFET within its safe operating area
(SOA). After a cool down timer cycle, the LT8228 allows
M1 to turn back on and resume its operation.
V2 PROTECTION MOSFET CONTROLLER OPERATION
The LT8228 provides protection functionality at the V2
terminal using two N-channel MOSFETs M4A and M4B
connected back-to-back in series or a single N-channel
MOSFET M4 as shown in Figure 3. In dual MOSFET backto-back configuration, DS2 is the source and DG2 is the
gate of both M4A and M4B. V2D is the drain of M4A and
V2 is the drain of M4B. In single MOSFET configuration,
the source of M4 is connected to DS2 and the V2 terminal,
DG2 is the gate and V2D is the drain. The advantages of
dual MOSFET configuration are inrush current control in
V2D
M4
V2
TERMINAL
V2D
M4A
V2
TERMINAL
RDG2
OR
DG2
M4B
In dual MOSFET configuration, inrush current to CDM4,
CDM2 and CDM1 in boost mode is limited by controlling
the DG2 pin voltage slew rate. In this configuration, the
resistor RDG2 and capacitor CDG2 are ground referenced
as shown in Figure 3. At start-up, a 10µA pull-up current
charges DG2, pulling up both MOSFET gates. M2B operates as a source follower (see Equation 13).
CDG2
DG2 DS2
DS2
boost mode and complete isolation of the V2 terminal in
a fault condition. In a BG MOSFET M3 short fault, dual
MOSFET configuration is necessary to isolate V2 from
ground. In normal operation, the controller drives DG2
high with a typical 10µA pull-up current that enhances
the V2 protection MOSFETs to provide a low loss conduction path between V2 and V2D. The DG2 voltage is
clamped at a typical value of 10V above DS2. The DG2
controller shorts DG2 to DS2 thereby isolating V2 from
the rest of the circuit when (1) the LT8228 is disabled or
(2) DS2 drops below –1.7V typically or (3) the internal
temperature rises above the overtemperature threshold
or (4) any of the switching MOSFET short conditions is
detected or (5) DRVCC pin voltage drops below its undervoltage threshold or rises above its overvoltage threshold
or (6) INTVCC pin voltage drops below its undervoltage
threshold or rises above its overvoltage threshold or (7)
the part fails the internal diagnostic tests. When M4 is
not enhanced in single MOSFET configuration, V2D is a
forward diode voltage away from V2 due to the M1 body
diode. In dual MOSFET configuration, V2D is fully isolated
from V2 when M4 is not enhanced.
V2D
DG2
CDG2
(13)
DS2
MODE OF OPERATION (DRXN)
10μA
MDG2
CHARGE
PUMP
LT8228
10µA • (CDM1 + CDM2 + CDM4 )
This feature is not available with single MOSFET due to
the M4 body diode connecting V2 to V2D.
V2
TERMINAL
M4
IINRUSH,BUCK =
DG2 OFF
CONTROL
LOGIC
8228 F03
Figure 3. M4 Control in Buck and Boost Mode
The DRXN pin selects the LT8228 mode of operation.
Pulling the pin high selects buck regulation mode and
pulling the pin low selects boost regulation mode. Drive
the DRXN pin with either external logic for manual control
or connect a pull-up resistor to INTVCC or an external
supply for auto-selection. The LT8228 auto-selects the
Rev. 0
28
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LT8228
OPERATION
regulation mode based on the UV1, UV2, FB1 and FB2 pin
voltages. When external logic is used, include the pull-up
resistor for cases where the external logic is accidently
disconnected for increased system reliability. This allows
the LT8228’s auto-selection of the operation mode to take
over. In buck mode, the DRXN pin goes high impedance
which externally pulls the pin voltage high through the
pull-up resistor. In boost mode, a typically 100μA pulldown is enabled which pulls the DRXN pin low.
When the LT8228 is enabled, and the DRXN pin is configured for auto-selection for the mode of operation, the
DRXN pin is high impedance until the internal regulators are functional. The LT8228 then selects the mode of
operation based on the logic shown in Figure 4. If the UV1
pin voltage is higher than 1.2V, the controller is in buck
mode operation. If the UV1 pin voltage is lower than 1.2V,
the controller goes into boost mode. During buck mode
operation, if the UV1 pin voltage drops lower than 1.2V or
FB2 pin voltage stays higher than 1.3V for 1024 switching cycles, the LT8228 changes mode of operation from
buck to boost. Additional time requirement for the FB2
overvoltage ensures no mode hopping during transients
at the load. In boost mode operation if the UV2 pin voltage drops lower than 1.2V or FB1 pin voltage stays higher
than 1.3V for 1024 switching cycles, the LT8228 changes
mode of operation from boost to buck. Anytime both UV1
and UV2 pin voltage drops below 1.2V or both FB1 and
FB2 pin voltage stays higher than 1.3V for 1024 switching
START-UP
(BUCK MODE)
UV1 > 1.2V
UV1 < 1.2V
UV1 < 1.2V
OR
FB2 > 1.3 FOR 1024 CYCLES
BUCK
MODE
UV2 < 1.2V
OR
FB1 > 1.3 FOR 1024 CYCLES
UV1 > 1.2V
OR FB2 < 1.3V
BOOST
MODE
UV2 > 1.2V
OR FB1 < 1.3V
FAULT
(BUCK MODE)
UV1 AND UV2 < 1.2V
OR
FB1 AND FB2 > 1.3 FOR 1024 CYCLES
8228 F04
Figure 4. Automatic Mode of Operation
cycles, the controller goes to buck mode operation, stops
switching, pulls down on the FAULT pin and report the
fault at the REPORT pin. For input undervoltage fault, the
SS pin is also pulled low. Anytime DRVCC or INTVCC pin
voltages fall below their respective undervoltage threshold, the part goes to buck mode, the FAULT and SS pin
pulls low and the LT8228 does not switch.
During startup or fast transient, output overshoot higher
than 10% is possible at light load. If the overshoot condition last more than 1024-clock cycle, the DRXN will
change state. Ensure minimum loading to avoid unintended DRXN change.
When the DRXN pin is driven high with external logic
for buck mode operation, and the UV1 pin voltage
drops lower than 1.2V or FB2 pin voltage stays higher
than 1.3V for 1024 switching cycles, the LT8228 stops
switching, pulls down on the FAULT and report the fault
at the REPORT pin. When the DRXN pin is driven low with
external logic for boost mode operation, and the UV2 pin
voltage drops lower than 1.2V or FB1 pin voltage stays
higher than 1.3V for 1024 switching cycles, the LT8228
stops switching, pulls down on the FAULT and report the
fault at the REPORT pin. For input undervoltage fault, the
SS pin is also pulled low.
When multiple LT8228s are in parallel, tie all the DRXN
pins together to operate all LT8228s in the same regulation mode. In the parallel configuration, the common
DRXN node must be pulled up to an external voltage
source through a pull-up resistor. If an external voltage
source is not available, each LT8228 needs its own pull-up
resistor in series with a diode whose anode is connected
to its own INTVCC pin. This diode prevents unintentional
boost mode selection when one or more channels are
disabled. Refer to the Paralleling Multiple LT8228s in
Applications Information section for more information.
ENABLE AND SOFT-START (ENABLE AND SS)
The LT8228 enters shutdown through the ENABLE pin.
Pulling this pin below 1.2V typically disables the controller and most of the internal circuitry. Pulling the ENABLE
pin below 0.5V transitions the LT8228 into complete
shutdown where the controller only consumes 2µA of
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29
LT8228
OPERATION
shutdown current from the BIAS pin and 10µA from the
V1 and V2 pins to ground typically. The ENABLE pin can
be directly driven by logic or it can be connected to BIAS
for an always-on operation. In normal operation when
the controller is not switching, the controller consumes
4mA of quiescent current from the BIAS pin, 200µA from
the V1 pin and 10µA from the V2 pin to ground typically.
In buck mode, the LT8228 limits the V1 input and the V2
output current by regulating the ISET1P and ISET2P pin
voltages respectively to the lower of the SS pin voltage
and the internal reference voltage of 1.21V typically. The
SS pin programs a current limit soft-start when connecting an external capacitor, CSS, from the SS pin to ground,
limiting inrush current during start-up. When the LT8228
is enabled, after the DRVCC and INTVCC voltages exceed
their undervoltage thresholds, and after the internal diagnostics are successfully completed, DG1 pin is charged
with a 10μA pull-up current. If dual MOSFET configuration
is used at the V1 terminal, inrush current is controlled
through CDG1 and V1D is charged to V1 as DG1 voltage
exceeds it undervoltage threshold. If single MOSFET configuration is used, V1D is a forward diode drop away from
V1 at start-up and charged to V1 as DG1 rises. Next, DG2
starts charging and after DG2 voltage exceeds its threshold voltage, an internal 10μA pull-up current charges the
CSS capacitor and creates a voltage ramp on the SS pin.
As the SS voltage rises linearly from 0V to the internal
reference voltage, the LT8228 starts switching and the
input and output current limits are increased to the values
set by the RSET1P and RSET2P resistors respectively.
In boost mode, the LT8228 limits the V2 input and the V1
output current by regulating the ISET2N and ISET1N pin
voltages respectively to the lower of the SS pin voltage and
the internal reference voltage of 1.21V typically. Similar
to the buck mode, the SS pin programs a soft-start when
connecting an external capacitor, CSS, from the SS pin to
ground. When the LT8228 is enabled, after the DRVCC and
INTVCC voltages exceed their undervoltage thresholds,
after the internal diagnostics are successfully completed,
DG2 pin is charged with a 10μA pull-up current. If dual
MOSFET configuration is used at the V2 terminal, inrush
current is controlled through CDG2 and V2D is charged to
V2 as DG2 voltage exceeds it undervoltage threshold. If
single MOSFET configuration is used, V2D is a forward
diode drop away from V2 at start-up and charged to V2
as DG2 rises. Charging V2D also charges V1D through the
body diode of TG MOSFET M3 and inductor. As the DG2
charging continues past its undervoltage threshold, V1D
is higher than V2 due to the residual current of inductor
and reverse current prevention by the body diode of the
TG MOSFET M3. Next DG1 starts charging and the output
current is limited through DG1 by regulating the ISET1N
pin voltage to 1.4V. In addition, the LT8228 includes an
adjustable fault timer to protect the V1 protection MOSFETs
from excessive power dissipation damage. Refer to the V1
Protection MOSFET Controller Operation section for more
details. After DG1 voltage exceeds its threshold voltage,
an internal 10μA pull-up current charges the CSS capacitor and creates a voltage ramp on the SS pin. As the SS
voltage rises linearly from 0V to the internal reference
voltage, the LT8228 starts switching and the input and
output current limits are increased to the values set by
the RSET2N and RSET1N resistors respectively.
When the LT8228 is disabled, or a fault is detected (refer
to the Fault Conditions in Applications Information section
for all the fault conditions), the LT8228 stops switching and the SS pin is actively pulled low by an internal
MOSFET to reset the soft-start.
PARALLELING MULTIPLE CONTROLLERS
(ISHARE AND IGND)
The LT8228 provides masterless fault tolerant output current sharing among multiple LT8228s in parallel, enabling
higher load current, better heat management and redundancy. Each LT8228 regulates to the average output current eliminating the need for a master controller. When
an individual LT8228 is disabled or in a fault condition, it
stops contributing to the average bus, making the current
sharing scheme fault tolerant. When multiple LT8228s are
in parallel, all the DRXN pins are tied together to operate
all LT8228s in the same regulation mode.
In buck mode when DRXN is high, the ISHARE pin outputs a current equal to the current out of the ISET2P pin
which represents V2 output current. In boost mode when
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LT8228
OPERATION
LT8228
µC VDD
RDRXN
RSET1N ISET1N
VL
RSET2P
In buck mode, ISET2P pin voltage regulates to the ISHARE
pin voltage. To regulate each LT8228’s V2 output current
to the average output current, make RSET2P and RSHARE
equal. In boost mode, ISET1N pin voltage regulates to the
ISHARE pin voltage. To regulate each LT8228’s V1 output
current to the average output current, make RSET1N and
RSHARE values equal. If RSET2P and RSET1N are set at different values, change the value of RSHARE based on the
mode of operation defined by the DRXN pin.
VSHARE
IV1BOOST
IV2BUCK
ISET2P
VH
DRXN
EN
100μA
ISHARE
ISHARE1
RSHARE1
IGND
DRXN + IGND
CONTROL
PHASE 1
RSET1N
ISET1N
ISHARE
RSET2P
ISET2P
DRXN
RSET1N
RSHARE2
PHASE 2
IGND
ISET1N
ISHARE
RSET2P
ISHARE2
LT8228
ISHAREN
LT8228
ISET2P
DRXN
RSHAREN
PHASE N
CSHARE
IGND
8228 F05
Figure 5. ISHARE and IGND Connection
DRXN is low, the ISHARE pin outputs a current equal to
the current out of the ISET1N pin which represents V1
output current. Each LT8228 contributes this current into
the common ISHARE node. When paralleling, the ISHARE
pins of all the LT8228s are tied together as shown in
Figure 5. For each LT8228, a local resistor RSHARE is connected from the ISHARE pin to its own IGND pin. Connect
a filtering capacitor between the ISHARE pin and ground
for average current regulation. The voltage at the common
ISHARE node VSHARE is found according to Equation 14.
VSHARE =
N
∑ n=1ISHAREn
1
N
∑ n=1
R SHAREn
(14)
When all the RSHARE resistors are equal, VSHARE represents the average output current IOUTAVG as shown in
Equation 15.
IOUTAVG =
1 N
∑ ISHAREn
N n=1
N
R
ISHARE = SHARE ∑ ISHAREn = IOUTAVG • R SHARE
N n=1
(15)
When the LT8228 is enabled and the internal diagnostic routine is passed, the IGND pin connects RSHARE to
ground through a typically 120Ω switch. During shutdown or a faulted condition, ISHARE stops generating
current and the switch at the IGND pin is opened so that
no current flows through the current sharing resistor. This
disconnects the RSHARE resistor from the VISHARE node
so that VISHARE continues to represent the average output current of the remaining active LT8228’s in parallel.
With this scheme, any paralleled LT8228 can be added
or subtracted without affecting current sharing accuracy.
The IGND pin along with the ISHARE pin provides current sharing that is masterless as well as fault tolerant.
Refer to the Paralleling Multiple LT8228s in Applications
Information section for more information.
BIAS SUPPLY AND VCC REGULATORS
Power for the top and bottom N-channel MOSFET drivers
comes from the DRVCC pin. An internal LDO (low-dropout
linear regulator) supplies 10V to DRVCC from the BIAS
pin. Another internal LDO generates 4V at the INTVCC pin
from DRVCC. The INTVCC LDO supplies the internal lowvoltage start-up and regulation circuitry. To enable the
LT8228, a minimal 8V BIAS supply is needed. If no external voltage source is available, BIAS can be connected to
either V1 or V2 or both diode-ORed for redundancy. If the
BIAS supply experiences negative voltage, place a diode
in series. Attention should be made to the power dissipation inside the controller by supplying BIAS with a lower
voltage supply if available.
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31
LT8228
OPERATION
STRONG GATE DRIVERS
The LT8228 contains very low impedance drivers capable
of supplying amperes of current to slew large N-channel
MOSFET gates quickly. These strong drivers minimize
transition losses and allow paralleling MOSFETs for higher
current applications. A 100V capable floating high side
gate driver controls the top MOSFET M2 and a low side
gate driver drives the bottom MOSFET M3. The DRVCC
LDO directly supplies the bottom side gate drive circuitry.
The top gate drivers are biased from the floating bootstrap
capacitor, CBST, which is recharged during each bottom
gate off cycle through an external diode from DRVCC. In
low dropout conditions where it is possible that the bottom MOSFET will be off for an extended period, an internal
timeout guarantees that the bottom MOSFET is turned on
at least once every 50μs to refresh CBST typically.
FREQUENCY SELECTION, SPREAD SPECTRUM AND
PHASE-LOCKED LOOP (RT AND SYNC)
The selection of switching frequency is a trade-off
between efficiency and component size. Low frequency
operation increases efficiency by reducing N-channel
MOSFET switching losses but requires larger inductance
and/or capacitance to maintain low output ripple voltage.
The switching frequency of the LT8228 gate drive controllers is selected using the RT pin. If the SYNC pin is not
being driven by an external clock source, the RT pin can
be used to program the controller’s operating frequency
from 80kHz to 600kHz. A single resistor from the RT pin to
ground determines the switching frequency. The controller regulates the RT pin voltage to 800mV. The regulated
current through the RT resistor commands a specific frequency. See the Applications Information section for the
method of selecting RT for a fixed frequency.
An integrated phase-locked loop (PLL) and filter network
synchronizes the internal oscillator to an external clock
source driving the SYNC pin. The PLL locks to any frequency in the range of 80kHz to 600kHz. The frequency
setting resistor RRT must always be present to (1) set
the controller’s initial switching frequency before locking
to the external clock and (2) provide a default switching
frequency if the external clock source is no longer present.
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve the EMI performance, the LT8228
includes the ability to spread out the frequency spectrum
of the external N-channel MOSFETs. This spreading feature is only available when the frequency of the controller
is set by the RT pin. Setting the SYNC pin to logic high
typically above 1V will activate the spread spectrum capability. If enabled, the spread spectrum feature modulates
the internal clock frequency ±30% of the full-scale value
programmed by the RT pin resistor. To disable the spread
spectrum feature, connect SYNC to ground.
FAULT MONITORING AND REPORT FEATURE
The LT8228 provides internal and external fault monitoring
and reporting. The part checks and reports the functionality of the error amplifiers, current sense amplifiers and the
oscillator at start-up while the internal reference, temperature, internal regulators and DG pin voltages are checked
and reported continuously. See the FAULT Conditions and
REPORT Feature in the Applications Information section
for full list of all the external faults. If the controller detects
any fault, switching stops, FAULT pin is pulled and low and
the failure is reported at the REPORT pin. The REPORT
pin uses the SYNC pin as its data clock. Therefore, the
report functionality is only available when the LT8228 is
syncing to an external clock. The continuous monitoring
and the reporting function allow the controller to improve
the safety rating of the system it is used in. Refer to the
Applications Information section for more details.
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LT8228
APPLICATIONS INFORMATION
INTRODUCTION
The Applications Information section serves as a guideline
for selecting external component based on the details of
the application. For this section, refer to the typical application circuit in the front page and the Block Diagram section. Component selection typically follows the approach
described below.
1. Switching frequency (fSW) and Inductor value (L) are
chosen to optimize efficiency, physical size and cost.
2. The inductor current sense resistor RSNS2 along with its
input gain resistors RIN2 are selected for peak inductor
current limit, efficiency and current sense accuracy.
3. The buck output current limit, boost input current limit,
and V2 current monitor are set by the RSET2P, RSET2N
and RMON2 resistors respectively. The V1 current sense
resistor RSNS1 along with its input gain resistors RIN1
is selected to optimize efficiency and current sense
accuracy. Then the boost output current limit, buck
input current limit, and V1 current monitor are set by
the RSET1N, RSET1P and RMON1 resistors respectively.
Capacitors parallel to the RSET resistors are selected
to set the current limits to the average current of the
current sense resistors.
4. The regulation voltages and overvoltage thresholds of
V1D and V2D are set by selecting the resistive dividers
to the FB1 and FB2 pins. The undervoltage threshold
of V1 and V2 are set by selecting the resistive dividers
to the UV1 and UV2 pins.
5. MOSFETs (M1, M2, M3 and M4) are selected based
on efficiency and breakdown voltage considerations.
Schottky diodes (D2 and D3) (optional) are selected
based on efficiency consideration. Top MOSFET driver
supply (CBST, DBST) are selected to store adequate
charge to drive the top MOSFET.
6. The capacitor CDM2 is chosen to optimize the buck input
and boost output ripple voltage and thermal requirements. Likewise, the capacitor CDM4 is chosen to optimize the boost input and buck output ripple voltage
and thermal requirements. The capacitor CDM1 at V1D
pin is used to bypass noise. The dampening capacitor
CV1 and CV2 are selected with their ESR to reduce the
resonance due to series wire inductance connected to
V1 and V2 respectively.
7. The compensations for the buck and boost regulation
loops are chosen to optimize bandwidth and stability.
8. Inrush current control limits are set by choosing CDG1
and CDG2. RDG1 is set to compensate boost mode output current limit loop when V1D is higher than V1.
9. CSS is selected to set soft-start behavior.
The examples and equations in this section assume continuous conduction mode unless otherwise noted. All
electric characteristics referred to in this section represent
typical values unless otherwise specified.
PROGRAMMING THE SWITCHING FREQUENCY
The RT frequency adjust pin allows the user to program
the switching frequency from 80kHz to 600kHz to optimize efficiency/performance and external component
size. Higher frequency operation yields smaller component size but increases switching losses and gate driving
current and may not allow sufficiently high or low duty
cycle operation. Lower frequency operation gives better
performance at the cost of larger external component
size. For an appropriate RT resistor value see Table 1. An
external resistor from the RT pin to ground is required.
Do not leave this pin open. Refer to the RT Pin Resistance
vs Switching Frequency curve in the Typical Performance
Characteristics section.
Table 1. RT Pin Resistance vs Switching Frequency
RRT (k)
fPROG
(kHz)
RRT (k)
fPROG
(kHz)
RRT (k)
fPROG
(kHz)
124
81
61.9
158
30.9
303
110
91
57.6
169
28.7
325
100
100
53.6
181
26.7
347
97.6
102
51.1
190
24.3
378
82.5
120
48.7
199
22.6
403
78.7
126
43.2
222
20.0
450
75.0
132
40.2
238
17.8
499
69.8
141
38.3
249
15.8
552
64.9
151
34.0
278
14.0
604
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LT8228
APPLICATIONS INFORMATION
FREQUENCY SYNCHRONIZATION AND
SPREAD SPECTRUM
The LT8228 switching frequency can be synchronized to an
external clock using the SYNC pin. The rising edge of the
external clock signal is synced with the turn-on of the top
MOSFET in forward buck mode or bottom MOSFET in reverse
boost mode. Driving SYNC with a 50% duty cycle waveform
is strongly recommended, otherwise maintain the duty cycle
between 5% and 95%. When there is no clock signal at the
SYNC pin, it is used as the enable pin for spread spectrum.
If there is a logic high DC signal at the SYNC pin, spread
spectrum is enabled. The threshold for logic high is 1V. The
spread spectrum feature modulates the internal clock frequency between ±30% of the base frequency set by the RT
pin resistor. At logic low signal at the SYNC pin, the controller
operates with the frequency set by RT pin without any spread
spectrum. The threshold for logic low signal is 0.5V.
INDUCTOR SELECTION
The selection of the LT8228’s inductor value is driven
by a trade-off between component size, efficiency and
operating frequency of the system. The inductor value has
a direct effect on its ripple current. Lower ripple current
reduces core losses in the inductor, ESR losses in the
capacitors and output ripple voltage. Highest efficiency
operation is obtained at low frequency with small ripple
current. However, achieving this requires a large inductor.
A reasonable starting point is to choose a peak-to-peak
ripple current that is 20% to 40% of the maximum average current of the inductor. Due to the bidirectional capability of the LT8228, the same inductor is used for both
buck and boost regulation. In buck mode, the inductor
current is the V2 output current and in boost mode, the
inductor current is the V2 input current. For a given inductor ripple current, the minimum inductor value in buck
and boost mode for their respective maximum average
current is given by Equation 16.
L BUCK >
V2 • (V1(MAX) – V2 )
ƒ • ∆IL • V1(MAX)
V • (V1 – V2 )
L BOOST > 2
ƒ • ∆IL • V1
(16)
where ƒ is switching frequency and ∆IL is the inductor
ripple current. For buck mode operation, the maximum
ripple current occurs when the input voltage V1 is highest.
For boost mode operation, the maximum ripple occurs
when the input voltage V2 is half of the output voltage
V1. For bidirectional operation, the chosen inductor value
should satisfy both minimum conditions set by the buck
and boost modes.
In addition to ripple requirements, the inductance should
be large enough to prevent subharmonic oscillations. In
a current mode regulator, the current sense loop creates
a double pole at half the switching frequency which can
degrade system stability when its quality factor (QCS) is
much greater than 1.0. The current sense loop damping
is a function of the slopes of the inductor current and the
internal slope compensating ramp. Lowering the inductance increases QCS, and a sufficiently undersized inductor will result in subharmonic oscillation for duty cycles
above 50% The minimum inductance for subharmonic
stability is given by Equation 17.
R
1
L SUBHARMONIC,MIN > 2 • 10 5 • SNS2 •
RIN2 fSW
(17)
The LT8228 slope compensation scheme is designed to
provide single-cycle settling of the current sense loop
(QCS = 0.637) when the inductor value is twice the minimum for subharmonic stability. This simplifies loop compensation as the current sense loop damping becomes
independent of duty cycle and switching region. Selecting
LOPTIMAL also optimizes line regulation and line step
response performance (see Equation 18).
R
1
L OPTIMAL > 4 • 10 5 • SNS2 •
RIN2 fSW
(18)
If V2 is higher than 50V in buck mode or the difference
between V1D and V2 is higher than 50V in boost mode,
the optimal inductor value is higher than the value stated
in the equation. Increase the inductor value by the same
percentage increase in V2 in buck mode or in the difference between V1D and V2 after 50V to get the optimal
value.
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LT8228
APPLICATIONS INFORMATION
For high efficiency, choose an inductor with low core
loss. Also, the inductor should have low DC resistance to
reduce the I2R losses and must be able to handle the peak
inductor current without saturating. To minimize radiated
noise, use a shielded inductor.
ILMAXBUCK =
1 V2 • (V1(MAX) – V2 )
ƒ • L • V1(MAX)
(19)
1 V2 • (V1 – V2 )
2
ƒ • L • V1
SNS2P
LT8228
RIN2
SNS2N
IB2
PEAK
DETECT
V2D
IB2
ICSA2
CURRENT SENSE
AMPLIFIER 2 (CSA2)
8228 F06
ISNS2 = IL – (IB2 +ICSA2 )
90µA FOR V
> 2.5V
IB2 = { –50µA FOR SNS2P
VSNS2P = 0V
•R
I
ICSA2 = SNS2 SNS2
RIN2
R • 72.5µA
IL(PEAK) = IN2
FOR IL >> IB2 = ICSA2
R SNS2
Figure 6. V2 Current Sense Amplifier Operation for
Positive Inductor Current
ILMAXBOOST =
I V2N(LIM) +
RSNS2
72.5µA
The LT8228 sets the peak inductor current by selecting
the current sense resistor RSNS2 and the input gain resistors RIN2. To select a peak inductor current, start with
finding the maximum current in the inductor. The LT8228
uses the same inductor for both the buck and boost mode
operation. In buck mode, inductor current is the V2 output current and in boost mode, the inductor current is
the V2 input current. For maximum inductor current in
each mode, add the maximum average current and half
the maximum peak-to-peak ripple current as shown in
Equation 19.
2
ISNS2
L
RIN2
RSNS2 AND RIN2 SELECTION FOR PEAK
INDUCTOR CURRENT
I V2P(LIM) +
IL
where ƒ is the switching frequency, L is the selected
inductor value, IV2P(LIM) is the buck mode V2 output current limit and IV2N(LIM) is the boost mode V2 input current
limit. ADI recommends setting the peak inductor current
at least 20% to 30% above the higher maximum inductor
current of the buck and boost modes. This ensures the
maximum average current regulation is not affected by the
peak inductor current limit in either mode of operation.
The inductor current is sensed using RSNS2 which is
placed in series with the inductor. Current sense polarity
is positive when current flows from the inductor to V2D.
Input gain resistors RIN2 are placed between RSNS2 and
the positive and negative sense pins, SNS2P and SNS2N
of the V2 bidirectional current sense amplifier CSA2 as
shown in Figure 6. The figure shows the circuit operation
of CSA2 for positive inductor current. When there is no
inductor current, both sense pins draw equal bias currents IB2 through RIN2. As inductor current flows through
RSNS2, CSA2 draws feedback current ICSA2 to servo the
SNS2P pin to the SNS2N pin voltage. The current through
RSNS2 is equal to the inductor current for inductor currents much larger than CSA2’s bias and feedback currents. The peak inductor current IL(PEAK) is detected
when ICSA2 reaches 72.5µA typically. When the current
through the sense resistor reverses direction, the current
sense amplifier is reconfigured to draw feedback current
to servo the SNS2N pin to the SNS2P pin voltage. As a
result, the peak inductor current is same in both buck and
boost mode of operation.
High RSNS2 values improve current sense accuracy while
low RSNS2 values improve efficiency. Input referred offset voltage of CSA2 is guaranteed across temperature to
±0.5mV at 50µA feedback current. Maximum power loss
occurs at the peak inductor current. Select the value of
RSNS2 so that the input referred offset voltage does not
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LT8228
APPLICATIONS INFORMATION
affect current sense accuracy while minimizing power
loss. ADI recommends a RSNS2 value that sets the voltage across RSNS2 at the peak inductor current between
50mV to 200mV. The power dissipation at the current
sense amplifier should not exceed its power rating for all
operating conditions.
Next, select RIN2 to set the peak inductor current limit
according to Equation 20.
RIN2 =
IL(PEAK) • R SNS2
72.5µA
(20)
RSET2P SELECTION FOR V2 OUTPUT CURRENT LIMIT
(BUCK MODE)
In buck mode, V2 output current limit is programmed by
connecting a resistor RSET2P from ISET2P to ground. The
V2 current sense amplifier CSA2 outputs current at the
ISET2P pin that is proportional to the current ISNS2 flowing through the sense resistor RSNS2 as shown in Figure 7.
The current through the sense resistor is equal to the V2
output current for V2 output currents much higher than
CSA2’s input bias current as stated in the RSNS2 and RIN2
Selection for Peak Inductor Current section.
The typical bias current into the SNS2P and SNS2N pins
is 90µA. For input common mode voltage lower than 2.5V,
the bias currents decrease and reverse polarity. When
the input common mode voltage reaches 0V, the typical
bias current is −50µA. Refer to the Input Bias Current
curve in the Typical Performance Characteristics section
for more information.
ISNS2
The CSA2 is internally compensated. Any capacitive load
at the SNS2P and SNS2N affects the feedback compensation of the amplifier and makes it unstable.
V2D
RIN2
RIN2
SNS2P
SNS2N
ICSA2 + IB2
LT8228
IB2
1.21V
CSA2
The current sense resistor RSNS2 and input gain resistors RIN2 are also used to sense the V2 output current in
buck mode and V2 input current in boost mode. In buck
mode, the sensed V2 output current is generated out of
the ISET2P and IMON2 pins for output current regulation
and monitoring. In boost mode, the sensed V2 input current is generated out of the ISET2N, ISHARE and IMON2
pins for output current regulation, sharing and monitoring. Refer to the ISET2P, ISET2N, ISHARE and IMON2 gain
error curves in the Typical Performance Characteristics
section for more information.
Additionally, the current sense resistor RSNS2 and input
gain resistors RIN2 are used to sense BG or TG MOSFET
short fault. During such short faults, the current through
RSNS2 is higher than peak current. A short fault current
is detected when ICSA2 reaches 105µA typically. Anytime
such a fault is detected through RSNS2 , the LT8228 shuts
down all four external N-channel MOSFETs, pulls the SS
pin low, asserts the FAULT pin, IGND goes high impedance and reports the status at the REPORT pin. The part
restarts after waiting 1024 switching clock cycles.
IV2
RSNS2
L
VC2
FB2
1.21V
SS
ICSA2
ISET1P
RC2
VIREF
MIN
CC2
MAX
ERROR AMPLIFIER 2
EA2
ISET2P
8228 F07
CSET2P
RSET2P
ISET2P =
ISNS2 • R SNS2
RIN2
I V2 = ISNS2 – IB2
I V2P(LIM) =
RIN2 • VIREF
R SNS2 • R SET2P
FOR I V2 >> IB2
VIREF IS LOWER OF THE VSS AND 1.21V
Figure 7. V2 Input Current Limit Programming at ISET2P
During current limit, the LT8228 regulates the voltage at
the ISET2P pin to the typical internal reference voltage
of 1.21V. For V2 output current limit IV2P(LIM), calculate
RSET2P according to Equation 21.
R SET2P =
RIN2 • 1.21V
R SNS2 • I V2P(LIM)
(21)
For example, if the values of RSNS2 and RIN2 set to 2mΩ
and 1.5k respectively, setting RSET2P to 22.6k programs
the V2 output current limit to 40.1A. During current limit,
current out of the ISET2P pin is 53.5µA.
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LT8228
APPLICATIONS INFORMATION
The current at the ISET2P pin represents the inductor
current. To ensure the current limit is set to the desired
average current, a parallel capacitor CSET2P to RSET2P is
required. The parallel capacitor CSET2P reduces the ripple voltage at the ISET2P pin and duty cycle jitter due
to noise. The capacitor CSET2P should not be arbitrarily
large as it will affect the stability of the current regulation
loop. Stability of the current regulation loop is discussed
in detail in the Regulation Loop and Stability section.
The current at the ISET2N pin represents the inductor
current. To ensure the current limit is set to the desired
average current, a parallel capacitor CSET2N to RSET2N is
required. The parallel capacitor CSET2N reduces the ripple
voltage at the ISET2N pin and duty cycle jitter due to
noise. The capacitor CSET2N should not be arbitrarily large
as it will affect the stability of the current regulation loop.
Stability of the current regulation loop is discussed in
detail in the Regulation Loop and Stability section.
For applications such as battery charging and discharging, the V2 output current limit is set according to the
charge current requirement. If V2 is connected to a current or resistive load, set the V2 output current limit 10%
to 20% above the maximum load current to allow for
large transient events and IV2P(LIM) threshold variations.
Dynamic current control can also be achieved through
modulating the ISET2P pin resistance. Some dynamic
methods include digital potentiometers or modulating
the ground node of the ISET2P resistor using a DAC or
injecting and subtracting current from the ISET2P node.
For applications such as battery charging and discharging,
the V2 input current limit is set according to the discharge
current requirement. If V1 is connected to a current or
resistive load, set the V2 input current limit 10% to 20%
above the maximum input current required to provide the
maximum load current at V1 to allow for large transient
events and IV2N(LIM) threshold variations. Dynamic current control can also be achieved through modulating the
ISET2N pin resistance. Some dynamic methods include
digital potentiometers or modulating the ground node of
the ISET2N resistor using a DAC or injecting and subtracting current from the ISET2N node.
RSET2N SELECTION FOR V2 INPUT CURRENT LIMIT
(BOOST MODE)
ISNS2
L
In boost mode, V2 input current limit is programmed by
connecting a resistor RSET2N from ISET2N to ground.
The V2 current sense amplifier CSA2 outputs current at
the ISET2N pin that is proportional to the current ISNS2
flowing through the sense resistor RSNS2 as shown in
Figure 8. The current through the sense resistor is equal
to the V2 input current for V2 input currents much higher
than CSA2’s input bias and feedback currents as stated
in the Peak Inductor Current section.
During current limit, the LT8228 regulates the voltage at
the ISET2N pin to the typical internal reference voltage
of 1.21V. For V2 input current limit IV2N(LIM), calculate
RSET2N according to Equation 22.
R SET2N =
RIN2 • 1.21V
R SNS2 • I V2N(LIM)
RIN2
V2D
RIN2
SNS2P
IB2
SNS2N
LT8228
IB2 + ICSA2
CSA2
1.21V
VC1
FB1
1.21V
SS
ICSA2
ISET1N
MIN
MAX
ISET2N
RC1
VIREF
CC1
ERROR AMPLIFIER 1
EA1
8228 F08
CSET2N
RSET2N
ISET2N =
–ISNS2 • R SNS2
RIN2
–I V2 = –ISNS2 +IB2 +ICSA2
I V2N(LIM) =
(22)
For example, if the values of RSNS2 and RIN2 set to 2mΩ
and 1.5k respectively, setting RSET2N to 22.6k programs
the V2 input current limit to 40A. During current limit,
current out of the ISET2N pin is 53.5µA.
IV2
RSNS2
RIN2 • 1.21V
R SNS2 • R SET2N
FOR –I V2 >> IB2 +ICSA2
VIREF IS LOWER OF THE VSS AND 1.21V
Figure 8. V2 Input Current Limit Programming at ISET2N
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37
LT8228
APPLICATIONS INFORMATION
RMON2 SELECTION FOR V2 CURRENT MONITORING
The current out of IMON2 pin is equal to the absolute voltage across the current sense resistor RSNS2 divided by the
value of the input sense resistor RIN2 as shown in Figure 9.
This current represents V2 output current in buck mode
and V2 input current in boost mode. Connecting a resistor
RMON2, from IMON2 to ground generates a voltage VMON2
for monitoring by an ADC. The maximum output voltage
VMON2MAX is typically set to be between 80% to 90% of
the ADC input dynamic range. Limit VMON2MAX to less
than 2.5V. Calculate the value of RMON2 with Equation 23.
R MON2 =
RIN2
ISNS2MAX • R SNS2
VMON2MAX
(23)
where ISNS2MAX is the greater of the programmed V2
output current limit IV2P(LIM) in buck mode and the programmed V2 input current limit IV2N(LIM) in boost mode.
A filtering capacitor CMON2 can be added to reduce ripple
voltage at the IMON2 pin.
For positive current through RSNS2 , V2 output current is
less by CSA2’s bias current. For negative current through
RSNS2, V2 input current is greater by CSA2’s bias and
feedback currents. As a result, for low V2 currents, CSA2’s
ISNS2
ISNS1
RSNS1
V1D
SNS2P
SNS2N
ISNSN2
RIN1
LT8228
SNS1P
TO M2
RIN1
SNS1N
–
IMON2 = |ISNSP2 – ISNSN2 |
| •R
|
= ISNS2 SNS2
RIN2
CSA2
±
ICSA2
The typical bias current into the SNS1P and SNS1N pins
is 90µA. For input common mode voltage lower than 2.5V,
the bias currents decrease and reverse polarity. When
the input common mode voltage reaches 0V, the typical
bias current is –50µA. Refer to the Input Bias Current
curve in the Typical Performance Characteristics section
for more information.
IV1
RIN2
+
The V1 current sense resistor RSNS1 and input gain resistor RIN1 are used to sense the V1 input current in buck
mode and V2 output current in boost mode. RSNS1 is
placed between V1D and the drain of the top MOSFET.
The V1 current sense amplifier CSA1 operates similarly
as the V2 current sense amplifier as shown in Figure 10.
For positive current through RSNS1, CSA1 draws feedback current ICSA1 to servo the SNS1P pin to the SNS1N
pin voltage. For negative current, CSA1 draws feedback
current to servo the SNS1N pin to the SNS1P pin voltage. The current through RSNS1 is equal to V1 current for
V1 currents much larger than CSA1’s bias and feedback
currents.
V2D
RIN2
ISNSP2
RSNS1 AND RIN1 SELECTION
IV2
RSNS2
L
bias and feedback currents introduce error to the current
monitor output IMON2.
IB1
IB1
ISNS1 = I V1 – (IB1 +ICSA1)t
VMON2 = IMON2 • R MON2
90µA FOR V
2.5V
IB1 = { –50µA FOR SNS1P
VSNS1P = 0V
LT8228
•R
I
ICSA1 = SNS1 SNS1 ≤ 72.5µA
RIN1
ICSA1
IMON2
8228 F09
VMON2
CMON2
CURRENT SENSE
AMPLIFIER 1 (CSA1)
RMON2
8228 F10
Figure 9. V1 V2 Current Monitoring at IMON2
Figure 10. V1 Current Sense Amplifier Operation
for Positive Current
Rev. 0
38
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LT8228
APPLICATIONS INFORMATION
In buck mode, CSA1’s feedback current is generated out
of the ISET1P and IMON1 pins for input current regulation
and monitoring. In boost mode, CSA1’s feedback current
is generated out of the ISET1N, ISHARE and IMON1 pins
for output current regulation, sharing and monitoring.
Refer to the ISET1P, ISET1N, ISHARE and IMON1 gain
error curves in the Typical Performance Characteristics
section for more information.
High RSNS1 values improve current sense accuracy while
low RSNS1 values improve efficiency. Input referred offset voltage of CSA1 is guaranteed across temperature
to ±0.5mV at 50µA feedback current. Select the value of
RSNS1 so that the input referred offset voltage does not
affect current sense accuracy while minimizing power
loss. The current through RSNS1 is discontinuous in both
buck and boost mode. the voltage across RSNS1 is highest at the peak inductor current. However, power loss at
the sense resistor depends on the peak inductor current,
power stage duty ratio, and the capacitors at the RSNS1
terminals. ADI recommends a RSNS1 value that sets the
maximum voltage across RSNS1 to a value between 50mV
to 200mV. The power dissipation at the current sense
amplifier should not exceed its power rating for all operating conditions.
Next, select RIN1 to set the gain of the V1 current sense
amplifier to maintain the following condition for current
sense accuracy (see Equation 24).
ISNS1(MAX) • R SNS1
RIN1 >
72.5µA
RSET1P SELECTION FOR V1 INPUT CURRENT LIMIT
(BUCK MODE)
In buck mode, V1 input current limit is programmed by
connecting a resistor RSET1P from ISET1P to ground.
The V1 current sense amplifier CSA1 outputs current at
the ISET1P pin that is proportional to the current ISNS1
flowing through the sense resistor RSNS1 as shown in
Figure 11. The current through the sense resistor is equal
to the V1 input current for V1 input currents much higher
than CSA1’s input bias and feedback currents as stated
in the RSNS1 and RIN1 Selection section.
During current limit, the LT8228 regulates the voltage at
the ISET1P pin to the typical internal reference voltage
of 1.21tV. For V1 output current limit IV1P(LIM), calculate
RSET1P according to Equation 25.
R SET1P =
IV1
RIN1 • 1.21V
R SNS1 • I V1P(LIM)
ISNS1
RSNS1
V1D
TO M2
RIN1
RIN1
SNS1P
SNS1N
ICSA1 + IB1
LT8228
IB1
CSA1
(24)
Additionally, the current sense resistor RSNS1 and input
gain resistors RIN1 are used to sense BG or TG MOSFET
short fault. A short fault current is detected when ICSA1
reaches 120µA typically. Anytime such a fault is detected
through RSNS1, the LT8228 shuts down all four external
N-channel MOSFETs, pulls the SS pin low, asserts the
FAULT pin, IGND goes high impedance and reports the
status at the REPORT pin. The part restarts after waiting
1024 switching clock cycles. The CSA1 is internally compensated. Any capacitive load at the SNS1P and SNS1N
affects the feedback compensation of the amplifier and
makes it unstable.
(25)
1.21V
VC2
FB2
1.21V
SS
ICSA1
ISET2P
RC2
VIREF
MIN
CC2
MAX
ERROR AMPLIFIER 2
EA2
ISET1P
8228 F11
CSET1P
RSET1P
ISET1N =
ISNS1 • R SNS1
RIN1
I V1 = ISNS1 – IB1
I V1N(LIM) =
RIN1 • 1.21V
R SNS1 • R SET1N
FOR I V1 >> IB1
VIREF IS LOWER OF THE VSS AND 1.21V
Figure 11. V1 Output Current Limit Programming at ISET1P
Rev. 0
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39
LT8228
APPLICATIONS INFORMATION
For example, if the values of RSNS1 and RIN1 set to 2mΩ
and 1.5k respectively, setting RSET1P to 37.4k programs
the V1 input current limit to 24.3A. During current limit,
current out of the ISET1P pin is 32.4µA.
of 1.21V. For V1 input current limit IV1N(LIM), calculate
RSET1N according to Equation 26.
The current at the ISET1P pin represents the inductor
when the top MOSFET is on during switching. The current is discontinuous with high slew rate. To ensure the
current limit is set to the desired average current, a parallel capacitor CSET1P to RSET1P is required. The parallel
capacitor CSET1P reduces the ripple voltage at the ISET1P
pin and duty cycle jitter due to noise. The capacitor CSET1P
should not be arbitrarily large as it will affect the stability of the current regulation loop. Stability of the current
regulation loop is discussed in detail in the Regulation
Loop and Stability section.
For applications such as battery charging and discharging,
the V1 input current limit is set according to the discharge
current requirement. If V2 is connected to a current or
resistive load, set the V1 input current limit 10% to 20%
above the maximum input current required to provide the
maximum load current at V2 to allow for large transient
events and IV1P(LIM) threshold variations. Dynamic current control can also be achieved through modulating the
ISET1P pin resistance. Some dynamic methods include
digital potentiometers or modulating the ground node of
the ISET1P resistor using a DAC or injecting and subtracting current from the ISET1P node.
RSET1N SELECTION FOR V1 OUTPUT CURRENT LIMIT
(BOOST MODE)
In buck mode, V1 output current limit is programmed
by connecting a resistor RSET1N from ISET1N to ground.
The V1 current sense amplifier CSA1 outputs current at
the ISET1N pin that is proportional to the current ISNS1
flowing through the sense resistor RSNS1 as shown in
Figure 12. The current through the sense resistor is equal
to the V1 output current for V1 output currents much
higher than CSA1’s input bias current as stated in the
RSNS1 and RIN1 Selection section.
During current limit, the LT8228 regulates the voltage at
the ISET1N pin to the typical internal reference voltage
RIN1 • 1.21V
R SET1N =
IV1
R SNS1 • I V1N(LIM)
(26)
ISNS1
RSNS1
V1
TO M2
RIN1
RIN1
SNS1P
SNS1N
IB1
LT8228
IB1 + ICSA1
CSA1
1.21V
VC1
FB1
1.21V
SS
ICSA1
ISET2N
MIN
MAX
ISET1N
RC1
VIREF
CC1
ERROR AMPLIFIER 1
EA1
8228 F12
CSET1N
RSET1N
•R
I
ISET1N = SNS1 SNS1
RIN1
I V1 = ISNS1 – IB1
I V1N(LIM) =
RIN1 • 1.21V
R SNS1 • R SET1N
FOR I V1 >> IB1
VIREF IS LOWER OF THE VSS AND 1.21V
Figure 12. V1 Output Current Limit Programming at ISET1N
For example, if the values of RSNS1 and RIN1 set to 2mΩ
and 1.5k respectively, setting RSET1N to 88.7k programs
the V1 output current limit to 10.2A. During current limit,
current out of the ISET1N pin is 13.6µA.
The current at the ISET1N pin represents the inductor
when the top MOSFET is on during switching. The current is discontinuous with high slew rate. To ensure the
current limit is set to the desired average current, a parallel capacitor CSET1N to RSET1N is required. The parallel
capacitor CSET1N reduces the ripple voltage at the ISET1N
pin and duty cycle jitter due to noise. The capacitor CSET1N
should not be arbitrarily large as it will affect the stability of the current regulation loop. Stability of the current
regulation loop is discussed in detail in the Regulation
Loop and Stability section.
Rev. 0
40
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LT8228
APPLICATIONS INFORMATION
For applications such as battery charging and discharging, the V1 output current limit is set according to the
charge current requirement. If V1 is connected to a current or resistive load, set the V1 output current limit 10%
to 20% above the maximum load current to allow for
large transient events and IV1P(LIM) threshold variations.
Dynamic current control can also be achieved through
modulating the ISET1N pin resistance. Some dynamic
methods include digital potentiometers or modulating
the ground node of the ISET1N resistor using a DAC or
injecting and subtracting current from the ISET1N node.
RMON1 SELECTION FOR V1 CURRENT MONITORING
The current out of IMON1 pin is equal to the absolute
voltage across the current sense resistor RSNS1 divided
by the value of the input sense resistor RIN1 as shown in
Figure 13. This current represents V1 input current in buck
mode and V1 output current in boost mode. Connecting
a resistor RMON1, from IMON1 to ground generates a
voltage VMON1 for monitoring by an ADC. The maximum
output voltage VMON1MAX is typically set to be between
80% to 90% of the ADC input dynamic range. Limit
VMON1MAX to less than 2.5V. Calculate the value of RMON1
with Equation 27.
IV1
ISNS1
RSNS1
V1D
TO M2
RIN1
RIN1
SNS1P
SNS1N
ISNSP1
ISNSN1
IMON1 = |ISNSP1 – ISNSN1 |
–
+
| •R
|
= ISNS1 SNS1
RIN1
CSA1
±
ICSA1
VMON1 = IMON1 • R MON1
LT8228
IMON1
8228 F13
VMON1
CMON1
RMON1
Figure 13. V1 Current Monitoring at IMON1
R MON1 =
RIN1
ISNS1MAX • R SNS1
VMON1MAX
(27)
where ISNS1MAX is the greater of the programmed V1 input
current limit IV1PLIM in buck mode and the programmed
V1 output current limit IV1NLIM in boost mode. A filtering
capacitor CMON1 can be added to reduce ripple voltage at
the IMON1 pin.
For positive current through RSNS1, V1 input current is
less by CSA1’s bias and feedback currents. For negative current through RSNS1, V1 output current is greater
by CSA1’s bias current. As a result, for low V1 currents,
CSA1’s bias and feedback currents introduce error to the
current monitor output IMON1.
OUTPUT VOLTAGE, INPUT UNDERVOLTAGE AND
OUTPUT OVERVOLTAGE PROGRAMMING
In buck mode, the LT8228 has a regulated V2D output
voltage range of 1.21V to 100V. The output voltage is set
by the ratio of two external resistors, RFB2A and RFB2B, at
the FB2 pin as shown in Figure 14. The LT8228 servos the
output to maintain the FB2 pin voltage at 1.21V referenced
to ground. Calculate the output voltage using the formula
in Figure 14. In boost mode, the LT8228 has a regulated
V1D output voltage range of 1.21V to 100V. The output
voltage is set by the ratio of two external resistors, RFB1A
and RFB1B, at the FB1 pin. Calculate the V1D output voltage similarly to V2D.
In boost mode, the LT8228 has V2 input undervoltage
detection at the UV2 pin. The falling undervoltage threshold V2UVTH is set by the ratio of two external resistors,
RUV2A and RUV2B, as shown in Figure 14. No DC current flows into the UV2 pin. Calculate the undervoltage
threshold using the formula in Figure 14. In buck mode,
the LT8228 has V1 input undervoltage detection at the
UV1 pin. The falling undervoltage threshold V1UVTH is set
by the ratio of two external resistors, RUV1A and RUV1B.
Calculate the undervoltage threshold similarly to V2UVTH.
After the undervoltage thresholds have triggered, the rising thresholds increase by 100mV typically. If application
does not require reverse voltage protection, the diode in
series with the external resistors is not needed.
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41
LT8228
APPLICATIONS INFORMATION
V1
M1B
M1A V1D
L
M2
V2D M4A
M4B
V2
M3
TG
BG
DG1
DS1
DG2
DS2
RFB2A
RFB1A
FB1
RUV1A
LT8228
FB2
RFB2B
RFB1B
UV1
RUV1B
RUV2A
UV2
RUV2B
8228 F14
⎛ R
⎞
V1D = VFB1 • ⎜ 1+ FB1A ⎟
⎝ R FB1B ⎠
⎛ R
⎞
V2D = VFB2 • ⎜ 1+ FB2A ⎟
⎝ R FB2B ⎠
VFB1 = 1.21V
VFB2 = 1.21V
V1D RANGE = 1.21V TO 100V
V2D RANGE = 1.21V TO 100V
⎛ R
⎞
V1DUVTH = 1.2V • ⎜ 1+ UV1A ⎟+ 0.7V
⎝ R UV1B ⎠
⎛ R
⎞
V2DUVTH = 1.2V • ⎜ 1+ UV2A ⎟+ 0.7V
⎝ R UV2B ⎠
⎛ R
⎞
V1D OVTH = 1.3V • ⎜ 1+ FB1A ⎟
⎝ R FB1B ⎠
⎛ R
⎞
V2D OVTH = 1.3V • ⎜ 1+ FB2A ⎟
⎝ R FB2B ⎠
Figure 14. V2D and V1D Output Voltage, Input
Undervoltage and Output Overvoltage Programming
The output overvoltage threshold is set about 10% higher
than the output regulation voltage. In buck mode, the
LT8228 has V2D output overvoltage detection at the FB2
pin. The rising overvoltage threshold V2DOVTH is set by the
same ratio of the two external resistors, RFB2A and RFB2B,
as shown in Figure 14. In boost mode, the LT8228 has
V1D output overvoltage detection at the FB1 pin. The rising overvoltage threshold V1DOVTH is set by the same ratio
of the two external resistors, RFB1A and RFB1B, as shown
in Figure 14. After the overvoltage thresholds have triggered, the falling thresholds decrease by 100mV typically.
POWER MOSFET SELECTION AND EFFICIENCY
CONSIDERATIONS
The LT8228 requires six external N-channel MOSFETs as
shown in Figure 15: (1) the V1 protection MOFSETs M1A
and M1B, (2) the V2 protection MOSFETs M4A and M4B,
(3) the switching top MOSFET M2 and (4) the switching
bottom MOSFET M3. M1B and M4B are optional if no
inrush current control or protection against M3 short fault
is not required. Important parameters for selecting the
MOSFETs are the breakdown voltage BVDSS, threshold
voltage VGS(TH), on-resistance RDS(ON), maximum power
dissipation PD(MAX) and safe operating area (SOA). For the
switching MOSFETs M2 and M3, the miller capacitance
CMILLER is another important parameter. Since the selection criteria for choosing the protection MOSFETs and the
switching MOSFETs are different, they are discussed in
separate sections.
Protection MOSFETs (M1 and M4) Selection
The drain-to-source breakdown voltage BVDSS of the protection MOSFETs M1 and M4 must be higher than the
maximum drain-to-source voltage that might apply.
For the protection MOSFET M1A, the drain is connected
to V1D. For the protection MOSFET M1B, the drain is connected to the V1 Terminal. The sources of both M1A and
M1B are connected to DS1. If V1 is shorted to ground or
connected to a reverse supply, M1A will be stressed by
the V1D voltage. In buck start-up when V1D voltage is 0V,
M1B will be stressed by the full supply voltage at V1. A
single MOSFET configuration at the V1 terminal will have
the same maximum stress voltage as M1A.
For the protection MOSFET M4A, the drain is connected
to V2D. For the protection MOSFET M4B, the drain is connected to the V2 Terminal. The sources of both M4A and
M4B are connected to DS2. If V2 is shorted to ground or
connected to a reverse supply, M4A will be stressed by
the V2D voltage. In boost start-up when V2D voltage is 0V,
M4B will be stressed by the full supply voltage at V2. A
single MOSFET configuration at the V2 terminal will have
the same maximum stress voltage as M4A.
D2
V1
M1B
M2
M1A
SW
L
M4A
M4B
V2
V1D
CBST
RG1B
DBST
D3
RG4B
M3
DV1
DV2
TG BST
DS1
DG1
DRVCC
LT8228
BG
DS2
DG2
8228 F15
Figure 15. Power MOSFETs and Components Selection
Rev. 0
42
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LT8228
APPLICATIONS INFORMATION
The LT8228 drives the gates of the protection MOSFETs
M1 and M4 to a typical value of 10V above their sources.
Internal clamps limit the gate drives to 12V maximum
across temperature. For applications with V1 or V2 voltages higher than 24V, an external Zener clamp must be
added between the gate and source of M1 and M4 in order
to not exceed the MOSFETs’ VGS(MAX) during extreme
transients. This external Zener clamp can also be used
to lower the gate drive voltage for use with logic-level
MOSFETs. The DG1 and DG2 undervoltage thresholds are
set at 5V typically. The gate drive should not be lower than
5.5V. Also, gate resistors RG1B and RG4B are necessary to
prevent MOSFET parasitic oscillations and must be placed
close to M1B and M4B respectively.
The MOSFETs’ on-resistance, RDS(ON), directly affects the
forward voltage drop and power dissipation. ADI recommends a forward voltage drop VFWD of 100mV or less for
reduced power dissipation. Ensure that the RDS(ON) of the
MOSFETs meet the Equation 28 condition.
R DS(ON) <
VFWD
IM1,4(MAX)
(28)
where IM1,4(MAX) is the maximum current through M1 or
M4. The higher of the V1 input and output current limit
is the maximum current through M1. The higher of the
V2 input and output current limit is the maximum current
through M4.
Next, calculate the maximum power dissipation of the
protection MOSFETs according to Equation 29.
PDM1,4(MAX) = I2M1,4(MAX) • R DS(ON)
(29)
The maximum power dissipation of M1 and M4 should be
lower than the power dissipation parameter given in the
MOSFET’s data sheet. Give careful consideration to the
temperature effect of the MOSFET’s RDS(ON) and PD(MAX)
parameter given in the Typical Characteristics curves in
the MOSFET’s data sheet to ensure the operation of the
MOSFETs in their safe operating area. Multiple MOSFETs
can be used in parallel to lower RDS(ON) and meet power
and thermal requirements.
In buck start-up, when DG1 is turned on, inrush current flows from V1 to charge CDM1 and CDM2. During the
inrush current, M1B is stressed by the full supply voltage.
Control the inrush current to maintain M1B is its safe
operating area. In boost start-up, when DG2 is turned on,
inrush current flows from V2 to charge CDM4 and CDM2.
During the inrush current, M4B is stressed by the full
supply voltage. Control the inrush current to maintain
M4B is its safe operating area. In addition, when DG1
is turned on in boost mode, inrush current flows from
V1D to V1 terminal to charge the output load till V1 and
V1D voltages are equal. During this in-rush period, M1A
is stressed by the voltage at V1D. M1A is again stressed
in boost mode if V1 is shorted to ground. The LT8228
employs an adjustable timer feature to maintain M1A in
its safe operating area. Refer to the Inrush Current Control
section for more information.
Switching MOSFETs (M2 and M3) Selection
The most important parameter for the switching MOSFETs
M2 and M3 in high voltage applications is the breakdown
voltage BVDSS. Both the top gate and bottom MOSFETs
will see maximum input voltage plus any additional ringing on the switch node across their drain-to-source during
their off-time. Therefore, the MOSFETs must be chosen
with the appropriate breakdown specification.
Since most MOSFETs in the 60V to 100V range have
higher thresholds (typically VGS(TH) ≥ 4V), the LT8228
is designed with a 10V gate drive supply at the DRVCC
pin. The M2 and M3 must satisfy the 10V maximum
VGS requirement.
It is also important to consider power dissipation when
selecting power MOSFETs. Power dissipation must be
limited to improve the system efficiency and avoid overheating that might damage the MOSFETs. The parameters
that determine the power dissipation includes on-resistance RDS(ON), input voltage, output voltage, maximum
output current, and Miller capacitance CMILLER.
In buck mode, V1D is the input voltage and V2D is the
output voltage. M2 is the main switch and M3 is the synchronous switch. In boost mode, V2D is the input voltage
and V1D is the output voltage. M3 is the main switch and
M2 is the synchronous switch.
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43
LT8228
APPLICATIONS INFORMATION
Miller capacitance CMILLER is the most important selection criteria for determining the transition loss in the main
switch MOSFET but is not directly specified on MOSFET
manufacturer’s data sheets. However, it can be approximated from the gate charge curve usually provided on the
MOSFET data sheet. The curve is generated by forcing a
constant input current into the gate of a common source,
current source loaded stage and then plotting the gate
voltage versus time as shown in Figure 16. The initial
slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-togate capacitance as the drain drops the voltage across
the current source load. The upper sloping line is due to
the drain-to-gate accumulation capacitance and the gateto-source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b, while the
curve is flat) is specified for a given VDS drain voltage, but
can be adjusted for different VDS voltages by multiplying
by the ratio of the application VDS to the curve specified
VDS values. A way to estimate the CMILLER term is to
take the change in gate charge from points a to b on a
manufacturers data sheet and divide by the stated VDS
voltage specified.
In buck and boost modes, the power dissipation equation
for M2 and M3 are different as they swap roles between
the main switch and the synchronous switch of the power
stage. The MOSFET power dissipations in buck mode at
maximum output current are given by Equation 30.
VIN
VGS
MILLER EFFECT
a
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
–
+
–
VDS
PM2(BUCK) =
V2D
V1D
• (I V2,M AX )2 • (1+ δ)R DS(ON) + V1D 2
I
• V2,MAX • R DR • CMILLER
2
⎡
1
1 ⎤
⎥ƒ
•⎢
+
⎢⎣ VDRVCC – VTH(IL) VTH(IL) ⎥⎦
(30)
V – V2D
• (I V2,M AX )2 • (1+ δ)R DS(ON)
PM3(BUCK) = 1D
V1D
In boost mode, the power dissipation at maximum current
is given by Equation 31.
PM2(BOOST) =
V2D
V1D
PM3(BOOST) =
• (I V1,M AX )2 • (1+ δ)R DS(ON)
(V1D – V2D ) • VID
V2D
2
(31)
• (I V1,M AX )2
V 3
•(1+ δ)R DS(ON) + k •I V1,MAX • 2D
V1D
•CMILLER • ƒ
Here δ is the temperature coefficient of RDS(ON), and RDR
is the effective top driver resistance approximately 1.5Ω
at VGS = VMILLER. The term (1 + δ) is generally given for a
MOSFET in the form of a normalized RDS(ON) vs temperature curve but δ equal to 0.6%/°C multiplied by the temperature difference can be used as an approximation for
high voltage MOSFETs. VTH(IL) is the typical gate threshold
voltage specified in the power MOSFET data sheet. The
constant k, which accounts for the loss caused by reverse
recovery current, is proportional to the gate drive current
and has an empirical value of 1.7. CMILLER is the calculated capacitance using the gate charge curve from the
MOSFET data sheet and the technique described above.
8228 F16
Figure 16. Gate Charge Characteristics and Miller
Capacitance Calculation
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In buck mode, both MOSFETs have I2R losses while the
main switch MOSFET M2 has an additional term for transition loss that increases as V1D voltage increases. For low
V1D voltages, larger MOSFETs (lower RDSON) generally
improve efficiency at high currents. For high V1D voltages, a smaller MOSFET (higher RDSON, lower CMILLER)
for the main switch may provide higher efficiency due to
the transition loss dominating the I2R loss. The synchronous switch MOSFET M3 losses are greater at higher V1D
voltages when the top MOSFET duty cycle factor is lower
or during a short-circuit when the synchronous switch is
on close to 100% of the switching period.
In boost mode, both MOSFETs have I2R losses while
the main switch bottom MOSFET M3 has an additional
term for transition loss that increases as V2D voltage
decreases. For high V2D voltages, larger MOSFETs (lower
RDSON) generally improve efficiency at high currents. For
low V2D voltages, a smaller MOSFET (higher RDSON, lower
CMILLER) for the main switch may provide higher efficiency due to the transition loss dominating the I2R loss.
The synchronous switch MOSFET M2 losses are greater
at higher V2D voltages when the top MOSFET duty cycle
factor is lower or during overvoltage when the synchronous switch is on close to 100% of the switching period.
In typical LT8228 applications, V1D is higher than V2D as
V1D is the buck input and boost output while V2D is the
buck output and boost input respectively. As a result, buck
mode demands a smaller M2 (higher RDSON but lower
CMILLER) while boost mode demands a larger M2 (lower
RDSON). Similarly, buck mode demands a larger M3 (lower
RDSON) while boost mode demands a smaller M3 (higher
RDSON but lower CMILLER). Select top MOSFET M2 and
bottom MOSFET M3 to optimize efficiency in both buck
and boost modes.
Multiple MOSFETs can be used in parallel to lower
RDS(ON) to meet the current and thermal requirements of
the application. The LT8228 contains large low impedance drivers capable of driving large gate capacitances
without significantly slowing transition times. When driving MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (2Ω or less) to reduce switch node ringing and
EMI caused by fast switch node transitions.
OPTIONAL SCHOTTKY DIODE (D2 AND D3) SELECTION
In buck mode, the body diode of the bottom MOSFET
M3 conducts during the transition time when the main
switch MOSFET M2 turns off and the synchronous switch
MOSFET M3 turns on. As the M3 body diode conducts
during this dead time, it stores charge. A Schottky diode
D3 is placed in parallel to bottom MOSFET M3 as shown in
the Block Diagram section to significantly reduce reverse
recovery current due to the body diode conduction which
improves the system efficiency and lowers power dissipation at M3. Similar to the buck mode, the body diode of
the top MOSFET M2 conducts during the transition time in
boost mode when the main switch bottom MOSFET M3 is
turning off and the synchronous switch top MOSFET M2
is turning on. A Schottky diode D2 is placed in parallel to
top MOSFET M2 as shown in the Block Diagram section
to reduce the reverse recovery current, improve system
efficiency and lowers power dissipation at M2.
In order for the diode to be effective, the inductance
between it and the switch must be as small as possible,
mandating that these components be placed adjacently.
For applications with V1D voltages typically greater than
40V, avoid Schottky diodes with excessive reverse leakage
currents particularly at high temperatures. Some ultralow
VF diodes will trade off increased high temperature leakage current for reduced forward voltage. The combination of high reverse voltage and current can lead to selfheating of the diode. Besides reducing efficiency, this can
increase leakage current which increases temperatures
even further. Choose packages with lower thermal resistance to minimize self-heating of the diodes.
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LT8228
APPLICATIONS INFORMATION
TOP MOSFET DRIVER SUPPLY (CBST, DBST)
An external bootstrap capacitor, CBST, connected from
the SW to the BST pins, supplies the gate drive voltage
for the top MOSFET M2. When the switch node is low,
DRVCC charges this capacitor through an external diode
DBST. When M2 turns on, the switch node rises to V1 and
the BST pin rises to approximately V1 + DRVCC. The boost
capacitor needs to store about 100 times the gate charge
required by the top MOSFET. In most applications a 0.1μF
to 0.47μF X5R or X7R dielectric capacitor is adequate.
The reverse breakdown of the external diode, DBST, must
be greater than V1(MAX). Another important consideration
for the external diode is its reverse recovery and reverse
leakage, either of which may cause excessive reverse current flow at full reverse voltage. If the reverse current
times the reverse voltage exceeds the maximum allowable power dissipation, the diode may get damaged. For
best results, use a diode that has very fast recovery and
low leakage.
POWER PATH CAPACITOR SELECTION
Capacitor Selection at V1 (CV1, CDM1 and CDM2)
In applications where the V1 terminal is connected to a
voltage source or load through long conducting wires,
parasitic wire inductance and CDM1 form a high-Q LC
resonant tank circuit. During a large V1 transient such
as a short, the resonant frequency creates large voltage
oscillations at V1. In this case, V1 goes negative which
turns off the V1 protection MOSFET M1. To prevent the
drain-to-source voltage breakdown of M1, add a bypass
capacitor, CV1, with series resistance at V1 which dampens
the resonant circuit. Since high ESR capacitors such as
R
M1 V1D SNS1
V1
RV1 DG1
CV1
TG
CDM1
CDM2
RSNS2 V2D
M4
L
M2
M3
BG
DG2
CDM4
V2
RV2
CV2
aluminum electrolytic cannot tolerate negative voltages,
use low ESR ceramic capacitors with additional resistors
in series.
The drain of the top MOSFET M2 is the input of the buck
power stage and output of the boost power stage. The
capacitor at this node, CDM2, and at V1D, CDM1 serve as
input bypass capacitors in buck mode and output filtering
capacitors in boost mode. RSNS1 connected between the
drain of M2 and V1D is used to monitor and regulate in the
V1 input and output current. RSNS1 is also used to sense
the instantaneous current through M2 for MOSFET short
detection. Due to their relative placement in the board,
RSNS1 does not sense the M2 instantaneous current coming out of CDM2. Thus, any capacitance at CDM2 hinders
LT8228’s MOSFET short detection capability. On the other
hand, capacitance of CDM2 is needed to reduce the EMI
and AC energy in the hot loop. The capacitance distribution between CDM1 and CDM2 needs to ensure effective MOSFET short detection as well as low EMI and AC
energy dissipation.
The current through the top MOSFET M2 is discontinuous in both buck and boost modes. In buck continuous
mode operation, the drain current of the top MOSFET
is approximately a square wave of duty cycle V2D/V1D
which is instantaneously supplied by CDM1 and CDM2. To
prevent large input voltage transients in buck mode, use
a low ESR capacitor sized for the maximum RMS current
through the top MOSFET M2, IRMS, given by Equation 32.
V
IRMS = I V2(MAX) • 2D
V1D
V1D
V2D
–1
(32)
where IV2(MAX) is the maximum output current in buck
mode. This formula has a maximum when the V1D voltage
is twice the regulated V2D voltage, where IRMS is half of
IV2(MAX). This simple worst-case condition is commonly
used for design. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required.
8228 F17
Figure 17. Power Path Capacitor Selection at V1 and V2
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CDM1 and CDM2 also serves as the output filtering capacitors in boost mode to reduce the ripple voltage caused by
the discontinuous current through the top MOSFET M2.
For boost mode, the effects of ESR and the bulk capacitance must be considered when choosing the capacitor
for a given output ripple voltage. The maximum steadystate ripple voltage due to charging and discharging the
bulk capacitance is given by Equation 33.
ΔVBULK =
I V1(MAX) • (V1D – V2D(MIN) )
CDM2 • V1D • ƒ
(33)
where IV1(MAX) is the maximum output current in boost
mode and ƒ is the switching frequency. The steady-state
ripple due to the voltage drop across the ESR is given by
Equation 33.
ΔVESR = IL(MAX) • ESR
(34)
where IL(MAX) is the maximum inductor current in boost
mode. The voltage ripple at the drain of the top MOSFET
M2 is the total ripple caused by the buck capacitance
and ESR. Low ESR tantalum and OS-CON capacitors are
typically not available in voltages above 35V. Therefore,
ceramics or aluminum electrolytics must be used for high
V1 and V2 voltages.
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics
are specified with EIA temperature characteristic codes
of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low
cost, but exhibit strong voltage and temperature coefficients. The X5R and X7R dielectrics yield much more
stable characteristics and are more suitable for use as
the CDM2 capacitor.
The X7R type works over a wider temperature range and
has better temperature stability, while the X5R is less
expensive and is available in higher values. Care still
must be exercised when using X5R and X7R capacitors;
the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance changes due to DC bias are less
with X5R and X7R capacitors, but can still be significant
enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as
component case size increases, but expected capacitance
at operating voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor, the stress is
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise.
A combination of aluminum electrolytic capacitors and
ceramic capacitors are typically needed to meet the size
or height requirements in a design. When used together,
the percentage of RMS current that will flow through the
aluminum electrolytic capacitor is given by Equation 35.
%IRMS,ALUM ≈
100%
(
(
1+ 8 • ƒ • C CER • R ESR(ALUM)
))
2
(35)
where RESR(ALUM) is the ESR of the aluminum electrolytic capacitor and CCER is the overall capacitance of the
ceramic capacitors. This reduces the RMS current at CDM2
allowing smaller capacitance. The ESR of the aluminum
electrolytic capacitors helps to dampen the high Q of the
ceramic, minimizing ringing. Additionally, it provides the
bulk capacitance for supplies with high source impedance
such as batteries.
Ensure the capacitor selection of CDM1 and CDM2 satisfies
both the buck and boost requirements for RMS current
and output ripple voltage respectively.
Capacitor Selection at V2 (CDM4 and CV2)
The drain of the V2 protection MOSFET M4 is the input of
the boost power stage and the output of the buck power
stage. The capacitor CDM4 serves as an output filtering
capacitor in buck mode and as an input bypass capacitor
in boost mode. The current through the V2 protection
MOSFET M4 is continuous in both buck and boost modes.
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LT8228
APPLICATIONS INFORMATION
In buck mode, the selection of CDM4 is primarily determined by the ESR required to minimize output ripple voltage followed by filtering and RMS current rating requirements. The output ripple voltage (�V2D) is approximately
equal to Equation 36.
⎛
⎞
1
ΔV2D =ΔIL • ⎜ESR +
⎟
8 • ƒ • CDM4 ⎠
⎝
(36)
Since �IL increases with input voltage, the output ripple
is highest at maximum input voltage. ESR also has a significant effect on the load transient response. Fast load
transitions at the output will appear as voltage across
the ESR of CDM4 until the feedback loop in the LT8228
can change the inductor current to match the new load
current value. Typically, once the output ripple voltage
requirement is satisfied, the capacitance is adequate for
filtering and has the required RMS current rating.
In boost mode, the minimum required value of CDM4 is
a function of the source impedance at V2, and typically
the higher the source impedance, the higher the required
capacitance. The required amount of boost input capacitance is also greatly affected by the duty cycle. High output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
As with CDM2, CDM4 needs to satisfy both the buck and
boost requirements for output ripple voltage and source
impedance, respectively. A combination of aluminum
electrolytic capacitors and ceramic capacitors are typically needed to meet the size or height requirements in
a design.
In applications where the V2 terminal is connected to a
voltage source or load through long conducting wires,
parasitic wire inductance and CDM4 form a high-Q LC
resonant tank circuit. During a large V2 transient such
as a short, the resonant frequency creates large voltage
oscillations at V2. In this case, V2 goes negative which
turns off the V2 protection MOSFET M4. To prevent the
drain-to-source voltage breakdown of M4, add a bypass
capacitor, CV2, at V2 with series resistance RV2 which
dampens the resonant circuit. Since high ESR capacitors
such as aluminum electrolytic cannot tolerate negative
voltages, use low ESR ceramic capacitors with additional
resistors in series.
LOOP COMPENSATION
There are three feedback loops to consider in both buck
and boost modes when setting up the compensation for
the LT8228. The loops are (1) the output voltage loop, (2)
the output current limit loop and (3) the input current limit
loop. In buck mode, the LT8228 uses an internal transconductance error amplifier EA2 to regulate V2D output
voltage, V2 output current limit and V1 input current limit.
The error amplifier output VC2 compensates the buck
mode voltage and current limit loops. In boost mode, the
LT8228 uses a separate transconductance error amplifier
EA1 to regulate V1D output voltage, V1 output current limit
and V2 input current limit. The error amplifier output VC1
compensates the boost mode voltage and current loops.
Separate compensation pins allow individual optimization
of both buck and boost modes. The voltage loop stability
is determined by the inductor value, the current sense
resistor and its input gain resistors, the output capacitance, the load current and the VC compensation resistor
and capacitor. The current loop stability is determined by
the inductor value, the ISET resistor and its capacitor, and
the VC compensation resistor and capacitor. The inductor, current sense resistor, input gain resistors, output
capacitor and ISET resistors have been chosen based on
performance, size and cost as discussed in the previous
sections. The VC compensation resistor and capacitor and
the ISET capacitor are set to optimize the voltage and current loop response and stability.
Buck mode compensation consists of a resistor RC2 and
a capacitor CC2 connected in series between the VC2 pin
and ground. An optional parallel capacitor can also be
connected between the VC2 pin and ground to filter high
frequency noise. Set RC2 and CC2 based on the V2D voltage loop stability. For typical buck mode applications, a
10nF compensation capacitor CC2 is adequate. Lowering
the compensation capacitance increases the bandwidth of
the loop. However, higher bandwidth may make the loop
unstable due to the LC output filer pole. Higher CC2 value
might be needed for stability if the output capacitance at
V2D is reduced. The series resistor RC2 is used to increase
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the slew rate of the VC2 pin to maintain tighter regulation
of the output current during a load or input transient. If
the resistance is too high, the loop gets unstable whereas
if it is too low, the transient response is too slow. For
typical buck mode applications, setting RC2 to 2kΩ is a
good starting point. Initially use an “R/C box” to quickly
iterate towards the final compensation value where the
bandwidth is highest with sufficient phase margin. Check
the loop stability at no load, maximum load, and all points
in between over the entire input voltage range with 20%
variation on the compensation values.
Once the RC2 and CC2 are set, select the ISET capacitors
next. Since the output capacitance is not part of the current loops; the typical output impedance of 1Meg at the
VC2 pin with CC2 is the dominant pole in the loop. Set the
ISET1P and ISET2P capacitors so that the pole formed
by the ISET pin resistor and capacitor does not make the
loop unstable.
Similarly, boost mode compensation consists of a resistor
RC1 and a capacitor CC1 connected in series between the
VC1 pin and ground. An optional parallel capacitor can
also be connected between the VC1 pin and ground to
filter high frequency noise. Set RC1 and CC1 based on the
V1D voltage loop stability. For typical boost mode applications, a 4nF compensation capacitor CC1 is adequate.
Lowering the compensation capacitance increases the
bandwidth of the loop. However, higher bandwidth may
M1B
M1A
V1
V1D RSNS1
CDM1
RG1B
make the loop unstable due to the LC output filer pole.
Higher CC1 value might be needed for stability if the output
capacitance at V1D is reduced. The series resistor RC1 is
used to increase the slew rate of the VC1 pin to maintain
tighter regulation of the output current during a load or
input transient. If the resistance is too high, the loop gets
unstable whereas if it is too low, the transient response is
too slow. For typical boost mode applications, setting RC1
to 8k is a good starting point. Initially use an “R/C box”
to quickly iterate towards the final compensation value
where the bandwidth is highest with sufficient phase margin. Check the loop stability at no load, maximum load,
and all points in between over the entire input voltage
range with 20% variation on the compensation values.
Once the RC1 and CC1 are set, select the ISET capacitors
next. Since the output capacitance is not part of the current loops; the typical output impedance of 1Meg at the
VC1 pin with CC1 is the dominant pole in the loop. Set the
ISET1N and ISET2N capacitors so that the pole formed
by the ISET pin resistor and capacitor does not make the
loop unstable.
INRUSH CURRENT CONTROL
In buck start-up, when DG1 is turned on, inrush current flows from V1 to charge CDM1 and CDM2. During the
inrush current, M1B is stressed by the full supply voltage at V1. Unless the inrush current is controlled, M1B
M2
SW
CDM2
RSNS2
L
M4B
V2
CDM4
M3
DV1
RG4B
DV2
TG
DS1
DG1
RDG1
M4A
LT8228
BG
DS2
DG2
8228 F18
RDG2
CDG2
CDG1
Figure 18. Input Inrush Current Control
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LT8228
APPLICATIONS INFORMATION
operates outside its SOA and gets damaged. The LT8228
limits the inrush current by controlling the DG1 pin voltage slew rate. As shown in Figure 18, the compensation
resistor RDG1 and capacitor CDG1 are used for this purpose. At start-up, a 10µA pull-up current charges DG1,
pulling up both M1A and M1B gates. M1B operates as a
source follower and Equation 37.
IINRUSH,BUCK =
10µA • (CDM1 + CDM2 )
CDG1
(37)
In typical applications, a CDG1 of 6.8nF and RDG1 of 10kΩ
is recommended. Carefully consider the SOA of M1B to
ensure it can withstand the maximum stress applied by
maximum voltage at V1 and inrush current IINRUSH,BUCK.
In boost start-up, when DG2 is turned on, inrush current
flows from V2 to charge CDM4, CDM2 and CDM1. During the
inrush current, M4B is stressed by the full supply voltage at V2. Unless the inrush current is controlled, M4B
operates outside its SOA and gets damaged. The LT8228
limits the inrush current by controlling the DG2 pin voltage slew rate. As shown in Figure 18, the resistor RDG2
and capacitor CDG2 are used for this purpose. At start-up,
a 10µA pull-up current charges DG2, pulling up both M4A
and M4B gates. M4B operates as a source follower and
Equation 38.
IINRUSH,BOOST =
10µA • (CDM1 + CDM2 + CDM4 )
CDG2
(38)
In typical applications, a CDG2 of 3.3nF and RDG1 of 10k
is recommended. Carefully consider the SOA of M4B to
ensure it can withstand the maximum stress applied by
maximum voltage at V2 and inrush current IINRUSH,BOOST.
In boost mode, DG2 is charged first which charged V2D to
V2 and V1D higher than V2D. When DG2 voltage exceeds
it undervoltage threshold, DG1 starts charging. Inrush
current flow from V1D to charge the load at V1. Similar to
buck mode, the boost output inrush current is limited by
capacitor CDG1. M1A operates as a source follower and
Equation 39.
IINRUSH,BOOST,OUTPUT =
10µA • (C V1)
CDG1
(39)
In buck mode, there is no output inrush current as V2D is
0V as DG2 starts charging. However, if the V2 is pre-biased
at start-up, output inrush current flows from V2 to V2D
which is similar to input inrush current in boost mode.
BOOST OUTPUT SHORT PROTECTION AND TIMER
Boost Output V1 Short Current Control
In boost mode when V1 drops below V2 due to excessive
load or V1 is shorted to ground, the output current cannot be regulated through the switching MOSFET due to
the body diode of the TG MOSFET M2. Unlike other boost
controllers that cannot limit current under such conditions, the LT8228 limits the output short current using
the V1 protection MOSFET M1 (M1A is dual MOSFET configuration). As shown in Figure 19, the LT8228 senses
the output current across the resistor RSNS1 and outputs
a proportional current at the ISET1N pin. M1 limits the
output current so that the ISET1N pin voltage is 1.4V by
controlling DG1. The output short current IV1,SHORT is set
according to Equation 40.
I V1,SHORT =
RIN1
R SNS1 • R SET1N
• 1.4V
(40)
The current limit can be lowered by injecting additional
current into the ISET1N pin or by dynamically increasing
the ISET1N resistor. As the ISET1N pin voltage is regulated
above the typical switching current limit reference during
V1 short current control, the boost V1 output current limit
loop stops the LT8228’s switching. This also ensures that
V1 output short current control has no interference during
V1 output current limit in boost mode. If dual back-to-back
MOSFET configuration is used, external compensation
resistor RDG1 and capacitor CDG1 are used to stabilize the
V1 output short current control loop. RDG1 and capacitor
CDG1 are connected in series from DG1 to ground in dual
back-to-back MOSFET configuration. In single MOSFET
configuration, they are placed across the DG1 and DS1
pins (the gate and source of the V1 protection MOSFET
M1). CDG1 is already set to limit the inrush current. Set
RDG1 to cancel the pole created by RSET1N and CSET1N.
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M1
V1
TERMINAL
RDG1
V1D
CDG2
V1
TERMINAL
M1B
DG1
DS1 DG1
CDG3
RSNS1
V1D
V1
TERMINAL
V1D
OR
RDG1
DS1
M1A
L
M2
RSNS2
V2D
M1
DS1
DG1
V1D
RIN1
RIN1
SNS1P
SNS1N
TG
M3
BG
LT8228
CHARGE
PUMP
CSA1
10μA
V1D V1
MDG1
V1D –0.5V
INRUSH
AMP
GMDG1
Gm = 1/500k +10μA
V1
GMDG1
1.3V
TMR
CTRL
1.4V
ISET1N
TMR
8228 F19
CSET1N
RSET1N
CTMR
Figure 19. M1 Protection During Output Short in Boost Mode
Overcurrent Fault and Fault Timer
During the V1 output short current control period, M1 or
M1A is stressed by the V1D voltage which can be as high
as V2 supply. Coupled with the current set by ISET1N,
the energy dissipation at M1 might take it out of its safe
operating area (SOA). To keep M1 operating in its SOA,
the LT8228 includes an overcurrent fault detection and an
adjustable fault timer. An overcurrent fault occurs when
the current limit circuitry at ISET1N has been engaged for
longer than the timeout delay set by the timer capacitor
at the TMR pin and V1D is higher than V1 (sensed using
DS1) by 500mV. The DG1 pin is then immediately pulled
low by 80mA to the DS1 pin, turning off the M1. After the
fault condition has disappeared and a cool down period
has transpired, the DG1 pin is allowed to pull back up and
turn on the protection MOSFET M1.
Connecting a capacitor from the TMR pin to ground sets
the delay period before the MOSFET M1 is turned off during an overcurrent fault condition. The same capacitor
also sets the cool down period before M1 is allowed to
turn back on after the fault condition has disappeared.
The current limit circuitry at ISET1N engages when the
ISET1N voltage is higher than 1.3V (Refer to the ISET1N
inrush current limit threshold curve in the Typical
Performance Characteristics section). Once the current
limit circuitry at ISET1N has engaged, a current source
charges up the TMR pin. The current level varies depending on the voltage drop across the V1D pin and the DS1
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LT8228
APPLICATIONS INFORMATION
pin, corresponding to the MOSFET M1’s or M1A’s VDS.
The on time is inversely proportional to the voltage drop
across the MOSFET. This scheme therefore takes better
advantage of the available safe operating area (SOA) of
the MOSFET than would a fixed timer current.
During an overcurrent fault, the timer current starts at
10µA with 0.5V of V1D – V1 and increases to 210µA with
100V of V1D – V2 (see Figure 20 and Equation 41).
ITMR(UP)OC = 10µA + 2 [µA / V ] • ( V1D – V1 – 0.5V )
(41)
VTMR (V)
1.4
TIME
6.7ms/µF
8228 F20
Figure 20. Fault Timer Current of the LT8228
This arrangement allows the pass device to turn off faster
during an overcurrent event with high VDS voltage at M1,
since more power is dissipated. Refer to the Typical
Performance Characteristics section for the timer current at different V1D – V1 in overcurrent events.
When the voltage at the TMR pin crosses the 1.4V threshold, the pass device M1 turns off immediately. Assuming
V1D – V1 remains constant, the on-time of DG1 during an
overcurrent fault is shown in Equation 41.
TOC =
ITMR(UP)OC
2µA
(43)
Refer to the Typical Performance Characteristics section
for the V1 protection MOSFET M1’s duty cycle under an
overcurrent fault.
1. Temperature Fault: The junction temperature exceeds
165°C typically.
tFLT
36.8ms/µF
C TMR • 1.4V
63 • C TMR • 1V
The FAULT pin is an open-drain logic output which flags
internal and external faults. Pull up the pin with a series
resistor to a microcontroller supply or the INTVCC pin. An
LED can be added in series with the pull-up resistor for
visual status indication. The LT8228 pulls down on the
FAULT pin under the following conditions.
tFLT
= 14V
TCOOL =
FAULT CONDITIONS
V1D – V1 = 100V
(ITMR = 210µA)
V1D – V1 = 14V
(ITMR = 38µA)
0
V1D – V1
= 100V
to form a long cool down timer period before retrying.
At the end of the cool down period (when the TMR pin
voltage drops to 0.4V the 32nd time), the LT8228 retries,
pulling the DG1 pin up and turning on the pass device M1.
The total cool down timer period is given by Equation 43.
(42)
As soon as TMR reaches 1.4V and DG1 pulls low in a
fault condition, the TMR pin starts discharging with a
2μA current. When the TMR pin voltage drops to 0.4V,
TMR charges with 2μA. When TMR reaches 1.4V, it starts
discharging again with 2μA. This pattern repeats 32 times
2. VCC Fault: DRVCC or INTVCC falls below their undervoltage threshold. The threshold is set at 6.5V for DRVCC
and 3.4V for INTVCC typically.
3. Input Undervoltage Fault: In buck mode, UV1 falls
below its undervoltage threshold of 1.2V typically. In
boost mode, UV2 falls below its undervoltage threshold
of 1.2V typically.
4. Output Overvoltage Fault: In buck mode, FB2 rises
above its overvoltage threshold of 1.3V typically. In
boost mode, FB1 rises above its overvoltage threshold
of 1.3V typically.
5. DG Fault: The DG1 or the DG2 falls below their undervoltage threshold of 4.5V typically.
6. TG MOSFET M2 or BG MOSFET M3 Short Fault: The
LT8228 detects the M2 or the M3 short damage using
the RSNS1 and RSNS2 resistors.
7. Reference Fault: The two internal references are more
that 10% away from each other.
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8. Internal Diagnostic Fault: The LT8228 checks the
functionality of the error amplifiers EA1 and EA2 and
the current sense amplifiers CSA1 and CSA2 and the
oscillator at start-up. Failure to pass the functionality
test results in internal diagnostic fault.
When the FAULT pin asserts, the LT8228 stops switching
and pulls the SS pin low except for the output overvoltage
fault. For a sink current of 2mA, the maximum voltage
over temperature at the FAULT pin is 0.5V.
SOFT-START
The LT8228 limits the input and the output currents by
limiting the corresponding ISET pin voltages to a current
limit reference voltage VIREF which is the lower of the SS
pin voltage and the internal reference voltage of 1.21V
typically as shown in Figure 21. Connecting an external
capacitor, CSS, from the SS pin to ground programs a
current limit soft-start during start-up. When the LT8228
is enabled, an internal 10μA pull-up current is activated
while the SS pin voltage remains low due to an active pull
down by an internal MOSFET. The pull-down is maintained
under the following fault conditions.
1. Temperature Fault: The junction temperature exceeds
165°C typically.
2. VCC Fault: DRVCC or INTVCC falls below their undervoltage threshold. The threshold is set at 6.5V for
DRVCC and 3.4V for INTVCC typically.
3. Input Undervoltage Fault: In buck mode, UV1 falls
below its undervoltage threshold of 1.2V typically. In
boost mode, UV2 falls below its undervoltage threshold
of 1.2V typically.
INTVCC
LT8228
10µA
SS
CSS
1.214V
MIN
VIREF
SS CONTROL
8228 F21
4. DG Fault: The DG1 or the DG2 falls below their undervoltage threshold of 4.5V typically.
5. TG MOSFET M2 or BG MOSFET M3 Short Fault: The
LT8228 detects the M2 or the M3 short damage using
the RSNS1 and RSNS2 resistors.
6. Internal Diagnostic Fault: The LT8228 checks the functionality of the references and the error amplifiers EA1
and EA2 and the current sense amplifiers CSA1 and CSA2
and the oscillator at start-up. Failure to pass the functionality test results in internal diagnostic fault.
If none of the fault conditions exist, SS pull-down is disabled allowing the SS pin voltage to rise linearly. Once the
SS pin voltage reaches the internal reference voltage, the
input and output current limits are set to their maximum
value. The total soft-start time tSS is given by Equation 44.
TSS = C SS •
1.21V
10µA
(44)
REPORT FEATURE
The LT8228 checks internal circuit blocks, fault conditions, and external MOSFETs for errors and reports the
result at the REPORT pin. The pin is an active low opendrain output. Pull up the REPORT pin to a microcontroller
supply through a series resistor. Set the resistance of the
pull-up resistor to meet the logic level needs of the application. For a sink current of 2mA, the maximum voltage
over temperature at the REPORT pin is 0.5V. The pin is
functional as long as the part is enabled and the INTVCC
pin voltage is higher than 2.8V typically. The FAULT pin
can be used as an interrupt for the microcontroller since
it is pulled “low” during an error. The microcontroller can
always read the REPORT pin data or only when interrupted
by the FAULT pin. At start-up, while INTVCC is rising from
0V to 4V with 20mA charging current, the FAULT pin pulldown activates at 1.2V typically. However, the REPORT is
not active until 2.8V typically. If microcontroller is reading
the REPORT pin data when interrupted by the FAULT pin,
allow enough time for the INTVCC capacitor to get charged
to 2.8V at start-up. Refresh the enable pin to reset all the
error latches.
Figure 21. Soft-Start Pin Control
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LT8228
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The LT8228 continuously reports a 32-bit word at the
active low REPORT pin using the SYNC pin as the data
clock. If the SYNC pin is unused, the REPORT pin remains
high impedance. The 32-bit word starts with a header
which consists of a sequence of 8 logic high (VH) synchronization bits. During the 8 “VH” synchronization bits,
the LT8228 checks the REPORT pin voltage at every clock
cycle to ensure external pull-up. The threshold voltage
for external pull-up detection is 1V typically. If the voltage drops below the threshold voltage during the 8 “VH”
synchronization bits, the part restarts the header. This
mechanism allows implementation of the “Chip Select”
feature where a multiplexer can be used to read multiple
LT8228 REPORT pins by a single microcontroller input.
counts the number of times the 32-bit word is repeated.
The counter restarts after every 4 counts. Once a fault is
detected, it is reported for a minimum of 3 counts. If a
fault condition lasts longer than 3 counts, the part reports
the fault till the condition no longer exists.
Table 2. Report Address Allocation and Check Time
Once the LT8228 completes the header bits without external pull-up error, it finishes reporting the rest of the 24
bits starting with a logic low (VL) bit, followed by 6 status
bits, a parity bit, a “VL” bit, followed by another 6 status
bits, a parity bit, a “VL” bit, followed by another 4 status
bits, 2 counter bits and a parity bit as shown in Figure 22.
The corresponding error of each status bit is listed in
Table 2. A status bit of “VL” indicates an error. The parity
bits ensure an even number of VH’s in the preceding 7
bits. The count bits are the output of 2-bit counter which
SYNC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BIT
DIAGNOSTIC
01010(S0)
Overtemperature
Always
01011(S1)
DRVCC Under/Overvoltage
Always
01100(S2)
INTVCC Under/Overvoltage
Always
01101(S3)
Input Undervoltage
Always
01110(S4)
Output Overvoltage
Always
01111(S5)
Reverse Current
Buck Only
10010(S6)
DG1 Undervoltage
Always
10011(S7)
DG2 Undervoltage
Always
10100(S8)
BG MOSFET M3 Short
Always
10101(S9)
TG MOSFET M2 Short
Always
10110(S10)
Reference
Always
10111(S11)
EA1
At Start-Up
11010(S12)
EA2
At Start-Up
11011(S13)
CSA1
At Start-Up
11100(S14)
CSA2
At Start-Up
11101(S15)
Oscillator
At Start-Up
17
18
19
20
21
22
23
24
CHECK TIME
25
26
27
28
29
30
31
0
VL
STATUS BITS
P2
VL
S12 S13 S14 S15
STATUS BITS
00000
S10 S11
11101
S9
11100
S8
11011
S7
11010
S6
C0
C1
COUNT
BIT
P3
EVEN PARITY BIT
STATUS BITS
P1
10111
S5
10110
S4
10101
S3
10100
S2
10011
S1
10010
S0
START BIT
OK
ERROR
VL
EVEN PARITY BIT
VH
VL
VH
START BIT
STATUS
VH
EVEN PARITY BIT
HEADER
REPORT
VH
01111
VH
01110
VH
01101
VH
01100
VH
01011
VH
START BIT
BIT
01010
00001
REPORT
8228 F22
Figure 22. The Address Sequence at the REPORT Pin
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Over Temperature (01010)
If the die junction temperature reaches 165°C typically, the
LT8228 shuts down all four external N-channel MOSFETs,
pulls the SS pin low, asserts the FAULT pin, IGND goes
high impedance and reports the status as a logic low.
DRVCC (01001): If the DRVCC pin voltage falls below its
undervoltage threshold of 6.5V typically, or rises above
its overvoltage threshold of 15.2V typically, the LT8228
shuts down all four external N-channel MOSFETs, pulls
the SS pin low, IGND goes high impedance and the status
is reported as a logic low. This error stops switching,
asserts the FAULT pin, pulls the SS pin low, and IGND
goes high impedance.
INTVCC (01100): If the INTVCC pin voltage falls below its
undervoltage threshold of 3.6V typically, or rises above
its overvoltage threshold of 4.7V typically, the LT8228
shuts down all four external N-channel MOSFETs, pulls
the SS pin low, IGND goes high impedance and the status
is reported as a logic low. This error stops switching,
asserts the FAULT pin, pulls the SS pin low, and IGND
goes high impedance.
Input Undervoltage (01101): Input undervoltage is
detected by the LT8228 by the UV1 and UV2 pins. In buck
mode, if the UV1 voltage falls below the undervoltage
threshold, the status is reported as a logic low. In boost
mode, if the UV2 voltage falls below the undervoltage
threshold, the status is reported as a logic low. This error
stops switching, asserts the FAULT pin, pulls the SS pin
low, and IGND goes high impedance.
Output Overvoltage (01110): Output overvoltage is
detected by the LT8228 by the FB1 and FB2 pins. In buck
mode, if the FB2 voltage rises above the overvoltage
threshold of 1.3V typically, the status is reported as a
logic low. In boost mode, if the FB1 voltage rises above
the overvoltage threshold of 1.3V typically, the status is
reported as a logic low. This error stops switching and
asserts the FAULT pin.
Reverse Current (01111): In buck mode, if the V1 voltage drops close to V2 voltage by 500mV or lower and
the current through RSNS1 is higher than the reverse
current threshold, the status is reported as a logic low.
The LT8228 shorts the DG1 pin to V1 pin, turning off the
protection MOSFET M1. As a result, the status of DG1
Undervoltage fault is also reported as a logic low. This
error stops switching, asserts the FAULT pin, pulls the SS
pin low, and IGND goes high impedance.
DG1 Undervoltage (0101): The LT8228 continuously
monitors the gate-to-source voltage of the V1 protection
MOSFET M1 (DG1 – V1). If the voltage drops below 4.5V
typically, the status is reported as a logic low. In buck
mode, this error stops switching, asserts the FAULT pin,
pulls the SS pin low, and IGND goes high impedance. In
boost mode, this error stops switching.
DG2 Undervoltage (0111): The LT8228 continuously
monitors the gate-to-source voltage of the V2 protection
MOSFET M4 (DG2 – V2). If the voltage drops below 4.5V
typically, the status is reported as a logic low. This error
stops switching, asserts the FAULT pin, pulls the SS pin
low, and IGND goes high impedance.
BG MOSFET M3 Short (10100): The LT8228 checks for
an BG MOSFET M3 short by looking at the overcurrent
conditions at RSNS1 or RSNS2 . If the LT8228 detect BG
MOSFET M3 short error, it shuts down all four external
N-channel MOSFETs, pulls the SS pin low, asserts the
FAULT pin, IGND goes high impedance and reports the
status as a logic low.
TG MOSFET M2 Short (10101): The LT8228 checks for
an TG MOSFET M3 short by looking at the overcurrent
conditions at RSNS1 or RSNS2 . If the LT8228 detect TG
MOSFET M2 short error, it shuts down all four external
N-channel MOSFETs, pulls the SS pin low, asserts the
FAULT pin, IGND goes high impedance and reports the
status as a logic low.
Reference (10110): The LT8228 has two independent references. If one of the reference fall below or rises above the
other reference by 10%, the LT8228 asserts the FAULT pin
and reports the status as a logic low. When the controller is
enabled or when any of the DRVCC or INTVCC pin voltages
are recovering from an undervoltage condition, and the
LT8228 detects reference error, the part does not start-up.
EA1 (10111): The V1 error amplifier regulates the FB1,
ISET1N and ISET2N voltages for boost mode V1D output
voltage, V1 output current and V2 input current regulation
respectively. When the controller is enabled or when any
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LT8228
APPLICATIONS INFORMATION
of the DRVCC or INTVCC pin voltages are recovering from
an undervoltage condition, the LT8228 checks the amplifier to validate its functionality. If EA1 fails this functionality check, the LT8228 does not start-up and the status is
reported as a logic low.
EA2 (11010): The V2 error amplifier regulates the FB2,
ISET1P and ISET2P voltages for buck mode V2D output
voltage, V1 input current and V2 output current regulation
respectively. When the controller is enabled, or when any
of the DRVCC or INTVCC pin voltages are recovering from
an undervoltage condition, the LT8228 checks the amplifier to validate its functionality. If EA2 fails this functionality check, the LT8228 does not start-up and the status is
reported as a logic low.
CSA1 (11011): The V1 current sense amplifier senses
V1 current for current limiting and monitoring. When the
controller is enabled or when any of the DRVCC or INTVCC
pin voltages are recovering from an undervoltage condition, the LT8228 checks the amplifier to validate its functionality. If CSA1 fails this functionality check, the LT8228
does not start-up and the status is reported as a logic low.
CSA2 (11100): The V2 current sense amplifier senses V2
current for current limiting and monitoring and inductor
current sensing for current mode control. When the controller is enabled or when any of the DRVCC or INTVCC pin
voltages are recovering from an undervoltage condition,
the LT8228 checks the amplifier to validate its functionality. If CSA2 fails this functionality check, the LT8228 does
not start-up and the status is reported as a logic low.
Oscillator (11101): The oscillator is used to generate the
LT8228’s switching frequency and to synchronize with
an external clock on the SYNC pin. When the controller
is enabled, or when any of the DRVCC or INTVCC pin voltages are recovering from an undervoltage condition, the
LT8228 checks to see if the oscillator is functional. If it
fails to oscillate, the LT8228 does not start-up and the
status is reported as a logic low.
PARALLELING MULTIPLE LT8228s
The LT8228 provides masterless fault tolerant output current sharing among multiple LT8228s in parallel, enabling
higher load current, better heat management and redundancy by using the ISHARE and IGND pins. The principle
of the operation has been described in Paralleling Multiple
Controllers in the Operation section.
In buck mode when the DRXN pin voltage is high, the
ISHARE pin outputs a current equal to the ISET2P pin output current which represents V2 output current. In boost
mode when the DRXN pin voltage is low, the ISHARE pin
outputs a current equal to the ISET1N pin output current
which represents V1 output current. Each LT8228 contributes their ISHARE pin current into a common node.
When paralleling, tie the ISHARE pins of all the LT8228s
together. For each LT8228, a local resistor RSHARE is connected from the ISHARE pin to its own IGND pin. In buck
mode, the ISET2P pin voltage regulates to the common
ISHARE node voltage by modulating the internal reference voltage. To regulate each LT8228’s V2 output current
to the average output current of all the LT8228s, make
RSET2P and RSHARE equal. In boost mode, ISET1N pin voltage regulates to the ISHARE node voltage by modulating
the internal reference voltage. To regulate each LT8228’s
V1 output current to the average output current, make
RSET1N and RSHARE values equal.
The maximum modulation of the internal reference voltage is ±5%. Refer to the Internal Reference vs ISHARE
curve in the Typical Performance Characteristics section.
The capacitor CSHARE at the common ISHARE node is
used for average current sharing. Select the ISET pin and
ISHARE pin capacitors CSET2P, CSET1N and CSHARE respectively such that the voltage ripple at these pins do not
cause significant duty cycle jitter. Minimum capacitance of
CSHARE is equal or higher than the capacitance of CSET2P
or CSET1N. The ground noise between the parallel stages
can be coupled to the VC1/VC2 nodes through ISHARE.
This noise translates to SW node jitter. Decrease the compensation resistors RC1/RC2 if such jitter problem arises.
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APPLICATIONS INFORMATION
RSET2P and RSET1N can be set at different values as long
as the ISHARE resistance is changed based on the mode
of operation defined by the DRXN pin. An implementation is shown in Figure 23 where the ISHARE resistance
is decreased when the DRXN pin voltage is high. This
implementation is useful for applications where the buck
output current is higher than the boost output current.
When multiple LT8228s are in parallel, they need to be in
the same mode of operation to prevent cross-conduction
between the phases. To keep the LT8228s in the same
mode of operation, the DRXN pins of all the phases are
connected together. Figure 24 shows two methods of
configuring the DRXN pin for automatic mode selection.
In the first method, the DRXN pins are tied together and
pulled-up with a single resistor to an independent supply
TO µC
ISET2P
CSET2P
RSH2
TO COMMON
ISHARE
ISHARE
RSH1
RSH2
ISET1N
CSET1N
RSH1
RSH1
CSHARE
LT8228
DRXN
MDRXN
LT8228s are typically paralleled in high current applications. Since the ISHARE node is shared between the
LT8228s but the grounds are not, differences in ground
potential will impact the accuracy of current sharing. The
differences between the ground potential of all the phases
should be minimized. When possible, kelvin all grounds
to a common ground.
BIAS, DRVCC, INTVCC AND POWER DISSIPATION
Figure 23. ISHARE Resistance Change Based on DRXN
INDEPENDENT
SUPPLY
PHASE 1
INTVCC
RDRXN
RDRXN1
DRXN
LT8228
DRXN
LT8228
PHASE 2
PHASE 2
INTVCC
RDRXN2
DRXN
LT8228
DRXN
LT8228
PHASE N
PHASE N
INTVCC
RDRXNN
DRXN
LT8228
In the second method, each LT8228’s DRXN pin is pulledup with its own pull-up resistor through a series diode to
its own INTVCC pin and tied to a common DRXN node. The
diode prevents any back conduction when an LT8228 is
disabled or in a fault condition where INTVCC pin voltage
is out of regulation. The resistance of the parallel connection of all the pull-up resistors should be 50k or higher to
ensure proper automatic mode selection.
IGND
8228 F23
PHASE 1
voltage. Only one phase is required to make the decision to enter boost mode while all phases are required to
make the decision to enter buck mode. The pull-up resistor at the common DRXN node should be 50k or higher
to ensure proper automatic mode selection.
METHOD 1
DRXN
LT8228
METHOD 2
8228 F24
Figure 24. DRXN Pin Connection for Parallel LT8228s
An internal P-channel low dropout regulator produces
10V at the DRVCC pin from the BIAS supply pin. Another
P-channel low dropout regulator produces 4V at the
INTVCC pin from the DRVCC pin. DRVCC powers the gate
drivers and is the supply for the INTVCC regulator. INTVCC
powers the internal circuitry.
The DRVCC pin regulator supplies a peak current of 160mA
and must be bypassed to ground with a minimum of 2.2µF
ceramic capacitor. An additional 0.1µF ceramic capacitor
placed directly adjacent to the DRVCC pin and ground is
highly recommended. Good bypassing is necessary to
supply the high transient current required by MOSFET
gate drivers.
Applications where the BIAS pin is supplied with high
voltage or where large MOSFETs are being driven at high
frequencies may cause the LT8228 to exceed its maximum junction temperature of 125°C (LT8228E, LT8228I)
or 150°C (LT8228H). The LT8228 incorporates current
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LT8228
APPLICATIONS INFORMATION
limit, power fold back and thermal overload protection for
the DRVCC regulator. The current limit at DRVCC should
be carefully considered when selecting the switching frequency and the switching MOSFETs. For maximum current capability, externally supply BIAS with voltage 20V or
less. Refer to the DRVCC Current Limit Fold back curve in
the Typical Performance Characteristics section.
The DRVCC current is typically dominated by the top and
bottom MOSFET gate charge current. The gate charge
current can be estimated by multiplying the total gate
charge Qg of the MOSFET and the switching frequency ƒ
of the LT8228. The total power dissipation PD inside the
LT8228 in normal operation is approximated by Equation
45.
PD = ( VBIAS – VDRVCC )
• Q g(TOP) + Q g(BOTTOM) • ƒ + IQBIAS (45)
((
)
)
where IQBIAS is the BIAS quiescent current when the
LT8228 is enabled. Once the power dissipation is known,
the junction temperature can be estimated by Equation 46.
(46)
TJ = TA + (PD • θ JA )
where θJA (in °C/W) is the package thermal resistance
from junction to ambient. For example, a typical application operating in continuous current operation where
the Infineon BSC035N10NS5 with Qg of 70nC is used
for top and bottom MOSFET and the BIAS pin voltage
is 48V while the LT8228 is operating at 150kHz switching frequency, the junction temperature is calculated by
Equation 47.
TJ = 70°C + (48V – 10V)
(47)
• ( ( 70nC + 70nC ) • 150kHz + 3mA )
• 25°C/W = 92.8°C
The BIAS pin supplies the gate driver and the internal
circuitry of the LT8228. This pin requires a minimum voltage of 8V. Since the BIAS pin is supplying the DRVCC and
INTVCC regulators, it should have the same level of capacitance or higher as the DRVCC pin. Three possible options
for the BIAS pin connection are shown in Figure 25.
BIAS
LT8228
V1 / V2
V1
BIAS
LT8228
CBIAS
OPTION 1A
V2
CBIAS
OPTION 1B
BIAS
BIAS
DRVCC
LT8228
CBIAS
8V TO 100V
LT8228
CDRVCC
6.8V to 15V
OPTION 2
OPTION 3
8228 F25
Figure 25. Possible Connections of BIAS Pin
1. Connect BIAS to either V1 or V2. The BIAS pin does
not have negative voltage protection. Connect BIAS to
the OR node of V1 and V2 using diodes if the terminal
voltages may go negative. A minimum 8V is required
at the BIAS pin for the LT8228 start-up and operation.
2. Connect BIAS to an independent supply. Minimize the
voltage at the BIAS pin to lower power dissipation.
Lowering the BIAS pin as low as 8V forces the DRVCC
LDO into dropout mode. Low BIAS pin voltage reduces
the maximum DRVCC current to 100mA. Refer to the
DRVCC Current Limit Fold back curve in the Typical
Performance Characteristics section.
3. Connect BIAS to an independent supply and tie the
BIAS and DRVCC pins together. This ensures zero
power dissipation in the DRVCC regulator. Limit the
supply voltage to 15V.
THERMAL SHUTDOWN
If the die junction temperature reaches approximately
165°C, the controller goes into thermal shutdown. All four
external N-channel MOSFETs M1, M2, M3 and M4 are
turned off, the FAULT and SS pins are pulled low and an
over temperature error is reported at the REPORT pin. The
controller will be re-enabled when the die temperature has
dropped by 10°C typically. After re-enabling, the controller
will turn on the V1 and V2 protection MOSFETs, perform
a soft-start and then enter normal operation.
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LT8228
APPLICATIONS INFORMATION
PIN CLEARANCE/CREEPAGE CONSIDERATION
The LT8228 is available in FE38 Package. FE38 package
has 0.5mm pitch between adjacent pins. ADI recommends conformal coating for FE38 packages in applications above 50V. For more information, refer to the
printed circuit board design standards described in IPC2221 (www.ipc.org).
EFFICIENCY CONSIDERATIONS
The efficiency of a switching regulator is equal to the output power divided by the input power times 100. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which changes would produce
the most improvements. Although all dissipative elements
in the circuit produce losses, four main sources account
for most of the losses in LT8228 circuits:
1. DC I2R Losses. These arise from the resistances of the
MOSFETs, current sensing resistors, inductor and PC
board traces which cause the efficiency to drop at high
output currents.
2. Switching Losses. These losses arise from the brief
amount of time top MOSFET M2 or bottom MOSFET
M3 spends in the saturated region during switch node
transitions. Power loss depends upon the input voltage,
load current, driver strength and MOSFET capacitance,
among other factors. See the Power MOSFET Selection
and Efficiency Considerations section for more details.
3. DRVCC Current. This is the sum of the MOSFET driver
current and internal INTVCC pin current. The difference
between the BIAS input voltage and DRVCC regulator’s
output voltage times the DRVCC current represents lost
power. This loss can be reduced by supplying BIAS with
a voltage close to 10V plus the dropout voltage of the
DRVCC regulator from a high efficiency source. Refer
to the DRVCC Dropout Voltage curve in the Typical
Performance Characteristics section. Lower capacitance MOSFETs can also reduce DRVCC current and
power loss.
4. CDM2 Loss. The capacitor at the drain of top MOSFET
M2 filters the large input RMS current in buck mode
and the large output RMS current in boost mode. CDM2
is required to have low ESR to minimize the AC I2R loss
and sufficient capacitance to prevent the RMS current
from causing additional upstream losses in fuses or
batteries.
5. Other Losses. Schottky diodes D2 and D3 are responsible for conduction losses during dead time and light
load conduction periods. Inductor core loss occurs
predominantly at light loads.
When adjusting to improve efficiency, the input current is
the best indicator of changes in efficiency. If one change is
made and the input current decreases, then the efficiency
has increased. If there is no change in input current, then
there is no change in efficiency.
PC BOARD LAYOUT CHECKLIST
The basic PC board layout requires a dedicated ground
plane layer. For high current, a multilayer board provides
heat sinking for power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with the
power MOSFETs.
• Place CDM2, top MOSFET M2, bottom MOSFET M3 and
D3 in one compact area.
• Use immediate vias to connect the components to the
ground plane if the components are not in the same
layer as the ground plane. Use several large vias for
each power component.
• Use planes for V1 and V2 to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. Connect the copper areas to
ground nets.
• Separate the signal and power grounds. All smallsignal components should return to the exposed pad
ground pin at one point.
Rev. 0
For more information www.analog.com
59
LT8228
APPLICATIONS INFORMATION
• Place bottom MOSFET M3 as close to the controller as
possible, keeping the GND, BG and SW traces short.
Output Voltage, V1 = 48V
Output Voltage Ripple, ∆V1 = 300mV
• Keep the high dV/dT SW, BST, and TG nodes away from
sensitive small-signal nodes.
V2 Input Current Limit, IV2N(LIM) = 40A
• The CDM4 (–) terminal should be connected as close
as possible to the (–) terminal of the CDM2 capacitor.
Switching Frequency, f = 125kHz
• Connect the top driver bootstrap capacitor, CBST,
closely to the BST and SW pins.
• Route the current sense leads, SNS1N with SNS1P and
SNS2N with SNS2P, together with minimum PC trace
spacing. Avoid sense lines passing through noisy areas,
such as switch nodes. Ensure accurate current sensing
with kelvin connections at the current sense resistors.
• Connect both VC pin compensation networks close
to the IC, between the VC pins and the exposed pad
ground pin.
• Connect the DRVCC bypass capacitor, CDRVCC, close to
the IC, between the DRVCC and exposed pad ground
pin. This capacitor carries the MOSFET drivers’ current
peaks. An additional 0.1μF ceramic capacitor placed
immediately next to the DRVCC and exposed pad ground
pin can help improve noise performance substantially.
• Connect the INTVCC bypass capacitor, CINTVCC, close
to the IC, between the INTVCC and the exposed pad
ground pin.
DESIGN EXAMPLE
V1 Output Current Limit, IV1N(LIM) = 10A
Maximum Ambient Temperature, TA(MAX) = 70°C
Reverse voltage protection needed at both the V1 and
the V2 terminal.
RT Selection: From Table 1, the RT resistance for 125kHz
switching frequency is 78.7kΩ.
Inductor Selection: In buck mode, the maximum inductor
ripple current occurs at highest input voltage. For 40%
maximum inductor peak-to-peak ripple current, the minimum inductance requirement for buck mode is given by
Equation 48.
L BUCK >
14V(54V − 14V)
125kHz • 16A • 54V
= 5.2µH
(48)
In boost mode, the maximum inductor ripple current
occurs when the V2 voltage is half of the V1 voltage.
Since the maximum V2 voltage is not as high as half of
the V1 voltage in this application, the maximum inductor
ripple current happens when the V2 voltage is highest.
For 40% maximum inductor peak-to-peak ripple current,
the minimum inductance requirement for boost mode is
given by Equation 49.
L BOOST >
18V(48V − 18V)
= 5.6µH
(49)
Requirements
Buck Mode:
A 10µH inductor is selected due to availability which
produces 20.7% ripple current in buck mode and 22.5%
ripple current in boost mode.
Input Voltage, V1 = 24V to 54V
Output Voltage, V2 = 14V
Output Voltage Ripple, ∆V2 = 100mV
RSNS2, and RIN2 Selection: The maximum current in the
inductor in buck and boost modes are given by Equation 50
V2 Output Current Limit, IV2P(LIM) = 40A
L LMAXBUCK = 40A +
V1 Input Current Limit, IV1P(LIM) = 24A
Boost Mode:
Input Voltage, V2 = 8V to 18V
125kHz • 16A • 48V
1
14V(54V − 14V)
2 125kHz • 10µH • 54V
L LMAXBOOST = 40A +
1
= 44.1A
18V(48V − 18V)
2 125kHz • 10µH • 48V
(50)
= 44.5A
Rev. 0
60
For more information www.analog.com
LT8228
APPLICATIONS INFORMATION
The maximum inductor current in boost mode is higher
than the buck mode. The peak inductor current IL(PEAK)
is selected to be 54A which is 21% higher than the maximum inductor current in buck mode. The voltage drop
across RSNS2 current sense resistor is selected to be
80mV for 40A V2 output current limit. RSNS2 value is calculated according to Equation 51.
R SNS2 =
80mV
40A
= 2mΩ
RIN2 =
72.5µA
= 1.5kΩ
(52)
RSNS2 and RIN2 resistance values are selected to be 2mΩ
and 1.5kΩ respectively based on availability. The power
dissipation at the current sense resistor RSNS2 at V2 output current limit is given by Equation 53.
(53)
PRSNS2 = 80mV • 40A = 3.2W
The selected RSNS2 has a power rating of 5W to ensure
performance. This combination of RSNS2, RIN2, and
switching frequency and Inductor also satisfies the condition for LOPTIMAL given in the inductor selection section.
RSET2P and RSET2N Selection: The resistance values
of RSET2P and RSET2N are calculated using Equation 54
based on the given specification for V2 output current
limit IV2P(LIM) in buck mode and V2 input current limit
IV2N(LIM) in boost mode.
R SET2P =
R SET2N =
1.5kΩ
2mΩ • 40A
1.5kΩ
2mΩ • 40A
RMON2 Selection: VMON2MAX is selected to be 2V based
on the ADC input specification. The resistance of RMON2
is calculated using Equation 55.
1.5kΩ
40A • 2mΩ
• 2V = 37.5kΩ
100mV
54A
= 1.9mΩ
(56)
RIN1 =
54A • 2mΩ
72.5µA
= 1.5kΩ
(57)
RSNS1 and RIN1 resistance values are selected to be 2mΩ
and 1.5kΩ respectively. The power dissipation at the current sense resistor RSNS1 at V1 input current limit is given
byEquation 58.
(58)
2
PRSNS1 = (24A) • 2mΩ = 1.2W
The selected RSNS1 has a power rating of 3W to ensure
performance.
RSET1P and RSET1N Selection: The resistance values
of RSET1P and RSET1N are calculated using Equation 59
based on the given specification for V1 input current
limit IV1P(LIM) in buck mode and V1 output current limit
IV1N(LIM) in boost mode.
R SET1P =
(54)
• 1.21V = 22.7kΩ
R SNS1 =
RSNS1 is selected to be 2mΩ due to availability. RIN1 is
chosen so that the maximum feedback current in CSA1
is less than 72.5µA (Equation 57).
• 1.21V = 22.7kΩ
RSET2P and RSET2N resistance values are selected to be
22.6kΩ based on availability.
R MON2 =
RSNS1 and RIN1 Selection: For accuracy consideration,
the maximum voltage drop across RSNS1 is selected to
be 100mV. Maximum current through RSNS1 is 54A peak
inductor current. The RSNS1 resistance is calculated using
Equation 56 based on the buck mode specification.
(51)
RIN2 value is calculated according to Equation 52.
54A • 2mΩ
RMON2 resistance value is selected to be 37.4kΩ based
on availability.
R SET1N =
1.5kΩ
2mΩ • 24A
1.5kΩ
2mΩ • 10A
• 1.21V = 37.8kΩ
(59)
• 1.21V = 90.8kΩ
RSET1P and RSET1N resistance values are selected to be
37.4kΩ and 88.7kΩ respectively based on availability.
RMON1 Selection: VMON1MAX is selected to be 2V based
on the ADC input specification. The resistance of RMON1
is calculated using Equation 60.
(55)
R MON1 =
1.5kΩ
24A • 2mΩ
• 2V = 62.5kΩ
(60)
Rev. 0
For more information www.analog.com
61
LT8228
APPLICATIONS INFORMATION
RMON1 resistance value is selected to be 61.9kΩ based
on availability.
For V2 protection MOSFET M4, the worst case is when V2
output current is maximum in buck mode (Equation 64).
RFB2B, RFB2A, RFB1B and RFB2B Selection: The bottom
resistors RFB2B and RFB1B are selected to be 1.21kΩ for
1mA bias current in the resistor dividers. The resistance
RFB2A and RFB1A are calculated based on Equation 61.
Pd(M4) = 402 • 0.75mΩ = 1.2W (64)
⎛ 14V
⎞
R FB2A = ⎜
− 1⎟ • 1.21kΩ = 12.8kΩ
⎝ 1.21V ⎠
⎛ 48V
⎞
R FB1A = ⎜
− 1⎟ • 1.21kΩ = 46.8kΩ
⎝ 1.21V ⎠
(61)
BVDSS = 80V
RDS(ON) = 7.4mΩ (Max)
CMILLER = 130pF
VTH(IL) = 3.0V
RFB2B and RFB1B resistance values are selected to be
13kΩ and 47.5kΩ respectively based on availability.
RUV2B, RUV2A, RUV1B and RUV2B Selection: The bottom
resistors RUV2B and RUV1B are selected to be 12.1kΩ for
100µA bias current in the resistor dividers. The resistance
RUV2A and RUV1A are calculated by Equation 62.
⎛ 14V
⎞
R FB2A = ⎜
− 1⎟ • 1.21kΩ = 12.8kΩ
⎝ 1.21V ⎠
The maximum voltage requirement for the switching
MOSFETs M2 and M3 are 54V plus some ringing. The
Infineon IAUC70N08S5N074 has:
(62)
⎛ 48V
⎞
− 1⎟ • 1.21kΩ = 46.8kΩ
R FB1A = ⎜
⎝ 1.21V ⎠
RUV2A and RUV1A resistance values are selected to be
69.8kΩ and 232kΩ respectively based on availability.
M1, M2, M3 and M4 Selection: In case of V1 protection
MOSFETs, the maximum voltage requirement is 54V. V2
protection MOSFETs need to protect against reverse voltage. Therefore, the maximum voltage requirement is 28V.
The Infineon IPT007N06N has:
BVDSS = 60V
RDS(ON) = 0.75mΩ (max)
JA = 42K/W
To reduce the temperature rise to meet ambient temperature specification, 4 MOSFETs are used in parallel for both
the TG MOSFET M2 and BG MOSFET M3. In buck mode,
power dissipation in the top MOSFET M2 and the bottom
MOSFET M3 are given by Equation 65.
2
14V ⎛ 40 ⎞
PM2(BUCK) =
• ⎜ ⎟ • 7.4mΩ + 48V 2 •
48V ⎝ 4 ⎠
⎡
1
1⎤
• 2Ω • 130pF • ⎢
+
•
⎣ 10V − 3V 3V ⎥⎦
2
40A
2
PM3(BUCK) =
48V − 14V ⎛ 40 ⎞
• ⎜ ⎟ • 7.4mΩ = 2.10W
⎝ 4 ⎠
48V
In Boost mode, power dissipation in the top MOSFET M2
and the bottom MOSFET M3 are given by Equation 66.
2
14V ⎛ 40 ⎞
PM2(BOOST) =
• ⎜ ⎟ • 7.4mΩ = 0.86W
48V ⎝ 4 ⎠
2
VTH(IL) = 2.8V
PM3(BOOST) =
The power dissipations of the MOSFETs are checked in
their worst-case condition. For V1 protection MOSFET M1,
the worst case is when the V1 input current is maximum
in buck mode (Equation 63).
7.4mΩ +
Pd(M1)
(65)
125kHz = 0.86W + 0.96W = 1.83W
= 242 • 0.75mΩ = 0.43W (63)
⎡
⎢⎣
48V = 14V • 48V ⎛ 10 ⎞
•⎜ ⎟ •
⎝ 4 ⎠
14V 2
48V 3 10 1
•
• 2Ω • 130pF •
4 2
14V
1
10V − 3V
+
(66)
1⎤
⎥ • 125kHz =
3V ⎦
1.54W + 0.02W = 1.56W
Rev. 0
62
For more information www.analog.com
LT8228
APPLICATIONS INFORMATION
The worst-case power dissipation is 1.83W in M2 and
2.10W in M3.
CDM2 and CDM1 Selection: CDM1 and CDM2 are selected
to meet the RMS current requirement in buck mode. For
ILMAXBUCK of 40A, the maximum RMS current is 20A.
Ten TDKCKG57NX72A capacitors are tied in parallel for
CDM1 where each capacitor has 2A of RMS current. Each
capacitor is 22µF with 10mΩ of ESR. One aluminum electrolytic capacitor with high bulk capacitance of 68µF and
high ESR of 320mΩ is selected for CDM1 to reduce the
source impedance. Six TDKCKG32KX7RA capacitors are
tied in parallel for CDM1 where each capacitor has 2A of
RMS current. Each capacitor is 1µF with 10mΩ of ESR.
The ESR dominates the boost mode ripple voltage which
is given by Equation 67.
∆VESR(CDM2) = 44.5A •
10mΩ
16
= 278mV
(67)
Therefore, the selected capacitors for CDM2 meet the given
voltage ripple specification for boost output.
CDM4 Selection: CDM4 is selected to meet the ripple voltage
requirement at V2D in buck mode. Eight TDKCGA8P1X7R
capacitors are tied in parallel at the V2D node. The ripple
voltage is given by Equation 68.
∆V2D = 44.5A •
10mΩ
16
= 278mV
Therefore, the selected capacitors for CDM4 meet the given
voltage ripple specification for buck output. One aluminum electrolytic capacitor with high bulk capacitance of
100µF and high ESR of 30mΩ are also added to reduce
the source impedance.
CV1 and CV2 Selection: A 10µF ceramic capacitor with
100mΩ series resistance is used at each V1 and V2 node
for input bypass and resonance reduction.
CDG1, CDG2, RDG1, and RDG2 Selection: For 500mA of
buck inrush current (Equation 69).
CDG1 =
10µA • (68µF + 10 • 22µF)
500mA
= 5.76nF
(69)
CDG1 is selected to be 6.8nF based on availability. RDG1
is selected to be 20kΩ to stabilize boost V1 short current
regulation loop.
For 1A of boost inrush current (Equation 70).
CDG2 =
10µA • (100µF + 8 • 22µF)
1A
= 2.76nF
(70)
CDG2 is selected to be 3.3nF based on availability. RDG2
is selected to be 10kΩ to prevent slowdown of DG2
turn-off speed.
(68)
Rev. 0
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63
LT8228
TYPICAL APPLICATIONS
2.5J Power Interrupt Protection
M4
V2 INPUT SUPPLY
8V TO 36V
V2 SYSTEM LOAD
10µF
100µF
10mΩ
L1
15µH
DS2
DG2
SNS2N
BG GND
DRVCC BST SW TG
20k
68µF
V1 BACKUP CAPACITOR
OUTPUT: 70V, 500mA
INPUT: 8V – 70V, 5A
6.8nF
6mF
1k
1k
SNS1N
SNS1P
1k
SNS2P
M1
22µF
(x6)
10µF
1k
6.81k
0.1µF
M3
22µF
(×4)
33.2k
10mΩ
M2
V1D DG1
UV2
DS1
BIAS
ENABLE
1.21k
10µF
FB2
1.21k
6.8k
REPORT
100k
100k
1.21k
SYNC
FB1
FAULT
DRXN
INTVCC
69.8k
UV1
LT8228
1.21k
RT
ISHARE
IGND
TMR
SS
ISET2P
ISET1P
VC2
IMON2
IMON1
1k
100nF
1µF
220nF
10nF
ISET2N
ISET1N
1k
18.2k
24.3k
VC1
22nF
18.2k
243k
68nF
10nF
100k
8228 TA03
Rev. 0
64
For more information www.analog.com
LT8228
TYPICAL APPLICATIONS
Buck 840W (14V 60A) and Boost 960W (48V 20A) Parallel Regulators
V1
INPUT: 24V – 54V, 20A
OUTPUT: 48V, 20A
M1
10µF
V1
M2
DS1
BIAS
V1DA
DG1 V1D
TG SW BST DRVCC
M5
22µF
(×8)
1.5k
SNS1P SNS1N
V2DA
10µF
1.5k
BIAS
ENABLE
V1
2mΩ
0.1µF
M4
(×4)
22µF
(×6)
1.5k
6.8nF
L1
10µH
M3 (×4)
68µF
(×2)
20k
V2
2mΩ
V1DA
10µF
100µF
10k
1.5k
3.3nF
GND BG SNS2P SNS2N
DG2
DS2
DRXN
FAULT
10µF
60.4k
REPORT
36.5k
UV1
V2
OUTPUT: 14V, 60A
INPUT: 8V – 18V, 60A
M6
100k
5V EXT
V2
V2DA
100k
10k
8.06k
1.21k
1.21k
FB1
1.33k
ISHARE
84k
FB2
ISHARE
5.62k
SYNC
IGND
42k
10nF
60.4k
UV2
LT8228
ISET1N
DRXN
ISET2N
VC1
10nF
IMON2
VC2
40.2k
10nF
ISET1P
ISET2P
84k
28k
SS
1k
1k
28k
84k
IMON1
40.2k
INTVCC
100nF
RT
2.2µF
220nF
10nF
10nF
22nF
68nF
TMR
LTC6902
OUT1 V+
100k
5V EXT
OUT2 DIV
MOD
M7
V1
M8
2mΩ
V1DB
20k
DS1
V1
60.4k
DG1 V1D
1.5k
SNS1P SNS1N
TG SW BST DRVCC
BIAS
ENABLE
V2DB
M11
M12
10k
1.5k
GND BG SNS2P SNS2N
DG2
DS2
DRXN
SYNC
36.5k
LT8228
ISET1N
ISET2N
VC1
IMON1
IMON2
DRXN
28k
84k
10nF
10nF
40.2k
68nF
VC2
ISET1P
ISET2P
SS
V2DB
60.4k
40.2k
INTVCC
28k
84k
22nF
TMR
FB2
RT
5.62k
100nF
1k
1k
84k
V2
10k
1.21k
ISHARE
10nF
5V EXT
UV2
FB1
IGND
100k
8.06k
1.21k
42k
1µF
3.3nF
REPORT
FAULT
1.33k
GND
100µF
10µF
UV1
PH
V2
10µF
22µF
(×8)
1.5k
1.5k
20k
SET
2mΩ
0.1µF
M10
(×4)
10µF
22µF
(×6)
6.8nF
V1DB
M9 (×4)
68µF
(×2)
10µF
L2
10µH
10nF
2.2µF
10nF
220nF
100k
8228 TA04
M1, M2, M5, M6, M7, M8, M11 AND M12: NVMFS5C673NL
M3, M4, M9 AND M10: IPT007N06N
L1, L2: WE7443763540100
Rev. 0
For more information www.analog.com
65
LT8228
TYPICAL APPLICATIONS
3kW (14V 240A) and Boost 3kW (48V 60A) 12-Phase Parallel Regulators
V1
INPUT: 24V – 54V, 120A
OUTPUT: 48V, 60A
M1
M2
20k
1.2k
DS1
DG1 V1D
3mΩ
1.2k
SNS1P SNS1N
TG SW BST DRVCC
M5
22µF
(×8)
10µF
1.2k
BIAS
V2D
0.1µF
M4
(×4)
22µF
(×6)
6.8nF
BIAS
L1
6.8µH
M3 (×4)
68µF
(×2)
10µF
V1 V1
4mΩ
V1D
V2
OUTPUT: 14V, 240A
INPUT: 8V – 18V, 240A
M6
10µF
100µF
10k
1.2k
3.3nF
GND BG SNS2P SNS2N
DG2
1.21k
FB2
36.5k
LT8228
(PHASE 1)
UV1
ENABLE
SYNC
1.21k
FB1
1.33k
ISHARE
72.7k
10nF
60.4k
UV2
10µF
60.4k
V2D
8.06k
DS2
V1
V1D
V2
36.5k
FAULT
REPORT
ISHARE
IGND
ISET1N
DRXN
ISET2N
24.3k
36.5k
10nF
VC1
IMON1
IMON2
VC2
ISET2P
SS
1k
1k
40.2k
22nF
TMR
220nF
10nF
10nF
RT
INTVCC
100nF
24.3k
36.5k
40.2k
68nF
10nF
ISET1P
68k
DRXN
5.62k
ENABLE1
SYNC1
FAULT1
100k
REPORT1
10k
DRXN
100k
5V EXT
2.2µF
M1, M2, M5, M6: NVMFS5C673NL
M3, M4: IPT007N06N
L1: WE7443763540100
V1
BIAS
V2
ENABLE
ISHARE
SYNC
LT8228
(PHASE 2)
FAULT
REPORT
DRXN
V1
ENABLE2
SYNC2
FAULT2
100k
REPORT2
10k
DRXN
V2
BIAS
ENABLE
ISHARE
SYNC
LT8228
(PHASE 12)
FAULT
REPORT
MICROCONTROLLER + DIGITAL LOGIC + EXT SUPPLY
BIAS
CLOCK: LTC6909CMS, 74LCX14
MUX: ADG715
GPIO EXPANSION: PCA9575
MICRO: ADICUP360
100k
REPORT12 10k
DRXN
REPORT12
REPORT1
REPORT2
FAULT12
FAULT1
FAULT2
SYNC12
SYNC1
SYNC2
ENABLE12
ENABLE1
ENABLE2
DRXN
ENABLE12
SYNC12
FAULT12
5V EXT
DRXN
8228 TA05
Rev. 0
66
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LT8228
PACKAGE DESCRIPTION
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1
0.25
REF
19
1.20
(.047)
MAX
0° – 8°
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AA) TSSOP REV C 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
moreby
information
www.analog.com
67
LT8228
TYPICAL APPLICATION
Buck 560W (14V 40A) and Boost 480W (48V 10A) Parallel Regulators
BOOST (48V AT 10A)
M1B
V1 SUPPLY
24V TO 54V
M1A
6.8nF
22µF
(×6)
DG1 V1D
M4A
10µF
SNS1P SNS1N
TG SW BST DRVCC
10k
3.3nF
GND BG SNS2P SNS2N
DG2
µC
V
100k DD
DS2
DRXN
UV1
10k
REPORT
LT8228
V2
100k
FAULT
10µF
1.21k
V2 14V
BATTERY
BACKUP
1.5k
232k
V1D
12.1k
47.5k
M4B
22µF
(×8)
1.5k
BIAS
ENABLE
V1
V2D
M3
1.5k
1.5k
DS1
BUCK (14V AT 40A)
RSNS2
2mΩ
0.1µF
68µF
22µF
(×8)
20k
V2
10µH
M2
+
10µF
V1
RSNS1
2mΩ
V1D
UV2
69.8k
V2D
12.8k
FB1
ISET1N
10nF
12.1k
FB2
ISET2N
VC1
22.6k
88.7k
10nF
IMON1
4.32k
IMON2
61.9k
VC2
37.4k
ISET1P
4.32k
SS
TMR
22.6k
10nF
220nF
10nF
1.21k
INTVCC ISHARE RT SYNC
100nF
37.4k
15nF
100nF
ISET2P
1µF
78.7k
TO
CLK
8228 TA02
* VMON1 FULL-SCALE IS 2V AT 24A, V MON2 FULL-SCALE IS 2V AT 40A
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Low EMI and Low Input/Output Ripple
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LTC3899
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Controller with 29µA Burst Mode Operation IQ
4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, Buck
VOUT Range: 0.8V to 60V, Boost VOUT Up to 60V
LTC3769
60V Low IQ Synchronous Boost Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, IQ =
28µA PLL Fixed Frequency 50kHz to 900kHz.
LTM®8056
58V Buck-Boost μModule Regulator, Adjustable Input and
Output Current Limiting
5V≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V, 15mm × 15mm × 4.92mm
BGA Package
LTC3895/
LTC7801
150V Low IQ, Synchronous Step-Down DC/DC Controller
with 100% Duty Cycle
4V ≤ VIN ≤ 140V, 150V ABS Max, PLL Fixed-Frequency 50kHz to
900kHz, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive,
IQ = 40µA, 4mm × 5mm QFN-24, TSSOP-24, TSSOP-38(31)
LTC7103
105V, 2.3A Low EMI Synchronous Step-Down Regulator
4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2µA, Fixed-Frequency 200kHz
to 2MHz, 5mm × 6mm QFN
Rev. 0
68
11/19
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