LTC2175-14/
LTC2174-14/LTC2173-14
14-Bit, 125Msps/105Msps/
80Msps Low Power Quad ADCs
Features
n
n
n
n
n
n
n
n
n
n
n
n
Description
4-Channel Simultaneous Sampling ADC
73.1dB SNR
88dB SFDR
Low Power: 558mW/450mW/376mW Total,
140mW/113mW/94mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1VP-P to 2VP-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
52-Pin (7mm × 8mm) QFN Package
The LTC®2175-14/LTC2174-14/LTC2173-14 are 4-channel,
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applications with AC performance that includes 73.1dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 1.2LSBRMS.
The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
Applications
Communications
Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multichannel Data Acquisition
n Nondestructive Testing
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of
clock duty cycles.
Typical Application
1.8V
VDD
CHANNEL 1
ANALOG
INPUT
LTC2175-14, 125Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
1.8V
OVDD
S/H
14-BIT
ADC CORE
OUT1A
0
OUT1B
–10
CHANNEL 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
OUT2A
CHANNEL 3
ANALOG
INPUT
S/H
14-BIT
ADC CORE
S/H
14-BIT
ADC CORE
CHANNEL 4
ANALOG
INPUT
ENCODE
INPUT
–20
OUT3A
OUT3B
OUT4A
OUT4B
DATA
CLOCK
OUT
PLL
FRAME
SERIALIZED
LVDS
OUTPUTS
AMPLITUDE (dBFS)
DATA
SERIALIZER
–30
OUT2B
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
217514 TA01b
GND
OGND
217514 TA01
21754314fa
1
LTC2175-14/
LTC2174-14/LTC2173-14
Absolute Maximum Ratings
Pin ConfigurationS
(Notes 1, 2)
OUT1B–
OUT1B+
OUT1A–
OUT1A+
GND
SDO
PAR/SER
VREF
GND
SENSE
VDD
TOP VIEW
VDD
Supply Voltages
VDD, OVDD................................................. –0.3V to 2V
Analog Input Voltage (AIN+, AIN –,
PAR/SER, SENSE) (Note 3)........... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4)..................................... –0.3V to 3.9V
SDO (Note 4).............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2175C, 2174C, 2173C.......................... 0°C to 70°C
LTC2175I, 2174I, 2173I.........................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
52 51 50 49 48 47 46 45 44 43 42 41
AIN1+ 1
40 OUT2A+
–
2
39 OUT2A–
VCM12 3
38 OUT2B+
AIN1
+
4
37 OUT2B–
–
5
36 DCO+
REFH 6
35 DCO–
AIN2
AIN2
REFH 7
34 OVDD
53
GND
REFL 8
33 OGND
REFL 9
32 FR+
AIN3+ 10
31 FR–
AIN3– 11
30 OUT3A+
VCM34 12
29 OUT3A–
AIN4+ 13
28 OUT3B+
–
27 OUT3B–
AIN4 14
OUT4A+
OUT4A–
OUT4B+
OUT4B–
GND
SDI
SCK
CS
ENC–
ENC+
VDD
VDD
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2175CUKG-14#PBF
LTC2175CUKG-14#TRPBF
LTC2175UKG-14
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2175IUKG-14#PBF
LTC2175IUKG-14#TRPBF
LTC2175UKG-14
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2174CUKG-14#PBF
LTC2174CUKG-14#TRPBF
LTC2174UKG-14
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2174IUKG-14#PBF
LTC2174IUKG-14#TRPBF
LTC2174UKG-14
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2173CUKG-14#PBF
LTC2173CUKG-14#TRPBF
LTC2173UKG-14
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2173IUKG-14#PBF
LTC2173IUKG-14#TRPBF
LTC2173UKG-14
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
21754314fa
2
LTC2175-14/
LTC2174-14/LTC2173-14
Converter
Characteristics l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2175-14
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
l
LTC2174-14
TYP
MAX
MIN
14
LTC2173-14
TYP
MAX
MIN
14
TYP
MAX
UNITS
14
Bits
Integral Linearity Error
Differential Analog Input (Note 6) l
–4.1
±1.2
4.1
–3.25
±1
3.25
–2.75
±1
2.75
LSB
Differential Linearity Error
Differential Analog Input
l
–0.9
±0.3
0.9
–0.8
±0.3
0.8
–0.8
±0.3
0.8
LSB
Offset Error
(Note 7)
l
–12
±3
12
–12
±3
12
–12
±3
12
mV
Gain Error
Internal Reference
External Reference
–2.6
–1.3
–1.3
–2.6
–1.3
–1.3
–2.6
–1.3
–1.3
0
%FS
%FS
l
Offset Drift
0
0
±20
±20
±20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
±35
±25
±35
±25
±35
±25
ppm/°C
ppm/°C
Gain Matching
External Reference
±0.2
±0.2
±0.2
%FS
±3
±3
±3
mV
External Reference
1.2
1.2
1.2
LSBRMS
Offset Matching
Transition Noise
Analog
Input
The
l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN(CM)
Analog Input Range (AIN+ – AIN–)
Analog Input Common Mode (AIN+ + AIN–)/2
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
IINCM
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
IIN1
Analog Input Leakage Current No Encode
0 < AIN+, AIN– < VDD,
l
–1
1
µA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
µA
IIN3
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
l
–6
6
µA
tAP
Sample-and-Hold Acquisition Delay Time
0
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.15
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
VIN
1.7V < VDD < 1.9V
l
Differential Analog Input (Note 8)
l
VCM – 100mV
VCM
VCM + 100mV
V
l
0.625
1.250
1.300
V
Figure 6 Test Circuit
1 to 2
VP-P
155
130
100
µA
µA
µA
ns
psRMS
80
dB
800
MHz
21754314fa
3
LTC2175-14/
LTC2174-14/LTC2173-14
Dynamic Accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2175-14
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
70MHz Input
140MHz Input
SFDR
S/(N+D)
MAX
LTC2174-14
MAX
LTC2173-14
MIN
TYP
MIN
TYP
MIN
TYP
l
71.1
73.1
73
72.6
70.7
73
72.9
72.6
70.9
73
72.9
72.5
MAX
UNITS
dBFS
dBFS
dBFS
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
l
75
88
85
82
75
88
85
82
77
88
85
82
dBFS
dBFS
dBFS
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
l
84
90
90
90
84
90
90
90
85
90
90
90
dBFS
dBFS
dBFS
l
69.6
73
72.6
72
70.2
73
72.6
72
70.4
72.9
72.6
72
dBFS
dBFS
dBFS
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
Crosstalk, Near Channel
10MHz Input (Note 12)
–90
–90
–90
dBc
Crosstalk, Far Channel
10MHz Input (Note 12)
–105
–105
–105
dBc
Internal
Reference Characteristics l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
±25
VCM Output Resistance
–600µA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
VREF Output Temperature Drift
1.250
±25
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
7
0.6
V
ppm/°C
4
1.225
UNITS
Ω
1.275
V
ppm/°C
Ω
mV/V
21754314fa
4
LTC2175-14/
LTC2174-14/LTC2173-14
Digital
Inputs and Outputs l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
l
0.2
VIN
Input Voltage Range
ENC+, ENC– to GND
RIN
Input Resistance
(See Figure 10)
CIN
Input Capacitance
V
1.2
1.6
V
V
3.6
V
10
kΩ
3.5
pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
(See Figure 11)
CIN
Input Capacitance
1.2
V
0.6
0
3.6
V
V
30
kΩ
3.5
pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
1.3
V
–10
0.6
V
10
µA
3
pF
200
Ω
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
l
–10
10
3
µA
pF
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
mV
mV
V
V
Ω
21754314fa
5
LTC2175-14/
LTC2174-14/LTC2173-14
Power
Requirements l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2175-14
SYMBOL PARAMETER
LTC2173-14
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
Analog Supply Current
Sine Wave Input
l
283
305
224
243
184
200
mA
IOVDD
Digital Supply Current
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
27
49
31
54
26
48
31
53
25
47
29
52
mA
mA
PDISS
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
558
598
605
646
450
490
493
533
376
416
412
454
mW
mW
PSLEEP
Sleep Mode Power
1
1
1
mW
PNAP
Nap Mode Power
85
85
85
mW
PDIFFCLK
Power Increase With Differential Encode Mode Enabled
(No Increase for Sleep Mode)
20
20
20
mW
VDD
Analog Supply Voltage
OVDD
IVDD
CONDITIONS
LTC2174-14
MAX UNITS
1.9
V
Timing
Characteristics
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2175-14
SYMBOL
PARAMETER
CONDITIONS
fS
Sampling Frequency
(Notes 10,11)
l
MIN
5
tENCL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
tENCH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
tAP
Sample-and-Hold
Acquisition Delay Time
SYMBOL
PARAMETER
TYP
LTC2174-14
MAX
MIN
125
5
4
4
100
100
4.52
2
4
4
100
100
4.52
2
0
TYP
LTC2173-14
MAX
MIN
105
5
4.76
4.76
100
100
5.93
2
4.76
4.76
100
100
5.93
2
0
CONDITIONS
MIN
TYP
MAX
MHz
6.25
6.25
100
100
ns
ns
6.25
6.25
100
100
ns
ns
0
TYP
UNITS
80
ns
MAX
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
1/(8 • fS)
1/(7 • fS)
1/(6 • fS)
1/(16 • fS)
1/(14 • fS)
1/(12 • fS)
s
s
s
s
s
s
tSER
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
tFRAME
FR to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
s
tDATA
DATA to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
s
tPD
Propagation Delay
(Note 8)
l
tR
Output Rise Time
tF
Output Fall Time
DCO Cycle-Cycle Jitter
tSER = 1ns
Pipeline Latency
0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER
s
Data, DCO, FR, 20% to 80%
0.17
ns
Data, DCO, FR, 20% to 80%
0.17
ns
60
psP-P
6
Cycles
21754314fa
6
LTC2175-14/
LTC2174-14/LTC2173-14
timing
characteristics
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP
= 2k
l
l
40
250
ns
ns
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP
= 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz
(LTC2174), or 80MHz (LTC2173), 2-lane output mode, differential ENC+/
ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
l
125
ns
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz
(LTC2174), or 80MHz (LTC2173), 2-lane output mode, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps so tSER must be greater than or equal to 1ns.
Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4.
Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and
Ch.2 to Ch.4.
21754314fa
7
LTC2175-14/
LTC2174-14/LTC2173-14
Timing Diagrams
2-Lane Output Mode, 16-Bit Serialization*
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
tDATA
tSER
tPD
OUT#A–
OUT#A+
OUT#B–
OUT#B+
tSER
D5
D3
D1
0
D13 D11 D9
D7
D5
D3
D1
0
D13 D11 D9
D4
D2
D0
0
D12 D10 D8
D6
D4
D2
D0
0
D12 D10 D8
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
217514 TD01
*SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP
ANALOG
INPUT
N+2
N
tENCH
ENC–
N+1
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
OUT#B–
OUT#B+
tDATA
tSER
tPD
tSER
D7
D5
D3
D1 D13 D11 D9
D7
D5
D3
D1 D13 D11 D9
D7
D5
D3
D1 D13 D11 D9
D6
D4
D2
D0 D12 D10 D8
D6
D4
D2
D0 D12 D10 D8
D6
D4
D2
D0 D12 D10 D8
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
SAMPLE N-3
217514 TD02
NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–
21754314fa
8
LTC2175-14/
LTC2174-14/LTC2173-14
timing DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
tAP
ANALOG
INPUT
N
N+1
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
FR+
tFRAME
tDATA
tPD
tSER
FR–
OUT#A–
OUT#A+
OUT#B–
OUT#B+
tSER
D9
D7
D5
D3 D13 D11 D9
D7
D5
D3 D13 D11 D9
D8
D6
D4
D2 D12 D10 D8
D6
D4
D2 D12 D10 D8
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
217514 TD03
1-Lane Output Mode, 16-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
tDATA
tSER
tPD
D1
D0
SAMPLE N-6
0
tSER
0
D13 D12 D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
D13 D12 D11 D10
SAMPLE N-4
217514 TD05
OUT#B+, OUT#B– ARE DISABLED
21754314fa
9
LTC2175-14/
LTC2174-14/LTC2173-14
timing DIAGRAMS
One-Lane Output Mode, 14-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
tDATA
tSER
tPD
D3
D2
tSER
D1
D0 D13 D12 D11 D10 D9
SAMPLE N-6
D8
D7
D6
D5
D4
D3
D2
D1
D0 D13 D12 D11 D10
SAMPLE N-5
SAMPLE N-4
217514 TD06
OUT#B+, OUT#B– ARE DISABLED
One-Lane Output Mode, 12-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
tDATA
tSER
tPD
D5
D4
D3
tSER
D2 D13 D12 D11 D10 D9
SAMPLE N-6
D8
D7
D6
D5
D4
D3
D2 D13 D12 D11
SAMPLE N-5
SAMPLE N-4
217514 TD07
OUT#B+, OUT#B– ARE DISABLED
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
217514 TD04
21754314fa
10
LTC2175-14/
LTC2174-14/LTC2173-14
Typical Performance Characteristics
LTC2175-14: Integral
Nonlinearity (INL)
LTC2175-14: Differential
Nonlinearity (DNL)
2.0
1.0
0
1.5
0.8
–10
0
–0.5
–1.0
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
0.5
0.2
0
–0.2
–0.4
–0.8
0
4096
8192
12288
OUTPUT CODE
–1.0
16384
0
4096
8192
12288
OUTPUT CODE
217514 G01
–60
–70
–80
–110
–120
16384
LTC2175-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 125Msps
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–110
–120
–110
–120
–110
–120
20
30
40
FREQUENCY (MHz)
50
60
0
10
20
30
40
FREQUENCY (MHz)
50
60
LTC2175-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
60
73
5000
72
–50
SNR (dBFS)
4000
–40
COUNT
AMPLITUDE (dBFS)
50
74
–30
3000
–60
–70
–80
2000
–90
–100
1000
–110
–120
20
30
40
FREQUENCY (MHz)
LTC2175-14: SNR vs Input
Frequency, –1dB, 2V Range,
125Msps
LTC2175-14: Shorted Input
Histogram
–10
–20
10
217514 G06
6000
0
0
217514 G05
217514 G04
60
–40
–90
–100
10
50
–50
–90
–100
0
20
30
40
FREQUENCY (MHz)
LTC2175-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 125Msps
0
–50
10
217514 G03
–10
–40
0
217514 G02
LTC2175-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 125Msps
AMPLITUDE (dBFS)
–40
–50
–90
–100
–0.6
–1.5
–2.0
–20
0.6
1.0
INL ERROR (LSB)
LTC2175-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 125Msps
71
70
69
68
0
10
20
30
40
FREQUENCY (MHz)
50
60
217514 G07
0
8178
67
8180
8182
8184
OUTPUT CODE
8186
217514 G08
66
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
217514 G09
21754314fa
11
LTC2175-14/
LTC2174-14/LTC2173-14
Typical Performance Characteristics
LTC2175-14: SFDR vs Input
Frequency, –1dB, 2V Range,
125Msps
110
95
90
80
dBFS
100
75
80
70
dBc
60
60
SNR (dBc AND dBFS)
SFDR (dBc AND dBFS)
80
50
40
30
40
30
20
10
10
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
350
217514 G10
280
73
40
270
IOVDD (mA)
230
72
1-LANE, 3.5mA
30
71
2-LANE, 1.75mA
20
70
69
1-LANE, 1.75mA
10
68
220
210
67
0
25
50
75
100
SAMPLE RATE (Msps)
0
125
0
25
50
75
100
SAMPLE RATE (Msps)
LTC2174-14: Integral Nonlinearity
(INL)
0.6
1.0
0
1.5
0.8
–10
–1.0
0.2
0
–0.2
–0.4
–0.8
0
4096
8192
12288
OUTPUT CODE
16384
217514 G14
–1.0
1.3
–40
–50
–60
–70
–80
–90
–100
–0.6
–1.5
1.2
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
–0.5
0.9
1
1.1
SENSE PIN (V)
–20
0.6
0
0.8
LTC2174-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 105Msps
2.0
0.5
0.7
217514 G12
LTC2174-14: Differential
Nonlinearity (DNL)
1.0
INL ERROR (LSB)
66
125
217514 G51
217514 G53
–2.0
0
74
2-LANE, 3.5mA
240
–10
LTC2175-14: SNR vs SENSE,
fIN = 5MHz, –1dB
50
250
–40
–30
–20
INPUT LEVEL (dBFS)
217514 G50
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
290
260
–50
217514 G11
LTC2175-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
IVDD (mA)
0
–60
0
SNR (dBFS)
65
dBc
50
20
70
dBFS
70
90
85
SFDR (dBFS)
LTC2175-14: SNR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
LTC2175-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
0
4096
8192
12288
OUTPUT CODE
16384
217514 G15
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
217514 G16
21754314fa
12
LTC2175-14/
LTC2174-14/LTC2173-14
Typical Performance Characteristics
LTC2174-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 105Msps
LTC2174-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 105Msps
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2174-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 105Msps
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
0
10
20
30
40
FREQUENCY (MHz)
50
217514 G18
217514 G17
LTC2174-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
105Msps
6000
73
72
–50
SNR (dBFS)
4000
–40
COUNT
3000
–60
–70
–80
2000
–90
–100
1000
0
10
20
30
40
FREQUENCY (MHz)
70
69
67
0
8195
50
8197
8199
8201
OUTPUT CODE
66
8203
95
110
100
90
SFDR (dBc AND dBFS)
75
220
80
70
60
210
dBc
50
40
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
217514 G23
200
190
180
30
170
10
0
350
230
dBFS
20
70
100 150 200 250 300
INPUT FREQUENCY (MHz)
LTC2174-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
90
80
50
217514 G22
LTC2174-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
85
0
217514 G21
217514 G20
LTC2174-14: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
SFDR (dBFS)
71
68
IVDD (mA)
AMPLITUDE (dBFS)
–30
65
50
74
5000
–20
20
30
40
FREQUENCY (MHz)
217514 G19
LTC2174-14: Shorted Input
Histogram
0
10
LTC2174-14: SNR vs Input
Frequency, –1dB, 2V Range,
105Msps
–10
–110
–120
0
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
217514 G24
160
0
25
50
75
SAMPLE RATE (Msps)
100
217514 G54
21754314fa
13
LTC2175-14/
LTC2174-14/LTC2173-14
Typical Performance Characteristics
LTC2174-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2173-14: Integral Nonlinearity
(INL)
2.0
1.0
73
1.5
0.8
72
1.0
SNR (dBFS)
70
69
0.5
0
–0.5
68
–1.0
67
–1.5
66
–2.0
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
0.6
DNL ERROR (LSB)
INL ERROR (LSB)
74
71
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0
4096
8192
12288
OUTPUT CODE
217514 G25
–1.0
16384
LTC2173-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 80Msps
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–40
–60
–70
–80
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
10
20
30
FREQUENCY (MHz)
40
0
10
20
30
FREQUENCY (MHz)
0
–10
–20
–20
–30
–30
–70
6000
5000
–40
4000
–50
–60
3000
–70
–80
2000
–90
–100
1000
–110
–120
–110
–120
0
10
20
30
FREQUENCY (MHz)
40
217514 G31
40
LTC2173-14: Shorted Input
Histogram
–90
–100
–80
20
30
FREQUENCY (MHz)
COUNT
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–60
10
217514 G30
LTC2173-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
LTC2173-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 80Msps
–40
0
217514 G29
217514 G28
–50
40
16384
–50
–90
–100
0
8192
12288
OUTPUT CODE
LTC2173-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 80Msps
0
–50
4096
217514 G27
–10
–40
0
217514 G26
LTC2173-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 80Msps
AMPLITUDE (dBFS)
LTC2173-14: Differential
Nonlinearity (DNL)
0
10
20
30
FREQUENCY (MHz)
40
217514 G32
0
8184
8186
8188
8190
OUTPUT CODE
8192
217514 G33
21754314fa
14
LTC2175-14/
LTC2174-14/LTC2173-14
Typical Performance Characteristics
LTC2173-14: SNR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTC2173-14: SFDR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTC2173-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
95
74
73
110
100
90
70
69
SFDR (dBc AND dBFS)
SFDR (dBFS)
SNR (dBFS)
72
71
85
80
75
68
66
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
dBc
60
50
40
30
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
DCO Cycle-Cycle Jitter vs Serial
Data Rate
74
350
73
300
PEAK-TO-PEAK JITTER (ps)
180
72
SNR (dBFS)
160
71
70
69
68
150
20
40
60
SAMPLE RATE (Msps)
80
217514 G55
66
250
200
150
100
50
67
0
0
217514 G36
LTC2173-14: SNR vs SENSE,
fIN = 5MHz, –1dB
190
170
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
350
217514 G35
LTC2173-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
IVDD (mA)
70
10
65
217514 G34
140
80
20
70
67
dBFS
90
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
217514 G37
0
0
200
400
600
800
SERIAL DATA RATE (Mbps)
1000
217514 G52
21754314fa
15
LTC2175-14/
LTC2174-14/LTC2173-14
Pin Functions
AIN1+ (Pin 1): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 2): Channel 1 Negative Differential Analog Input.
VCM12 (Pin 3): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 1 and 2. Bypass
to ground with a 0.1µF ceramic capacitor.
AIN2+ (Pin 4): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 5): Channel 2 Negative Differential Analog Input.
REFH (Pins 6,7): ADC High Reference. Bypass to pins 8, 9
with a 2.2µF ceramic capacitor and to ground with a 0.1µF
ceramic capacitor.
REFL (Pins 8,9): ADC Low Reference. Bypass to pins 6, 7
with a 2.2µF ceramic capacitor and to ground with a 0.1µF
ceramic capacitor.
AIN3+ (Pin 10): Channel 3 Positive Differential Analog Input.
AIN3– (Pin 11): Channel 3 Negative Differential Analog Input.
VCM34 (Pin 12): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 3 and 4. Bypass
to ground with a 0.1µF ceramic capacitor.
AIN4+ (Pin 13): Channel 4 Positive Differential Analog Input.
AIN4– (Pin 14): Channel 4 Negative Differential Analog Input.
VDD (Pins 15, 16, 51, 52): 1.8V Analog Power Supply.
Bypass to ground with 0.1µF ceramic capacitors. Adjacent
pins can share a bypass capacitor.
ENC+ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When CS is
low, SCK is enabled for shifting data on SDI into the mode
control registers. In the parallel programming mode (PAR/
SER = VDD), CS selects 2-lane or 1-lane output mode. CS
can be driven with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK selects 3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 21): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data Input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
GND (Pins 22, 45, 49): ADC Power Ground.
OGND (Pin 33): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO is an
input that enables internal 100Ω termination resistors on
the digital outputs. When used as an input, SDO can be
driven with 1.8V to 3.3V logic through a 1k series resistor.
PAR/SER (Pin 47): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
VREF (Pin 48): Reference Voltage Output. Bypass to ground
with a 1µF ceramic capacitor, nominally 1.25V.
21754314fa
16
LTC2175-14/
LTC2174-14/LTC2173-14
Pin Functions
SENSE (Pin 50): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
Exposed Pad (Pin 53): Ground. The Exposed Pad must
be soldered to the PCB ground.
LVDS Outputs
All pins in this section are differential LVDS outputs.
The output current level is programmable. There is an
optional internal 100Ω termination resistor between
the pins of each LVDS output pair.
OUT3B–/OUT3B+, OUT3A–/OUT3A+ (Pins 27/28, 29/30):
Serial data outputs for Channel 3. In 1-lane output mode
only OUT3A–/OUT3A+ are used.
FR–/FR+ (Pins 31/32): Frame Start Outputs.
DCO–/DCO+ (Pins 35/36): Data Clock Outputs.
OUT2B–/OUT2B+, OUT2A–/OUT2A+ (Pins 37/38, 39/40):
Serial data outputs for Channel 2. In 1-lane output mode
only OUT2A–/OUT2A+ are used.
OUT1B–/OUT1B+, OUT1A–/OUT1A+ (Pins 41/42, 43/44):
Serial data outputs for Channel 1. In 1-lane output mode
only OUT1A–/OUT1A+ are used.
OUT4B–/OUT4B+, OUT4A–/OUT4A+ (Pins 23/24, 25/26):
Serial data outputs for Channel 4. In 1-lane output mode
only OUT4A–/OUT4A+ are used.
21754314fa
17
LTC2175-14/
LTC2174-14/LTC2173-14
Functional Block Diagram
1.8V
ENC+ ENC–
VDD
CH 1
ANALOG
INPUT
1.8V
OVDD
OUT1A
14-BIT
ADC CORE
S/H
OUT1B
PLL
OUT2A
CH 2
ANALOG
INPUT
DATA
SERIALIZER
14-BIT
ADC CORE
S/H
OUT2B
OUT3A
OUT3B
CH 3
ANALOG
INPUT
14-BIT
ADC CORE
S/H
OUT4A
OUT4B
CH 4
ANALOG
INPUT
VREF
1µF
DATA CLOCK OUT
14-BIT
ADC CORE
S/H
FRAME
1.25V
REFERENCE
OGND
RANGE
SELECT
SENSE
REFH
REF
BUF
REFL
VDD/2
DIFF
REF
AMP
GND
MODE
CONTROL
REGISTERS
REFH
0.1µF
REFL
0.1µF
2.2µF
0.1µF
VCM12
217514 F01
VCM34
0.1µF
PAR/SER CS SCK SDI SDO
0.1µF
Figure 1. Functional Block Diagram
21754314fa
18
LTC2175-14/
LTC2174-14/LTC2173-14
Applications Information
CONVERTER OPERATION
The LTC2175-14/LTC2174-14/LTC2173-14 are low power,
4-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The
digital outputs are serial LVDS to minimize the number
of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). Many additional features
can be chosen by programming the mode control registers
through a serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM12
or VCM34 output pins, which are nominally VDD/2. For the
LTC2175-14
VDD
AIN+
RON
25Ω
10Ω
AIN–
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC low pass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
50Ω
VCM
0.1µF
0.1µF
RON
25Ω
10Ω
The four channels are simultaneously sampled by a shared
encode circuit (Figure 2).
CSAMPLE
3.5pF
CPARASITIC
1.8pF
VDD
2V input range, the inputs should swing from VCM – 0.5V
to VCM + 0.5V. There should be 180° phase difference
between the inputs.
CSAMPLE
3.5pF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTC2175-14
0.1µF
12pF
CPARASITIC
1.8pF
25Ω
VDD
25Ω
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
217514 F03
1.2V
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz.
10k
ENC+
ENC–
10k
1.2V
217514 F02
Figure 2. Equivalent Input Circuit. Only One of the Four
Analog Channels is Shown.
21754314fa
19
LTC2175-14/
LTC2174-14/LTC2173-14
Applications Information
tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission
line balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
50Ω
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
4 to 6) should convert the signal to differential before
driving the A/D.
Reference
The LTC2175-14/LTC2174-14/LTC2173-14 has an internal
1.25V voltage reference. For a 2V input range using the
internal reference, connect SENSE to VDD. For a 1V input
range using the internal reference, connect SENSE to
50Ω
VCM
0.1µF
0.1µF
0.1µF
ANALOG
INPUT
T1
0.1µF
AIN+
T2
25Ω
LTC2175-14
0.1µF
25Ω
HIGH SPEED
DIFFERENTIAL
0.1µF
AMPLIFIER
AIN+
25Ω
LTC2175-14
0.1µF
1.8pF
0.1µF
25Ω
AIN–
217514 F06
VCM
VCM
0.1µF
T1
2.7nH
Figure 6. Recommended Front End Circuit for Input
Frequencies Above 300MHz
Figure 4. Recommended Front End Circuit for Input
Frequencies from 70MHz to 170MHz
T2
25Ω
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
0.1µF
LTC2175-14
T1
217514 F04
ANALOG
INPUT
AIN+
0.1µF
25Ω
0.1µF
AIN–
50Ω
2.7nH
ANALOG
INPUT
4.7pF
0.1µF
VCM
AIN–
ANALOG
INPUT
+
+
–
–
200Ω
200Ω
25Ω
0.1µF
AIN+
LTC2175-14
12pF
0.1µF
25Ω
AIN–
217514 F07
217514 F05
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 7. Front End Circuit Using a High Speed
Differential Amplifier
Figure 5. Recommended Front End Circuit for Input
Frequencies from 170MHz to 300MHz
21754314fa
20
LTC2175-14/
LTC2174-14/LTC2173-14
Applications Information
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
and REFL should be as close to the pins as possible (not
on the backside of the circuit board).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
Encode Input
The reference is shared by all four ADC channels, so it is
not possible to independently adjust the input range of
individual channels.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8. The 0.1µF capacitor between REFH
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
LTC2175-14
LTC2175-14
VREF
1.25V
5Ω
1.25V BANDGAP
REFERENCE
1µF
VDD
DIFFERENTIAL
COMPARATOR
VDD
0.625V
15k
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.65V < VSENSE < 1.300V
RANGE
DETECT
AND
CONTROL
ENC+
ENC–
SENSE
30k
BUFFER
INTERNAL ADC
HIGH REFERENCE
0.1µF
217514 F10
REFH
Figure 10. Equivalent Encode Input Circuit for
Differential Encode Mode
2.2µF
0.1µF
0.1µF
0.8x
DIFF AMP
REFL
LTC2175-14
INTERNAL ADC
LOW REFERENCE
1.8V TO 3.3V
0V
217514 F08
Figure 8. Reference Circuit
1.25V
EXTERNAL
REFERENCE
ENC–
30k
CMOS LOGIC
BUFFER
217514 F11
Figure 11. Equivalent Encode Input Circuit for
Single-Ended Encode Mode
VREF
1µF
ENC+
LTC2175-14
SENSE
1µF
217514 F09
Figure 9. Using an External 1.25V Reference
21754314fa
21
LTC2175-14/
LTC2174-14/LTC2173-14
Applications Information
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range is
from 1.1V to 1.6V. In the differential encode mode, ENC–
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
performance ENC+ should have fast rise and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC– is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC+ threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
0.1µF
0.1µF
ENC+
T1
50Ω
0.1µF
LTC2175-14
PECL OR
LVDS
CLOCK
100Ω
50Ω
0.1µF
ENC+
LTC2175-14
0.1µF
ENC–
217514 F13
ENC–
217514 F12
Figure 13. PECL or LVDS Encode Drive
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
21754314fa
22
LTC2175-14/
LTC2174-14/LTC2173-14
Applications Information
DIGITAL OUTPUTS
The digital outputs of the LTC2175-14/LTC2174-14/
LTC2173-14 are serialized LVDS signals. Each channel
outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane
mode). The data can be serialized with 16, 14, or 12-bit
serialization (see timing diagrams for details). Note that
with 12-bit serialization the two LSBs are not available—
this mode is included for compatibility with the 12-bit
versions of these parts.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins. In the 2-lane, 14-bit serialization
mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the
parallel programming mode the SCK pin can select either
3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current is
doubled to maintain the same output voltage swing. In the
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2175-14. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTC2174-14) or 80MHz (LTC2173-14).
SERIALIZATION MODE
MAXIMUM SAMPLING
FREQUENCY, fS (MHz)
DCO FREQUENCY
FR FREQUENCY
SERIAL DATA RATE
2-Lane
16-Bit Serialization
125
4 • fS
fS
8 • fS
2-Lane
14-Bit Serialization
125
3.5 • fS
0.5 • fS
7 • fS
2-Lane
12-Bit Serialization
125
3 • fS
fS
6 • fS
1-Lane
16-Bit Serialization
62.5
8 • fS
fS
16 • fS
1-Lane
14-Bit Serialization
71.4
7 • fS
fS
14 • fS
1-Lane
12-Bit Serialization
83.3
6 • fS
fS
12 • fS
21754314fa
23
LTC2175-14/
LTC2174-14/LTC2173-14
Applications Information
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
and all other bits. The FR and DCO outputs are not affected.
The output randomizer is enabled by serially programming
mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D13-D0) of all channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A3 and A4. When enabled, the test
patterns override all other formatting modes: 2’s complement and randomizer.
AIN+ – AIN–
(2V RANGE)
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
11 1111 1111 1111
01 1111 1111 1111
+0.999878V
11 1111 1111 1111
01 1111 1111 1111
+0.999756V
11 1111 1111 1110
01 1111 1111 1110
+0.000122V
10 0000 0000 0001
00 0000 0000 0001
Output Disable
+0.000000V
10 0000 0000 0000
00 0000 0000 0000
–0.000122V
01 1111 1111 1111
11 1111 1111 1111
–0.000244V
01 1111 1111 1110
11 1111 1111 1110
–0.999878V
00 0000 0000 0001
10 0000 0000 0001
–1.000000V
00 0000 0000 0000
10 0000 0000 0000
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