SSM2166_03

Microphone Preamplifier with Variable Compression and Noise Gating SSM2166* FEATURES Complete Microphone Conditioner in a 14-Lead Package Single +5 V Operation Adjustable Noise Gate Threshold Compression Ratio Set by External Resistor Automatic Limiting Feature—Prevents ADC Overload Adjustable Release Time Low Noise and Distortion Power-Down Feature 20 kHz Bandwidth ( 1 dB) Low Cost APPLICATIONS Microphone Preamplifier/Processors Computer Sound Cards Public Address/Paging Systems Communication Headsets Telephone Conferencing Guitar Sustain Effects Generators Computerized Voice Recognition Surveillance Systems Karaoke and DJ Mixers GENERAL DESCRIPTION this gain is in addition to the variable gain in other compression settings. The input buffer can also be configured for front-end gains of 0 dB to 20 dB. A downward expander (noise gate) prevents amplification of noise or hum. This results in optimized signal levels prior to digitization, thereby eliminating the need for additional gain or attenuation in the digital domain that could add noise or impair accuracy of speech recognition algorithms. The compression ratio and time constants are set externally. A high degree of flexibility is provided by the VCA Gain, Rotation Point, and Noise Gate adjustment pins. The SSM2166 is an ideal companion product for audio codecs used in computer systems, such as the AD1845 and AD1847. The device is available in a 14-lead SOIC package, and is guaranteed for operation over the extended industrial temperature range of –40°C to +85°C. For similar features and performance in an 8-lead package, please refer to the SSM2165. 10 0 –10 RATIO = 10:1 RATIO = 2:1 OUTPUT – dBu –20 –30 –40 –50 –60 –70 RATIO = 1:1 The SSM2166 integrates a complete and flexible solution for conditioning microphone inputs in computer audio systems. It is also excellent for improving vocal clarity in communications and public address systems. A low noise voltage-controlled amplifier (VCA) provides a gain that is dynamically adjusted by a control loop to maintain a set compression characteristic. The compression ratio is set by a single resistor and can be varied from 1:1 to over 15:1 relative to a user defined “rotation point”; signals above the rotation point are limited to prevent overload and eliminate “popping.” In the 1:1 compression setting, the SSM2166 can be programmed with a fixed gain of up to 20 dB; R1 = 10k 5 BUFOUT –IN AUDIO +IN 6 7 0.1 F LEVEL DETECTOR R2 = 10k + 1F BUFFER 1k 10 F + 3 VCAIN 4 –60 –50 –40 –30 INPUT – dBu –20 –10 0 Figure 1. SSM2166 Compression and Gating Characteristics with 10 dB of Fixed Gain (The Gain Adjust Pin Can Be Used to Vary This Fixed Gain Amount) 10 F* + 14 VCAR 1k VCA V+ 2 2.3k V+ VCA GAIN ADJ 13 OUTPUT 9 500k NOISE GATE SET 11 17k ROTATION POINT SET CONTROL SSM2166 12 POWER DOWN 1 GND 10 8+ AVG 25k CAP 22 F *Patents pending. COMPRESSION RATIO SET *OPTIONAL R EV. B Figure 2. Functional Block Diagram and Typical Speech Application Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. (V+ , R = 600 k R k, 2 SSM2166–SPECIFICATIONS R1 ==05 V,, fR=21=kHz, R, T==1005 kC, unless otherwise ,noted, V ==3300 mVR rms.)= 0 L GATE ROTATION COMP A IN , Parameter Symbol Conditions Min Typ Max Unit AUDIO SIGNAL PATH Voltage Noise Density Noise Total Harmonic Distortion Input Impedance Output Impedance Load Drive Buffer Input Voltage Range Output Voltage Range VCA Input Voltage Range Output Voltage Range Gain Bandwidth Product CONTROL SECTION VCA Dynamic Gain Range VCA Fixed Gain Range Compression Ratio, Min Compression Ratio, Max Control Feedthrough POWER SUPPLY Supply Voltage Range Supply Current Quiescent Output Voltage Level Power Supply Rejection Ratio POWER DOWN Supply Current NOTES 1 0 dBu = 0.775 V rms. 2 Normal operation: Pin 12 = 0 V. en THD+N ZIN ZOUT 15:1 Compression 20 kHz Bandwidth, VIN = GND 2nd and 3rd Harmonics, VIN = –20 dBu 22 kHz Low-Pass Filter 17 –109 0.25 180 75 0.5 nV/√Hz dBu1 % kΩ Ω kΩ nF V rms V rms V rms V rms MHz dB dB Resistive Capacitive 1% THD 1% THD 1% THD 1% THD 1:1 Compression, VCA G = 60 dB 5 2 1 1 1 1.4 30 60 –60 to +19 1:1 15:1 ±5 4.5 7.5 2.2 50 5.5 10 See TPC 3 for RCOMP/RROT 15:1 Compression, Rotation Point = –10 dBu VS ISY PSRR Pin 12 = V+2 mV V mA V dB µA 10 100 Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Temperature Range Package Description Package Option Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10 V Audio Input Voltage . . . . . . . . . . . . . . . . . . . . . Supply Voltage Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ ) . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C ESD RATINGS Model SSM2166S –40°C to +85°C Narrow SOIC R-14 883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 2.0 kV THERMAL CHARACTERISTICS Thermal Resistance 14-Lead SOIC θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2166 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –2– R EV. B SSM2166 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 2 GND GAIN ADJUST Ground VCA Gain Adjust Pin. A resistor from this pin to ground sets the fixed gain of the VCA. To check the setting of this pin, make sure the compression pin (Pin 10) is grounded for no compression. The gain can be varied from 0 dB to 20 dB. For 20 dB, leave the pin open. For 0 dB of fixed gain, a typical resistor value is approximately 1 kΩ. For 10 dB of fixed gain, the resistor value is approximately 2 kΩ to 3 kΩ. For resistor values 1 V rms (3 V p-p) into loads >5 kΩ. The internal rms detector has a time constant set by an external capacitor. The SSM2166 contains an input buffer and automatic gain control (AGC) circuit for audio- and voice-band signals. Circuit operation is optimized by providing a user adjustable time constant and compression ratio. A downward expansion (noise gating) feature eliminates circuit noise in the absence of an input signal. The SSM2166 allows the user to set the downward expansion threshold, the limiting threshold (rotation point), input buffer fixed gain, and the internal VCA’s nominal gain at the rotation point. The SSM2166 also features a power-down mode and muting capability. Theory of Operation LIMITING THRESHOLD (ROTATION POINT) DOWNWARD COMPRESSION REGION EXPANSION THRESHOLD 1 (NOISE GATE) r LIMITING REGION VCA GAIN OUTPUT – dB DOWNWARD EXPANSION REGION 1 1 VDE INPUT – dB VRP Figure 3. General Input/Output Characteristics of the SSM2166 SSM2166 Signal Path Figure 3 illustrates a typical transfer characteristic for the SSM2166 where the output level in dB is plotted as a function of the input level in dB. The dotted line indicates the transfer characteristic for a unity-gain amplifier. For input signals in the range of VDE (Downward Expansion) to VRP (Rotation Point), an “r” dB change in the input level causes a 1 dB change in the output level. Here, “r” is defined as the “compression ratio.” The compression ratio may be varied from 1:1 (no compression) to over 15:1 via a single resistor, RCOMP. Input signals above VRP are compressed with a fixed compression ratio of approximately 15:1. This region of operation is the “limiting region.” Varying the compression ratio has no effect on the limiting region. The breakpoint between the compression region and the limiting region is referred to as the “limiting threshold” or the “rotation point,” and is user specified in the SSM2166. The term “rotation point” derives from the observation that the straight line in the compression region “rotates” about this point on the input/ output characteristic as the compression ratio is changed. The gain of the system with an input signal level of VRP is fixed by RGAIN regardless of the compression ratio, and is the “nominal gain” of the system. The nominal gain of the system may be increased by the user via the on-board VCA by up to 20 dB. Additionally, the input buffer of the SSM2166 can be configured to provide fixed gains of 0 dB to 20 dB with R1 and R2. Input signals below VDE are downward expanded; that is, a –1 dB change in the input signal level causes approximately a –3 dB change in the output level. As a result, the gain of the system is small for very small input signal levels, even though it may be quite large for small input signals above VDE. The downward expansion threshold, VDE, is set externally by the user via RGATE at Pin 9 (NOISE GATE). Finally, the SSM2166 provides an active high, CMOS compatible digital input whereby a power-down feature will reduce device supply current to less than 100 µA. Figure 4 illustrates the block diagram of the SSM2166. The audio input signal is processed by the input buffer and then by the VCA. The input buffer presents an input impedance of approximately 180 kΩ to the source. A dc voltage of approximately 1.5 V is present at AUDIO +IN (Pin 7 of the SSM2166), requiring the use of a blocking capacitor (C1) for groundreferenced sources. A 0.1 µF capacitor is a good choice for most audio applications. The input buffer is a unity-gain stable amplifier that can drive the low impedance input of the VCA. The VCA is a low distortion, variable-gain amplifier whose gain is set by the side-chain control circuitry. The input to the VCA is a virtual ground in series with approximately 1 kΩ. An external blocking capacitor (C6) must be used between the buffer’s output and the VCA input. The 1 kΩ impedance between amplifiers determines the value of this capacitor, which is typically between 4.7 µF and 10 µF. An aluminum electrolytic capacitor is an economical choice. The VCA amplifies the input signal current flowing through C6 and converts this current to a voltage at the SSM2166’s output pin (Pin 13). The net gain from input to output can be as high as 60 dB (without additional buffer gain), depending on the gain set by the control circuitry. The gain of the VCA at the rotation point is set by the value of a resistor connected between Pin 2 and GND, RGAIN. The relationship between the VCA gain and RGAIN is shown in TPC 4. The AGC range of the SSM2166 can be as high as 60 dB. The VCAIN pin (Pin 3) on the SSM2166 is the noninverting input terminal to the VCA. The inverting input of the VCA is also available on the SSM2166’s Pin 4 (VCAR) and exhibits an input impedance of 1 kΩ, as well. As a result, this pin can be used for differential inputs or for the elimination of grounding problems by connecting a capacitor whose value equals that used in series with the VCAIN pin, to ground. See Figure 12, Evaluation Board, for more details. The output impedance of the SSM2166 is typically less than 75 Ω, and the external load on Pin 13 should be >5 kΩ. The nominal output dc voltage of the device is approximately 2.2 V. Use a blocking capacitor for grounded loads. The bandwidth of the SSM2166 is quite wide at all gain settings. The upper 3 dB point is approximately 30 kHz at gains as high as 60 dB (using the input buffer for additional gain, circuit –6– R EV. B SSM2166 C6 10 F V+ 14 R1 = 10k 5 BUFOUT INPUT BUFFER –IN 6 AUDIO +IN R2 = 10k + 1F 7 0.1 F VCA GAIN ADJUST 2 RGAIN NOISE GATE RGATE 9 RROT PT 3 VCAIN 1k 4 VCAR 1k OUTPUT 13 C7* 10 F VOUT V+ SSM2166 RMS LEVEL DETECTOR CONTROL CIRCUITRY ROTATION POINT ADJUST 11 POWER DOWN 12 GND 1 8 AVG CAP CAVG 2.2 F 10 COMPRESSION RATIO SET RCOMP POWER DOWN *OPTIONAL GND Figure 4. Functional Block Diagram and Typical Application bandwidth is unaffected). The GBW plots are shown in TPC 8b. The lower 3 dB cutoff frequency of the SSM2166 is set by the input impedance of the VCA (1 kΩ) and C6. While the noise of the input buffer is fixed, the input referred noise of the VCA is a function of gain. The VCA input noise is designed to be a minimum when the gain is at a maximum, thereby optimizing the usable dynamic range of the part. An image of the SSM2166’s wideband peak-to-peak output noise is illustrated in TPC 8a. Level Detector by internal circuitry that speeds up the attack for large level changes. This limits overload time to under 1 ms in most cases. The performance of the rms level detector is illustrated in Figure 5 for a CAVG of 2.2 µF (Figure 5a) and 22 µF (Figure 5b). In each of these images, the input signal to the SSM2166 (not shown) is a series of tone bursts in six successive 10 dB steps. The tone bursts range from –66 dBV (0.5 mV rms) to –6 dBV (0.5 V rms). As illustrated in the images, the attack time of the rms level detector is dependent only on CAVG, but the release times are linear ramps whose decay times are dependent on both CAVG and the input signal step size. The rate of release is approximately 240 dB/s for a CAVG of 2.2 µF, and 12 dB/s for a CAVG of 22 µF. The SSM2166 incorporates a full-wave rectifier and a patentpending, true rms level detector circuit whose averaging time constant is set by an external capacitor connected to the AVG CAP pin (Pin 8). For optimal low frequency operation of the level detector down to 10 Hz, the value of the capacitor should be 2.2 µF. Some experimentation with larger values for the AVG CAP may be necessary to reduce the effects of excessive low frequency ambient background noise. The value of the averaging capacitor affects sound quality: too small a value for this capacitor may cause a “pumping effect” for some signals, while too large a value can result in slow response times to signal dynamics. Electrolytic capacitors are recommended here for lowest cost and should be in the range of 2 µF to 47 µF. Capacitor values from 18 µF to 22 µF have been found to be more appropriate in voice-band applications, where capacitors on the low end of the range seem more appropriate for music program material. The rms detector filter time constant is approximately given by 10 CAVG milliseconds where CAVG is in µF. This time constant controls both the steady-state averaging in the rms detector as well as the release time for compression; that is, the time it takes for the system gain to react when a large input is followed by a small signal. The attack time, the time it takes for the gain to be reduced when a small signal is followed by a large signal, is controlled partly by the AVG CAP value, but is mainly controlled 100mV 100 90 –6dBV –66dBV 10 0% –85dBV 100ms Figure 5a. RMS Level Detector Performance with CAVG = 2.2 µ F R EV. B –7– SSM2166 Rotation Point 100mV 100 1S –6dBV 90 –66dBV 10 An internal dc reference voltage in the control circuitry, used to set the rotation point, is user specified, as illustrated in TPC 7. The effect on rotation point is shown in Figure 7. By varying a resistor, RROT PT, connected between the positive supply and the ROTATION POINT SET pin (Pin 11), the rotation point may be varied from approximately 20 mV rms to 1 V rms. From the figure, the rotation point is inversely proportional to RROT PT. For example, a 1 kΩ resistor would typically set the rotation point at 1 V rms, whereas a 55 kΩ resistor would typically set the rotation point at approximately 30 mV rms. Since limiting occurs for signals larger than the rotation point (VIN > VRP), the rotation point effectively sets the maximum output signal level. It is recommended that the rotation point be set at the upper extreme of the range of typical input signals so that the compression region will cover the entire desired input signal range. Occasional larger signal transients will then be attenuated by the action of the limiter. 0% –85dBV Figure 5b. RMS Level Detector Performance with CAVG = 22 µ F Control Circuitry OUTPUT – dB The output of the rms level detector is a signal proportional to the log of the true rms value of the buffer output with an added dc offset. The control circuitry subtracts a dc voltage from this signal, scales it, and sends the result to the VCA to control the gain. The VCA’s gain control is logarithmic—a linear change in control signal causes a dB change in gain. It is this control law that allows linear processing of the log rms signal to provide the flat compression characteristic on the input/output characteristic shown in Figure 3. Compression Ratio r:1 VCA GAIN Changing the scaling of the control signal fed to the VCA causes a change in the circuit’s compression ratio, “r.” This effect is shown in Figure 6. The compression ratio can be set by connecting a resistor between the COMP RATIO pin (Pin 10) and GND. Lowering RCOMP gives smaller compression ratios as indicated in TPC 3, with values of about 17 kΩ or less resulting in a compression ratio of 1:1. AGC performance is achieved with compression ratios between 2:1 and 15:1, and is dependent on the application. A 100 kΩ potentiometer may be used to allow this parameter to be adjusted. On the evaluation board (Figure 12), an optional resistor can be used to set the compression equal to 1:1 when the wiper of the potentiometer is at its full CCW position. 1 1 VDE VRP1 VRP2 VRP3 INPUT – dB Figure 7. Effect of Varying the Rotation Point VCA Gain Setting and Muting 15:1 5:1 2:1 VCA GAIN The maximum gain of the SSM2166 is set by the GAIN ADJUST pin (Pin 2) via RGAIN. This resistor, with a range between 1 kΩ and 20 kΩ, will cause the nominal VCA gain to vary from 0 dB to approximately 20 dB, respectively. Setting the VCA gain to its maximum can also be achieved by leaving the GAIN ADJUST pin in an OPEN condition (no connect). Figure 8 illustrates the effect on the transfer characteristic by varying this parameter. For low level signal sources, the VCA should be set to maximum gain using a 20 kΩ resistor. OUTPUT – dB 1:1 1 1 VDE INPUT – dB VRP Figure 6. Effect of Varying the Compression Ratio –8– R EV. B SSM2166 r:1 r:1 VCA GAIN OUTPUT – dB VCA GAIN OUTPUT – dB 1 1 1 1 VDE INPUT – dB VRP VDE2 VDE1 VDE3 INPUT – dB VRP Figure 8. Effect of Varying the VCA Gain Setting The gain of the VCA can be reduced below 0 dB by making RGAIN smaller than 1 kΩ. Switching Pin 2 through 330 Ω or less to ground will mute the output. Either a switch connected to ground or a transistor may be used, as shown in Figure 9. To avoid audible “clicks” when using this mute feature, a capacitor (C5 in figure) can be connected from Pin 2 to GND. The value of the capacitor is arbitrary and should be determined empirically, but a 0.01 µF capacitor is a good starting value. SSM2166 GAIN ADJUST 2 330 C5 RGAIN MUTE (CLOSED SWITCH) Figure 10. Effect of Varying the Downward Expansion (Noise Gate) Threshold Power-Down Feature The supply current of the SSM2166 can be reduced to under 100 µA by applying an active high, 5 V CMOS compatible input to the SSM2166’s POWER DOWN pin (Pin 12). In this state, the input and output circuitry of the SSM2166 will assume a high impedance state; as such, the potentials at the input pin and the output pin will be determined by the external circuitry connected to the SSM2166. The SSM2166 takes approximately 200 ms to settle from a POWER-DOWN to POWER-ON command. For POWER-ON to POWER-DOWN, the SSM2166 requires more time, typically less than 1 second. Cycling the power supply to the SSM2166 can result in quicker settling times: the off-to-on settling time of the SSM2166 is less than 200 ms, while the on-to-off settling time is less than 1 ms. In either implementation, transients may appear at the output of the device. To avoid these output transients, use mute control of the VCA’s gain as previously mentioned. PC Board Layout Considerations NOTE: ADDITIONAL CIRCUIT DETAILS OMITTED FOR CLARITY. Figure 9. Details of SSM2166 Mute Option Downward Expansion Threshold The downward expansion, or noise gate, threshold is determined via a second reference voltage internal to the control circuitry. This second reference can be varied in the SSM2166 using a resistor, RGATE, connected between the positive supply and the NOISE GATE SET pin (Pin 9) of the SSM2166. The effect of varying this threshold is shown in Figure 10. The downward expansion threshold may be set between 300 µV rms and 20 mV rms by varying the resistance value between Pin 9 and the supply voltage. Like the ROTATION PT ADJUST, the downward expansion threshold is inversely proportional to the value of this resistance: setting this resistance to 1 MΩ sets the threshold at approximately 250 µV rms, whereas a 10 kΩ resistance sets the threshold at approximately 20 mV rms. This relationship is illustrated in TPC 2. A potentiometer network is provided on the evaluation board for this adjustment. In general, the downward expansion threshold should be set at the lower extreme of the desired range of the input signals, so that signals below this level will be attenuated. Since the SSM2166 is capable of wide bandwidth operation and can be configured for as much as 80 dB of gain, special care must be exercised in the layout of the PC board that contains the IC and its associated components. The following applications hints should be considered and/or followed: (1) In some high system gain applications, the shielding of input wires to minimize possible feedback from the output of the SSM2166 back to the input circuit may be necessary. (2) A single-point (“star”) ground implementation is recommended in addition to maintaining short lead lengths and PC board runs. The evaluation board layout shown in Figure 13 for the SSM2166 demonstrates the single-point grounding scheme. In applications where an analog ground and a digital ground are available, the SSM2166 and its surrounding circuitry should be connected to the system’s analog ground. As a result of these recommendations, wire-wrap board connections and grounding implementations are to be explicitly avoided. (3) The internal buffer of the SSM2166 was designed to drive only the input of the internal VCA and its own feedback network. Stray capacitive loading to ground from the BUFOUT pin in excess of 5 pF to 10 pF can cause excessive phase shift and can lead to circuit instability. R EV. B –9– SSM2166 (4) When using high impedance sources (≥5 kΩ), system gains in excess of 60 dB are not recommended. This configuration is rarely appropriate, as virtually all high impedance inputs provide larger amplitude signals that do not require as much amplification. When using high impedance sources, however, it can be advantageous to shunt the source with a capacitor to ground at the input pin of the IC (Pin 7) to lower the source impedance at high frequencies, as shown in Figure 11. A capacitor with a value of 1000 pF is a good starting value and sets a low-pass corner at 31 kHz for 5 kΩ sources. In applications where the source ground is not as “clean” as would be desirable, a capacitor (illustrated as C7 on the evaluation board) from the VCAR input to the source ground might prove beneficial. This capacitor is used in addition to the grounded capacitor (illustrated as C2 on the evaluation board) used in the feedback around the buffer, assuming that the buffer is configured for gain. The value of the C7 should be the same as C6, the capacitor value used between BUFOUT and VCAIN. This connection makes the source ground noise appear as a common-mode signal to the VCA, allowing the common-mode noise to be rejected by the VCA’s differential input circuitry. C7 can also be useful in reducing ground loop problems and in reducing noise coupling from the power supply by balancing the impedances connected to the inputs of the internal VCA. SSM2166 Evaluation Board A schematic diagram of the SSM2166 evaluation board, available upon request from Analog Devices, is illustrated in Figure 12. As a design aid, the layouts for the topside silkscreen and the topside and backside metallization layers are shown in Figures 13a, 13b, and 13c. Although not shown to scale, the finished dimension of the evaluation board is 3.5 inches by 3.5 inches, and comes complete with pin sockets and a sample of the SSM2166. C1 0.1 F AUDIO IN (RS > 5k ) 7 +IN CX 1000pF SSM2166 NOTE: ADDITIONAL CIRCUIT DETAILS OMITTED FOR CLARITY. Figure 11. Circuit Configuration for Use with High Impedance Signal Sources +V ROTATION PT ADJ R3 50k CW C3 0.1 F R7 1M 14 V+ CW NOISE GATE R8 1k 9 NOISE GATE ADJ 12 POWER DN R12 100k J3 R1 10k 5 C6 10 F + 3 VCAIN 11 R4 1k BUFOUT ROT PT. ADJ 6 –INPUT SSM2166 1 GND R2 10k +INPUT 7 VCAR 4 AVG CAP 8 GAIN ADJUST 2 C5 0.01 F COMP RATIO 10 OUTPUT 13 5 4 C2 1F MIC PWR INPUT JACK 1/8" PHONE C1 0.1 F + C7 10 F + C4 22 F R9 1k R11 330 1 3 2 COMP RATIO R10 20k GAIN CW ADJ MUTE SWITCH OP113 R6 100k CW 6 7 OUTPUT JACK RCA PHONO Figure 12. Evaluation Board –10– R EV. B SSM2166 Figure 13a. Evaluation Board Topside Silkscreen (Not to Scale) Figure 13c. Evaluation Board Backside Metallization (Not to Scale) Signal sources are connected to the SSM2166 through a 1/8" phone jack where a 0.1 µF capacitor couples the input signal to the SSM2166’s +IN pin (Pin 7). As shown in Figure 12 and in microphone applications, the phone jack shield can be optionally connected to the board’s ground plane (Jumper J1 inserted into board socket pins labeled “1” and “2”) or to the SSM2166’s VCAR input at Pin 4 (Jumper J1 inserted into board socket pins labeled “1” and “3”). If the signal source is a waveform or function generator, the phone jack shield is to be connected to ground. For ease in making adjustments for all of the SSM2166’s configuration parameters, single-turn potentiometers are used throughout. Optional Jumper J2 connects the COMP RATIO pin to ground and sets the SSM2166 for no compression (that is, compression ratio = 1:1). Optional Jumper J3 connects the SSM2166’s POWER DOWN input to ground for normal operation. Jumper J3 can be replaced by an open-drain logic buffer for a digitally controlled shutdown function. An output signal mute function can be implemented on the SSM2166 by connecting the GAIN ADJUST pin (Pin 2) through a 330 Ω resistance to ground. This is provided on the evaluation board via R11 and S1. A capacitor C5, connected between Pin 2 and ground and provided on the evaluation board, can be used to avoid audible “clicks” when using the mute function. To configure the SSM2166’s input buffer for gain, provisions for R1, R2, and C2 have been included. To configure the input buffer for unity-gain operation, R1 and R2 are removed, and a direct connection is made between the –IN pin (Pin 6) and the BUFOUT pin (Pin 5) of the SSM2166. The output stage of the SSM2166 is capable of driving >1 V rms (3 V p-p) into >5 kΩ loads, and is externally available through an RCA phono jack provided on the board. If the output of the SSM2166 is required to drive a lower load resistance or an audio cable, then the on-board OP113 can be used. To use the OP113 buffer, insert Jumper J4 into board socket pins labeled “4” and “5” and insert Jumper J5 into board socket pins labeled “6” and “7.” If the output buffer is not required, remove Jumper J5 and insert Jumper J4 into board socket pins “5” and “7.” There are no blocking capacitors either on the input nor at the output of the buffer. R EV. B –11– Figure 13b. Evaluation Board Topside Metallization (Not to Scale) SSM2166 As a result, the output dc level of the buffer will match the output dc level of the SSM2166, which is approximately 2.3 V. A dc blocking capacitor may be inserted on Pins 6 and 7. An evaluation board and setup procedure is available from your Analog Devices representative. Setup Procedure with Evaluation Board Evaluation Board When building a breadboard, keep the leads to Pins 3, 4, and 5 short. A convenient evaluation board is available from an ADI sales representative. The R and C designations refer to the demonstration board schematic of Figure 12 and parts list, Table I. Test Equipment Setup To illustrate how easy it is to program the SSM2166, we will take a practical example. The SSM2166 will be used to interface an electret-type microphone to a postamplifier. The evaluation board or the circuit configuration shown in Figure 12 can be used. The signal from the microphone was measured under actual conditions to vary from 1 mV to 15 mV. The postamplifier requires no more than 500 mV at its input. The required gain from the SSM2166 is, therefore: GTOT = 20 × log (500/15) = 30 dB We will set the input buffer gain to 20 dB and adjust the VCA gain to 10 dB. The limiting or “rotation” point will be set at 500 mV output. From prior experience, we will start with a 2:1 compression ratio, and a noise gate threshold that operates below 100 µV. These objectives are summarized in Figure 14, and we will fine-tune them later on. The transfer characteristic we will implement is illustrated in Figure 15. INPUT RANGE OUTPUT RANGE LIMITING LEVEL COMPRESSION BUFFER GAIN VCA GAIN NOISE GATE 1 mV–15 mV TO 500 mV 500 mV 2:1 20 dB 10 dB 100 V The recommended equipment and configuration is shown in Figure 16. A low noise audio generator with a smooth output adjustment range of 50 µV to 50 mV is a suitable signal source. A 40 dB pad would be useful to reduce the level of most generators by 100× to simulate the microphone levels. The input voltmeter could be connected before the pad, and need only go down to 10 mV. The output voltmeter should go up to 2 V. The oscilloscope is used to verify that the output is sinusoidal and that no clipping is occurring in the buffer, and to set the limiting and noise gating “knees.” SSM2166 EVALUATION BOARD SIGNAL GENERATOR OSCILLOSCOPE AC VOLTMETER AC VOLTMETER Figure 16. Test Equipment Setup STEP 1. Configure the Buffer Figure 14. Objective Specifications Note: The SSM2166 processes the output of the buffer, which in our example is 20 dB or 10 times the input level. Use the oscilloscope to verify that the buffer is not being driven into clipping with excessive input signals. In the application, take the minimum gain in the buffer consistent with the average source level as well as the crest factor (ratio of peak to rms). ROTATION POINT 500 The SSM2166 has an input buffer that may be used when the overall gain required exceeds 20 dB, the maximum user selectable gain of the VCA. In our example, the desired output is 500 mV for an input around 15 mV, requiring a total gain of 30 dB. We will set the buffer gain at 20 dB, and adjust the VCA for 10 dB. In the socket pins provided on the evaluation board, insert R1 = 100 kΩ, and R2 = 11 kΩ. The buffer gain has been set to 20 dB (×10). STEP 2. Initializing Potentiometers With power off, preset the potentiometers per the table of Figure 17 below. INITIAL INITIAL POT RANGE POSITION RESISTANCE R10 0–20 k R3 R6 R7 0–50 k 0–100 k 0–1 M CCW CCW CCW CW ZERO ZERO ZERO 1M OUTPUT – mV COMPRESSION REGION 2 1 LIMITING REGION FUNCTION GAIN ADJUST (VCA) ROTATION POINT COMPRESSION RATIO EFFECT OF CHANGE 0 dB; CW TO INCREASE VCA GAIN 1 V; CW TO REDUCE ROTATION POINT 1:1; CW TO INCREASE COMPRESSION 300 V; CCW TO INCREASE THRESHOLD 40 GATE THRESHOLD NOISE GATE 0.1 1.0 15 10 INPUT – mV Figure 17. Initial Potentiometer Settings STEP 3. Testing Setup Figure 15. Transfer Characteristic With power on, adjust the generator for an input level of 15 mV, 1 kHz. The output meter should indicate approximately 100 mV. If not, check the setup. STEP 4. Adjusting the VCA Gain Set the input level to 15 mV. Adjust R10—GAIN ADJ CW for an output level of 500 mV. The VCA gain has been set to 10 dB. –12– R EV. B SSM2166 STEP 5. Adjusting the Rotation Point Set the input level to 15 mV, and observe the output on the oscilloscope. Adjust R3—ROTATION PT ADJ CW until the output level just begins to drop, then reverse so that the output is 500 mV. The limiting has now been set to 500 mV. STEP 6. Adjusting the Compression Ratio will keep the output steady over a range of microphone to speaker distance, and the noise gate will keep the background sounds subdued. STEP 9. Recording Values Set the input signal for an output of 500 mV but not in limiting. Note the value (around 15 mV). Next, reduce the input to 1/10 the value noted (around 1.5 mV), for a change of –20 dB. Next, adjust R6—COMP RATIO CW until the output is 160 mV, for an output change of –10 dB. The compression, which is the ratio of output change to input change, in dB, has now been set to 2:1. STEP 7. Setting the Noise Gate With the power removed from the test fixture, measure and record the values of all potentiometers, including any fixed resistance in series with them. If the averaging capacitor, C4, has been changed, note its value, too. SUMMARY With the input set at 100 µV, observe the output on the oscilloscope, and adjust R7—ROT PT SET CCW until the output drops rapidly. “Rock” the control back and forth to find the “knee.” The noise gate has now been set to 100 µV. The range of the noise gate is from 0.3 mV to over 0.5 mV relative to the output of the buffer. To fit this range to the application, it may be necessary to attenuate the input or apportion the buffer gain and VCA gain differently. STEP 8. Listening At this time, it may be desirable to connect an electret microphone to the SSM2166 and listen to the results. Be sure to include the proper power for the microphone’s internal FET (usually +2 V to +5 V dc through a 2.2 kΩ resistor). Experiment with the settings to hear how the results change. Varying the averaging capacitor, C4, changes the attack and decay times, which are best determined empirically. The compression ratio We have implemented the transfer condition of Figure 2. For inputs below the 100 µV noise gate threshold, circuit and background noise will be minimized. Above it, the output will increase at a rate of 1 dB for each 2 dB input increase, until the 500 mV rotation point is reached at an input of approximately 15 mV. For higher inputs that would drive the output beyond 500 mV, limiting will occur, and there will be little further increase. The SSM2166 processes the output of the buffer, which in our example is 20 dB, or 10 times the input level. Use the oscilloscope to ensure that the buffer is not being driven into clipping with the highest expected input peaks. Always take the minimum gain in the buffer consistent with the average source level and crest factor (ratio of peak to rms). The wide program range of the SSM2166 makes it useful in many applications other than microphone signal conditioning. Other Versions The SSM2165 is an 8-lead version of this microphone preamp with unity buffer gain and preset noise gate threshold. Customized parts are available for large volume users. For further information, contact an ADI sales representative. R EV. B –13– SSM2166 Table I. SSM2166 Demo Board Parts List R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 C1 C2 C3 C4 C5 C6 C7 IC1 IC2 S1 J1 J2 10 kΩ 10 kΩ 50 kΩ Pot 1 kΩ 0Ω 100 kΩ Pot 1 MΩ Pot 1 kΩ 1 kΩ 20 kΩ Pot 330 Ω 100 kΩ 0.1 µF 1 µF 0.1 µF 2.2 µF–22 µF 0.01 µF 10 µF 10 µF SSM2166P OP113FP SPST 1/8" Mini Phone Plug RCA Female Feedback Input Rotation Point, Adj. Rotation Point, Fixed Comp Ratio, Fixed Comp Ratio, Adj. Noise Gate, Adj. Noise Gate, Fixed Gain Adj., Fixed Gain Adj. Mute Power Down Pull-Up Input DC Block Buffer Low f, G = 1 +V Bypass Avg. Cap Mute Click Suppress Coupling VCA Noise/DC Balance Mic Preamp Op Amp, Output Buffer Mute MIC Input Output Jack –14– R EV. B SSM2166 OUTLINE DIMENSIONS 14-Lead Standard Small Outline Package [SOIC] Narrow Body (R-14) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 14 1 8 7 6.20 (0.2441) 5.80 (0.2283) 0.25 (0.0098) 0.10 (0.0039) 1.27 (0.0500) BSC 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 45 COPLANARITY 0.10 0.51 (0.0201) 0.33 (0.0130) SEATING PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.19 (0.0075) COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN R EV. B –15– SSM2166 Revision History Location 3/03—Data Sheet changed from REV. A to REV. B. Page Deleted Plastic DIP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Deleted 14-Lead Plastic DIP, OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated 14-Lead Narrow-Body SOIC, OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 C00357-0-3/03(B) PRINTED IN U.S.A. Change to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 –16– R EV. B