APW7101-15BI-TRG

APW7101 1.5MHz, 600mA, Synchronous Buck Regulator Features • • • • • • • • • • • • 600mA Output Current 2.5V to 5.5V Input Voltage Range 1.5MHz Constant Frequency Operation Low Dropout Operation at 100% Duty Cycle Synchronous Topology: No Schottky Diode Required 0.6V Low Reference Voltage Shutdown Mode Supply Current Under 1µA Current Mode Operation for Excellent Line and Load Transient Response Over-Temperature Protection Over Current Protection SOT-23-5 Package Lead Free and Green Devices Available (RoHS Compliant) General Description The APW7101 is a high efficiency monolithic synchronous buck regulator. APW 7101 operates with a constant 1.5MHz switching frequency and using the inductor current as a controlled quantity in the current mode architecture. The device is available in an adjustable version and fixed output voltages of 1.5V and 1.8V. The 2.5V to 5.5V input voltage range makes the APW7101 ideally suited for single Li-Ion battery powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable electrical devices. The internally fixed 1.5MHz operating frequency allows the use of small surface mount inductors and capacitors. The synchronous switches included inside increase the efficiency and eliminate the need for an external Schottky diode. Low output voltages are easily supported with the 0.6V feedback reference voltage. The APW7101 is available in a low profile SOT package for saving the printed circuit board area. Applications • • • • • • Cellular Telephones Personal Information Appliances Wireless and DSL Modems MP3 Players Digital Still Cameras Portable Instruments Pin Configuration Top View RUN 1 GND 2 SW 3 APW7101 ADJ Top View RUN 1 GND 2 SW 3 4 VIN 5 VOUT 4 VIN 5 VFB APW7101 1.5V/1.8V ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright © ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 1 www.anpec.com.tw APW7101 Ordering and Marking Information APW7101 Package Code B : SOT-23-5 Temperature Range Assembly Material I : -40 to 85 °C Handling Code Handling Code Temperature Range TR : Tape & Reel Voltage Code Package Code 15: 1.5V 18: 1.8V Blank : Adjustable Version Voltage Code Assembly Material L : Lead Free Device G : Halogen and Lead Free Device 019X W01X X - Date Code X - Date Code APW7101-18 : 01CX X - Date Code APW7101-15 : APW7101 : Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCC VRUN VFB VSW ISW_PEAK PD TJ TSTG TSDR Parameter Input Supply Voltage (VCC to GND) RUN Pin Voltage Feedback Voltage Switching Voltage Peak SW Current Average Power Dissipation Junction Temperature, TA < 50° Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds Value -0.3V to 6V -0.3V to (VCC+0.3V) -0.3V to (VCC+0.3V) -0.3V to (VCC+0.3V) 1.3 0.5 150 -65 ~ 150 260 Unit V V V V A W °C °C °C Thermal Characteristics Symbol θJA Parameter Junction to Ambient Thermal Resistance in Free Air Typical Value 250 Unit °C/W C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 2 www.anpec.com.tw APW7101 Electrical Characteristics The * denotes the specifications that apply over TA = -40°C ~ 85°C, otherwise specifications are at TA=25°C. APW7101 Symbol IVFB VIN VFB ∆VFB Parameter Feedback Current Input Voltage Range Regulated Feedback Voltage Reference Voltage Line Regulation *Note -40°C ≤ TA ≤ 85°C VIN = 2.5V to 5.5V APW7101-1.5, IOUT = 100mA VOUT ∆VOUT Regulated Output Voltage APW7101-1.8, IOUT=100mA Output Voltage Line Regulation VIN = 2.5V to 5.5V VIN = 3V, VFB = 0.5V or IPK Peak Inductor Current VOUT = 90% Duty < 35% 0.75 1 1.25 A * * 1.746 1.800 0.04 1.854 0.4 V %/V Test conditions Min. * * * * * -30 2.5 0.585 1.455 Typ. 0.6 0.04 1.500 Max. 30 5.5 0.615 0.4 1.545 nA V V %/V V Unit VLOADR IQ IQ_SD fOSC fOSC_FFB RDSON_P RDSON_N ILSW VRUN IRUN Output Voltage Load Regulation Quiescent Current Quiescent Current in Shutdown Oscillator Frequency Frequency Foldback On Resistance of P MOSFET On Resistance of N MOSFET SW Leakage Current RUN Threashold RUN Leakage Current VFB = 0.6V or VOUT = 100% VFB = 0V or VOUT = 0V ISW = 100mA ISW = -100mA VRUN = 0V, VSW = 0V or 5V, VIN = 5V * * Duty Cycle = 0; VFB = 1.5V 1.2 0.3 - 0.5 300 0.1 1.5 300 0.4 0.35 ±0.01 1 ±0.01 400 1 1.8 0.5 0.45 ±1 1.5 ±1 % µA µA MHz kHz Ω Ω µA V µA Note: The Maximum output current didn’ reach 600mA when the supply voltage below 2.7V. t Pin Descrpition No. 1 2 3 4 5 PIN RUN GND SW VIN VFB/VOUT FUNCTION Control input pin. Forcing this pin above 1.5V enables APW7101. Forcing this pin below 0.3V shuts down APW7101. In shutdown situation, all functions are disabled to decrease the supply current below 1µA.There is no pull high or pull low ability inside. Ground pin. Connected this pin to the inductor of the power stage. This pin connected to the drain terminals of the main and synchronous power MOSFET switches inside. Must be closely decoupled to GND with 4.7µF or greater ceramic capacitor. In the adjustable version, feedback function is available. The feedback voltage decided by an external resistive divider across the output. In the fixed version, an internal resistive divider divides the output voltage down for comparison to the internal reference voltage. C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 3 www.anpec.com.tw APW7101 Block Diagram Slop Compensation Σ ICOMP Frequency Shift RSENSE VFB EA 0.6V RQ SQ RUN Shutdown Control Logic QSENSE QP SW QN Reverse detect Oscillator VIN GND Application Circuit VIN 2.5V TO 5.5V APW7101 L 2.2µH 3 5 RF1 470K RF2 150K 4 1 VOUT=2.5V VIN 2.5V TO 5.5V APW7101/1.5V/1.8V L 2.2µH 3 5 VDD RUN GND SW FB 4 1 VOUT VDD RUN GND SW FB CIN 4.7µF 2 COUT 10µF CIN 4.7µF 2 COUT 10µF CIN: Murata GRM31CR61C475K COUT: Murata GRM31CR61A106K L: Gotrend GTSD53 C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 4 www.anpec.com.tw APW7101 Typical Operating Characteristics Reference Voltage 0.615 0.610 1800 1700 VIN=5.5V Oscillator Frequency Reference Voltage (V) 0.600 0.595 0.590 0.585 -50 -25 0 25 50 75 100 125 Frequency (kHz) 0.605 VIN=2.5V 1600 1500 1400 1300 1200 -50 -25 0 25 VIN=3.6V 50 75 100 125 Temperature (o C) Temperature (o C) Oscillator Frequency vs Supply Voltage 1800 700 RDS(ON) vs Temperature TA=25o C 1700 600 VIN=4.2V VIN=3.6V VIN=2.7V 500 Frequency (kHz) ON Resistance (mΩ) 1600 1500 1400 1300 1200 2 3 4 5 6 400 300 200 100 0 -50 -25 0 25 50 75 100 125 NMOS PMOS Supply Voltage (V) Temperature (o C) C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 5 www.anpec.com.tw APW7101 Typical Operating Characteristics (Cont.) RDS(ON) vs Input Voltage 600 500 Efficiency vs Output Current 100 90 PMOS VOUT=1.2V TA=25o C VIN=2.7V 80 70 ON Resistance (mΩ) 400 Efficiency (%) 60 50 40 30 20 10 300 NMOS VIN=3.6V 200 100 0 0 1 2 3 4 5 6 VIN=4.2V 0 0.1 1.0 10.0 100.0 1000.0 Input Voltage (V) Output Current (mA) Efficiency vs Output Current 100 90 80 70 100 Efficiency vs Output Current VOUT=1.5V TA=25o C VIN=2.7V 90 80 VOUT=2.5V TA=25o C VIN=4.2V VIN=3.6V Efficiency (%) 70 60 50 40 30 20 10 0 Efficiency (%) VIN=3.6V 60 50 40 30 20 10 0 0.1 1.0 10.0 100.0 1000.0 VIN=4.2V VIN=2.7V 0.1 1.0 10.0 100.0 1000.0 Output Current (mA) Output Current (mA) C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 6 www.anpec.com.tw APW7101 Typical Operating Characteristics (Cont.) Efficiency vs Output Current 100 90 80 V OUT=1V L=2.2uH TA=25°C 1.008 1.006 1.004 Output Voltage vs Output Current L=2.2uH TA=25°C 60 50 40 30 20 10 0 0.1 V IN=3.3V Output Voltage (mV) Efficiency (%) 70 1.002 1 0.998 0.996 0.994 0.992 0.99 0.988 V IN=5V V IN=5V V IN=3.3V 1 10 100 1000 0 100 200 300 400 500 600 Output Current (mA) Output Current (mA) Efficiency vs Input Voltage 100 95 90 85 Efficiency vs Input Voltage 100 95 IOUT=100mA IOUT=600mA IOUT=100mA IOUT=600mA Efficiency (%) 90 85 80 75 70 65 60 VOUT=1.8V TA=25o C Efficiency (%) 80 75 IOUT=10mA 70 65 60 55 50 2 3 4 5 6 IOUT=10mA VOUT=1.5V TA=25o C 55 50 2 3 4 Input Voltage (V) 5 6 Input Voltage (V) C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 7 www.anpec.com.tw APW7101 Typical Operating Characteristics (Cont.) Efficiency vs Input Voltage 100 95 90 85 Dynamic Supply Current vs Supply Voltage 400 IOUT=100mA Dynamic Supply Current (µA) 5 6 380 360 IOUT=600mA 340 320 300 280 260 240 220 200 2 3 4 5 6 Efficiency (%) 80 75 70 65 60 55 50 2 3 4 IOUT=10mA VOUT=2.5V TA=25o C Input Voltage (V) Supply Voltage (V) P-FET Leakage vs Temperature 300 250 N-FET Leakage vs Temperature 800 750 P-FET Leakage(nA) 200 150 100 50 0 -50 -25 0 25 50 o N-FET Leakage(nA) 700 650 600 550 500 VIN=5.5V VIN=5.5V 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 8 www.anpec.com.tw APW7101 Function Description Main Control Loop The APW7101 uses a constant frequency, current mode step-down architecture. Both the main and synchronous switches are internal to reduce the external components. During normal operation, the internal PMOSFET is turned on, but is turned off when the inductor current at the input of ICOMP to reset the RS latch. The load current increases, it causes a slight decrease in the feedback voltage, which in turn, causes the EA’ outs put voltage to increase until the average inductor current matches the new load current. While the internal power PMOSFET is off, the internal power NMOSFET is turned on until the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of next cycle. When the NMOSFET is turned off by IRCMP, it operates in the discontinuous conduction mode. Pulse Skipping Mode Operation At light load with a relative small inductance, the inductor current may reach zero. The internal power NMOSFET is turned off by the current reversal comparator, IRCMP, and the switching voltage will ring. This is discontinuous mode operation, and is normal behavior for the switching regulator. At very light load, the APW7101 will automatically skip some pulses in the pulse skipping mode to maintain the output regulation. The skipping process modulates smoothly depend on the load. Short Circuit Protection In the short circuit situation, the output voltage is almost zero volts. Output current is limited by the ICOMP to prevent the damage of electrical circuit. In the normal operation, the two straight line of the inductor current ripple have the same height, it means the volts-seconds product is the same. When the short circuit operation occurs, the output voltage down to zero leads to the voltage across the inductor maximum in the on period and the voltage across the inductor minimum in the off period. In order to maintain the volts-seconds balance, the offtime must be extended to prevent the inductor current run away. Frequency decay will extend the switching period to provide more times to the off-period, then the inductor C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 9 www.anpec.com.tw current has to restrict to protect the electrical circuit in the short situation. Dropout Operation As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the PMOSFET and the inductor. An important detail to remember is that on resistance of PMOSFET switch will increase at low input supply voltage. Therefore, the user should calculate the power dissipation when the APW7101 is used at 100% duty cycle with low input voltage. Slope Compensation Slope compensation provides stability in constant frequency current mode architecture by preventing subharmonic oscillations at high duty cycle. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycle in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles greater than 40%. In the APW7101, the reduction of inductor peak current recovered by a special skill at high duty ratio. This allows the maximum inductor peak current maintain a constant level through all duty ratio. APW7101 Application Information Inductor Selection Due to the high switching frequency as 1.5MHz, the inductor value of the application field of APW7101 is usually from 1µH to 4.7µH. The criterion to select a suitable inductor is dependent on the worst current ripple throughout the inductor. The worst current ripple defines as 40% of the fully load capability. In the APW7101 applications, the worst value of current ripple is 240mA, the 40% of 600mA. Evaluate L by equation (1): L= 0A Figure-1 shows a schematic of a Buck structure. The waveforms is shown as Figure-2. IL IOUT IIN (VIN − V OUT ) ⋅ V OUT 1 ⋅ VIN ∆ IL ⋅ f S 0A IIN I(CIN) ......( 1) where fS is the switching frequency of APW7101 and ∆IL is the value of the worst current ripple, it can be any value of current ripple that smaller than the worst value you can accept. In order to perform high efficiency, selecting a low DC resistance inductor is a helpful way. Another important parameter is the DC current rating of the inductor. The minimum value of DC current rating equals the full load value of 600mA, plus the half of the worst current ripple, 120mA. Choose inductors with suitable DC current rating to ensure the inductors don’ operate in the t saturation. Input Capacitor Selection 0A (1-D)*TS 0A D*TS PWM 0A I(COUT) I(Q1) IOUT The input capacitor must be able to support the maximum input operating voltage and maximum RMS input current. The Buck converter absorbs current from input in pulses. Figure-2 Observe the waveform of I(CIN),the RMS value of I(CIN) is I(CIN ) = [(I OUT − IIN ) ⋅ D + IIN ⋅ 1 − D 2 2 ]( ) 2 ......( 2) Replace D and IIN by following relation: D= VOUT ......( 3) VIN IIN = D ⋅ IOUT ......( 4) The RMS value of input capacitor current equal: I(CIN ) = IOUT ⋅ D(1 − D) ......( 5) Figure-1 When D=0.5 the RMS current of input capacitor will be maximum value. Use this value to choose the input capacitor with suitable current rating. C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 10 www.anpec.com.tw APW7101 Application Information (Cont.) Output Capacitor Selection The output voltage ripple is a significant parameter to estimate the performance of a convertor. There are two discrete components that affect the output voltage ripple bigger or smaller. It is recommended to use the criterion has mentioned above to choose a suitable inductor. Then based on this known inductor current ripple condition, the value and properties of output capacitor will affect the output voltage ripple better or worse. The output voltage ripple consists of two portions, one is the product of ESR and inductor current ripple, the other portion is the function of the inductor current ripple and the output capacitance. Figure-3 shows the waveforms to explain the part decided by the output capacitance.  TS ∆ VOUT = ∆ IL ⋅  ESL +  8 ⋅ C OUT  Thermal Consideration   ......( 8 )   APW7101 is a high efficiency switching converter, it means less power loss transferred into heat. Due to the on resistance difference between internal power PMOSFET and NMOSFET, the power dissipation in the high converting ratio is greater than low converting ratio. The worst case is in the dropout operation, the mainly conduction loss dissipate on the internal power PMOSFET. The power dissipation nearly defined as: PD = (IOUT ) R DS _ ONP ⋅ D + R DS _ ONN ⋅ (1 − D) ......( 9) 2 [ ] APW7101 has internal over temperature protection. When the junction temperature reaches 150 centigrade, APW7101 will turn off both internal power PMOSFET and 0A ∆IL I(COUT) NMOSFET. The estimation of the junction temperature, TJ, defined as: TJ = PD ⋅ θ JA ......(10 ) 0.5TS ∆VOUT1 VOUT where the θJA i s the thermal resistance of the package utilized by APW7101. Output Voltage Setting Figure-3 Evaluate the ∆VOUT1 by the ideal of energy equalization. According to the definition of Q, Q= 11 1   ∆ IL ⋅ TS  = C OUT ⋅ ∆ V OUT 1 ......( 6 ) 22 2  APW7101 has the adjustable version for output voltage setting by the users. A suggestion of maximum value of RF2 is 200kΩ to keep the minimum current that provides enough noise rejection ability through the resistor divider. The output voltage programmed by the equation:  R V OUT = 0 . 6 ⋅  1 + F1  R F2    ......( 11)   VOUT where TS is the inverse of switching frequency and the ∆IL is the inductor current ripple. Move the COUT to the left side to estimate the value of ∆VOUT1 as equation (7). APW7101 RF1 ∆ V OUT 1 = ∆ IL ⋅ TS 8 ⋅ C OUT ......( 7 ) FB As mentioned above, one part of output voltage ripple is the product of the inductor current ripple and ESR of output capacitor. The equation (8) explains the output voltage ripple estimation. C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 11 RF2 Figure-4 www.anpec.com.tw APW7101 Application Description (Cont.) PCB Layout Consideration APW7101 is a high efficiency DC-DC converter which is a noise source in the electrical circuit by its switching operating. Some PCB layout considerations suppress the effect of switching operating by APW7101 itself to improve the better regulation. Keep the power trace wide and short as possible. The power trace shows in the Figure-6 as thick solid lines. Put the CIN to VIN close and COUT near the inductor as possible. Keep the ground terminal of CIN and COUT as close as possible to minimize the AC current loop. Put the voltage divider consist of RF1 and RF2 closely to FB, the connection path between RF1 and VOUT must far away the SW to prevent the switch noise coupling into FB by crosstalk. If necessary, the connection path between RF1 and VOUT must near to SW, put a ground trace between the feedback trace and SW to prevent the coupling. VIN 2.5V TO 5.5V CIN 4.7µF APW7101 Figure-6 Suggested layout Top Side 4 1 VDD RUN GND SW FB 3 5 L 2.2µH RF1 RF2 VOUT 2 COUT 10µF VIN 2.5V TO 5.5V CIN 4.7µF APW7101/1.5V/1.8V 4 1 VDD RUN GND SW FB 3 5 L 2.2µH VOUT 2 COUT 10µF Figure-5 Figure-7 Suggested layout Button Side C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 12 www.anpec.com.tw APW7101 Package Information SOT-23-5 D e SEE VIEW A E1 b e1 E c 0.25 GAUGE PLANE SEATING PLANE VIEW A SOT-23-5 INCHES MIN. MAX. 0.057 0.000 0.035 0.012 0.003 0.106 0.102 0.055 0.037 BSC 0.075 BSC 0.60 8° 0.012 0° 0.024 8° 0.006 0.051 0.020 0.009 0.122 0.118 0.071 MAX. 1.45 0.15 1.30 0.50 0.22 3.10 3.00 1.80 A2 A1 A S Y M B O L A A1 A2 b c D E E1 e e1 L 0 MILLIMETERS MIN. 0.00 0.90 0.30 0.08 2.70 2.60 1.40 0.95 BSC 1.90 BSC 0.30 0° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 13 0 L www.anpec.com.tw APW7101 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A H H A T1 T1 C d D 20.2 MIN. T W E1 W F 3.5± 0.05 K0 178.0± 2.00 50 MIN. SOT-23-5 P0 4.0± 0.10 P1 4.0± 0.10 8.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 2.0± 0.05 D0 1.5+0.10 -0.00 D1 1.0 MIN. 8.0± 0.30 1.75± 0.10 A0 B0 0.6+0.00 0.20 3.10± 0.20 1.50± 0.20 -0.40 3.20± (mm) Devices Per Unit Package Type SOT-23-5 Unit Tape & Reel Quantity 3000 C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 14 www.anpec.com.tw APW7101 Reflow Condition TP Ramp-up TL Tsmax (IR/Convection or VPR Reflow) tp Critical Zone TL to TP Temperature tL Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. C opyright © A NPEC Electronics Corp. Rev. A.4 - Jun., 2008 15 www.anpec.com.tw APW7101 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 Package Thickness Volume mm