AT32UC3A3256S_10

Features • High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing up to 1.51DMIPS/MHz • Up to 92DMIPS Running at 66MHz from Flash (1 Wait-State) • Up to 54 DMIPS Running at 36MHz from Flash (0 Wait-State) – Memory Protection Unit Multi-Layer Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral Communication – 4 generic DMA Channels for High Bandwidth Data Paths Internal High-Speed Flash – 256KBytes, 128KBytes, 64KBytes versions – Single-Cycle Flash Access up to 36MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4 ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM – 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus – 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority System Functions – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), – Watchdog Timer, Real-Time Clock Timer External Memories – Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash – Up to 66 MHz External Storage device support – MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1 – CE-ATA V1.1, FastSD, SmartMedia, Compact Flash – Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities Universal Serial Bus (USB) – High-Speed USB (480Mbit/s) Device/MiniHost with On-The-Go (OTG) – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-Chip Transceivers Including Pull-Ups One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Two Three-Channel 16-bit Timer/Counter (TC) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Fractionnal Baudrate Generator • 32-bit AVR® Microcontroller AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 AT32UC3A4256S AT32UC3A4256 AT32UC3A4128S AT32UC3A4128 AT32UC3A464S AT32UC3A464 • • • • • • Preliminary • • • • • 32072C–03/2010 AT32UC3A3/A4 – Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible 16-bit Stereo Audio Bitstream – Sample Rate Up to 50 KHz On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace 110 General Purpose Input/Output (GPIOs) – Standard or High Speed mode – Toggle capability: up to 66MHz Packages – 144-ball TFBGA, 11x11 mm, pitch 0.8 mm – 144-pin LQFP, 22x22 mm, pitch 0.5 mm – 100-ball VFBGA, 7x7 mm, pitch 0.65 mm Single 3.3V Power Supply • • • • • • • • 2 32072C–AVR32–2010/03 AT32UC3A3/A4 1. Description The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The AT32UC3A3/A4 incorporates on-chip Flash and SRAM memories for secure and fast access. 64 KBytes of SRAM are directly coupled to the AVR32 UC for performances optimization. Two blocks of 32 Kbytes SRAM are independently attached to the High Speed Bus Matrix, allowing real ping-pong management. The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit channels are combined to operate as 32-bit channels. The AT32UC3A3/A4 also features many communication interfaces for communication intensive applications like UART, SPI or TWI. Additionally, a flexible Synchronous Serial Controller (SSC) is available. The SSC provides easy access to serial communication protocols and audio standards like I2S. The AT32UC3A3/A4 includes a powerfull External Bus Interface to interface all standard memory device like SRAM, SDRAM, NAND Flash or parallel interfaces like LCD Module. The peripheral set includes a High Speed MCI for SDIO/SD/MMC and a hardware encryption module based on AES algorithm. The device embeds a 10-bit ADC and a Digital Audio bistream DAC. The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal features (AES, internal memories). The High-Speed (480MBit/s) USB 2.0 Device and Host interface supports several USB Classes at the same time thanks to the rich Endpoint configuration. The On-The-Go (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. This periphal has its own dedicated DMA and is perfect for Mass Storage application. AT32UC3A3/A4 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. 3 32072C–AVR32–2010/03 AT32UC3A3/A4 2. Blockdiagram Figure 2-1. Blockdiagram MEMORY INTERFACE TCK TDO TDI TMS JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N NEXUS CLASS 2+ OCD AVR32 UC CPU MEMORY PROTECTION UNIT LOCAL BUS INTERFACE FAST GPIO PBB ID VBOF FLASH CONTROLLER USB_VBIAS USB_VBUS DMFS, DMHS DPFS, DPHS INSTR INTERFACE DATA INTERFACE 64 KB SRAM USB HS INTERFACE DMA 32KB RAM 32KB RAM HRAM0/1 S M S S M M M M M S S 256/128/64 KB FLASH DMACA GENERAL PURPOSE IOs S EXTERNAL BUS INTERFACE (SDRAM, STATIC MEMORY, COMPACT FLASH & NAND FLASH) HIGH SPEED BUS MATRIX DATA[15..0] ADDR[23..0] NCS[5..0] NRD NWAIT NWE0 NWE1 NWE3 RAS CAS SDA10 SDCK SDCKE SDWE CFCE1 CFCE2 CFRW NANDOE NANDWE AES DMA S S CONFIGURATION S REGISTERS BUS M PB HSB HSB HSB-PB BRIDGE B HSB-PB BRIDGE A PB PBA PERIPHERAL DMA CONTROLLER CLK DMA CMD[1..0] PA PB PC PX DATA[15..0] PDC GENERAL PURPOSE IOs MULTIMEDIA CARD & MEMORY STICK INTERFACE USART1 RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS EXTINT[7..0] SCAN[7..0] NMI PDC EXTERNAL INTERRUPT CONTROLLER REAL TIME COUNTER PDC INTERRUPT CONTROLLER PA PB PC PX USART0 USART2 RXD USART3 TXD CLK VDDIN GNDCORE VDDCORE 1V8 Regulator SERIAL PERIPHERAL INTERFACE 0/1 SYNCHRONOUS SERIAL CONTROLLER SPCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA WATCHDOG TIMER PDC 115 kHz RCSYS XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 POWER MANAGER PDC PDC 32 KHz OSC OSC0 OSC1 PLL0 PLL1 TWCK CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER TWO-WIRE INTERFACE 0/1 TWD TWALM ANALOG TO DIGITAL CONVERTER AUDIO BITSTREAM DAC PDC AD[7..0] PDC DATA[1..0] DATAN[1..0] RESET_N GCLK[3..0] A[2..0] B[2..0] CLK[2..0] TIMER/COUNTER 0/1 4 32072C–AVR32–2010/03 AT32UC3A3/A4 2.1 2.1.1 Processor and Architecture AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extension with saturating arithmetic, and a wide variety of multiply instructions • Three stage pipeline allows one instruction per clock cycle for most instructions – Byte, halfword, word and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection – – – – – 2.1.2 Debug and Test System • IEEE1149.1 compliant JTAG and boundary scan • Direct memory access and programming capabilities through JTAG interface • Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ • • • • – Low-cost NanoTrace supported Auxiliary port for high-speed trace information Hardware support for six Program and two data breakpoints Unlimited number of software breakpoints supported Advanced Program, Data, Ownership and Watchpoint trace supported 2.1.3 Peripheral DMA Controller • Transfers from/to peripheral to/from any memory space without intervention of the processor • Next Pointer Support, forbids strong real-time constraints on buffer management • Eight channels and 24 Handshake interfaces – – – – – – Two for each USART Two for each Serial Synchronous Controller (SSC) Two for each Serial Peripheral Interface (SPI) One for ADC Four for each TWI Interface Two for each Audio Bit Stream DAC 2.1.4 Bus System • High Speed Bus (HSB) matrix with 7 Masters and 10 Slaves handled – Handles Requests from • Masters: the CPU (Instruction and Data Fetch), PDCA, CPU SAB, USBB, DMACA • Slaves: the internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, External Bus Interface (EBI), Advanced Encrytion Standard (AES) – Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) – Burst breaking with Slot Cycle Limit – One address decoder provided per master • Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus 5 32072C–AVR32–2010/03 AT32UC3A3/A4 3. Signals Description The following table gives details on the signal name classified by peripheral Table 3-1. Signal Name Signal Description List Function Power Type Active Level Comments VDDIO VDDANA VDDIN ONREG I/O Power Supply Analog Power Supply Voltage Regulator Input Supply Voltage Regulator ON/OFF Power Power Power Power Control Power Output Ground Ground Ground Ground Clocks, Oscillators, and PLL’s 1 3.0 to 3.6 V 3.0 to 3.6 V 2.7 to 3.6 V 2.7 to 3.6 V VDDCORE GNDANA GNDIO GNDCORE GNDPLL Voltage Regulator Output for Digital Supply Analog Ground I/O Ground DIgital Ground PLL Ground 1.65 to 1.95V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG Analog Analog TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input Auxiliary Port - AUX MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Output Output Power Manager - PM Low Low 6 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-1. Signal Name GCLK[2:0] RESET_N Signal Description List Function Generic Clock Pins Reset Pin Type Output Input DMA Controller - DMACA (optional) Low Active Level Comments DMAACK[1:0] DMARQ[1:0] DMA Acknowledge DMA Requests Output Input External Interrupt Module - EIM EXTINT[7:0] KPS0 - KPS7 NMI_N External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin Input Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] PB[11:0] PC[5:0] PX[59:0] Parallel I/O Controller GPIOA Parallel I/O Controller GPIOB Parallel I/O Controller GPIOC Parallel I/O Controller GPIO X I/O I/O I/O I/O External Bus Interface - EBI ADDR[23:0] CAS CFCE1 CFCE2 CFRNW DATA[15:0] NANDOE NANDWE NCS[5:0] NRD NWAIT NWE0 NWE1 Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Output Output Output Output Output I/O Output Output Output Output Input Output Output Low Low Low Low Low Low Low Low Low Low 7 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-1. Signal Name RAS SDA10 SDCK SDCKE SDCS SDWE Signal Description List Function Row Signal SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Chip Select SDRAM Write Enable Type Output Output Output Output Output Output MultiMedia Card Interface - MCI Low Low Active Level Low Comments CLK CMD[1:0] DATA[15:0] Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O Serial Peripheral Interface - SPI0 MISO MOSI NPCS[3:0] SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC Low RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TC0, TC1 A0 A1 A2 B0 B1 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B I/O I/O I/O I/O I/O 8 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-1. Signal Name B2 CLK0 CLK1 CLK2 Signal Description List Function Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O Input Input Input Active Level Comments Two-wire Interface - TWI0, TWI1 SCL SDA Serial Clock Serial Data I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS DCD DSR DTR RI RTS RXD RXDN TXD TXDN Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Inverted Receive Data Transmit Data Inverted Transmit Data Output Input Input Output Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Audio Bitstream DAC (ABDAC) DATA0-DATA1 DATAN0-DATAN1 D/A Data out D/A Data inverted out Output Output Universal Serial Bus Device - USB FSDM FSDP HSDM USB Full Speed Data USB Full Speed Data + USB High Speed Data Analog Analog Analog Low Low I/O Input Only USART1 Only USART1 Only USART1 Only USART1 9 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-1. Signal Name HSDP USB_VBIAS USB_VBUS Signal Description List Function USB High Speed Data + USB VBIAS reference USB VBUS for OTG feature Type Analog Analog Output Connect to the ground through a 6810ohms (+/- 0.5%) resistor Active Level Comments 10 32072C–AVR32–2010/03 AT32UC3A3/A4 4. Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 4-1. TFBGA144 Pinout (top view) 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12 Table 4-1. 1 A B C D E F G H J K L M PX40 PX10 PX09 PX08 PX38 PX39 PX00 PX01 PX04 PX03 PX11 PX22 TFBGA144 Package Pinout 2 PB00 PB11 PX35 PX37 VDDIO PX07 PX05 VDDIO PX02 PX44 GNDIO PX41 3 PA28 PA31 GNDIO PX36 PX54 PX06 PX59 PX58 PX34 GNDIO PX45 PX42 4 PA27 PB02 PB01 PX47 PX53 PX49 PX50 PX57 PX56 PX46 PX20 PX14 5 PB03 VDDIO PX16 PX19 VDDIO PX48 PX51 VDDIO PX55 PC00 VDDIO PX21 6 PA29 PB04 PX13 PX12 PX15 GNDIO GNDIO PC01 PA14 PX17 PX18 PX23 7 PC02 PC03 PA30 PB10 PB09 GNDIO GNDIO PA17 PA15 PX52 PX43 PX24 8 PC04 VDDIO PB08 PA02 VDDIN PA06 PA23 VDDIO PA19 PA18 VDDIN PX25 9 PC05 USB_VBIAS 10 DPHS DMFS GNDCORE 11 DMHS GNDPLL PA08 PB07 VDDCORE 12 USB_VBUS PA09 PA10 PB06 PA12 PA16 PA01 PB05 RESET_N DPFS PA26 PA25 PA04 PA24 PA21 PA20 PX27 PX26 PX32 PA11 PA07 PA05 PA03 PA22 TMS GNDIO PX28 PX31 PA13 PA00 VDDANA TDO PX29 GNDANA PX30 TCK TDI PX33 11 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 4-2. LQFP144 Pinout 108 109 73 72 144 1 Table 4-2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 LQFP144 Package Pinout 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PB02 PA27 PB01 PA28 PA31 PB00 PB11 PX16 PX13 PX12 PX19 PX40 PX10 PX35 PX47 PX15 PX48 PX53 PX49 PX36 PX37 PX54 GNDIO VDDIO 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PX09 PX08 PX38 PX39 PX06 PX07 PX00 PX59 PX58 PX05 PX01 PX04 PX34 PX02 PX03 VDDIO GNDIO PX44 PX11 PX14 PX42 PX45 PX41 PX22 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PX20 PX46 PX50 PX57 PX51 PX56 PX55 PX21 VDDIO GNDIO PX17 PX18 PX23 PX24 PX52 PX43 PX27 PX26 PX28 PX25 PX32 PX29 PX33 PX30 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PX31 PC00 PC01 PA14 PA15 GNDIO VDDIO TMS TDO RESET_N TCK TDI PA21 PA22 PA23 PA24 PA20 PA19 PA18 PA17 GNDANA VDDANA PA25 PA26 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PB05 PA00 PA01 PA05 PA03 PA04 PA06 PA16 PA13 VDDIO GNDIO PA12 PA07 PB06 PB07 PA11 PA08 PA10 PA09 GNDCORE VDDCORE VDDIN VDDIN GNDPLL USB_VBUS VDDIO USB_VBIAS GNDIO DMHS DPHS GNDIO DMFS DPFS VDDIO PB08 PC05 PC04 PA30 PA02 PB10 PB09 PC02 PC03 GNDIO VDDIO PB04 PA29 PB03 12 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 4-3. VFBGA100 Pinout (top view) 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 Table 4-3. 1 A B C D E F G H J K PA28 PB00 PB11 PX12 PA02/PX47 (1) VFBGA100 Package Pinout 2 PA27 PB01 PA31 PX10 GNDIO VDDIO PX01 PX21 PX24 PX27 3 PB04 PB02 GNDIO PX13 PX08 PX06 PX02 GNDIO PX26 PX28 4 PA30 PA29 PB03 PX16/PX53 (1) 5 PC02 VDDIO PB09 PB10 VDDIO GNDIO PX30 PX31 VDDIO PC00/PX14(1) 6 PC03 VDDIO PB08 PB07 GNDIO VDDIO PA23/PX46(1) PA22/PX20(1) 7 PC05 PC04 USB_VBIAS 8 DPHS DPFS GNDIO PA09 PA06/PA13 (1) 9 DMHS DMFS PA11 VDDIN PA04 PA03 PA05 PA20/PX18(1) 10 USB_VBUS GNDPLL PA10 VDDIN VDDCORE GNDCORE PA01/PA17(1) PA07/PA19(1) PA24/PX17(1) PA21/PX22(1) PB06 PA16 PA26/PB05(1) PA12/PA25(1) PX09 PX07 PX00 PX25 PX29 PX15/PX32(1) PX19/PX59(1) PA08 PA00/PA18(1) PX05 PX04 PX03 PX23 TMS PA15/PX45(1) PA14/PX11(1) GNDANA TDO TDI VDDANA PC01 RESET_N TCK Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 13 32072C–AVR32–2010/03 AT32UC3A3/A4 4.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C, or D. The following table defines how the I/O lines on the peripherals A, B, C, or D are multiplexed by the GPIO. Table 4-4. TFBGA GPIO Controller Function Multiplexing QFP VFBGA 144 G11 G12 D8 G10 F9 F10 F8 E10 C11 B12 C12 D10 E12 F11 J6 J7 F12 H7 K8 J8 J9 H9 H10 G8 G9 E9 D9 A4 A3 A6 C7 B3 A2 C4 144 122 123 15 125 126 124 127 133 137 139 138 136 132 129 100 101 128 116 115 114 113 109 110 111 112 119 120 26 28 23 14 29 30 27 100 G8 (1) (1) Pin PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 GPIO Pin GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 Function A USART0 - RTS USART0 - CTS USART0 - CLK USART0 - RXD USART0 - TXD USART1 - RXD USART1 - TXD SPI0 - NPCS[3] SPI0 - SPCK SPI0 - NPCS[0] SPI0 - MOSI SPI0 - MISO USART1 - CTS USART1 - RTS SPI0 - NPCS[1] MCI - CMD[1] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] EIC - NMI ADC - AD[0] ADC - AD[1] ADC - AD[2] ADC - AD[3] TWIMS0 - TWD TWIMS0 - TWCK MCI - CLK MCI - CMD[0] MCI - DATA[0] MCI - DATA[1] MCI - DATA[2] MCI - DATA[3] MCI - DATA[4] Function B TC0 - CLK1 TC0 - A1 TC0 - B1 EIC - EXTINT[4] EIC - EXTINT[5] TC1 - CLK0 TC1 - CLK1 ABDAC - DATAN[0] ABDAC - DATA[0] EIC - EXTINT[6] USB - VBOF USB - ID SPI0 - NPCS[2] SPI0 - NPCS[1] TWIMS0 - TWALM SPI1 - SPCK SPI1 - MOSI SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - MISO SSC - RX_FRAME_SYNC Function C SPI1 - NPCS[3] USART2 - RTS SPI0 - NPCS[0] ABDAC - DATA[0] ABDAC - DATAN[0] USB - ID USB - VBOF USART1 - CLK TC1 - B1 TC1 - A1 TC1 - B0 TC1 - A2 TC1 - A0 EIC - EXTINT[7] TWIMS1 - TWCK TWIMS1 - TWD TC1 - CLK2 ADC - AD[7] ADC - AD[6] ADC - AD[5] ADC - AD[4] USB - ID USB - VBOF ABDAC - DATA[1] ABDAC - DATAN[1] USART1 - DCD USART1 - DSR USART3 - RTS USART3 - CTS TC0 - CLK0 DMACA - DMAACK[0] DMACA - DMARQ[0] Function D G10 E1 (1) F9 E9 G9 E8 (1) (1) H10 F8 D8 C10 C9 G7 E8 (1) (1) (1) K7 J7 (1) E7 G10 G8 (1) (1) (1) H10 H9 (1) (1) K10 H6 EIC - EXTINT[0] EIC - EXTINT[1] EIC - EXTINT[2] EIC - EXTINT[3] TWIMS1 - TWALM USART2 - CTS SSC - RX_DATA SSC - RX_CLOCK USART3 - TXD USART3 - CLK USART2 - RXD USART2 - TXD ABDAC - DATA[1] (1) (1) (1) G6 J10 G7 (1) F7 ) A2 A1 B4 A4 C2 B1 B2 (1) MSI - SCLK MSI - BS MSI - DATA[0] MSI - DATA[1] MSI - DATA[2] MSI - DATA[3] MSI - INS ADC - TRIGGER EIC - SCAN[0] 14 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-4. B4 A5 B6 H12 D12 D11 C8 E7 D7 B2 K5 H6 A7 B7 A8 A9 G1 H1 J2 K1 J1 G2 F3 F2 D1 C1 B1 L1 D6 C6 M4 E6 C5 K6 L6 D5 L4 M5 M1 GPIO Controller Function Multiplexing 25 24 22 121 134 135 11 17 16 31 98 99 18 19 13 12 55 59 62 63 60 58 53 54 50 49 37 67 34 33 68 40 32 83 84 35 73 80 72 B3 C4 A3 F7(1) D7 D6 C6 C5 D5 C1 K5(1) K6 A5 A6 B7 A7 G4 G2 G3 J1 H1 G1 F3 F4 E3 E4 D2 K7(1) D1 D3 K5(1) K4(1) D4(1) J10(1) H9(1) F1(1) H6(1) H2 K10(1) PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 68 GPIO 69 GPIO 70 GPIO 71 GPIO 72 GPIO 73 EBI - DATA[10] EBI - DATA[9] EBI - DATA[8] EBI - DATA[7] EBI - DATA[6] EBI - DATA[5] EBI - DATA[4] EBI - DATA[3] EBI - DATA[2] EBI - DATA[1] EBI - DATA[0] EBI - NWE1 EBI - NWE0 EBI - NRD EBI - NCS[1] EBI - ADDR[19] EBI - ADDR[18] EBI - ADDR[17] EBI - ADDR[16] EBI - ADDR[15] EBI - ADDR[14] EBI - ADDR[13] EBI - ADDR[12] USART3 - RTS USART3 - CTS DMACA - DMARQ[1] DMACA - DMAACK[1] EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] USART0 - RXD USART0 - TXD USART0 - CTS USART0 - RTS USART1 - RXD USART1 - TXD USART1 - CTS USART1 - RTS USART3 - RXD USART3 - TXD USART2 - RXD USART2 - TXD USART2 - CTS USART2 - RTS MCI - CLK MCI - CLK TC0 - A0 TC0 - B0 TC0 - A1 TC0 - B1 TC0 - A2 TC0 - B2 TC0 - CLK0 TC0 - CLK1 TC0 - CLK2 USART1 - RI USART1 - DTR PM - GCLK[0] MCI - DATA[5] MCI - DATA[6] MCI - DATA[7] USB - ID USB - VBOF SPI1 - SPCK SPI1 - MISO SPI1 - NPCS[0] SPI1 - MOSI USART1 - RXD ABDAC - DATAN[1] USART2 - CLK USART3 - RXD TC0 - A0 TC0 - B0 SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC - RX_FRAME_SYNC SSC - TX_FRAME_SYNC EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] EBI - NCS[4] EBI - NCS[5] PM - GCLK[1] 15 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-4. M6 M7 M8 L9 K9 L10 K11 M11 M10 M9 M12 J3 C2 D3 D2 E1 F1 A1 M2 M3 L7 K2 L3 K4 D4 F5 F4 G4 G5 K7 E4 E3 J5 J4 H4 H3 G3 GPIO Controller Function Multiplexing 85 86 92 90 89 91 94 96 97 93 95 61 38 44 45 51 52 36 71 69 88 66 70 74 39 41 43 75 77 87 42 46 79 78 76 57 56 F1(1) D4(1) J7(1) G6(1) E1(1) K1 J2 H4 J3 K2 K3 J4 G5 H5 K4(1) PX23 PX24 PX25 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 GPIO 74 GPIO 75 GPIO 76 GPIO 77 GPIO 78 GPIO 79 GPIO 80 GPIO 81 GPIO 82 GPIO 83 GPIO 84 GPIO 85 GPIO 86 GPIO 87 GPIO 88 GPIO 89 GPIO 90 GPIO 91 GPIO 92 GPIO 93 GPIO 94 GPIO 95 GPIO 96 GPIO 97 GPIO 98 GPIO 99 GPIO 100 GPIO 101 GPIO 102 GPIO 103 GPIO 104 GPIO 105 GPIO 106 GPIO 107 GPIO 108 GPIO 109 GPIO 110 EBI - CAS EBI - RAS EBI - SDA10 EBI - SDWE EBI - SDCK EBI - SDCKE EBI - NANDOE EBI - ADDR[23] EBI - CFRNW EBI - CFCE2 EBI - CFCE1 EBI - NCS[3] EBI - NCS[2] EBI - NWAIT EBI - ADDR[22] EBI - ADDR[21] EBI - ADDR[20] EBI - NCS[0] EBI - NANDWE USART3 - TXD EIC - SCAN[3] EIC - SCAN[2] EIC - SCAN[1] EIC - SCAN[0] ADC - TRIGGER USB - VBOF USB - ID TC1 - B2 DMACA - DMAACK[0] DMACA - DMARQ[0] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] MCI - DATA[15] MCI - DATA[14] MCI - DATA[13] MCI - DATA[12] USART2 - RXD USART2 - TXD USART3 - RXD USART3 - TXD MCI - CMD[1] USART1 - RI USART1 - DTR EBI - ADDR[11] EBI - ADDR[10] EBI - ADDR[9] EBI - ADDR[8] EBI - ADDR[7] EBI - ADDR[6] EBI - ADDR[5] EBI - ADDR[4] EBI - ADDR[3] EBI - ADDR[2] EBI - ADDR[1] EBI - ADDR[0] EBI - DATA[15] EBI - DATA[14] EBI - DATA[13] EBI - DATA[12] EBI - DATA[11] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] SPI0 - MISO SPI0 - MOSI SPI0 - SPCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] SPI0 - NPCS[3] SPI1 - MISO SPI1 - MOSI SPI1 - SPCK SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] MCI - CLK PM - GCLK[0] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] USART1 - DCD USART1 - DSR SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC - RX_FRAME_SYNC SSC - TX_FRAME_SYNC SSC - RX_CLOCK Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 16 32072C–AVR32–2010/03 AT32UC3A3/A4 4.2.1 Table 4-5. Oscillator Pinout Oscillator Pinout QFP144 18 19 13 12 98 99 Note: VFBGA100 A5 A6 B7 A7 K5 (1) TFBGA144 A7 B7 A8 A9 K5 H6 Pin name PC02 PC03 PC04 PC05 PC00 PC01 Oscillator pin XIN0 XOUT0 XIN1 XIN1 XIN32 XOUT32 K6 1. This ball is physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 4.2.2 Table 4-6. JTAG port connections JTAG Pinout QFP144 107 108 105 104 VFBGA100 K9 K8 J8 H7 Pin name TCK TDI TDO TMS JTAG pin TCK TDI TDO TMS TFBGA144 K12 L12 J11 J10 4.2.3 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespective of the GPIO configuration. Three differents OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 4-7. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] MSEO[1] MSEO[0] MCKO EVTO_N Nexus OCD AUX port connections AXS=0 PB05 PA00 PA01 PA03 PA16 PA13 PA12 PA10 PA11 PB07 PB06 AXS=1 PA08 PX56 PX57 PX58 PA24 PA23 PA22 PA07 PX55 PX00 PB06 AXS=2 PX00 PX06 PX05 PX04 PX03 PX02 PX01 PX08 PX07 PB09 PB06 17 32072C–AVR32–2010/03 AT32UC3A3/A4 4.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-8. Signal Name Signal Description List Function Power Type Active Level Comments VDDIO VDDANA VDDIN VDDCORE GNDANA GNDIO GNDCORE GNDPLL I/O Power Supply Analog Power Supply Voltage Regulator Input Supply Voltage Regulator Output for Digital Supply Analog Ground I/O Ground Digital Ground PLL Ground Power Power Power Power Output Ground Ground Ground Ground Clocks, Oscillators, and PLL’s 3.0 to 3.6V 3.0 to 3.6V 3.0 to 3.6V 1.65 to 1.95 V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG Analog Analog TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input Auxiliary Port - AUX MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Output Output Power Manager - PM Low Low GCLK[3:0] Generic Clock Pins Output 18 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-8. Signal Name RESET_N Signal Description List Function Reset Pin Type Input DMA Controller - DMACA (optional) Active Level Low Comments DMAACK[1:0] DMARQ[1:0] DMA Acknowledge DMA Requests Output Input External Interrupt Controller - EIC EXTINT[7:0] SCAN[7:0] NMI External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin Input Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] PB[11:0] PC[5:0] PX[59:0] Parallel I/O Controller GPIO port A Parallel I/O Controller GPIO port B Parallel I/O Controller GPIO port C Parallel I/O Controller GPIO port X I/O I/O I/O I/O External Bus Interface - EBI ADDR[23:0] CAS CFCE1 CFCE2 CFRNW DATA[15:0] NANDOE NANDWE NCS[5:0] NRD NWAIT NWE0 NWE1 RAS Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Row Signal Output Output Output Output Output I/O Output Output Output Output Input Output Output Output Low Low Low Low Low Low Low Low Low Low Low 19 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-8. Signal Name SDA10 SDCK SDCKE SDWE Signal Description List Function SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Write Enable Type Output Output Output Output MultiMedia Card Interface - MCI Low Active Level Comments CLK CMD[1:0] DATA[15:0] Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O Memory Stick Interface - MSI SCLK BS DATA[3:0] Memory Stick Clock Memory Stick Command Multimedia Card Data Output I/O I/O Serial Peripheral Interface - SPI0, SPI1 MISO MOSI NPCS[3:0] SPCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TC0, TC1 A0 A1 A2 Channel 0 Line A Channel 1 Line A Channel 2 Line A I/O I/O I/O Low 20 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-8. Signal Name B0 B1 B2 CLK0 CLK1 CLK2 Signal Description List Function Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O I/O I/O Input Input Input Active Level Comments Two-wire Interface - TWI0, TWI1 TWCK TWD TWALM Serial Clock Serial Data SMBALERT signal I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS DCD DSR DTR RI RTS RXD TXD Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Transmit Data Output Input Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Audio Bitstream DAC (ABDAC) DATA0-DATA1 DATAN0-DATAN1 D/A Data out D/A Data inverted out Output Output Universal Serial Bus Device - USB DMFS DPFS USB Full Speed Data USB Full Speed Data + Analog Analog I/O Input Only USART1 Only USART1 Only USART1 Only USART1 21 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-8. Signal Name DMHS DPHS Signal Description List Function USB High Speed Data USB High Speed Data + Type Analog Analog Connect to the ground through a 6810 ohms (+/- 1%) resistor in parallel with a 10pf capacitor. If USB hi-speed feature is not required, leave this pin unconnected to save power Active Level Comments USB_VBIAS USB VBIAS reference Analog USB_VBUS VBOF ID USB VBUS for OTG feature USB VBUS on/off bus power control port ID Pin fo the USB bus Output Output Input 22 32072C–AVR32–2010/03 AT32UC3A3/A4 4.4 4.4.1 I/O Line Considerations JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 4.4.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 4.4.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 4.4.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset State” of the I/O Controller multiplexing tables. 23 32072C–AVR32–2010/03 AT32UC3A3/A4 4.5 4.5.1 Power Considerations Power Supplies The AT32UC3A3 has several types of power supply pins: • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC. Voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pin GNDCORE is common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pins for VDDIO are GNDIO. Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 4.5.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: • One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. • One external 2.2µF (or 3.3µF) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (1nF NPO and 4.7µF X7R). 3.3V CIN2 CIN1 VDDIN 1.8V Regulator VDDCORE 1.8V COUT2 COUT1 24 32072C–AVR32–2010/03 AT32UC3A3/A4 5. Power Considerations 5.1 Power Supplies The AT32UC3A3/A4 has several types of power supply pins: • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pins GNDCORE are common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pin for VDDIO is GNDIO Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 5.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: • One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. • One external 2.2µF (or 3.3µF) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (100nF NPO and 4.7µF X7R). 3.3V CIN2 CIN1 VDDIN ONREG 1.8V Regulator 1.8 V VDDCORE COUT2 COUT1 ONREG input must be tied to VDDIN. 25 32072C–AVR32–2010/03 AT32UC3A3/A4 6. I/O Line Considerations 6.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 6.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 6.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 6.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset State” of the I/O Controller multiplexing tables. 26 32072C–AVR32–2010/03 AT32UC3A3/A4 7. Memories 7.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • 0 wait state access at up to 36MHz in worst case conditions • 1 wait state access at up to 66MHz in worst case conditions • Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access • Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation • 100 000 write cycles, 15-year data retention capability • Sector lock capabilities, Bootloader protection, Security Bit • 32 fuses, preserved during Chip Erase • User page for data to be preserved during Chip Erase • Internal High-Speed SRAM – 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud (HSB) matrix – 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix 7.2 Physical Memory Map The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical address space is mapped as follows: Table 7-1. AT32UC3A3A4 Physical Memory Map Size Device Start Address AT32UC3A3256S AT32UC3A3256 AT32UC3A4256S AT32UC3A4256 64KByte 256KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Size AT32UC3A3128S AT32UC3A3128 AT32UC3A4128S AT32UC3A4128 64KByte 128KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Size AT32UC3A364S AT32UC3A364 AT32UC3A464S AT32UC3A464 64KByte 64KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Embedded CPU SRAM Embedded Flash EBI SRAM CS0 EBI SRAM CS2 EBI SRAM CS3 EBI SRAM CS4 EBI SRAM CS5 EBI SRAM CS1 /SDRAM CS0 USB Data 0x00000000 0x80000000 0xC0000000 0xC8000000 0xCC000000 0xD8000000 0xDC000000 0xD0000000 0xE0000000 27 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 7-1. AT32UC3A3A4 Physical Memory Map Size Device Start Address AT32UC3A3256S AT32UC3A3256 AT32UC3A4256S AT32UC3A4256 32KByte 32KByte 64KByte 64KByte Size AT32UC3A3128S AT32UC3A3128 AT32UC3A4128S AT32UC3A4128 32KByte 32KByte 64KByte 64KByte Size AT32UC3A364S AT32UC3A364 AT32UC3A464S AT32UC3A464 32KByte 32KByte 64KByte 64KByte HRAMC0 HRAMC1 HSB-PB Bridge A HSB-PB Bridge B 0xFF000000 0xFF008000 0xFFFF0000 0xFFFE0000 7.3 Peripheral Address Map Peripheral Address Mapping Address 0xFF100000 Table 7-2. Peripheral Name DMACA DMA Controller - DMACA 0xFFFD0000 AES 0xFFFE0000 Advanced Encryption Standard - AES USB 0xFFFE1000 USB 2.0 OTG Interface - USB HMATRIX 0xFFFE1400 HSB Matrix - HMATRIX FLASHC 0xFFFE1C00 Flash Controller - FLASHC SMC 0xFFFE2000 Static Memory Controller - SMC SDRAMC 0xFFFE2400 SDRAM Controller - SDRAMC Error code corrector Hamming and Reed Solomon ECCHRS Bus Monitor module - BUSMON ECCHRS 0xFFFE2800 BUSMON 0xFFFE4000 MCI 0xFFFE8000 Mulitmedia Card Interface - MCI MSI 0xFFFF0000 Memory Stick Interface - MSI PDCA 0xFFFF0800 Peripheral DMA Controller - PDCA INTC Interrupt controller - INTC 28 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 7-2. Peripheral Address Mapping 0xFFFF0C00 PM 0xFFFF0D00 Power Manager - PM RTC 0xFFFF0D30 Real Time Counter - RTC WDT 0xFFFF0D80 Watchdog Timer - WDT EIC 0xFFFF1000 External Interrupt Controller - EIC GPIO 0xFFFF1400 General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 Serial Peripheral Interface - SPI0 USART0 0xFFFF1800 USART1 0xFFFF1C00 USART2 0xFFFF2000 USART3 0xFFFF2400 SPI0 0xFFFF2800 SPI1 0xFFFF2C00 Serial Peripheral Interface - SPI1 TWIM0 0xFFFF3000 Two-wire Master Interface - TWIM0 TWIM1 0xFFFF3400 Two-wire Master Interface - TWIM1 SSC 0xFFFF3800 Synchronous Serial Controller - SSC TC0 0xFFFF3C00 Timer/Counter - TC0 ADC 0xFFFF4000 Analog to Digital Converter - ADC ABDAC 0xFFFF4400 Audio Bitstream DAC - ABDAC TC1 Timer/Counter - TC1 29 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 7-2. Peripheral Address Mapping 0xFFFF5000 TWIS0 0xFFFF5400 Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 7.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 7-3. Port 0 Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000040 0x40000044 0x40000048 0x4000004C 0x40000050 0x40000054 0x40000058 0x4000005C 0x40000060 0x40000140 0x40000144 0x40000148 0x4000014C 0x40000150 0x40000154 0x40000158 0x4000015C 0x40000160 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 1 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 30 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 7-3. Port 2 Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000240 0x40000244 0x40000248 0x4000024C 0x40000250 0x40000254 0x40000258 0x4000025C 0x40000260 0x40000340 0x40000344 0x40000348 0x4000034C 0x40000350 0x40000354 0x40000358 0x4000035C 0x40000360 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 3 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 31 32072C–AVR32–2010/03 AT32UC3A3/A4 8. Peripherals 8.1 8.1.1 Clock Connections Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 8-1. Source Internal Timer/Counter clock connections Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Connection 32 KHz clock PBA Clock / 2 PBA Clock / 8 PBA Clock / 32 PBA Clock / 128 See Table 8.2 on page 32 External XC0 XC1 XC2 8.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C or D. The following table define how the I/O lines on the peripherals A, B, C or D are multiplexed by the GPIO. Table 8-2. BGA144 G11 G12 D8 G10 F9 F10 F8 E10 C11 B12 C12 D10 E12 F11 GPIO Controller Function Multiplexing QFP144 122 123 15 125 126 124 127 133 137 139 138 136 132 129 PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 GPIO Pin GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 Function A USART0 - RTS USART0 - CTS USART0 - CLK USART0 - RXD USART0 - TXD USART1 - RXD USART1 - TXD SPI0 - NPCS[3] SPI0 - SCK SPI0 - NPCS[0] SPI0 - MOSI SPI0 - MISO USART1 - CTS USART1 - RTS Function B TC0 - CLK1 TC0 - A1 TC0 - B1 EIC - EXTINT[4] EIC - EXTINT[5] TC1 - CLK0 TC1 - CLK1 DAC - DATAN[0] DAC - DATA[0] EIC - EXTINT[6] USB USB_VBOF USB - USB_ID SPI0 - NPCS[2] SPI0 - NPCS[1] Function C SPI1 - NPCS[3] USART2 - RTS SPI0 - NPCS[0] DAC - DATA[0] DAC - DATAN[0] USB - USB_ID USB USB_VBOF USART1 - CLK TC1 - B1 TC1 - A1 TC1 - B0 TC1 - A2 TC1 - A0 EIC - EXTINT[7] Function D 32 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 8-2. J6 J7 F12 H7 K8 J8 GPIO Controller Function Multiplexing 100 101 128 116 115 114 PA14 PA15 PA16 PA17 PA18 PA19 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 SPI0 - NPCS[1] MCI - CMD[1] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] TWIMS0 TWALM SPI1 - SCK SPI1 - MOSI SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - MISO SSC RX_FRAME_SYN C EIC - EXTINT[0] EIC - EXTINT[1] EIC - EXTINT[2] EIC - EXTINT[3] TWIMS1 TWALM USART2 - CTS SSC - RX_DATA SSC RX_CLOCK USART3 - TXD USART3 - CLK USART2 - RXD USART2 - TXD DAC - DATA[1] DAC - DATAN[1] USART2 - CLK USART3 - RXD TC0 - A0 TC0 - B0 SSC TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC RX_FRAME_SYN C SSC TX_FRAME_SYN C TWIMS1 - TWCK TWIMS1 - TWD TC1 - CLK2 ADC - AD[7] ADC - AD[6] ADC - AD[5] J9 H9 H10 G8 G9 E9 D9 A4 A3 A6 C7 B3 A2 C4 B4 A5 B6 H12 D12 D11 C8 E7 113 109 110 111 112 119 120 26 28 23 14 29 30 27 25 24 22 121 134 135 11 17 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 NMI ADC - AD[0] ADC - AD[1] ADC - AD[2] ADC - AD[3] TWIMS0 - TWD TWIMS0 - TWCK MCI - CLK MCI - CMD[0] MCI - DATA[0] MCI - DATA[1] MCI - DATA[2] MCI - DATA[3] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] MCI - DATA[7] USB - USB_ID USB USB_VBOF SPI1 - SCK SPI1 - MISO SPI1 - NPCS[0] ADC - AD[4] USB - USB_ID USB USB_VBOF DAC - DATA[1] DAC - DATAN[1] USART1 - DCD USART1 - DSR USART3 - RTS USART3 - CTS TC0 - CLK0 DMACA DMAACK[0] DMACA DMARQ[0] ADC - TRIGGER EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] EBI - NCS[4] MSI - SCLK MSI - BS MSI - DATA[0] MSI - DATA[1] MSI - DATA[2] MSI - DATA[3] MSI - INS D7 16 PB10 GPIO 42 SPI1 - MOSI EBI - NCS[5] B2 K5 31 98 PB11 PC00 GPIO 43 GPIO 45 USART1 - RXD PM - GCLK[1] 33 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 8-2. H6 A7 B7 A8 A9 G1 H1 J2 K1 J1 G2 F3 F2 D1 C1 B1 L1 D6 C6 M4 E6 C5 K6 L6 D5 L4 M5 M1 M6 M7 M8 GPIO Controller Function Multiplexing 99 18 19 13 12 55 59 62 63 60 58 53 54 50 49 37 67 34 33 68 40 32 83 84 35 73 80 72 85 86 92 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 PX24 PX25 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 68 GPIO 69 GPIO 70 GPIO 71 GPIO 72 GPIO 73 GPIO 74 GPIO 75 GPIO 76 EBI - DATA[10] EBI - DATA[9] EBI - DATA[8] EBI - DATA[7] EBI - DATA[6] EBI - DATA[5] EBI - DATA[4] EBI - DATA[3] EBI - DATA[2] EBI - DATA[1] EBI - DATA[0] EBI - NWE1 EBI - NWE0 EBI - NRD EBI - NCS[1] EBI - ADDR[19] EBI - ADDR[18] EBI - ADDR[17] EBI - ADDR[16] EBI - ADDR[15] EBI - ADDR[14] EBI - ADDR[13] EBI - ADDR[12] EBI - ADDR[11] EBI - ADDR[10] EBI - ADDR[9] USART3 - RTS USART3 - CTS DMACA DMARQ[1] DMACA DMAACK[1] EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] USART0 - RXD USART0 - TXD USART0 - CTS USART0 - RTS USART1 - RXD USART1 - TXD USART1 - CTS USART1 - RTS USART3 - RXD USART3 - TXD USART2 - RXD USART2 - TXD USART2 - CTS USART2 - RTS TC0 - A0 TC0 - B0 TC0 - A1 TC0 - B1 TC0 - A2 TC0 - B2 TC0 - CLK0 TC0 - CLK1 TC0 - CLK2 SSC TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC RX_FRAME_SYN C SSC TX_FRAME_SYN C SSC RX_CLOCK USART1 - RI USART1 - DTR PM - GCLK[0] L9 90 PX26 GPIO 77 EBI - ADDR[8] EIC - SCAN[7] K9 L10 89 91 PX27 PX28 GPIO 78 GPIO 79 EBI - ADDR[7] EBI - ADDR[6] SPI0 - MISO SPI0 - MOSI 34 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 8-2. K11 M11 M10 M9 M12 J3 C2 D3 D2 E1 F1 A1 M2 M3 L7 K2 L3 K4 D4 F5 F4 G4 G5 K7 E4 E3 J5 J4 H4 H3 G3 GPIO Controller Function Multiplexing 94 96 97 93 95 61 38 44 45 51 52 36 71 69 88 66 70 74 39 41 43 75 77 87 42 46 79 78 76 57 56 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 GPIO 80 GPIO 81 GPIO 82 GPIO 83 GPIO 84 GPIO 85 GPIO 86 GPIO 87 GPIO 88 GPIO 89 GPIO 90 GPIO 91 GPIO 92 GPIO 93 GPIO 94 GPIO 95 GPIO 96 GPIO 97 GPIO 98 GPIO 99 GPIO 100 GPIO 101 GPIO 102 GPIO 103 GPIO 104 GPIO 105 GPIO 106 GPIO 107 GPIO 108 GPIO 109 GPIO 110 EBI - ADDR[5] EBI - ADDR[4] EBI - ADDR[3] EBI - ADDR[2] EBI - ADDR[1] EBI - ADDR[0] EBI - DATA[15] EBI - DATA[14] EBI - DATA[13] EBI - DATA[12] EBI - DATA[11] EBI - SDCS EBI - CAS EBI - RAS EBI - SDA10 EBI - SDWE EBI - SDCK EBI - SDCKE EBI - NANDOE EBI - ADDR[23] EBI - CFRNW EBI - CFCE2 EBI - CFCE1 EBI - NCS[3] EBI - NCS[2] EBI - NWAIT EBI - ADDR[22] EBI - ADDR[21] EBI - ADDR[20] EBI - NCS[0] EBI - NANDWE USART3 - TXD EIC - SCAN[3] EIC - SCAN[2] EIC - SCAN[1] EIC - SCAN[0] ADC - TRIGGER USB USB_VBOF USB - USB_ID TC1 - B2 DMACA DMAACK[0] DMACA DMARQ[0] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] MCI - DATA[15] MCI - DATA[14] MCI - DATA[13] MCI - DATA[12] USART2 - RXD USART2 - TXD USART3 - RXD USART3 - TXD MCI - CMD[1] USART1 - RI USART1 - DTR SPI0 - SCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] SPI0 - NPCS[3] SPI1 - MISO SPI1 - MOSI SPI1 - SCK SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] PM - GCLK[0] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] USART1 - DCD USART1 - DSR 8.3 Oscillator Pinout Table 8-3. pin A7 A8 Oscillator Pinout pin 18 13 Pad PC02 PC04 Oscillator pin xin0 xin1 35 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 8-3. K5 B7 A9 H6 Oscillator Pinout 98 19 12 99 PC00 PC03 PC05 PC01 xin32 xout0 xout1 xout32 36 32072C–AVR32–2010/03 AT32UC3A3/A4 8.4 8.4.1 Peripheral overview Power Manager • • • • • • • • • • • • • Controls integrated oscillators and PLLs Generates clocks and resets for digital logic Supports 2 crystal oscillators 0.4-20MHz Supports 2 PLLs 40-240MHz Supports 32KHz ultra-low power oscillator Integrated low-power RC oscillator On-the fly frequency change of CPU, HSB, PBA, and PBB clocks Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators Module-level clock gating through maskable peripheral clocks Wake-up from internal or external interrupts Generic clocks with wide frequency range provided Automatic identification of reset sources Controls brownout detector (BOD and BOD33), RC oscillator, and bandgap voltage reference through control and calibration registers 8.4.2 Real Time Counter • 32-bit real-time counter with 16-bit prescaler • Clocked from RC oscillator or 32KHz oscillator • Long delays • • • • – Max timeout 272years High resolution: Max count frequency 16KHz Extremely low power consumption Available in all sleep modes except Static Interrupt on wrap 8.4.3 Watchdog Timer • Watchdog timer counter with 32-bit prescaler • Clocked from the system RC oscillator (RCSYS) Interrupt Controller • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt 8.4.4 37 32072C–AVR32–2010/03 AT32UC3A3/A4 • Up to 64 groups of interrupts with up to 32 interrupt requests in each group 8.4.5 External Interrupts Controller • Dedicated interrupt request for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt on high or low level • Asynchronous interrupts for sleep modes without clock • Filtering of interrupt lines • Maskable NMI interrupt • Keypad scan support • Flash Controller • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle. 8.4.6 • 32-bit HSB interface for reads from flash array and writes to page buffer. • 32-bit PB interface for issuing commands to and configuration of the controller. • 16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16) • • • • • • • 8.4.7 HSB Bus Matrix • • • • • • • pages. Regions can be individually protected or unprotected. Additional protection of the Boot Loader pages. Supports reads and writes of general-purpose NVM bits. Supports reads and writes of additional NVM pages. Supports device protection through a security bit. Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing flash and clearing security bit. Interface to Power Manager for power-down of flash-blocks in sleep mode. User Interface on peripheral bus Configurable Number of Masters (Up to sixteen) Configurable Number of Slaves (Up to sixteen) One Decoder for Each Master Three Different Memory Mappings for Each Master (Internal and External boot, Remap) One Remap Function for Each Master Programmable Arbitration for Each Slave – Round-Robin – Fixed Priority • Programmable Default Master for Each Slave – No Default Master – Last Accessed Default Master – Fixed Default Master 38 32072C–AVR32–2010/03 AT32UC3A3/A4 • One Cycle Latency for the First Access of a Burst • Zero Cycle Latency for Default Master • One Special Function Register for Each Slave (Not dedicated) 8.4.8 External Bus Interface • Optimized for application memory space support • Integrates three external memory controllers: – Static Memory Controller (SMC) – SDRAM Controller (SDRAMC) – Error Corrected Code (ECCHRS) controller • Additional logic for NAND Flash/SmartMediaTM and CompactFlashTM support – NAND Flash support: 8-bit as well as 16-bit devices are supported – CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. • Optimized external bus:16-bit data bus – Up to 24-bit Address Bus, Up to 8-Mbytes Addressable – Optimized pin multiplexing to reduce latencies on external memories • Up to 6 Chip Selects, Configurable Assignment: – Static Memory Controller on Chip Select 0 – SDRAM Controller or Static Memory Controller on Chip Select 1 – Static Memory Controller on Chip Select 2, Optional NAND Flash support – Static Memory Controller on Chip Select 3, Optional NAND Flash support – Static Memory Controller on Chip Select 4, Optional CompactFlashTM support – Static Memory Controller on Chip Select 5, Optional CompactFlashTM support 8.4.9 Static Memory Controller • 6 chip selects available • 16-Mbytes address space per chip select • 8- or 16-bit data bus • Word, halfword, byte transfers • Byte write or byte select lines • Programmable setup, pulse and hold time for read signals per chip select • Programmable setup, pulse and hold time for write signals per chip select • Programmable data float time per chip select • Compliant with LCD module • External wait request • Automatic switch to slow clock mode • Asynchronous read in page mode supported: page size ranges from 4 to 32 bytes SDRAM Controller • 128-Mbytes address space • Numerous configurations supported – 2K, 4K, 8K row address memory parts – SDRAM with two or four internal banks – SDRAM with 16-bit data path • Programming facilities – Word, halfword, byte access – Automatic page break when memory boundary has been reached – Multibank ping-pong access 8.4.10 39 32072C–AVR32–2010/03 AT32UC3A3/A4 – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable – Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices) Energy-saving capabilities – Self-refresh, power-down, and deep power-down modes supported – Supports mobile SDRAM devices Error detection – Refresh error interrupt SDRAM power-up initialization by software CAS latency of one, two, and three supported Auto Precharge command not used • • • • • 8.4.11 Peripheral DMA Controller • Multiple channels • Generates transfers to/from peripherals such as USART and SPI • Two address pointers/counters per channel allowing double buffering • Performance monitors to measure average and maximum transfer latency DMA Controller • 2 HSB Master Interfaces • Channels • Software and Hardware Handshaking Interfaces – 9 Hardware Handshaking Interfaces 8.4.12 • Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer • Single-block DMA Transfer • Multi-block DMA Transfer – Linked Lists – Auto-Reloading – Contiguous Blocks • DMA Controller is Always the Flow Controller • Additional Features – Scatter and Gather Operations – Channel Locking – Bus Locking – FIFO Mode – Pseudo Fly-by Operation 8.4.13 General-Purpose Input/Output Controller • • • • • Each I/O line of the GPIO features: Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line A glitch filter providing rejection of pulses shorter than one clock cycle Input visibility and output control Multiplexing of up to four peripheral functions per I/O line Programmable internal pull-up resistor Serial Peripheral Interface • Compatible with an embedded 32-bit microcontroller • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals 40 32072C–AVR32–2010/03 AT32UC3A3/A4 – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors – External co-processors • Master or Slave Serial Peripheral Bus Interface – 4 - to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Connection to Peripheral DMA Controller channel capabilities optimizes data transfers – One channel for the receiver, one channel for the transmitter – Next buffer support – Four character FIFO in reception 8.4.14 Two-Wire Slave Interface • Compatible with I²C standard – 100 and 400 kbit/s transfer speeds – 7 and 10-bit and General Call addressing Compatible with SMBus standard – Hardware Packet Error Checking (CRC) generation and verification with ACK response – SMBALERT interface – 25 ms clock low timeout delay – 25 ms slave cumulative clock low extend time Compatible with PMBus DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer 32-bit Peripheral Bus interface for configuration of the interface • • • • • • 8.4.15 Two-Wire Master Interface • Compatible with I²C standard – Multi-master support – 100 and 400 kbit/s transfer speeds – 7- and 10-bit and General Call addressing • Compatible with SMBus standard – Hardware Packet Error Checking (CRC) generation and verification with ACK control – SMBus ALERT interface – 25 ms clock low timeout delay – 10 ms master cumulative clock low extend time – 25 ms slave cumulative clock low extend time 41 32072C–AVR32–2010/03 AT32UC3A3/A4 • • • • • 8.4.16 Compatible with PMBus Compatible with Atmel Two-Wire Interface Serial Memories DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer Synchronous Serial Controller • Provides serial synchronous communication links used in audio and telecom applications • Independent receiver and transmitter, common clock divider • Interfaced with two Peripheral DMA Controller channels to reduce processor overhead • Configurable frame sync and data length • Receiver and transmitter can be configured to start automatically or on detection of different events on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 8.4.17 Universal Synchronous Asynchronous Receiver Transmitter • Programmable Baud Rate Generator • 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications – 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode – Parity Generation and Error Detection – Framing Error Detection, Overrun Error Detection – MSB- or LSB-first – Optional Break Generation and Detection – By 8 or by 16 Over-sampling Receiver Frequency – Optional Hardware Handshaking RTS-CTS – Optional Modem Signal Management DTR-DSR-DCD-RI – Receiver Time-out and Transmitter Timeguard – Optional Multidrop Mode with Address Generation and Detection RS485 with Driver Control Signal ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards – NACK Handling, Error Counter with Repetition and Iteration Limit IrDA Modulation and Demodulation – Communication at up to 115.2 Kbps SPI Mode – Master or Slave – Serial Clock Programmable Phase and Polarity – SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4 LIN Mode – Compliant with LIN 1.3 and LIN 2.0 specifications – Master or Slave – Processing of frames with up to 256 data bytes – Response Data length can be configurable or defined automatically by the Identifier – Self synchronization in Slave node configuration – Automatic processing and verification of the “Synch Break” and the “Synch Field” – The “Synch Break” is detected even if it is partially superimposed with a data byte – Automatic Identifier parity calculation/sending and verification – Parity sending and verification can be disabled – Automatic Checksum calculation/sending and verification – Checksum sending and verification can be disabled – Support both “Classic” and “Enhanced” checksum types • • • • • 42 32072C–AVR32–2010/03 AT32UC3A3/A4 – Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Supports Connection of Two Peripheral DMA Controller Channels (PDCA) – Offers Buffer Transfer without Processor Intervention 8.4.18 USB On-The-Go Interface • Compatible with the USB 2.0 specification • Supports High (480Mbit/s), Full (12Mbit/s) and Low (1.5Mbit/s) speed communication and On• • • • • • The-Go eight pipes/endpoints 2368 of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint) Flexible Pipe/Endpoint configuration and management with dedicated DMA channels On-Chip UTMI transceiver including Pull-Ups/Pull-downs On-Chip OTG pad including VBUS analog comparator 8.4.19 Timer/Counter • Three 16-bit Timer Counter channels • A wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse width modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Internal interrupt signal • Two global registers that act on all three TC channels 8.4.20 Analog-to-Digital Converter • Integrated multiplexer offering up to eight independent analog inputs • Individual enable and disable of each channel • Hardware or software trigger – External trigger pin – Timer counter outputs (corresponding TIOA trigger) • Peripheral DMA Controller support • Possibility of ADC timings configuration • Sleep mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 43 32072C–AVR32–2010/03 AT32UC3A3/A4 8.4.21 HSB Bus Performance Monitor • Allows performance monitoring of High Speed Bus master interfaces – Up to 4 masters can be monitored – Peripheral Bus access to monitor registers • The following is monitored – Data transfer cycles – Bus stall cycles – Maximum access latency for a single transfer • Automatic handling of event overflow 8.4.22 Multimedia Card Interface • Compatible with Multimedia Card specification version 4.3 • Compatible with SD Memory Card specification version 2.0 • Compatible with SDIO specification version 1.1 • Compatible with CE-ATA specification 1.1 • Cards clock rate up to master clock divided by two • Boot Operation Mode support • High Speed mode support • Embedded power management to slow down clock rate when not used • Supports 2 Slots • • • • • – Each slot for either a MultiMediaCard bus (up to 30 cards) or an SD Memory Card Support for stream, block and multi-block data read and write Supports connection to DMA Controller – Minimizes processor intervention for large buffer transfers Built in FIFO (from 16 to 256 bytes) with large memory aperture supporting incremental access Support for CE-ATA completion cignal disable command Protection against unexpected modification on-the-Fly of the configuration registers 8.4.23 Error Corrected Code Controller • Hardware Error Corrected Code Generation with two methods : – Hamming code detection and correction by software (ECC-H) – Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS) Supports NAND Flash and SmartMedia™ devices with 8- or 16-bit data path for ECC-H, and with 8-bit data path for ECC-RS Supports NAND Flash and SmartMedia™ with page sizes of 528, 1056, 2112, and 4224 bytes (specified by software) ECC_H supports : – One bit correction per page of 512,1024,2048, or 4096 bytes – One bit correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, or 4096 bytes – One bit correction per sector of 256 bytes of data for a page size of 512, 1024, 2048, or 4096 bytes ECC_RS supports : – 4 errors correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, and 4096 bytes with 8-bit data path • • • • 44 32072C–AVR32–2010/03 AT32UC3A3/A4 8.4.24 Advanced Encryption Standart • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit/192-bit/256-bit cryptographic key • 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key • Support of the five standard modes of operation specified in the NIST Special Publication 80038A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques: – Electronic Code Book (ECB) – Cipher Block Chaining (CBC) – Cipher Feedback (CFB) – Output Feedback (OFB) – Counter (CTR) 8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode Last output data mode allows optimized Message Authentication Code (MAC) generation Hardware counter measures against differential power analysis attacks Connection to DMA Controller capabilities optimizes data transfers for all operating modes • • • • 8.4.25 Audio Bitstream DAC • Digital Stereo DAC • Oversampled D/A conversion architecture – Oversampling ratio fixed 128x – FIR equalization filter – Digital interpolation filter: Comb4 – 3rd Order Sigma-Delta D/A converters • Digital bitstream outputs • Parallel interface • Connected to DMA Controller for background transfer without CPU intervention 8.4.26 On-Chip Debug • • • • • • • • Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ JTAG access to all on-chip debug functions Advanced program, data, ownership, and watchpoint trace supported NanoTrace JTAG-based trace access Auxiliary port for high-speed trace information Hardware support for 6 program and 2 data breakpoints Unlimited number of software breakpoints supported Automatic CRC check of memory regions 8.4.27 JTAG and Boundary Scan • IEEE1149.1 compliant JTAG Interface • Boundary-Scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface • 45 32072C–AVR32–2010/03 AT32UC3A3/A4 9. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after powerup is controlled by the Power Manager. For specific details, refer to Section 9. ”Power Manager (PM)” on page 39. 9.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system receives a clock with the same frequency as the internal RC Oscillator. 9.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 46 32072C–AVR32–2010/03 AT32UC3A3/A4 10. Electrical Characteristics 10.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V Total DC Output Current on all I/O Pin for TQFP144 package ................................................. 370 mA for TFBGA144 package ............................................... 370 mA 10.2 DC Characteristics The following characteristics are applicable to the operating temperature range: T A = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up toTJ = 100°C. Table 10-1. Symbol VVDDCORE VVDDIO VIL VIH DC Characteristics Parameter DC Supply Core DC Supply Peripheral I/Os Input Low-level Voltage Input High-level Voltage IOL = -2mA for Pin drive x1 IOL = -4mA for Pin drive x2 IOL = -8mA for Pin drive x3 IOL = 2mA for Pin drive x1 IOL = 4mA for Pin drive x2 IOL = 8mA for Pin drive x3 Pullup resistors disabled 7 9 15 25 2.0 4.0 8.0 On VVDDIN = 3.3V, CPU in static mode TA = 25°C TA = 85°C 30 175 VVDDIO -0.4 1 Conditions Min. 1.65 3.0 -0.3 2.0 Typ. Max. 1.95 3.6 +0.8 VVDDIO +0.3 0.4 Unit V V V V VOL Output Low-level Voltage V VOH ILEAK CIN RPULLUP Output High-level Voltage Input Leakage Current Input Capacitance Pull-up Resistance Output Current Pin drive 1x Pin drive 2x Pin drive 3x See Table 10-2 Static Current V µA pF KΩ IO mA µA µA ISC 47 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 10-2. PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 Pins Drive Capabilities Drive 3x 1x 1x 1x 1x 1x 1x 1x 3x 2x 2x 2x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x PIN PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 Drive 1x 1x 1x 1x 1x 2x 1x 1x 1x 1x 1x 1x 1x 1x 1x 3x 1x 3x 2x 2x 2x 1x PIN PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 P1x0 P1x1 P1x2 P1x3 P1x4 P1x5 Drive 1x 1x 1x 1x 1x 1x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x PIN P1x6 P1x7 P1x8 P1x9 P2x0 P21x P2x2 P2x3 P2x4 P2x5 P2x6 P2x7 P2x8 P2x9 P3x0 P31x P32x P3x3 P3x4 P3x5 P3x6 P3x7 Drive 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x PIN P3x8 P3x9 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 Drive 2x 2x 2x 2x 2x 2x 2x 3x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 48 32072C–AVR32–2010/03 AT32UC3A3/A4 10.3 Regulator characteristics Electrical Characteristics Parameter Supply voltage (input) Supply voltage (output) Conditions Min. 2.7 1.81 Typ. 3.3 1.85 Max. 3.6 1.89 Unit V V Table 10-3. Symbol VVDDIN VVDDCORE Table 10-4. Symbol CIN1 CIN2 COUT1 COUT2 Decoupling Requirements Parameter Input Regulator Capacitor 1 Input Regulator Capacitor 2 Output Regulator Capacitor 1 Output Regulator Capacitor 2 Conditions Typ. 1 4.7 470 2.2 Technology NPO X7R NPO X7R Unit nF µF pF µF 10.4 10.4.1 Analog characteristics ADC Electrical Characteristics Parameter Analog Power Supply Conditions Min. 3.0 Typ. Max. 3.6 Unit V Table 10-5. Symbol VVDDANA Table 10-6. Symbol CVDDANA Decoupling Requirements Parameter Power Supply Capacitor Conditions Typ. 100 Technology NPO Unit nF 10.4.2 BOD BOD Level Values Parameter Value 00 1111b 01 0111b Conditions Min. Typ. 1.78 1.69 1.60 1.51 Max. Unit V V V V Table 10-7. Symbol BODLEVEL 01 1111b 10 0111b Table 10-7 describes the values of the BODLEVEL field in the flash FGPFR register. Table 10-8. Symbol TBOD BOD Timing Parameter Minimum time with VDDCORE < VBOD to detect power failure Conditions Falling VDDCORE from 1.8V to 1.1V Min. Typ. 300 Max. 800 Unit ns 49 32072C–AVR32–2010/03 AT32UC3A3/A4 10.4.3 Reset Sequence Electrical Characteristics Parameter VDDCORE rise rate to ensure poweron-reset VDDCORE fall rate to ensure poweron-reset Rising threshold voltage: voltage up to which device is kept under reset by POR on rising VDDCORE Falling threshold voltage: voltage when POR resets device on falling VDDCORE On falling VDDCORE, voltage must go down to this value before supply can rise again to ensure reset signal is released at VPOR+ Minimum time with VDDCORE < VPORTime for reset signal to be propagated to system Time for Cold System Startup: Time for CPU to fetch its first instruction (RCosc not calibrated) Time for Hot System Startup: Time for CPU to fetch its first instruction (RCosc calibrated) 480 Rising VDDCORE: VRESTART -> VPOR+ Conditions Min. 0.01 0.01 400 Typ. Max. Unit V/ms V/ms Table 10-9. Symbol VDDRR VDDFR VPOR+ 1.35 1.5 1.6 V VPOR- Falling VDDCORE: 1.8V -> VPOR+ 1.25 1.3 1.4 V VRESTART Falling VDDCORE: 1.8V -> VRESTART -0.1 0.5 V TPOR TRST Falling VDDCORE: 1.8V -> 1.1V 15 200 400 µs µs TSSU1 960 µs TSSU2 420 µs 50 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 10-1. MCU Cold Start-Up RESET_N tied to VDDIN VDDCORE VPORVRESTART VPOR+ RESET_N Internal POR Reset TPOR Internal MCU Reset TRST TSSU1 Figure 10-2. MCU Cold Start-Up RESET_N Externally Driven VDDCORE VPORVRESTART VPOR+ RESET_N Internal POR Reset TPOR Internal MCU Reset TRST TSSU1 Figure 10-3. MCU Hot Start-Up VDDCORE RESET_N BOD Reset WDT Reset TSSU2 Internal MCU Reset 51 32072C–AVR32–2010/03 AT32UC3A3/A4 10.4.4 RESET_N Characteristics Table 10-10. RESET_N Waveform Parameters Symbol tRESET Parameter RESET_N minimum pulse width Conditions Min. 10 Typ. Max. Unit ns 52 32072C–AVR32–2010/03 AT32UC3A3/A4 10.5 Power Consumption The values in Table 10-11 and Table 10-12 on page 54 are measured values of power consumption with operating conditions as follows: •VDDIO = 3.3V •TA = 25°C •I/Os are configured in input, pull-up enabled. Figure 10-4. Measurement Setup VDDANA Amp0 VDDIO Amp1 VDDIN Internal Voltage Regulator VDDCORE GNDCORE GNDPLL 53 32072C–AVR32–2010/03 AT32UC3A3/A4 These figures represent the power consumption measured on the power supplies. Table 10-11. Power Consumption for Different Modes Mode Conditions(1) CPU running from flash CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0: external clock (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated GPIOs on internal pull-up JTAG unconnected with ext pull-up TA = 25 °C CPU is in static mode GPIOs on internal pull-up All peripheral clocks de-activated DM and DP pins connected to ground XIN0, Xin1 and XIN32 are stopped f = 12 MHz f = 24 MHz f = 36 MHz f = 50 MHz f = 60 MHz Typ. 10 18 27 34 42 Unit mA mA mA mA mA Active on Amp0 0 µA Static on Amp1