AT32UC3A3256S_2

Features • High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing up to 1.51DMIPS/MHz • Up to 92DMIPS Running at 66MHz from Flash (1 Wait-State) • Up to 54 DMIPS Running at 36MHz from Flash (0 Wait-State) – Memory Protection Unit Multi-Layer Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral Communication – 4 generic DMA Channels for High Bandwidth Data Paths Internal High-Speed Flash – 256KBytes, 128KBytes, 64KBytes versions – Single-Cycle Flash Access up to 36MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4 ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM – 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus – 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority System Functions – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), – Watchdog Timer, Real-Time Clock Timer External Memories – Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash – Up to 66 MHz External Storage device support – MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1 – CE-ATA V1.1, FastSD, SmartMedia, Compact Flash – Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities Universal Serial Bus (USB) – High-Speed USB (480Mbit/s) Device/MiniHost with On-The-Go (OTG) – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-Chip Transceivers Including Pull-Ups One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Two Three-Channel 16-bit Timer/Counter (TC) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Fractionnal Baudrate Generator • 32-bit AVR® Microcontroller AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 AT32UC3A4256S AT32UC3A4256 AT32UC3A4128S AT32UC3A4128 AT32UC3A464S AT32UC3A464 • • • • • • Preliminary • • • • • 32072C–03/2010 AT32UC3A3/A4 – Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible 16-bit Stereo Audio Bitstream – Sample Rate Up to 50 KHz On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace 110 General Purpose Input/Output (GPIOs) – Standard or High Speed mode – Toggle capability: up to 66MHz Packages – 144-ball TFBGA, 11x11 mm, pitch 0.8 mm – 144-pin LQFP, 22x22 mm, pitch 0.5 mm – 100-ball VFBGA, 7x7 mm, pitch 0.65 mm Single 3.3V Power Supply • • • • • • • • 2 32072C–AVR32–2010/03 AT32UC3A3/A4 1. Description The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The AT32UC3A3/A4 incorporates on-chip Flash and SRAM memories for secure and fast access. 64 KBytes of SRAM are directly coupled to the AVR32 UC for performances optimization. Two blocks of 32 Kbytes SRAM are independently attached to the High Speed Bus Matrix, allowing real ping-pong management. The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit channels are combined to operate as 32-bit channels. The AT32UC3A3/A4 also features many communication interfaces for communication intensive applications like UART, SPI or TWI. Additionally, a flexible Synchronous Serial Controller (SSC) is available. The SSC provides easy access to serial communication protocols and audio standards like I2S. The AT32UC3A3/A4 includes a powerfull External Bus Interface to interface all standard memory device like SRAM, SDRAM, NAND Flash or parallel interfaces like LCD Module. The peripheral set includes a High Speed MCI for SDIO/SD/MMC and a hardware encryption module based on AES algorithm. The device embeds a 10-bit ADC and a Digital Audio bistream DAC. The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal features (AES, internal memories). The High-Speed (480MBit/s) USB 2.0 Device and Host interface supports several USB Classes at the same time thanks to the rich Endpoint configuration. The On-The-Go (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. This periphal has its own dedicated DMA and is perfect for Mass Storage application. AT32UC3A3/A4 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. 3 32072C–AVR32–2010/03 AT32UC3A3/A4 2. Overview 2.1 Block Diagram Figure 2-1. TCK TDO TDI TMS Block Diagram PBB ID VBOF FLASH CONTROLLER USB_VBIAS USB_VBUS DMFS, DMHS DPFS, DPHS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N NEXUS CLASS 2+ OCD MEMORY PROTECTION UNIT MEMORY INTERFACE JTAG INTERFACE AVR32 UC CPU INSTR INTERFACE DATA INTERFACE LOCAL BUS INTERFACE FAST GPIO 64 KB SRAM USB HS INTERFACE DMA 32KB RAM 32KB RAM HRAM0/1 S M S S M M M M M S S 256/128/64 KB FLASH DMACA GENERAL PURPOSE IOs S EXTERNAL BUS INTERFACE (SDRAM, STATIC MEMORY, COMPACT FLASH & NAND FLASH) HIGH SPEED BUS MATRIX DATA[15..0] ADDR[23..0] NCS[5..0] NRD NWAIT NWE0 NWE1 NWE3 RAS CAS SDA10 SDCK SDCKE SDWE CFCE1 CFCE2 CFRW NANDOE NANDWE AES DMA S S CONFIGURATION S REGISTERS BUS M PB HSB HSB HSB-PB BRIDGE B HSB-PB BRIDGE A PB PBA PERIPHERAL DMA CONTROLLER CLK DMA CMD[1..0] PA PB PC PX DATA[15..0] PDC GENERAL PURPOSE IOs MULTIMEDIA CARD & MEMORY STICK INTERFACE USART1 RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS PDC EXTINT[7..0] SCAN[7..0] NMI EXTERNAL INTERRUPT CONTROLLER REAL TIME COUNTER PDC INTERRUPT CONTROLLER PA PB PC PX USART0 USART2 RXD USART3 TXD CLK VDDIN GNDCORE VDDCORE 1V8 Regulator SERIAL PERIPHERAL INTERFACE 0/1 SYNCHRONOUS SERIAL CONTROLLER SPCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA WATCHDOG TIMER PDC 115 kHz RCSYS XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 POWER MANAGER PDC PDC 32 KHz OSC OSC0 OSC1 PLL0 PLL1 TWCK CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER TWO-WIRE INTERFACE 0/1 TWD TWALM ANALOG TO DIGITAL CONVERTER AUDIO BITSTREAM DAC PDC AD[7..0] PDC DATA[1..0] DATAN[1..0] RESET_N GCLK[3..0] A[2..0] B[2..0] CLK[2..0] TIMER/COUNTER 0/1 4 32072C–AVR32–2010/03 AT32UC3A3/A4 2.2 Configuration Summary The table below lists all AT32UC3A3 memory and package configurations: Table 2-1. Device AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 AT32UC3A4256S AT32UC3A4256 AT32UC3A4128S AT32UC3A4128 AT32UC3A464S AT32UC3A464 Memory and Package Configurations Flash 256KB 256KB 128KB 128KB 64KB 64KB 256KB 256KB 128KB 128KB 64KB 64KB SRAM 128KB 128KB 128KB 128KB 128KB 128KB 128KB 128KB 128KB 128KB 128KB 128KB AES Yes No Yes No Yes No Yes No Yes No Yes No Package 144-ball TFBGA/ 144-lead LQFP 144-ball TFBGA/ 144-lead LQFP 144-ball TFBGA/ 144-lead LQFP 144-ball TFBGA/ 144-lead LQFP 144-ball TFBGA/ 144-lead LQFP 144-ball TFBGA/ 144-lead LQFP 144-ball VFBGA 144-ball VFBGA 144-ball VFBGA 144-ball VFBGA 144-ball VFBGA 144-ball VFBGA 5 32072C–AVR32–2010/03 AT32UC3A3/A4 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 3-1. TFBGA144 Pinout (top view) 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12 Table 3-1. 1 A B C D E F G H J K L M PX40 PX10 PX09 PX08 PX38 PX39 PX00 PX01 PX04 PX03 PX11 PX22 TFBGA144 Package Pinout 2 PB00 PB11 PX35 PX37 VDDIO PX07 PX05 VDDIO PX02 PX44 GNDIO PX41 3 PA28 PA31 GNDIO PX36 PX54 PX06 PX59 PX58 PX34 GNDIO PX45 PX42 4 PA27 PB02 PB01 PX47 PX53 PX49 PX50 PX57 PX56 PX46 PX20 PX14 5 PB03 VDDIO PX16 PX19 VDDIO PX48 PX51 VDDIO PX55 PC00 VDDIO PX21 6 PA29 PB04 PX13 PX12 PX15 GNDIO GNDIO PC01 PA14 PX17 PX18 PX23 7 PC02 PC03 PA30 PB10 PB09 GNDIO GNDIO PA17 PA15 PX52 PX43 PX24 8 PC04 VDDIO PB08 PA02 VDDIN PA06 PA23 VDDIO PA19 PA18 VDDIN PX25 9 PC05 USB_VBIAS 10 DPHS DMFS GNDCORE 11 DMHS GNDPLL PA08 PB07 VDDCORE 12 USB_VBUS PA09 PA10 PB06 PA12 PA16 PA01 PB05 RESET_N DPFS PA26 PA25 PA04 PA24 PA21 PA20 PX27 PX26 PX32 PA11 PA07 PA05 PA03 PA22 TMS GNDIO PX28 PX31 PA13 PA00 VDDANA TDO PX29 GNDANA PX30 TCK TDI PX33 6 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 3-2. LQFP144 Pinout 108 109 73 72 144 1 Table 3-2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 LQFP144 Package Pinout 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PB02 PA27 PB01 PA28 PA31 PB00 PB11 PX16 PX13 PX12 PX19 PX40 PX10 PX35 PX47 PX15 PX48 PX53 PX49 PX36 PX37 PX54 GNDIO VDDIO 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PX09 PX08 PX38 PX39 PX06 PX07 PX00 PX59 PX58 PX05 PX01 PX04 PX34 PX02 PX03 VDDIO GNDIO PX44 PX11 PX14 PX42 PX45 PX41 PX22 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PX20 PX46 PX50 PX57 PX51 PX56 PX55 PX21 VDDIO GNDIO PX17 PX18 PX23 PX24 PX52 PX43 PX27 PX26 PX28 PX25 PX32 PX29 PX33 PX30 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PX31 PC00 PC01 PA14 PA15 GNDIO VDDIO TMS TDO RESET_N TCK TDI PA21 PA22 PA23 PA24 PA20 PA19 PA18 PA17 GNDANA VDDANA PA25 PA26 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PB05 PA00 PA01 PA05 PA03 PA04 PA06 PA16 PA13 VDDIO GNDIO PA12 PA07 PB06 PB07 PA11 PA08 PA10 PA09 GNDCORE VDDCORE VDDIN VDDIN GNDPLL USB_VBUS VDDIO USB_VBIAS GNDIO DMHS DPHS GNDIO DMFS DPFS VDDIO PB08 PC05 PC04 PA30 PA02 PB10 PB09 PC02 PC03 GNDIO VDDIO PB04 PA29 PB03 7 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 3-3. VFBGA100 Pinout (top view) 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 Table 3-3. 1 A B C D E F G H J K PA28 PB00 PB11 PX12 PA02/PX47 (1) VFBGA100 Package Pinout 2 PA27 PB01 PA31 PX10 GNDIO VDDIO PX01 PX21 PX24 PX27 3 PB04 PB02 GNDIO PX13 PX08 PX06 PX02 GNDIO PX26 PX28 4 PA30 PA29 PB03 PX16/PX53 (1) 5 PC02 VDDIO PB09 PB10 VDDIO GNDIO PX30 PX31 VDDIO PC00/PX14(1) 6 PC03 VDDIO PB08 PB07 GNDIO VDDIO PA23/PX46(1) PA22/PX20(1) 7 PC05 PC04 USB_VBIAS 8 DPHS DPFS GNDIO PA09 PA06/PA13 (1) 9 DMHS DMFS PA11 VDDIN PA04 PA03 PA05 PA20/PX18(1) 10 USB_VBUS GNDPLL PA10 VDDIN VDDCORE GNDCORE PA01/PA17(1) PA07/PA19(1) PA24/PX17(1) PA21/PX22(1) PB06 PA16 PA26/PB05(1) PA12/PA25(1) PX09 PX07 PX00 PX25 PX29 PX15/PX32(1) PX19/PX59(1) PA08 PA00/PA18(1) PX05 PX04 PX03 PX23 TMS PA15/PX45(1) PA14/PX11(1) GNDANA TDO TDI VDDANA PC01 RESET_N TCK Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 8 32072C–AVR32–2010/03 AT32UC3A3/A4 3.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C, or D. The following table defines how the I/O lines on the peripherals A, B, C, or D are multiplexed by the GPIO. Table 3-4. TFBGA GPIO Controller Function Multiplexing QFP VFBGA 144 G11 G12 D8 G10 F9 F10 F8 E10 C11 B12 C12 D10 E12 F11 J6 J7 F12 H7 K8 J8 J9 H9 H10 G8 G9 E9 D9 A4 A3 A6 C7 B3 A2 C4 144 122 123 15 125 126 124 127 133 137 139 138 136 132 129 100 101 128 116 115 114 113 109 110 111 112 119 120 26 28 23 14 29 30 27 100 G8 (1) (1) Pin PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 GPIO Pin GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 Function A USART0 - RTS USART0 - CTS USART0 - CLK USART0 - RXD USART0 - TXD USART1 - RXD USART1 - TXD SPI0 - NPCS[3] SPI0 - SPCK SPI0 - NPCS[0] SPI0 - MOSI SPI0 - MISO USART1 - CTS USART1 - RTS SPI0 - NPCS[1] MCI - CMD[1] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] EIC - NMI ADC - AD[0] ADC - AD[1] ADC - AD[2] ADC - AD[3] TWIMS0 - TWD TWIMS0 - TWCK MCI - CLK MCI - CMD[0] MCI - DATA[0] MCI - DATA[1] MCI - DATA[2] MCI - DATA[3] MCI - DATA[4] Function B TC0 - CLK1 TC0 - A1 TC0 - B1 EIC - EXTINT[4] EIC - EXTINT[5] TC1 - CLK0 TC1 - CLK1 ABDAC - DATAN[0] ABDAC - DATA[0] EIC - EXTINT[6] USB - VBOF USB - ID SPI0 - NPCS[2] SPI0 - NPCS[1] TWIMS0 - TWALM SPI1 - SPCK SPI1 - MOSI SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - MISO SSC - RX_FRAME_SYNC Function C SPI1 - NPCS[3] USART2 - RTS SPI0 - NPCS[0] ABDAC - DATA[0] ABDAC - DATAN[0] USB - ID USB - VBOF USART1 - CLK TC1 - B1 TC1 - A1 TC1 - B0 TC1 - A2 TC1 - A0 EIC - EXTINT[7] TWIMS1 - TWCK TWIMS1 - TWD TC1 - CLK2 ADC - AD[7] ADC - AD[6] ADC - AD[5] ADC - AD[4] USB - ID USB - VBOF ABDAC - DATA[1] ABDAC - DATAN[1] USART1 - DCD USART1 - DSR USART3 - RTS USART3 - CTS TC0 - CLK0 DMACA - DMAACK[0] DMACA - DMARQ[0] Function D G10 E1 (1) F9 E9 G9 E8 (1) (1) H10 F8 D8 C10 C9 G7 E8 (1) (1) (1) K7 J7 (1) E7 G10 G8 (1) (1) (1) H10 H9 (1) (1) K10 H6 EIC - EXTINT[0] EIC - EXTINT[1] EIC - EXTINT[2] EIC - EXTINT[3] TWIMS1 - TWALM USART2 - CTS SSC - RX_DATA SSC - RX_CLOCK USART3 - TXD USART3 - CLK USART2 - RXD USART2 - TXD ABDAC - DATA[1] (1) (1) (1) G6 J10 G7 (1) F7 ) A2 A1 B4 A4 C2 B1 B2 (1) MSI - SCLK MSI - BS MSI - DATA[0] MSI - DATA[1] MSI - DATA[2] MSI - DATA[3] MSI - INS ADC - TRIGGER EIC - SCAN[0] 9 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-4. B4 A5 B6 H12 D12 D11 C8 E7 D7 B2 K5 H6 A7 B7 A8 A9 G1 H1 J2 K1 J1 G2 F3 F2 D1 C1 B1 L1 D6 C6 M4 E6 C5 K6 L6 D5 L4 M5 M1 GPIO Controller Function Multiplexing 25 24 22 121 134 135 11 17 16 31 98 99 18 19 13 12 55 59 62 63 60 58 53 54 50 49 37 67 34 33 68 40 32 83 84 35 73 80 72 B3 C4 A3 F7(1) D7 D6 C6 C5 D5 C1 K5(1) K6 A5 A6 B7 A7 G4 G2 G3 J1 H1 G1 F3 F4 E3 E4 D2 K7(1) D1 D3 K5(1) K4(1) D4(1) J10(1) H9(1) F1(1) H6(1) H2 K10(1) PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 68 GPIO 69 GPIO 70 GPIO 71 GPIO 72 GPIO 73 EBI - DATA[10] EBI - DATA[9] EBI - DATA[8] EBI - DATA[7] EBI - DATA[6] EBI - DATA[5] EBI - DATA[4] EBI - DATA[3] EBI - DATA[2] EBI - DATA[1] EBI - DATA[0] EBI - NWE1 EBI - NWE0 EBI - NRD EBI - NCS[1] EBI - ADDR[19] EBI - ADDR[18] EBI - ADDR[17] EBI - ADDR[16] EBI - ADDR[15] EBI - ADDR[14] EBI - ADDR[13] EBI - ADDR[12] USART3 - RTS USART3 - CTS DMACA - DMARQ[1] DMACA - DMAACK[1] EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] USART0 - RXD USART0 - TXD USART0 - CTS USART0 - RTS USART1 - RXD USART1 - TXD USART1 - CTS USART1 - RTS USART3 - RXD USART3 - TXD USART2 - RXD USART2 - TXD USART2 - CTS USART2 - RTS MCI - CLK MCI - CLK TC0 - A0 TC0 - B0 TC0 - A1 TC0 - B1 TC0 - A2 TC0 - B2 TC0 - CLK0 TC0 - CLK1 TC0 - CLK2 USART1 - RI USART1 - DTR PM - GCLK[0] MCI - DATA[5] MCI - DATA[6] MCI - DATA[7] USB - ID USB - VBOF SPI1 - SPCK SPI1 - MISO SPI1 - NPCS[0] SPI1 - MOSI USART1 - RXD ABDAC - DATAN[1] USART2 - CLK USART3 - RXD TC0 - A0 TC0 - B0 SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC - RX_FRAME_SYNC SSC - TX_FRAME_SYNC EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] EBI - NCS[4] EBI - NCS[5] PM - GCLK[1] 10 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-4. M6 M7 M8 L9 K9 L10 K11 M11 M10 M9 M12 J3 C2 D3 D2 E1 F1 A1 M2 M3 L7 K2 L3 K4 D4 F5 F4 G4 G5 K7 E4 E3 J5 J4 H4 H3 G3 GPIO Controller Function Multiplexing 85 86 92 90 89 91 94 96 97 93 95 61 38 44 45 51 52 36 71 69 88 66 70 74 39 41 43 75 77 87 42 46 79 78 76 57 56 F1(1) D4(1) J7(1) G6(1) E1(1) K1 J2 H4 J3 K2 K3 J4 G5 H5 K4(1) PX23 PX24 PX25 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 GPIO 74 GPIO 75 GPIO 76 GPIO 77 GPIO 78 GPIO 79 GPIO 80 GPIO 81 GPIO 82 GPIO 83 GPIO 84 GPIO 85 GPIO 86 GPIO 87 GPIO 88 GPIO 89 GPIO 90 GPIO 91 GPIO 92 GPIO 93 GPIO 94 GPIO 95 GPIO 96 GPIO 97 GPIO 98 GPIO 99 GPIO 100 GPIO 101 GPIO 102 GPIO 103 GPIO 104 GPIO 105 GPIO 106 GPIO 107 GPIO 108 GPIO 109 GPIO 110 EBI - CAS EBI - RAS EBI - SDA10 EBI - SDWE EBI - SDCK EBI - SDCKE EBI - NANDOE EBI - ADDR[23] EBI - CFRNW EBI - CFCE2 EBI - CFCE1 EBI - NCS[3] EBI - NCS[2] EBI - NWAIT EBI - ADDR[22] EBI - ADDR[21] EBI - ADDR[20] EBI - NCS[0] EBI - NANDWE USART3 - TXD EIC - SCAN[3] EIC - SCAN[2] EIC - SCAN[1] EIC - SCAN[0] ADC - TRIGGER USB - VBOF USB - ID TC1 - B2 DMACA - DMAACK[0] DMACA - DMARQ[0] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] MCI - DATA[15] MCI - DATA[14] MCI - DATA[13] MCI - DATA[12] USART2 - RXD USART2 - TXD USART3 - RXD USART3 - TXD MCI - CMD[1] USART1 - RI USART1 - DTR EBI - ADDR[11] EBI - ADDR[10] EBI - ADDR[9] EBI - ADDR[8] EBI - ADDR[7] EBI - ADDR[6] EBI - ADDR[5] EBI - ADDR[4] EBI - ADDR[3] EBI - ADDR[2] EBI - ADDR[1] EBI - ADDR[0] EBI - DATA[15] EBI - DATA[14] EBI - DATA[13] EBI - DATA[12] EBI - DATA[11] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] SPI0 - MISO SPI0 - MOSI SPI0 - SPCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] SPI0 - NPCS[3] SPI1 - MISO SPI1 - MOSI SPI1 - SPCK SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] MCI - CLK PM - GCLK[0] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] USART1 - DCD USART1 - DSR SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC - RX_FRAME_SYNC SSC - TX_FRAME_SYNC SSC - RX_CLOCK Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 11 32072C–AVR32–2010/03 AT32UC3A3/A4 3.2.1 Table 3-5. Oscillator Pinout Oscillator Pinout QFP144 18 19 13 12 98 99 Note: VFBGA100 A5 A6 B7 A7 K5 (1) TFBGA144 A7 B7 A8 A9 K5 H6 Pin name PC02 PC03 PC04 PC05 PC00 PC01 Oscillator pin XIN0 XOUT0 XIN1 XIN1 XIN32 XOUT32 K6 1. This ball is physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 3.2.2 Table 3-6. JTAG port connections JTAG Pinout QFP144 107 108 105 104 VFBGA100 K9 K8 J8 H7 Pin name TCK TDI TDO TMS JTAG pin TCK TDI TDO TMS TFBGA144 K12 L12 J11 J10 3.2.3 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespective of the GPIO configuration. Three differents OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 3-7. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] MSEO[1] MSEO[0] MCKO EVTO_N Nexus OCD AUX port connections AXS=0 PB05 PA00 PA01 PA03 PA16 PA13 PA12 PA10 PA11 PB07 PB06 AXS=1 PA08 PX56 PX57 PX58 PA24 PA23 PA22 PA07 PX55 PX00 PB06 AXS=2 PX00 PX06 PX05 PX04 PX03 PX02 PX01 PX08 PX07 PB09 PB06 12 32072C–AVR32–2010/03 AT32UC3A3/A4 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-8. Signal Name Signal Description List Function Power Type Active Level Comments VDDIO VDDANA VDDIN VDDCORE GNDANA GNDIO GNDCORE GNDPLL I/O Power Supply Analog Power Supply Voltage Regulator Input Supply Voltage Regulator Output for Digital Supply Analog Ground I/O Ground Digital Ground PLL Ground Power Power Power Power Output Ground Ground Ground Ground Clocks, Oscillators, and PLL’s 3.0 to 3.6V 3.0 to 3.6V 3.0 to 3.6V 1.65 to 1.95 V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG Analog Analog TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input Auxiliary Port - AUX MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Output Output Power Manager - PM Low Low GCLK[3:0] Generic Clock Pins Output 13 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-8. Signal Name RESET_N Signal Description List Function Reset Pin Type Input DMA Controller - DMACA (optional) Active Level Low Comments DMAACK[1:0] DMARQ[1:0] DMA Acknowledge DMA Requests Output Input External Interrupt Controller - EIC EXTINT[7:0] SCAN[7:0] NMI External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin Input Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] PB[11:0] PC[5:0] PX[59:0] Parallel I/O Controller GPIO port A Parallel I/O Controller GPIO port B Parallel I/O Controller GPIO port C Parallel I/O Controller GPIO port X I/O I/O I/O I/O External Bus Interface - EBI ADDR[23:0] CAS CFCE1 CFCE2 CFRNW DATA[15:0] NANDOE NANDWE NCS[5:0] NRD NWAIT NWE0 NWE1 RAS Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Row Signal Output Output Output Output Output I/O Output Output Output Output Input Output Output Output Low Low Low Low Low Low Low Low Low Low Low 14 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-8. Signal Name SDA10 SDCK SDCKE SDWE Signal Description List Function SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Write Enable Type Output Output Output Output MultiMedia Card Interface - MCI Low Active Level Comments CLK CMD[1:0] DATA[15:0] Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O Memory Stick Interface - MSI SCLK BS DATA[3:0] Memory Stick Clock Memory Stick Command Multimedia Card Data Output I/O I/O Serial Peripheral Interface - SPI0, SPI1 MISO MOSI NPCS[3:0] SPCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TC0, TC1 A0 A1 A2 Channel 0 Line A Channel 1 Line A Channel 2 Line A I/O I/O I/O Low 15 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-8. Signal Name B0 B1 B2 CLK0 CLK1 CLK2 Signal Description List Function Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O I/O I/O Input Input Input Active Level Comments Two-wire Interface - TWI0, TWI1 TWCK TWD TWALM Serial Clock Serial Data SMBALERT signal I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS DCD DSR DTR RI RTS RXD TXD Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Transmit Data Output Input Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Audio Bitstream DAC (ABDAC) DATA0-DATA1 DATAN0-DATAN1 D/A Data out D/A Data inverted out Output Output Universal Serial Bus Device - USB DMFS DPFS USB Full Speed Data USB Full Speed Data + Analog Analog I/O Input Only USART1 Only USART1 Only USART1 Only USART1 16 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 3-8. Signal Name DMHS DPHS Signal Description List Function USB High Speed Data USB High Speed Data + Type Analog Analog Connect to the ground through a 6810 ohms (+/- 1%) resistor in parallel with a 10pf capacitor. If USB hi-speed feature is not required, leave this pin unconnected to save power Active Level Comments USB_VBIAS USB VBIAS reference Analog USB_VBUS VBOF ID USB VBUS for OTG feature USB VBUS on/off bus power control port ID Pin fo the USB bus Output Output Input 17 32072C–AVR32–2010/03 AT32UC3A3/A4 3.4 3.4.1 I/O Line Considerations JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 3.4.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 3.4.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 3.4.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset State” of the I/O Controller multiplexing tables. 18 32072C–AVR32–2010/03 AT32UC3A3/A4 3.5 3.5.1 Power Considerations Power Supplies The AT32UC3A3 has several types of power supply pins: • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC. Voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pin GNDCORE is common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pins for VDDIO are GNDIO. Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 3.5.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: • One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. • One external 2.2µF (or 3.3µF) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (1nF NPO and 4.7µF X7R). 3.3V CIN2 CIN1 VDDIN 1.8V Regulator VDDCORE 1.8V COUT2 COUT1 19 32072C–AVR32–2010/03 AT32UC3A3/A4 4. Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.1 Features • 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extention with saturating arithmetic, and a wide variety of multiply instructions • 3-stage pipeline allows one instruction per clock cycle for most instructions – Byte, halfword, word and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection – – – – – 4.2 AVR32 Architecture AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 20 32072C–AVR32–2010/03 AT32UC3A3/A4 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the Memories chapter of this data sheet. Figure 4-1 on page 22 displays the contents of AVR32UC. 21 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 4-1. Interrupt controller interface Overview of the AVR32UC CPU Reset interface OCD interface OCD system Power/ Reset control AVR32UC CPU pipeline MPU Instruction memory controller High Speed Bus master High Speed Bus Data memory controller High Speed Bus slave High Speed Bus High Speed Bus master High Speed Bus 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 4-2 on page 23 shows an overview of the AVR32UC pipeline stages. CPU Local Bus Data RAM interface CPU Local Bus master 22 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 4-2. The AVR32UC Pipeline MUL Multiply unit IF ID Regf ile Read A LU Regf ile w rite A LU unit Pref etch unit Decode unit Load-store unit LS 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.3 Java Support AVR32UC does not provide Java hardware acceleration. 4.3.4 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. 4.3.5 23 32072C–AVR32–2010/03 AT32UC3A3/A4 The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d Instructions with Unaligned Reference Support Supported alignment Word Word 4.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: • All SIMD instructions • All coprocessor instructions if no coprocessors are present • retj, incjosp, popjc, pushjc • tlbr, tlbs, tlbw • cache 4.3.7 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 24 32072C–AVR32–2010/03 AT32UC3A3/A4 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit 0 Bit 31 The AVR32UC Register File INT0 Bit 31 Bit 0 Supervisor Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 Secure Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 4.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4 on page 25 and Figure 4-5 on page 26. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 4-4. Bit 31 The Status Register High Halfword Bit 16 - LC 1 0 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Reserved 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 25 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 4-5. Bit 15 The Status Register Low Halfword Bit 0 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 4.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2 on page 26. Table 4-2. Priority 1 2 3 4 5 6 N/A N/A Overview of Execution Modes, their Priorities and Privilege Levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 4.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. 26 32072C–AVR32–2010/03 AT32UC3A3/A4 All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 4-3. Reg # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 System Registers Address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 Name SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 JAVA_LV1 JAVA_LV2 Function Status Register Exception Vector Base Address Application Call Base Address CPU Control Register Exception Cause Register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Status Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Address Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC 27 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-3. Reg # 26 27 28 29 30 31 32 33-63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 System Registers (Continued) Address 104 108 112 116 120 124 128 132-252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316 320 324 328 332 336 340 344 348 352 356 360 364 Name JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA JBCR Reserved CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 MPUPSR0 MPUPSR1 MPUPSR2 MPUPSR3 Function Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Reserved for future use Configuration register 0 Configuration register 1 Cycle Counter register Compare register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Bus Error Address Register MPU Address Register region 0 MPU Address Register region 1 MPU Address Register region 2 MPU Address Register region 3 MPU Address Register region 4 MPU Address Register region 5 MPU Address Register region 6 MPU Address Register region 7 MPU Privilege Select Register region 0 MPU Privilege Select Register region 1 MPU Privilege Select Register region 2 MPU Privilege Select Register region 3 28 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-3. Reg # 92 93 94 95 96 97 98 99 100 101 102 103-191 192-255 System Registers (Continued) Address 368 372 376 380 384 388 392 396 400 404 408 448-764 768-1020 Name MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR Reserved IMPL Function MPU Privilege Select Register region 4 MPU Privilege Select Register region 5 MPU Privilege Select Register region 6 MPU Privilege Select Register region 7 Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC MPU Access Permission Register A MPU Access Permission Register B MPU Control Register Reserved for future use IMPLEMENTATION DEFINED 4.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in Table 4-4 on page 32. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. 4.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. 29 32072C–AVR32–2010/03 AT32UC3A3/A4 The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 4.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 4-4, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete i nstruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 4.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the 30 32072C–AVR32–2010/03 AT32UC3A3/A4 status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 4.5.5 Entry Points for Events Several different event handler entry points exists. In AVR32UC, the reset address is 0x8000_0000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 4-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit. 31 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 4-4. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and Handler Addresses for Events Handler Address 0x8000_0000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal MPU Data bus Data bus External input External input External input External input External input CPU MPU MPU OCD system Instruction Instruction Instruction UNUSED Instruction Instruction CPU CPU MPU MPU MPU MPU UNUSED PC of offending instruction PC of offending instruction PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction Stored Return Address Undefined First non-completed instruction PC of offending instruction 32 32072C–AVR32–2010/03 AT32UC3A3/A4 4.6 Module Configuration All AT32UC3A3 parts implement the CPU and Architecture Revision 2. 33 32072C–AVR32–2010/03 AT32UC3A3/A4 5. Memories 5.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • 0 wait state access at up to 36MHz in worst case conditions • 1 wait state access at up to 66MHz in worst case conditions • Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access • Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation • 100 000 write cycles, 15-year data retention capability • Sector lock capabilities, Bootloader protection, Security Bit • 32 fuses, preserved during Chip Erase • User page for data to be preserved during Chip Erase • Internal High-Speed SRAM – 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud (HSB) matrix – 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix 5.2 Physical Memory Map The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1. AT32UC3A3A4 Physical Memory Map Size Device Start Address AT32UC3A3256S AT32UC3A3256 AT32UC3A4256S AT32UC3A4256 64KByte 256KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Size AT32UC3A3128S AT32UC3A3128 AT32UC3A4128S AT32UC3A4128 64KByte 128KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Size AT32UC3A364S AT32UC3A364 AT32UC3A464S AT32UC3A464 64KByte 64KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Embedded CPU SRAM Embedded Flash EBI SRAM CS0 EBI SRAM CS2 EBI SRAM CS3 EBI SRAM CS4 EBI SRAM CS5 EBI SRAM CS1 /SDRAM CS0 USB Data 0x00000000 0x80000000 0xC0000000 0xC8000000 0xCC000000 0xD8000000 0xDC000000 0xD0000000 0xE0000000 34 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 5-1. AT32UC3A3A4 Physical Memory Map Size Device Start Address AT32UC3A3256S AT32UC3A3256 AT32UC3A4256S AT32UC3A4256 32KByte 32KByte 64KByte 64KByte Size AT32UC3A3128S AT32UC3A3128 AT32UC3A4128S AT32UC3A4128 32KByte 32KByte 64KByte 64KByte Size AT32UC3A364S AT32UC3A364 AT32UC3A464S AT32UC3A464 32KByte 32KByte 64KByte 64KByte HRAMC0 HRAMC1 HSB-PB Bridge A HSB-PB Bridge B 0xFF000000 0xFF008000 0xFFFF0000 0xFFFE0000 5.3 Peripheral Address Map Peripheral Address Mapping Address 0xFF100000 Table 5-2. Peripheral Name DMACA DMA Controller - DMACA 0xFFFD0000 AES 0xFFFE0000 Advanced Encryption Standard - AES USB 0xFFFE1000 USB 2.0 OTG Interface - USB HMATRIX 0xFFFE1400 HSB Matrix - HMATRIX FLASHC 0xFFFE1C00 Flash Controller - FLASHC SMC 0xFFFE2000 Static Memory Controller - SMC SDRAMC 0xFFFE2400 SDRAM Controller - SDRAMC Error code corrector Hamming and Reed Solomon ECCHRS Bus Monitor module - BUSMON ECCHRS 0xFFFE2800 BUSMON 0xFFFE4000 MCI 0xFFFE8000 Mulitmedia Card Interface - MCI MSI 0xFFFF0000 Memory Stick Interface - MSI PDCA 0xFFFF0800 Peripheral DMA Controller - PDCA INTC Interrupt controller - INTC 35 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 5-2. Peripheral Address Mapping 0xFFFF0C00 PM 0xFFFF0D00 Power Manager - PM RTC 0xFFFF0D30 Real Time Counter - RTC WDT 0xFFFF0D80 Watchdog Timer - WDT EIC 0xFFFF1000 External Interrupt Controller - EIC GPIO 0xFFFF1400 General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 Serial Peripheral Interface - SPI0 USART0 0xFFFF1800 USART1 0xFFFF1C00 USART2 0xFFFF2000 USART3 0xFFFF2400 SPI0 0xFFFF2800 SPI1 0xFFFF2C00 Serial Peripheral Interface - SPI1 TWIM0 0xFFFF3000 Two-wire Master Interface - TWIM0 TWIM1 0xFFFF3400 Two-wire Master Interface - TWIM1 SSC 0xFFFF3800 Synchronous Serial Controller - SSC TC0 0xFFFF3C00 Timer/Counter - TC0 ADC 0xFFFF4000 Analog to Digital Converter - ADC ABDAC 0xFFFF4400 Audio Bitstream DAC - ABDAC TC1 Timer/Counter - TC1 36 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 5-2. Peripheral Address Mapping 0xFFFF5000 TWIS0 0xFFFF5400 Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 5-3. Port 0 Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000040 0x40000044 0x40000048 0x4000004C 0x40000050 0x40000054 0x40000058 0x4000005C 0x40000060 0x40000140 0x40000144 0x40000148 0x4000014C 0x40000150 0x40000154 0x40000158 0x4000015C 0x40000160 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 1 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 37 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 5-3. Port 2 Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000240 0x40000244 0x40000248 0x4000024C 0x40000250 0x40000254 0x40000258 0x4000025C 0x40000260 0x40000340 0x40000344 0x40000348 0x4000034C 0x40000350 0x40000354 0x40000358 0x4000035C 0x40000360 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 3 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 38 32072C–AVR32–2010/03 AT32UC3A3/A4 6. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after powerup is controlled by the Power Manager. For specific details, refer to Section 7. ”Power Manager (PM)” on page 40. 6.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system receives a clock with the same frequency as the internal RC Oscillator. 6.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 39 32072C–AVR32–2010/03 AT32UC3A3/A4 7. Power Manager (PM) Rev: 2.3.1.0 7.1 Features • • • • • • • • • • • • • Controls integrated oscillators and PLLs Generates clocks and resets for digital logic Supports 2 crystal oscillators 0.4-20MHz Supports 2 PLLs 40-240MHz Supports 32KHz ultra-low power oscillator Integrated low-power RC oscillator On-the fly frequency change of CPU, HSB, PBA, and PBB clocks Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators Module-level clock gating through maskable peripheral clocks Wake-up from internal or external interrupts Generic clocks with wide frequency range provided Automatic identification of reset sources Controls brownout detector (BOD and BOD33), RC oscillator, and bandgap voltage reference through control and calibration registers 7.2 Overview The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power 32KHz oscillator is used to generate the real-time counter clock for high accuracy real-time measurements. The PM also contains a low-power RC oscillator with fast start-up time, which can be used to clock the digital logic. The provided clocks are divided into synchronous and generic clocks. The synchronous clocks are used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous clocks, which can be tuned precisely within a wide frequency range, which makes them suitable for peripherals that require specific frequencies, such as timers and communication modules. The PM also contains advanced power-saving features, allowing the user to optimize the power consumption for an application. The synchronous clocks are divided into three clock domains, one for the CPU and HSB, one for modules on the PBA bus, and one for modules on the PBB bus.The three clocks can run at different speeds, so the user can save power by running peripherals at a relatively low clock, while maintaining a high CPU performance. Additionally, the clocks can be independently changed on-the-fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and memories to the dynamic load of the application, without disturbing or re-configuring active peripherals. Each module also has a separate clock, enabling the user to switch off the clock for inactive modules, to save further power. Additionally, clocks and oscillators can be automatically switched off during idle periods by using the sleep instruction on the CPU. The system will return to normal on occurrence of interrupts. The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software. 40 32072C–AVR32–2010/03 AT32UC3A3/A4 7.3 Block Diagram Figure 7-1. Power Manager Block Diagram Synchronous clocks CPU, HSB, PBA, PBB RCSYS Synchronous Clock Generator PLL0 Oscillator 0 Oscillator 1 PLL1 Generic Clock Generator G eneric clocks 32 KHz Oscillator O SC/PLL Control signals CLK_32 RC Oscillator Slow clock Oscillator and PLL Control Voltage Regulator Startup Counter Interrupts Sleep Controller Sleep instruction fuses Calibration Registers Brown-Out Detector Power-On Detector O ther reset sources External Reset Pad Reset Controller resets 41 32072C–AVR32–2010/03 AT32UC3A3/A4 7.4 7.4.1 Product Dependencies I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with I/O lines. The programmer must first program the I/O controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the I/O controller. 7.4.2 Interrupt The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using the PM interrupt requires the interrupt controller to be programmed first. 7.5 7.5.1 Functional Description Slow Clock The slow clock is generated from an internal RC oscillator which is always running, except in Static mode. The slow clock can be used for the main clock in the device, as described in Section 7.5.5. The slow clock is also used for the Watchdog Timer and measuring various delays in the Power Manager. The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running. The RC oscillator operates at approximately 115 kHz. Software can change RC oscillator calibration through the use of the RCCR register. Please see the Electrical Characteristics section for details. RC oscillator can also be used as the RTC clock when crystal accuracy is not required. 7.5.2 Oscillator 0 and 1 Operation The two main oscillators are designed to be used with an external crystal and two biasing capacitors, as shown in Figure 7-2 on page 43. Oscillator 0 can be used for the main clock in the device, as described in Section 7.5.5. Both oscillators can be used as source for the generic clocks, as described in Section 7.5.8. The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a general purpose I/O. The oscillators can be enabled by writing to the OSCnEN bits in MCCTRL. Operation mode (external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are automatically switched off in certain sleep modes to reduce power consumption, as described in Section 7.5.7. After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscillators may need a certain amount of time to stabilize on the correct frequency. This start-up time can be set in the OSCCTRLn register. The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero to one transition on these bits can also be configured to generate an interrupt, as described in Section 7.6.7. 42 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 7-2. Oscillator Connections C2 XO UT XIN C1 7.5.3 32 KHz Oscillator Operation The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter. The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static mode. While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin can be used as a general purpose I/O. The startup time of the 32 KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY in POSCSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY. As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz oscillator will keep running across resets, except Power-On-Reset. 7.5.4 PLL Operation The device contains two PLLs, PLL0 and PLL1. These are disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks. The PLLs can take either Oscillator 0 or 1 as reference clock. The PLL output is divided by a multiplication factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its output frequency until the two compared clocks are equal, thus locking the output frequency to a multiple of the reference clock frequency. When the PLL is switched on, or when changing the clock source or multiplication factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable. 43 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 7-3. PLL with Control Logic and Filters PLLMUL Output Divider Mask PLL clock Osc0 clock Osc1 clock 0 1 Input Divider PLLDIV Fin PLL PLLEN PLLOPT LOCK PLLOSC 7.5.4.1 Enabling the PLL PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and division factors, respectively, creating the voltage controlled ocillator frequency fVCO and the PLL frequency fPLL : if PLLDIV > 0 fIN = fOSC/2 • PLLDIV fVCO = (PLLMUL+1)/(PLLDIV) • fOSC if PLLDIV = 0 fIN = fOSC fVCO = 2 • (PLLMUL+1) • fOSC Note: Refer to Electrical Characteristics section for FIN and FVCO frequency range. If PLLOPT[1] field is set to 0: fPLL = fVCO. If PLLOPT[1] field is set to 1: fPLL = fVCO / 2. 44 32072C–AVR32–2010/03 AT32UC3A3/A4 The PLLn:PLLOPT field should be set to proper values according to the PLL operating frequency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2. The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be generated on a 0 to 1 transition of these bits. 7.5.5 Synchronous Clocks The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tapping of this prescaler, or the undivided main clock, as long as fCPU ≥ fPBA,B,. The synchronous clock source can be changed on-the fly, responding to varying load in the application. The clock domains can be shut down in sleep mode, as described in Section 7.5.7. Additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules. Figure 7-4. Synchronous Clock Generation Sleep instruction Sleep Controller 0 Slow clock Osc0 clock PLL0 clock Main clock Mask CPUMASK CPU clocks AHB clocks APBAclocks APBB clocks Prescaler 1 CPUDIV MCSEL CPUSEL 7.5.5.1 Selecting PLL or oscillator for the main clock The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default, the main clock will be connected to the slow clock. The user can connect the main clock to Oscillator 0 or PLL0 by writing the MCSEL field in the Main Clock Control Register (MCCTRL). This must only be done after that unit has been enabled, otherwise a deadlock will occur. Care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain. 45 32072C–AVR32–2010/03 AT32UC3A3/A4 7.5.5.2 Selecting synchronous clock division ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing CKSEL.CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: f CPU = f main ⁄ 2 ( CPUSEL + 1 ) Similarly, the clock for the PBA, and PBB can be divided by writing their respective fields. To ensure correct operation, frequencies must be selected so that fCPU ≥ fPBA,B. Also, frequencies must never exceed the specified maximum frequency for each clock domain. CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL fields. This way, it is possible to e.g. scale CPU and HSB speed according to the required performance, while keeping the PBA and PBB frequency constant. For modules connected to the HSB bus, the PB clock frequency must be set to the same frequency than the CPU clock. 7.5.5.3 Clock ready flag There is a slight delay from CKSEL is written and the new clock setting becomes effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER.CKRDY is written to 1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL must not be re-written while CKRDY is 0, or the system may become unstable or hang. Peripheral Clock Masking By default, the clock for all modules are enabled, regardless of which modules are actually being used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0. When a module is not clocked, it will cease operation, and its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to 1. A module may be connected to several clock domains, in which case it will have several mask bits. Table 7-7 on page 57 contains the list of implemented maskable clocks. 7.5.6.1 Cautionary note The OCD clock must never be switched off if the user wishes to debug the device with a JTAG debugger. Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the internal RAM will cause a problem if the stack is mapped there. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. 7.5.6.2 Mask ready flag Due to synchronization in the clock generator, there is a slight delay from a mask register is written until the new mask setting goes into effect. When clearing mask bits, this delay can usually 46 32072C–AVR32–2010/03 7.5.6 AT32UC3A3/A4 be ignored. However, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR provides the required mask status information. When writing either mask register with any value, this bit is cleared. The bit is set when the clocks have been enabled and disabled according to the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the MSKRDY bit in IER. 7.5.7 Sleep Modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument. 7.5.7.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings of the mask registers. Oscillators and PLLs can also be switched off to save power. Some of these modules have a relatively long start-up time, and are only switched off when very low power consumption is required. The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked. 7.5.7.2 Supported sleep modes The following sleep modes are supported. These are detailed in Table 7-1 on page 48. • Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt. • Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources are any interrupt from PB modules. • Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing quick wake-up to normal mode. Wake-up sources are RTC or external interrupt. • Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and RC oscillators and RTC/WDT still operate. Wake-up sources are RTC, external interrupt, or external reset pin. • DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference, BOD and BOD33 are turned off. • Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage reference, BOD and BOD33 detectors areturned off. 47 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 7-1. Sleep Modes PBA,B GCLK Run Run Stop Stop Stop Stop Osc0,1 PLL0,1, SYSTIMER Run Run Run Stop Stop Stop BOD & BOD33 & Bandgap On On On On Off Off Voltage Regulator Full power Full power Full power Low power Low power Low power Index 0 1 2 3 4 5 Sleep Mode Idle Frozen Standby Stop DeepStop Static CPU Stop Stop Stop Stop Stop Stop HSB Run Stop Stop Stop Stop Stop Osc32 Run Run Run Run Run Stop RCSYS Run Run Run Run Run Stop The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 7.5.7.3 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions. Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. This means that bus transactions are not allowed between clock domains affected by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus transaction. The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary. When entering a sleep mode (except Idle mode), all HSB masters must be stopped before entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete, the CPU should perform a read operation from any register on the PB bus before executing the sleep instruction. This will stall the CPU while waiting for any pending PB operations to complete. 7.5.7.4 Wake Up The USB can be used to wake up the part from sleep modes through register AWEN of the Power Manager. 7.5.8 Generic Clocks Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The Power Manager contains an implementation defined number of generic clocks that can provide a wide range of accurate clock frequencies. Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 256. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller. 48 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 7-5. Generic Clock Generation Sleep Controller 0 Osc0 clock Osc1 clock PLL0 clock PLL1 clock 0 Mask Divider 1 Generic Clock 1 PLLSEL OSCSEL DIV DIVEN CEN 7.5.8.1 Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits. The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV, resulting in the output frequency: f GCLK = f SRC ⁄ ( 2 × ( DIV + 1 ) ) 7.5.8.2 Disabling a generic clock The generic clock can be disabled by writing CEN to zero or entering a sleep mode that disables the PB clocks. In either case, the generic clock will be switched off on the first falling edge after the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as 1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0, the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the generic clock. When the clock is disabled, both the prescaler and output are reset. 7.5.8.3 Changing clock frequency When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition. 49 32072C–AVR32–2010/03 AT32UC3A3/A4 7.5.8.4 Generic clock implementation The generic clocks are allocated to different functions as shown in Table 7-2 on page 50. Table 7-2. Generic Clock Allocation Function GCLK0 pin GCLK1 pin GCLK2 pin GCLK3 pin GCLK_USBB GCLK_ABDAC Clock number 0 1 2 3 4 5 7.5.9 Divided PB Clocks The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock. This is described in the documentation for the relevant modules. The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx clocks are stopped. 7.5.10 Debug Operation The OCD clock must never be switched off if the user wishes to debug the device with a JTAG debugger. During a debug session, the user may need to halt the system to inspect memory and CPU registers. The clocks normally keep running during this debug operation, but some peripherals may require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx clocks. This is described in the documentation for the relevant modules. The divided PBx clocks are always debug qualified clocks. Debug qualified PBx clocks are stopped during debug operation. The debug system can optionally keep these clocks running during the debug operation. This is described in the documentation for the On-Chip Debug system. 7.5.11 Reset Controller The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic. The device contains a Power-On Detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pullup, and does not need to be driven externally when negated. Table 7-4 on page 52 lists these and other reset sources supported by the Reset Controller. 50 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 7-6. Reset Controller Block Diagram RC_RCAUSE R ESET_N P o w e r-O n D e te c to r B ro w n o u t D e te c to r JTAG OCD WDT CPU, HSB, PBA, PBB R eset C o n tro lle r O C D , R T C /W D T , C lo c k G e n e ra to r In addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation for details. Table 7-3. Reset source Reset Description Description Supply voltage below the power-on reset detector threshold voltage RESET_N pin asserted Supply voltage below the brownout reset detector threshold voltage Caused by an illegal CPU access to external memory while in Supervisor mode See watchdog timer documentation. See On-Chip Debug documentation Power-on Reset External Reset Brownout Reset CPU Error Watchdog Timer OCD When a reset occurs, some parts of the chip are not necessarily reset, depending on the reset source. Only the Power On Reset (POR) will force a reset of the whole chip. 51 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 7-4 on page 52 lists parts of the device that are reset, depending on the reset source. Table 7-4. Effect of the Different Reset Events Power-On Reset CPU/HSB/PBA/PBB (excluding Power Manager) 32 KHz oscillator RTC control register GPLP registers Watchdog control register Voltage calibration register RCSYS Calibration register BOD control register BOD33 control register Bandgap control register Clock control registers Osc0/Osc1 and control registers PLL0/PLL1 and control registers OCD system and OCD registers Y Y Y Y Y Y Y Y Y Y Y Y Y Y External Reset Y N N N Y N N Y Y Y Y Y Y Y Watchdog Reset Y N N N N N N N N N Y Y Y N BOD Reset Y N N N Y N N N N N Y Y Y Y BOD33 Reset Y N N N Y N N N N N Y Y Y Y CPU Error Reset Y N N N Y N N N N N Y Y Y Y OCD Reset Y N N N Y N N N N N Y Y Y N The cause of the last reset can be read from the RCAUSE register. This register contains one bit for each reset source, and can be read during the boot sequence of an application to determine the proper action to be taken. 7.5.11.1 Power-On detector The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the device is powered on. The reset is active until the supply voltage from the linear regulator is above the power-on threshold level. The reset will be re-activated if the voltage drops below the power-on threshold level. See Electrical Characteristics for parametric details. Brown-Out detector The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default, but can be enabled either by software or by flash fuses. The Brown-Out Detector can either generate an interrupt or a reset when the supply voltage is below the brown-out detection level. In any case, the BOD output is available in bit POSCSR.BODDET bit. Note that any change to the BOD.LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt. See Electrical Characteristics chapter for parametric details. 7.5.11.2 52 32072C–AVR32–2010/03 AT32UC3A3/A4 7.5.11.3 Brown-Out detector 3V3 The Brown-Out Detector 3V3 (BOD33) monitors one VDDIO supply pin and compares the supply voltage to the brown-out detection 3V3 level, which is typically calibrated at 2V7. The BOD33 is enabled by default, but can be disabled by software. The Brown-Out Detector 3V3 can either generate an interrupt or a reset when the supply voltage is below the brown-out detection3V3 level. In any case, the BOD33 output is available in bit POSCSR.BOD33DET bit. Note that any change to the BOD33.LEVEL field of the BOD33 register should be done with the BOD33 deactivated to avoid spurious reset or interrupt. The BOD33.LEVEL default value is calibrated to 2V7 See Electrical Characteristics chapter for parametric details. Table 7-5. VDDIO pin monitored by BOD33 QFP144 81 VFBGA100 E5 TFBGA144 H5 7.5.11.4 External reset The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset. Calibration Registers The Power Manager controls the calibration of the RC oscillator, voltage regulator, bandgap voltage reference through several calibrations registers. Those calibration registers are loaded after a Power On Reset with default values stored in factory-programmed flash fuses. Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to these registers is protected by a “key”. First, a write to the register must be made with the field “KEY” equal to 0x55 then a second write must be issued with the “KEY” field equal to 0xAA. 7.5.12 53 32072C–AVR32–2010/03 AT32UC3A3/A4 7.6 User Interface Table 7-6. Offset 0x000 0x0004 0x008 0x00C 0x010 0x014 0x020 0x024 0x028 0x02C 0x030 0x040 0x044 0x048 0x04C 00050 0x054 0x060 0x064 0x068 0x06C 0x070 0x0C0 0x0C4 0x0C8 0x0D0 0x0D4 0x0140 0x0144 0x200 PM Register Memory Map Register Register Name MCCTRL CKSEL CPUMASK HSBMASK PBAMASK PBBMASK PLL0 PLL1 OSCCTRL0 OSCCTRL1 OSCCTRL32 IER IDR IMR ISR ICR POSCSR GCCTRL0 GCCTRL1 GCCTRL2 GCCTRL3 GCCTRL4 RCCR BGCR VREGCR BOD BOD33 RCAUSE AWEN GPLP Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset State 0x00000000 0x00000000 0x00000003 0x00000FFF 0x001FFFFF 0x000003FF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Factory settings Factory settings Factory settings BOD fuses in Flash BOD33 reset enable BOD33 LEVEL=2V7 Latest Reset Source 0x00000000 0x00000000 Main Clock Control Clock Select CPU Mask HSB Mask PBA Mask PBB Mask PLL0 Control PLL1 Control Oscillator 0 Control Register Oscillator 1 Control Register Oscillator 32 Control Register PM Interrupt Enable Register PM Interrupt Disable Register PM Interrupt Mask Register PM Interrupt Status Register PM Interrupt Clear Register Power and Oscillators Status Register Generic Clock Control 0 Generic Clock Control 1 Generic Clock Control 2 Generic Clock Control 3 Generic Clock Control 4 RC Oscillator Calibration Register Bandgap Calibration Register Linear Regulator Calibration Register BOD Level Register BOD33 Level Register Reset Cause Register Asynchronous Wake Enable Register General Purpose Low-Power register 54 32072C–AVR32–2010/03 AT32UC3A3/A4 7.6.1 Name: Main Clock Control Register MCCTRL Read/Write 0x00 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 OSC1EN 2 OSC0EN 1 MCSEL 0 • OSC1EN: Oscillator 1 Enable 1: Oscillator 1 is enabled 0: Oscillator 1 is disabled • OSC0EN: Oscillator 0 Enable 1: Oscillator 0 is enabled 0: Oscillator 0 is disabled • MCSEL: Main Clock Select This field contains the clock selected as the main clock. MCSEL 0b00 0b01 0b10 0b11 Selected Clock Slow Clock Oscillator 0 PLL 0 Reserved 55 32072C–AVR32–2010/03 AT32UC3A3/A4 7.6.2 Name: Clock Select Register CKSEL Read/Write 0x04 0x00000000 30 29 28 27 26 25 PBBSEL 24 Access Type: Offset: Reset Value: 31 PBBDIV 23 PBADIV 22 - 21 - 20 - 19 - 18 17 PBASEL 16 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 CPUDIV 6 - 5 - 4 - 3 - 2 1 CPUSEL 0 • PBBDIV: PBB Division Enable PBBDIV = 0: PBB clock equals main clock. PBBDIV = 1: PBB clock equals main clock divided by 2(PBBSEL+1). • PBADIV, PBASEL: PBA Division and Clock Select PBADIV = 0: PBA clock equals main clock. PBADIV = 1: PBA clock equals main clock divided by 2(PBASEL+1). • CPUDIV, CPUSEL: CPU/HSB Division and Clock Select CPUDIV = 0: CPU/HSB clock equals main clock. CPUDIV = 1: CPU/HSB clock equals main clock divided by 2(CPUSEL+1). Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation. Also note that writing this register clears POSCSR.CKRDY. The register must not be re-written until CKRDY goes high. 56 32072C–AVR32–2010/03 AT32UC3A3/A4 7.6.3 Name: Clock Mask Registers CPU/HSB/PBA/PBBMASK Read/Write 0x08-0x14 0x00000003/0x00000FFF/0x001FFFFF/0x000003FF 30 29 28 MASK[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 MASK[23:16] 19 18 17 16 15 14 13 12 MASK[15:8] 11 10 9 8 7 6 5 4 MASK[7:0] 3 2 1 0 • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in Table 7-7 on page 57. Table 7-7. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Maskable module clocks in AT32UC3A3. HSBMASK FLASHC PBA Bridge PBB Bridge USBB PDCA EBI PBC Bridge DMACA BUSMON HRAMC0 HRAMC1 (2) CPUMASK OCD(1) - PBAMASK INTC I/O PDCA PM/RTC/EIC ADC SPI0 SPI1 TWIM0 TWIM1 TWIS0 TWIS1 USART0 USART1 USART2 USART3 SSC PBBMASK HMATRIX USBB FLASHC SMC SDRAMC ECCHRS MCI BUSMON MSI AES - - 57 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 7-7. Bit 16 Maskable module clocks in AT32UC3A3. HSBMASK PBAMASK TC0 PBBMASK - CPUMASK SYSTIMER (compare/count registers clk) - 17 18 19 20 31: 21 - TC1 ABDAC (2) (2) - - Note: 1. This bit must be set to one if the user wishes to debug the device with a JTAG debugger. 2. This bits must be set to one 58 32072C–AVR32–2010/03 AT32UC3A3/A4 7.6.4 Name: PLL Control Registers PLL0,1 Read/Write 0x20-0x24 0x00000000 30 29 28 27 PLLCOUNT 26 25 24 Access Type: Offset: Reset Value: 31 PLLTEST 23 - 22 - 21 - 20 - 19 18 PLLMUL 17 16 15 - 14 - 13 - 12 - 11 10 PLLDIV 9 8 7 - 6 - 5 - 4 3 PLLOPT 2 1 PLLOSC 0 PLLEN • PLLTEST: PLL Test Reserved for internal use. Always write to 0. • PLLCOUNT: PLL Count Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode. • PLLMUL: PLL Multiply Factor • PLLDIV: PLL Division Factor These fields determine the ratio of the PLL output frequency to the source oscillator frequency. Formula is detallied in ”Enabling the PLL” on page 44 • PLLOPT: PLL Option Select the operating range for the PLL. PLLOPT[0]: Select the VCO frequency range PLLOPT[1]: Enable the extra output divider PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time) Description PLLOPT[0]: VCO frequency 0 1 PLLOPT[1]: Output divider 0 1 fPLL = fvco fPLL = fvco/2 160MHz1 1 0 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider SYNC 0 1 2 3 16-bit Counter glitch-free logic 0 BaudRate Clock 25.6.1.4 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in BRGR. BaudRate = SelectedClock ------------------------------------CD 549 32072C–AVR32–2010/03 AT32UC3A3/A4 In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART CLK pin. No division is active. The value written in BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock CLK or the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the CLK pin. If the internal clock CLK_USART is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the CLK pin, even if the value programmed in CD is odd. 25.6.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- × f Fi where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 25-4. Table 25-4. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 25-5. Table 25-5. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 25-6 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 25-6. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (MR) is first divided by the value programmed in the field CD in the Baud Rate 550 32072C–AVR32–2010/03 AT32UC3A3/A4 Generator Register (BRGR). The resulting clock can be provided to the CLK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 25-4 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 25-4. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on CLK ISO7816 I/O Line on TXD 1 ETU 25.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (THR). If a timeguard is programmed, it is handled normally. 551 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.3 25.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in MR. The 1.5 stop bit is supported in asynchronous mode only. Figure 25-5. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed. When the current character processing is completed, the last character written in THR is transferred into the Shift Register of the transmitter and THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in THR while TXRDY is low has no effect and the written character is lost. Figure 25-6. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY 552 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 25-7 illustrates this coding scheme. Figure 25-7. NRZ to Manchester Encoding NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1 Txd The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the MAN register, the field TX_PL is used to configure the preamble length. Figure 25-8 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. 553 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-8. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 25-9 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in MR register must be set to 1. In this case, the MODSYNC field in MR is bypassed and the sync configuration is held in the TXSYNH in the THR register. The USART character format is modified and includes sync information. 554 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-9. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data Txd DATA One bit start frame delimiter SFD Manchester encoded data Txd DATA SFD Manchester encoded data Txd Command Sync start frame delimiter DATA Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. Figure 25-10. Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error Synchro. Jump Tolerance Sync Jump Synchro. Error 25.6.3.3 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (MR). 555 32072C–AVR32–2010/03 AT32UC3A3/A4 The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 25-11 and Figure 25-12 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 25-11. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 25-12. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 556 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.3.4 Manchester Decoder When the MAN field in MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in MAN. See Figure 25-8 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 25-13. The sample pulse rejection mechanism applies. Figure 25-13. Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 25-14 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in CSR register is raised. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. See Figure 25-15 for an example of Manchester error detection during data phase. 557 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-14. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Preamble Mismatch invalid pattern Manchester encoded data Txd SFD DATA Preamble Length is set to 8 Figure 25-15. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition. 25.6.3.5 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 25-16. 558 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-16. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line ASK/FSK downstream transmitter Manchester decoder USART Receiver Downstream Receiver Manchester encoder PA RF filter Mod VCO USART Emitter control The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 25-17 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 25-18. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 25-17. ASK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 0 0 1 Txd 559 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-18. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 0 0 1 Txd 25.6.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 25-19 illustrates a character reception in synchronous mode. Figure 25-19. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 25.6.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. 560 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-20. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR Read RHR RXRDY OVRE 561 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.3.8 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (MR). The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 563. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 25-7 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 25-7. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (CSR). The PARE bit can be cleared by writing the Control Register (CR) with the RSTSTA bit at 1. Figure 25-21 illustrates the parity bit status setting and clearing. 562 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-21. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write CR PARE RXRDY 25.6.3.9 Multidrop Mode If the PAR field in the Mode Register (MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to CR. In this case, the next byte written to THR is transmitted as an address. Any character written in THR without having written the command SENDA is transmitted normally with the parity at 0. 25.6.3.10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 25-22, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 563 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-22. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write THR TXRDY TXEMPTY Table 25-8 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 25-8. Maximum Timeguard Length Depending on Baud Rate Bit time µs 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 25.6.3.11 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at 0. Otherwise, the receiver loads a counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing the Control Register (CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to 564 32072C–AVR32–2010/03 AT32UC3A3/A4 handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 25-23 shows the block diagram of the Receiver Time-out feature. Figure 25-23. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 25-9 gives the maximum time-out period for some standard baud rates. Table 25-9. Maximum Time-out Period Bit Time µs 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 565 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 25-9. Maximum Time-out Period (Continued) Bit Time 18 17 5 Time-out 1 170 1 138 328 Baud Rate 56000 57600 200000 25.6.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. Figure 25-24. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR FRAME RXRDY 25.6.3.13 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 566 32072C–AVR32–2010/03 AT32UC3A3/A4 The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 25-25 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 25-25. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write CR TXRDY TXEMPTY 25.6.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in CSR. This bit may be cleared by writing the Control Register (CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 25.6.3.15 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 25-26. 567 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-26. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the MODE field in the Mode Register (MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the Peripheral DMA Controller channel for reception. The transmitter can handle hardware handshaking in any case. Figure 25-27 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the Peripheral DMA Controller channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the Peripheral DMA Controller clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 25-27. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write CR RTS RXBUFF RXDIS = 1 Figure 25-28 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 25-28. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 568 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the MODE field in the Mode Register (MR) to the value 0x4 for protocol T = 0 and to the value 0x6 for protocol T = 1. 25.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see ”Baud Rate Generator” on page 547). The USART connects to a smart card as shown in Figure 25-29. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the CLK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 25-29. Connection of a Smart Card to the USART USART CLK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to ”Mode Register” on page 605 and ”PAR: Parity Type” on page 606. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (THR) or after reading it in the Receive Holding Register (RHR). 25.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 25-30. 569 32072C–AVR32–2010/03 AT32UC3A3/A4 If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 25-31. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (RHR). It appropriately sets the PARE bit in the Status Register (SR) so that the software can handle the error. Figure 25-30. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 25-31. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 25.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (NER) register. The NB_ERRORS field can record up to 255 errors. Reading NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does raise. 25.6.4.4 25.6.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. 570 32072C–AVR32–2010/03 AT32UC3A3/A4 The ITERATION bit in CSR can be cleared by writing the Control Register with the RSIT bit at 1. 25.6.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 25-32. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the MODE field in the Mode Register (MR) to the value 0x8. The IrDA Filter Register (IFR) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible (except those fixed by IrDA specification : one start bit , 8 data bits and one stop bit). Note that the modulator and the demodulator are activated. Figure 25-32. Connection to IrDA Transceivers 25.6.4.7 25.6.5 USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX • Configure the TXD pin as I/O and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). • Receive data 571 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 25-10. Table 25-10. IrDA Pulse Duration Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s Pulse Duration (3/16) 78.13 µs 19.53 µs 9.77 µs 4.88 µs 3.26 µs 1.63 µs Figure 25-33 shows an example of character transmission. Figure 25-33. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1 TXD Bit Period 3 16 Bit Period 25.6.5.2 IrDA Baud Rate Table 25-11 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 25-11. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 CD 2 11 18 22 4 22 36 43 6 33 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88 572 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 25-11. IrDA Baud Rate Error (Continued) Peripheral Clock 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 25.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in IFR. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the CLK_USART speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with IFR. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 25-34 illustrates the operations of the IrDA demodulator. Figure 25-34. IrDA Demodulator Operations CLK_USART RXD Counter Value Receiver Input Pulse Accepted 6 5 4 3 2 6 6 5 4 3 2 1 0 Pulse Rejected Driven Low During 16 Baud Rate Clock Cycles As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 573 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 25-35. Figure 25-35. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the MODE field in the Mode Register (MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 25-36 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 25-36. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY RTS 574 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the MODE field in the Mode Register (MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 25-12 gives the correspondence of the USART signals with modem connection standards. Table 25-12. Circuit References USART Pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem The control of the DTR output pin is performed by writing the Control Register (CR) with the DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 575 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.8 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one master may simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address only one SPI Slave because it can generate only one NSS signal. The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the slave. • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. • Serial Clock (CLK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The CLK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows the master to select or deselect the slave. 25.6.8.1 Modes of Operation The USART can operate in Master Mode or in Slave Mode. Operation in SPI Master Mode is programmed by writing at 0xE the MODE field in the Mode Register. In this case the SPI lines must be connected as described below: • the MOSI line is driven by the output pin TXD • the MISO line drives the input pin RXD • the CLK line is driven by the output pin CLK • the NSS line is driven by the output pin RTS Operation in SPI Slave Mode is programmed by writing at 0xF the MODE field in the Mode Register. In this case the SPI lines must be connected as described below: • the MOSI line drives the input pin RXD • the MISO line is driven by the output pin TXD • the CLK line drives the input pin CLK • the NSS line drives the input pin CTS In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). 25.6.8.2 Baud Rate In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See Section “25.6.1.4” on page 549. However, there are some restrictions: 576 32072C–AVR32–2010/03 AT32UC3A3/A4 In SPI Master Mode: • the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK pin. • to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of must be superior or equal to 4. • if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the internal clock is selected (CLK_USART). In SPI Slave Mode: • the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is provided directly by the signal on the USART CLK pin. • to obtain correct behavior of the receiver and the transmitter, the external clock (CLK) frequency must be at least 4 times lower than the system clock. 577 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.8.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave). Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 25-13. SPI Bus Protocol Mode SPI Bus Protocol Mode 0 1 2 3 CPOL 0 0 1 1 CPHA 1 0 1 0 578 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-37. SPI Transfer Format (CPHA=1, 8 bits per transfer) CLK cycle (for reference) CLK (CPOL= 0) 1 2 3 4 5 6 7 8 CLK (CPOL= 1) MOSI SPI Master ->TXD SPI Slave ->RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master ->RXD SPI Slave ->TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master ->RTS SPI Slave ->CTS Figure 25-38. SPI Transfer Format (CPHA=0, 8 bits per transfer) CLK cycle (for reference) CLK (CPOL= 0) 1 2 3 4 5 6 7 8 CLK (CPOL= 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 579 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.8.4 Receiver and Transmitter Control See Section “25.6.2” on page 551. Character Transmission The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed. When the current character processing is completed, the last character written in THR is transferred into the Shift Register of the transmitter and THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (THR) is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit before the transmission of the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing the Control Register (CR) with the RTSEN bit at 1. The slave select line (NSS) can be released at high level only by writing the Control Register (CR) with the RTSDIS bit at 1 (for example, when all data have been transferred to the slave device). In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 25.6.8.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding Register (RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 25.6.8.7 Receiver Timeout Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (RTOR). 25.6.8.5 580 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.9 LIN Mode The LIN Mode provides Master node and Slave node connectivity on a LIN bus. The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: • Single Master/Multiple Slaves concept • Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine. • Self synchronization without quartz or ceramic resonator in the slave nodes • Deterministic signal transmission • Low cost single-wire implementation • Speed up to 20 kbit/s LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required. The LIN Mode enables processing LIN frames with a minimum of action from the microprocessor. 25.6.9.1 Modes of operation The USART can act either as a LIN Master node or as a LIN Slave node. The node configuration is chosen by setting the MODE field in the Mode Register (MR): • LIN Master Node (MODE=0xA) • LIN Slave Node (MODE=0xB) In order to avoid unpredicted behavior, any change of the LIN node configuration must be followed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See Section 25.6.9.2) 25.6.9.2 Receiver and Transmitter Control See Section “25.6.2” on page 551. Character Transmission See Section “25.6.3.1” on page 552. Character Reception See Section “25.6.3.7” on page 560. 25.6.9.3 25.6.9.4 581 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.9.5 Header Transmission (Master Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. So in Master node configuration, the frame handling starts with the sending of the header. The header is transmitted as soon as the identifier is written in the LIN Identifier register (LINIR). At this moment the flag TXRDY falls. The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other. The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the Identifier corresponds to the character written in the LIN Identifier Register (LINIR). The Identifier parity bits can be automatically computed and sent (see Section 25.6.9.8). The flag TXRDY rises when the identifier character is transferred into the Shift Register of the transmitter. Figure 25-39. Header Transmission Baud Rate Clock TXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit Write LINIR LINIR TXRDY ID 582 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.9.6 Header Reception (Slave Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In Slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field. As long as a Break Field has not been detected, the USART stays idle and the received data are not taken in account. When a Break Field has been detected, the USART expects the Synch Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized (see Section 25.6.9.7). If the received Synch character is not 0x55, an Inconsistent Synch Field error is generated (see Section 25.6.10). After receiving the Synch Field, the USART expects to receive the Identifier Field. When the Identifier has been received, the flag LINID is set to “1”. At this moment the field IDCHR in the LIN Identifier register (LINIR) is updated with the received character. The Identifier parity bits can be automatically computed and checked (see Section 25.6.9.8). Figure 25-40. Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 1 0 Synch Byte = 0x55 Stop Stop Start ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINID US_LINIR Write US_CR With RSTSTA=1 25.6.9.7 Slave Node Synchronization The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times. Figure 25-41. Synch Field Synch Field 8 Tbit 2 Tbit 2 Tbit 2 Tbit 2 Tbit Start bit Stop bit The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 25.6.1). 583 32072C–AVR32–2010/03 AT32UC3A3/A4 When the start bit of the Synch Field is detected the counter is reset. Then during the next 8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (CD) and the 3 least significant bits of this value (the remainder) gives the new fractional part (FP). When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in the Baud Rate Generator register (BRGR). Figure 25-42. Slave Node Synchronization Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINIDRX Reset Synchro Counter BRGR Clcok Divider (CD) BRGR Fractional Part (FP) Initial CD Initial FP 000_0011_0001_0110_1101 0000_0110_0010_1101 101 The accuracy of the synchronization depends on several parameters: • The nominal clock frequency (FNom) (the theoretical slave node clock frequency) • The Baudrate • The oversampling (Over=0 => 16X or Over=0 => 8X) The following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (FSLAVE is the real slave node clock frequency). [ α × 8 × ( 2 – Over ) + β ] × Baudrate Baudrate_deviation = ⎛ 100 × --------------------------------------------------------------------------------------------⎞ % ⎝ ⎠ 8 × F SLAVE ⎛ ⎞ ⎜ [ α × 8 × ( 2 – Over ) + β ] × Baudrate⎟ Baudrate_deviation = ⎜ 100 × --------------------------------------------------------------------------------------------⎟ % F TOL_UNSYNCH ⎜ ⎟ ⎛ -------------------------------------- ⎞ xF 8× ⎝ ⎠ ⎝ ⎠ Nom 100 – 0.5 ≤ α ≤ +0.5 -1 < β < +1 FTOL_UNSYNCH is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard imposes that it must not exceed ±15%. The LIN Standard imposes also that for communication between two nodes, their bit rate must not differ by more than ±2%. This means that the Baudrate_deviation must not exceed ±1%. It follows from that, a minimum value for the nominal clock frequency: 584 32072C–AVR32–2010/03 AT32UC3A3/A4 ⎛ ⎞ ⎜ [ 0.5 × 8 × ( 2 – Over ) + 1 ] × Baudrate⎟ F NOM ( min ) = ⎜ 100 × ----------------------------------------------------------------------------------------------- ⎟ Hz – 15 ⎜ ⎟ 8 × ⎛ --------- + 1⎞ × 1% ⎝ ⎠ ⎝ 100 ⎠ Examples: • Baudrate = 20 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 2.64 MHz • Baudrate = 20 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 1.47 MHz • Baudrate = 1 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 132 kHz • Baudrate = 1 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 74 kHz If the fractional baud rate is not used, the accuracy of the synchronization becomes much lower. When the counter is stopped, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (CD). This value is rounded by adding the first insignificant bit. The equation of the Baudrate deviation is the same as given above, but the constants are as follows: – 4 ≤ α ≤ +4 -1 < β < +1 It follows from that, a minimum value for the nominal clock frequency: ⎛ ⎞ ⎜ [ 4 × 8 × ( 2 – Over ) + 1 ] × Baudrate⎟ F (min) = ⎜ 100 × ------------------------------------------------------------------------------------------ ⎟ Hz NOM – 15 ⎜ ⎟ 8 × ⎛ --------- + 1⎞ × 1% ⎝ ⎠ ⎝ 100 ⎠ Examples: • Baudrate = 20 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 19.12 MHz • Baudrate = 20 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 9.71 MHz • Baudrate = 1 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 956 kHz • Baudrate = 1 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 485 kHz 25.6.9.8 Identifier Parity A protected identifier consists of two sub-fields; the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. The USART interface can generate/check these parity bits, but this feature can also be disabled. The user can choose between two modes by the PARDIS bit of the LIN Mode register (LINMR): • PARDIS = 0: During header transmission, the parity bits are computed and sent with the 6 least significant bits of the IDCHR field of the LIN Identifier register (LINIR). The bits 6 and 7 of this register are discarded. During header reception, the parity bits of the identifier are checked. If the parity bits are wrong, an Identifier Parity error occurs (see Section 25.6.3.8). Only the 6 least significant bits of the IDCHR field are updated with the received Identifier. The bits 6 and 7 are stuck at 0. • PARDIS = 1: During header transmission, all the bits of the IDCHR field of the LIN Identifier register (LINIR) are sent on the bus. During header reception, all the bits of the IDCHR field are updated with the received Identifier. 585 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.9.9 Node Action In function of the identifier, the node is concerned, or not, by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations: • PUBLISH: the node sends the response. • SUBSCRIBE: the node receives the response. • IGNORE: the node is not concerned by the response, it does not send and does not receive the response. This configuration is made by the field, Node Action (NACT), in the LINMR register (see Section 25.7.16). Example: a LIN cluster that contains a Master and two Slaves: • Data transfer from the Master to the Slave 1 and to the Slave 2: NACT(Master)=PUBLISH NACT(Slave1)=SUBSCRIBE NACT(Slave2)=SUBSCRIBE • Data transfer from the Master to the Slave 1 only: NACT(Master)=PUBLISH NACT(Slave1)=SUBSCRIBE NACT(Slave2)=IGNORE • Data transfer from the Slave 1 to the Master: NACT(Master)=SUBSCRIBE NACT(Slave1)=PUBLISH NACT(Slave2)=IGNORE • Data transfer from the Slave1 to the Slave2: NACT(Master)=IGNORE NACT(Slave1)=PUBLISH NACT(Slave2)=SUBSCRIBE • Data transfer from the Slave2 to the Master and to the Slave1: NACT(Master)=SUBSCRIBE NACT(Slave1)=SUBSCRIBE NACT(Slave2)=PUBLISH 586 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.9.10 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1). The user can choose between these two modes by the DLM bit of the LIN Mode register (LINMR): • DLM = 0: the response data length is configured by the user via the DLC field of the LIN Mode register (LINMR). The response data length is equal to (DLC + 1) bytes. DLC can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes. • DLM = 1: the response data length is defined by the Identifier (IDCHR in LINIR) according to the table below. The DLC field of the LIN Mode register (LINMR) is discarded. The response can contain 2 or 4 or 8 data bytes. Table 25-14. Response Data Length if DLM = 1 IDCHR[5] 0 0 1 1 IDCHR[4] 0 1 0 1 Response Data Length [bytes] 2 2 4 8 Figure 25-43. Response Data Length User configuration: 1 - 256 data fields (DLC+1) Identifier configuration: 2/4/8 data fields Sync Break Sync Field Identifier Field Data Field Data Field Data Field Data Field Checksum Field 587 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.9.11 Checksum The last field of a frame is the checksum. The checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic checksum and it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves. The USART can be configured to: • Send/Check an Enhanced checksum automatically (CHKDIS = 0 & CHKTYP = 0) • Send/Check a Classic checksum automatically (CHKDIS = 0 & CHKTYP = 1) • Not send/check a checksum (CHKDIS = 1) This configuration is made by the Checksum Type (CHKTYP) and Checksum Disable (CHKDIS) fields of the LIN Mode register (LINMR). If the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see Section 25.6.9.10). 588 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.9.12 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to TFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum. If the Frame Slot Mode is disabled (FSDIS = 1) and a frame transfer has been completed, the TXRDY flag is set again immediately. The TFrame_Maximum is calculated as below: If the Checksum is sent (CHKDIS = 0): • THeader_Nominal = 34 x TBit • TResponse_Nominal = 10 x (NData + 1) x TBit • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)(Note:) • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1) x TBIT • TFrame_Maximum = (77 + 14 x DLC) x TBIT If the Checksum is not sent (CHKDIS = 1): • THeader_Nominal = 34 x TBit • TResponse_Nominal = 10 x NData x TBit • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1(Note:)) • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1) x TBIT • TFrame_Maximum = (63 + 14 x DLC) x TBIT Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3) Figure 25-44. Frame Slot Mode Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY Frame Slot Mode Frame Slot Mode Disabled Enabled Write LINID Write THR LINTC Data 1 Data 2 Data 3 Data N 589 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.10 25.6.10.1 LIN Errors Bit Error This error is generated when the USART is transmitting and if the transmitted value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is aborted at the next byte border. 25.6.10.2 Inconsistent Synch Field Error This error is generated in Slave node configuration if the Synch Field character received is other than 0x55. Parity Error This error is generated if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). 25.6.10.4 Checksum Error This error is set if the received checksum is wrong. This error can be generated only if the checksum feature is enabled (CHKDIS = 0). Slave Not Responding Error This error is set when the USART expects a response from another node (NACT = SUBSCRIBE) but no valid message appears on the bus within the time frame given by the maximum length of the message frame, TFrame_Maximum (see Section 25.6.9.12). This error is disabled if the USART does not expect any message (NACT = PUBLISH or NACT = IGNORE). 25.6.10.3 25.6.10.5 590 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.11 25.6.11.1 LIN Frame Handling Master Node Configuration • Write TXEN and RXEN in CR to enable both the transmitter and the receiver. • Write MODE in MR to select the LIN mode and the Master Node configuration. • Write CD and FP in BRGR to configure the baud rate. • Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FSDIS and DLC in LINMR to configure the frame transfer. • Check that TXRDY in CSR is set to “1” • Write IDCHR in LINIR to send the header What comes next depends on the NACT configuration: • Case 1: NACT = PUBLISH, the USART sends the response – Wait until TXRDY in CSR rises – Write TCHR in THR to send a byte – If all the data have not been written, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors • Case 2: NACT = SUBSCRIBE, the USART receives the response – Wait until RXRDY in CSR rises – Read RCHR in RHR – If all the data have not been read, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors • Case 3: NACT = IGNORE, the USART is not concerned by the response – Wait until LINTC in CSR rises – Check the LIN errors 591 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-45. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Data3 Response space Interframe space Response Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 RXRDY Write LINIR Write THR LINTC Data 1 Data 2 Data 3 Data N FSDIS=0 Figure 25-46. Master Node Configuration, NACT=SUBSCRIBE Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Read RHR LINTC Data 1 Data N-2 Data N-1 Data N 592 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-47. Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 RXRDY Write LINIR LINTC FSDIS=0 25.6.11.2 Slave Node Configuration • Write TXEN and RXEN in CR to enable both the transmitter and the receiver. • Write MODE in MR to select the LIN mode and the Slave Node configuration. • Write CD and FP in BRGR to configure the baud rate. • Wait until LINID in CSR rises • Check LINISFE and LINPE errors • Read IDCHR in RHR • Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in LINMR to configure the frame transfer. IMPORTANT: if the NACT configuration for this frame is PUBLISH, the US_LINMR register, must be write with NACT=PUBLISH even if this field is already correctly configured, that in order to set the TXREADY flag and the corresponding Peripheral DMA Controller write transfer request. What comes next depends on the NACT configuration: • Case 1: NACT = PUBLISH, the USART sends the response – Wait until TXRDY in CSR rises – Write TCHR in THR to send a byte – If all the data have not been written, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors • Case 2: NACT = SUBSCRIBE, the USART receives the response – Wait until RXRDY in CSR rises – Read RCHR in RHR – If all the data have not been read, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors 593 32072C–AVR32–2010/03 AT32UC3A3/A4 • Case 3: NACT = IGNORE, the USART is not concerned by the response – Wait until LINTC in CSR rises – Check the LIN errors Figure 25-48. Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Write THR LINTC Data 1 Data 2 Data 3 Data N Figure 25-49. Slave Node Configuration, NACT = SUBSCRIBE Break TXRDY RXRDY LINIDRX Read LINID Read RHR LINTC Data 1 Data N-2 Data N-1 Data N Synch Protected Identifier Data 1 Data N-1 Data N Checksum Figure 25-50. Slave Node Configuration, NACT = IGNORE Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Read RHR LINTC 594 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.12 LIN Frame Handling With The Peripheral DMA Controller The USART can be used in association with the Peripheral DMA Controller in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. The Peripheral DMA Controller uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The Peripheral DMA Controller always writes in the Transmit Holding register (THR) and it always reads in the Receive Holding register (RHR). The size of the data written or read by the Peripheral DMA Controller in the USART is always a byte. 25.6.12.1 Master Node Configuration The user can choose between two Peripheral DMA Controller modes by the PDCM bit in the LIN Mode register (LINMR): • PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the Peripheral DMA Controller in the Transmit Holding register THR (instead of the LIN Mode register LINMR). Because the Peripheral DMA Controller transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is written. • PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the LIN Mode register (LINMR). The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT = PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE). Figure 25-51. Master Node with Peripheral DMA Controller (PDCM=1) WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS DLC DLC Peripheral bus IDENTIFIER NODE ACTION = PUBLISH IDENTIFIER Peripheral bus NODE ACTION = SUBSCRIBE Peripheral DMA Controller DATA 0 RXRDY USART LIN CONTROLLER READ BUFFER Peripheral DMA Controller RXRDY TXRDY USART LIN CONTROLLER DATA 0 | | | | | | | | DATA N DATA N 595 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 25-52. Master Node with Peripheral DMA Controller (PDCM=0) WRITE BUFFER DATA 0 NODE ACTION = PUBLISH READ BUFFER USART LIN CONTROLLER RXRDY DATA 0 Peripheral DMA Controller RXRDY TXRDY | | | | DATA N USART LIN CONTROLLER NODE ACTION = SUBSCRIBE Peripheral bus DATA 1 Peripheral DMA Controller | | | | Peripheral bus DATA N 25.6.12.2 Slave Node Configuration In this configuration, the Peripheral DMA Controller transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (LINIR). The LIN mode must be written by the user in the LIN Mode register (LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE). IMPORTANT: if the NACT configuration for a frame is PUBLISH, the US_LINMR register, must be write with NACT=PUBLISH even if this field is already correctly configured, that in order to set the TXREADY flag and the corresponding Peripheral DMA Controller write transfer request. Figure 25-53. Slave Node with Peripheral DMA Controller WRITE BUFFER DA 0 TA READ BUFFER DATA 0 P eripheral Bus USART LIN CONTROLLER | | | | P eriphe ral bus Peripheral DMA Controller NACT = SUBSCRIBE | | | | Peripheral DMA Controller USART LIN CONTROLLER TXRDY RXRDY DA N TA DA N TA 596 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.13 Wake-up Request Any node in a sleeping LIN cluster may request a wake-up. In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 µs to 5 ms. For this, it is necessary to send the character 0xF0 in order to impose 5 successive dominant bits. Whatever the baud rate is, this character respects the specified timings. • Baud rate min = 1 kbit/s -> Tbit = 1ms -> 5 Tbits = 5 ms • Baud rate max = 20 kbit/s -> Tbi t= 50 µs -> 5 Tbits = 250 µs In the LIN 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose 8 successive dominant bits. The user can choose by the WKUPTYP bit in the LIN Mode register (LINMR) either to send a LIN 2.0 wakeup request (WKUPTYP=0) or to send a LIN 1.3 wakeup request (WKUPTYP=1). A wake-up request is transmitted by writing the Control Register (CR) with the LINWKUP bit at 1. Once the transfer is completed, the LINTC flag is asserted in the Status Register (SR). It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. 597 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.14 Bus Idle Time-out If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. In the LIN 2.0 specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25000 Tbits. In Slave Node configuration, the Receiver Time-out detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver to go into sleep mode. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at 0. Otherwise, the receiver loads a 17-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. If STTTO is performed, the counter clock is stopped until a first character is received. If RETTO is performed, the counter starts counting down immediately from the value TO. Table 25-15. Receiver Time-out programming LIN Specification Baud Rate 1 000 bit/s 2 400 bit/s 2.0 9 600 bit/s 19 200 bit/s 20 000 bit/s 1.3 25 000 Tbits 4s Time-out period TO 4 000 9 600 38 400 76 800 80 000 25 000 598 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.15 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 25.6.15.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 25-54. Normal Mode Configuration RXD Receiver TXD Transmitter 25.6.15.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 25-55. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 25-55. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 25.6.15.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 25-56. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 25-56. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 599 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.15.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 25-57. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 25-57. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 600 32072C–AVR32–2010/03 AT32UC3A3/A4 25.6.16 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register (WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the USART Write Protect Mode Register (WPMR) with the appropriate access key, WPKEY. The protected registers are: • ”Mode Register” on page 605 • ”Baud Rate Generator Register” on page 615 • ”Receiver Time-out Register” on page 616 • ”Transmitter Timeguard Register” on page 617 • ”FI DI RATIO Register” on page 618 • ”IrDA FILTER Register” on page 620 • ”Manchester Configuration Register” on page 621 601 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7 User Interface Table 25-16. USART Register Memory Map Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x0040 0x0044 0x004C 0x0050 0x0054 0x0058 0x00E4 0x00E8 0x00FC Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register FI DI Ratio Register Number of Errors Register IrDA Filter Register Manchester Encoder Decoder Register LIN Mode Register LIN Identifier Register Write Protect Mode Register Write Protect Status Register Version Register Note: Name CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IFR MAN LINMR LINIR WPMR WPSR VERSION Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write Read-write Read-write Read-write Read-only Read-write Read-write Read-write Read-write Read-write Read-only Read-only Reset – 0x00000000 – – 0x00000000 0x00000000 0x00000000 – 0x00000000 0x00000000 0x00000000 0x00000174 0x00000000 0x00000000 0x30011004 0x00000000 0x00000000 0x00000000 0x00000000 0x–(1) 1. Values in the Version Register vary with the version of the IP block implementation. 602 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.1 Name: Control Register CR Write-only 0x0 30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 LINWKUP 13 RSTIT 5 RXDIS 28 – 20 LINABT 12 SENDA 4 RXEN 27 – 19 RTSDIS/RCS 11 STTTO 3 RSTTX 26 – 18 RTSEN/FCS 10 STPBRK 2 RSTRX 25 – 17 DTRDIS 9 STTBRK 1 – 24 – 16 DTREN 8 RSTSTA 0 – Access Type: Offset: Reset Value: 31 – 23 – 15 RETTO 7 TXDIS • LINWKUP: Send LIN Wakeup Signal 0: No effect: 1: Sends a wakeup signal on the LIN bus. LINABT: Abort LIN Transmission 0: No effect. 1: Abort the current LIN transmission. RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select If USART does not operate in SPI Master Mode (MODE … 0xE): 0: No effect. 1: Drives the pin RTS to 1. If USART operates in SPI Master Mode (MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin). RTSEN/FCS: Request to Send Enable/Force SPI Chip Select If USART does not operate in SPI Master Mode (MODE … 0xE): 0: No effect. 1: Drives the pin RTS to 0. If USART operates in SPI Master Mode (MODE = 0xE): FCS = 0: No effect. FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • • • • • • 603 32072C–AVR32–2010/03 AT32UC3A3/A4 • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in CSR. RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in CSR. No effect if the ISO7816 is not enabled. SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the THR is sent with the address bit set. STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in CSR. STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINSFE, LINIPE, LINCE, LINSNRE and RXBRK in CSR. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • • • • • • • • • • • • 604 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.2 Name: Mode Register MR Read-write 0x4 30 MODSYNC 22 VAR_SYNC 14 CHMODE 7 CHRL 6 5 USCLKS 29 MAN 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Access Type: Offset: Reset Value: 31 ONEBIT 23 – 15 18 CLKO 10 PAR 2 MODE 16 MSBF/CPOL 8 SYNC/CPHA 0 1 This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register(if exists). • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit. MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into THR register. DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • • • • • • • • 605 32072C–AVR32–2010/03 AT32UC3A3/A4 • CLKO: Clock Output Select 0: The USART does not drive the CLK pin. 1: The USART drives the CLK pin if USCLKS does not select the external clock CLK. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • MSBF/CPOL: Bit Order or SPI Clock Polarity If USART does not operate in SPI Mode (MODE … 0xE and 0xF): MSBF = 0: Least Significant Bit is sent/received first. MSBF = 1: Most Significant Bit is sent/received first. If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF): CPOL = 0: The inactive state value of SPCK is logic level zero. CPOL = 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices. • CHMODE: Channel Mode Table 25-17. CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • NBSTOP: Number of Stop Bits Table 25-18. NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved • PAR: Parity Type Table 25-19. PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode • SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase If USART does not operate in SPI Mode (MODE is … 0xE and 0xF): 606 32072C–AVR32–2010/03 AT32UC3A3/A4 SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode. If USART operates in SPI Mode (MODE = 0xE or 0xF): CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CHRL: Character Length. Table 25-20. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits • USCLKS: Clock Selection Table 25-21. USCLKS 0 0 1 1 0 1 0 1 Note: Selected Clock CLK_USART CLK_USART/DIV(1) Reserved CLK 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter. • MODE Table 25-22. MODE 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 Others 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 1 0 1 Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 IS07816 Protocol: T = 1 IrDA LIN Master LIN Slave SPI Master SPI Slave Reserved 607 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.3 Name: Interrupt Enable Register IER Write-only 0x8 30 – 22 – 14 LINiD 6 FRAME 29 LINSNRE 21 – 13 NACK/LINBK 5 OVRE 28 LINCE 20 MANE 12 RXBUFF 4 – 27 LINIPE 19 CTSIC 11 – 3 – 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANEA 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 – 23 – 15 LINTC 7 PARE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has the same effect. 608 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.4 Name: Interrupt Disable Register IDR Write-only 0xC 30 – 22 – 14 LINID 6 FRAME 29 LINSNRE 21 – 13 NACK/LINBK 5 OVRE 28 LINCE 20 MANE 12 RXBUFF 4 – 27 LINIPE 19 CTSIC 11 – 3 – 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANEA 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 – 23 – 15 LINTC 7 PARE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has the same effect. 609 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.5 Name: Interrupt Mask Register IMR Read-only 0x10 30 – 22 – 14 LINID 6 FRAME 29 LINSNRE 21 – 13 NACK/LINBK 5 OVRE 28 LINCE 20 MANE 12 RXBUFF 4 – 27 LINIPE 19 CTSIC 11 – 3 – 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANEA 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 – 23 – 15 LINTC 7 PARE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Reading either one or the other has the same effect. 25.7.6 Name: Channel Status Register CSR Read-only 0x14 30 – 22 DCD 14 LINID 6 FRAME 29 LINSNRE 21 DSR 13 NACK/LINBK 5 OVRE 28 LINCE 20 RI 12 RXBUFF 4 – 27 LINIPE 19 CTSIC 11 – 3 – 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANERR 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 – 23 CTS 15 LINTC 7 PARE • LINSNRE: LIN Slave Not Responding Error 0: No LIN Slave Not Responding Error has been detected since the last RSTSTA. 610 32072C–AVR32–2010/03 AT32UC3A3/A4 1: A LIN Slave Not Responding Error has been detected since the last RSTSTA. • LINCE: LIN Checksum Error 0: No LIN Checksum Error has been detected since the last RSTSTA. 1: A LIN Checksum Error has been detected since the last RSTSTA. LINIPE: LIN Identifier Parity Error 0: No LIN Identifier Parity Error has been detected since the last RSTSTA. 1: A LIN Identifier Parity Error has been detected since the last RSTSTA. LINISFE: LIN Inconsistent Synch Field Error 0: No LIN Inconsistent Synch Field Error has been detected since the last RSTSTA 1: The USART is configured as a Slave node and a LIN Inconsistent Synch Field Error has been detected since the last RSTSTA. LINBE: LIN Bit Error 0: No Bit Error has been detected since the last RSTSTA. 1: A Bit Error has been detected since the last RSTSTA. MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of CSR. 1: At least one input change has been detected on the CTS pin since the last read of CSR. DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of CSR. 1: At least one input change has been detected on the DCD pin since the last read of CSR. DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of CSR. 1: At least one input change has been detected on the DSR pin since the last read of CSR. RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of CSR. 1: At least one input change has been detected on the RI pin since the last read of CSR. LINTC: LIN Transfer Completed 0: The USART is idle or a LIN transfer is ongoing. 1: A LIN transfer has been completed since the last RSTSTA. LINID: LIN Identifier 0: No LIN Identifier received or sent 1: The USART is configured as a Slave node and a LIN Identifier has been received or the USART is configured as a Master node and a LIN Identifier has been sent since the last RSTSTA. NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. • • • • • • • • • • • • • • • 611 32072C–AVR32–2010/03 AT32UC3A3/A4 1: At least one Non Acknowledge has been detected since the last RSTNACK. • RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive Peripheral DMA Controller channel is inactive. 1: The signal Buffer Full from the Receive Peripheral DMA Controller channel is active. ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error If USART does not operate in SPI Slave Mode (MODE … 0xF): ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA. ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA. If USART operates in SPI Slave Mode (MODE = 0xF): UNRE = 0: No SPI underrun error has occurred since the last RSTSTA. UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty 0: There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in THR, nor in the Transmit Shift Register. TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in CR). PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. TXRDY: Transmitter Ready 0: A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the THR. RXRDY: Receiver Ready 0: No complete character has been received since the last read of RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and RHR has not yet been read. • • • • • • • • • 612 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.7 Name: Receive Holding Register RHR Read-only 0x18 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0 Access Type: Offset: Reset Value: 31 – 23 – 15 RXSYNH 7 • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. • RXCHR: Received Character Last character received if RXRDY is set. 613 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.8 Name: USART Transmit Holding Register THR Write-only 0x1C 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0 Access Type: Offset: Reset Value: 31 – 23 – 15 TXSYNH 7 • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 614 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.9 Name: Baud Rate Generator Register BRGR Read-write 0x20 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 25 – 17 FP 9 24 – 16 Access Type: Offset: Reset Value: 31 – 23 – 15 10 8 This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. • CD: Clock Divider Table 25-23. MODE ≠ ISO7816 SYNC = 1 or MODE = SPI (Master or Slave) OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/16/CD Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO MODE = ISO7816 SYNC = 0 CD 0 1 to 65535 OVER = 0 615 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.10 Name: Receiver Time-out Register RTOR Read-write 0x24 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 TO 7 6 5 4 TO 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 TO 8 Access Type: Offset: Reset Value: 31 – 23 – 15 This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 131071: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. Note that the size of the TO counter can change depending of implementation. See the Module Configuration section. 616 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.11 Name: Transmitter Timeguard Register TTGR Read-write 0x28 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 617 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.12 Name: FI DI RATIO Register FIDI Read-write 0x40 0x00000174 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 2 0 This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on CLK divided by FI_DI_RATIO. 618 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.13 Name: Number of Errors Register NER Read-only 0x44 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 619 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.14 Name: IrDA FILTER Register IFR Read-write 0x4C 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IRDA_FILTER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register(if exists). IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 620 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.15 Name: Manchester Configuration Register MAN Read-write 0x50 0x30011004 30 DRIFT 22 – 14 – 6 – 29 1 21 – 13 – 5 – 28 RX_MPOL 20 – 12 TX_MPOL 4 – 27 – 19 26 – 18 RX_PL 11 – 3 10 – 2 TX_PL 9 TX_PP 1 0 8 25 RX_PP 17 16 24 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register(if exists). • DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • RX_PP: Receiver Preamble Pattern detected Table 25-24. RX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (RX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO • RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1 - 15: The detected preamble length is RX_PL x Bit Period • TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. 621 32072C–AVR32–2010/03 AT32UC3A3/A4 • TX_PP: Transmitter Preamble Pattern Table 25-25. TX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO • TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period 622 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.16 Name: LIN Mode Register LINMR Read-write 0x54 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 3 CHKDIS 2 PARDIS 1 NACT 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 PDCM 8 Access Type: Offset: Reset Value: 31 – 23 – 15 • PDCM: Peripheral DMA Controller Mode 0: The LIN mode register LINMR is not written by the Peripheral DMA Controller. 1: The LIN mode register LINMR (excepting that bit) is written by the Peripheral DMA Controller. DLC: Data Length Control 0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes. WKUPTYP: Wakeup Signal Type 0: setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. FSDIS: Frame Slot Mode Disable 0: The Frame Slot Mode is enabled. 1: The Frame Slot Mode is disabled. DLM: Data Length Mode 0: The response data length is defined by the field DLC of this register. 1: The response data length is defined by the bits 4 and 5 of the Identifier (IDCHR in LINIR). CHKTYP: Checksum Type 0: LIN 2.0 “Enhanced” Checksum 1: LIN 1.3 “Classic” Checksum CHKDIS: Checksum Disable 0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the checksum is checked automatically. 1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked. PARDIS: Parity Disable 0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node configuration, the parity is checked automatically. 1:Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked. • • • • • • • 623 32072C–AVR32–2010/03 AT32UC3A3/A4 • NACT: LIN Node Action Table 1. NACT 0 0 1 1 0 1 0 1 Mode Description PUBLISH: The USART transmits the response. SUBSCRIBE: The USART receives the response. IGNORE: The USART does not transmit and does not receive the response. Reserved 624 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.17 Name: LIN Identifier Register LINIR Read-write or Read-only 0x58 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IDCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 • IDCHR: Identifier Character If MODE=0xA (Master node configuration): IDCHR is Read-write and its value is the Identifier character to be transmitted. if MODE=0xB (Slave node configuration): IDCHR is Read-only and its value is the last Identifier character that has been received. 625 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.18 Write Protect Mode Register Register Name: WPMR Access Type: Offset: Reset Value: 31 Read-write 0xE4 See Table 25-16 30 29 28 WPKEY 27 26 25 24 23 22 21 20 WPKEY 19 18 17 16 15 14 13 12 WPKEY 11 10 9 8 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 WPEN • WPKEY: Write Protect KEY Should be written at value 0x555341 ("USA" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x555341 ("USA" in ASCII). Protects the registers: • ”Mode Register” on page 605 • ”Baud Rate Generator Register” on page 615 • ”Receiver Time-out Register” on page 616 • ”Transmitter Timeguard Register” on page 617 • ”FI DI RATIO Register” on page 618 • ”IrDA FILTER Register” on page 620 • ”Manchester Configuration Register” on page 621 626 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.19 Write Protect Status Register Register Name: WPSR Access Type: Offset: Reset Value: 31 — 23 Read-only 0xE8 See Table 25-16 30 — 22 29 — 21 28 — 20 WPVSRC 27 — 19 26 — 18 25 — 17 24 — 16 15 14 13 12 WPVSRC 11 10 9 8 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 WPVS • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the WPSR register. 1 = A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. Note: Reading WPSR automatically clears all fields. 627 32072C–AVR32–2010/03 AT32UC3A3/A4 25.7.20 Name: Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 Version Register VERSION Read-only 0xFC 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 VERSION 27 – 19 26 – 18 VARIANT 11 10 VERSION 3 2 1 0 9 8 25 – 17 24 – 16 • VARIANT Reserved. No functionality associated. • VERSION Version of the module. No functionality associated. 628 32072C–AVR32–2010/03 AT32UC3A3/A4 25.8 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 25-26. Module Configuration Feature SPI Logic LIN Logic Manchester Logic Modem Logic IRDA Logic Fractional Baudrate ISO7816 DIV Receiver Time-out Counter Size USART0 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented 8 8-bits USART1 Implemented Implemented Implemented Implemented Implemented Implemented Implemented 8 17-bits USART2 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented 8 8-bits USART3 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented 8 8-bits Table 25-27. Module Clock Name Module name USART0 USART1 USART2 USART3 Clock name CLK_USART0 CLK_USART1 CLK_USART2 CLK_USART3 Table 25-28. Register Reset Values Module name VERSION Reset Value 0x00000420 629 32072C–AVR32–2010/03 AT32UC3A3/A4 26. Hi-Speed USB On-The-Go Interface (USBB) Rev: 3.2.0.5 26.1 Features • Compatible with the USB 2.0 specification • Supports High (480Mbit/s), Full (12Mbit/s) and Low (1.5Mbit/s) speed communication and On• • • • • • The-Go eight pipes/endpoints 2368 of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint) Flexible Pipe/Endpoint configuration and management with dedicated DMA channels On-Chip UTMI transceiver including Pull-Ups/Pull-downs On-Chip OTG pad including VBUS analog comparator 26.2 Overview The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0 specification, in all speeds. Each pipe/endpoint can be configured in one of several transfer types. It can be associated with one or more banks of a dual-port RAM (DPRAM) used to store the current data payload. If several banks are used (“ping-pong” mode), then one DPRAM bank is read or written by the CPU or the DMA while the other is read or written by the USBB core. This feature is mandatory for isochronous pipes/endpoints. Table 26-1 on page 630 describes the hardware configuration of the USB MCU device. Table 26-1. Description of USB Pipes/Endpoints Mnemonic PEP0 PEP1 PEP2 PEP3 PEP4 PEP5 PEP6 PEP7 Max. Size 64 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes Max. Nb. Banks 1 2 2 2 2 2 2 2 DMA N Y Y Y Y Y Y Y Type Control Isochronous/Bulk/Interrupt/Control Isochronous/Bulk/Interrupt/Control Isochronous/Bulk/Interrupt Isochronous/Bulk/Interrupt/Control Isochronous/Bulk/Interrupt/Control Isochronous/Bulk/Interrupt/Control Isochronous/Bulk/Interrupt/Control Pipe/Endpoint 0 1 2 3 4 5 6 7 The theoretical maximal pipe/endpoint configuration (458752) exceeds the real DPRAM size (2368). The user needs to be aware of this when configuring pipes/endpoints. To fully use the 630 32072C–AVR32–2010/03 AT32UC3A3/A4 2368 of DPRAM, the user could for example use the configuration described inTable 26-2 on page 631. Table 26-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM Mnemonic PEP0 PEP1 PEP2 PEP3 Size 64 bytes 512 bytes 512 bytes 256 bytes Nb. Banks 1 2 2 1 Pipe/Endpoint 0 1 2 3 26.3 Block Diagram The USBB provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM). The UTMI transceiver requires an external 12MHz clock as a reference to its internal 480MHz PLL. The internal 480MHz PLL is used to clock an internal DLL module to recover the USB differential data at 480Mbit/s. Figure 26-1. USBB Block Diagram HSB Slave Slave Local HSB Slave Interface HSB0 DPRAM HSB Mux Master Master DMA HSB1 PEP Allocation OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS PB User Interface USB 2.0 Core I/O Controller UTMI DMHS DPHS GCLK_USBB 631 32072C–AVR32–2010/03 AT32UC3A3/A4 26.4 Application Block Diagram Depending on the USB operating mode (device-only, reduced-host or OTG mode) and the power source (bus-powered or self-powered), there are different typical hardware implementations. 26.4.1 26.4.1.1 Device Mode Bus-Powered device Figure 26-2. Bus-Powered Device Application Block Diagram VDD 3.3 V Regulator OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS USB Connector VBus ID 39 ohms 39 ohms USB 2.0 Core I/O Controller DD+ GND UTMI DMHS DPHS 632 32072C–AVR32–2010/03 AT32UC3A3/A4 26.4.1.2 Self-Powered device Figure 26-3. Self-powered Device Application Block Diagram USB Connector VBus ID 39 ohms 39 ohms OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS USB 2.0 Core I/O Controller DD+ GND UTMI DMHS DPHS 26.4.2 Host and OTG Modes Figure 26-4. Host and OTG Application Block Diagram VDD 5V DC/DC Generator OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS USB Connector VBus ID 39 ohms 39 ohms USB 2.0 Core I/O Controller DD+ GND UTMI DMHS DPHS 633 32072C–AVR32–2010/03 AT32UC3A3/A4 26.5 I/O Lines Description I/O Lines Description Pin Description USB VBus On/Off: Bus Power Control Port VBus: Bus Power Measurement Port FS Data -: Full-Speed Differential Data Line - Port FS Data +: Full-Speed Differential Data Line + Port HS Data -: Hi-Speed Differential Data Line - Port HS Data +: Hi-Speed Differential Data Line + Port USB Identification: Mini Connector Identification Port Type Output Input Input/Output Input/Output Input/Output Input/Output Input Low: Mini-A plug High Z: Mini-B plug Active Level VBUSPO Table 26-3. PIn Name USB_VBOF USB_VBUS DMFS DPFS DMHS DPHS USB_ID 634 32072C–AVR32–2010/03 AT32UC3A3/A4 26.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 26.6.1 I/O Lines The USB_VBOF and USB_ID pins are multiplexed with I/O Controller lines and may also be multiplexed with lines of other peripherals. In order to use them with the USB, the user must first configure the I/O Controller to assign them to their USB peripheral functions. If USB_ID is used, the I/O Controller must be configured to enable the internal pull-up resistor of its pin. If USB_VBOF or USB_ID is not used by the application, the corresponding pin can be used for other purposes by the I/O Controller or by other peripherals. 26.6.2 Clocks The clock for the USBB bus interface (CLK_USBB) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the USBB before disabling the clock, to avoid freezing the USBB in an undefined state. The UTMI transceiver needs a 12MHz clock as a clock reference for its internal 480MHz PLL. Before using the USB, the user must ensure that this 12 MHz clock is available. The 12 MHz input is connected to a Generic Clock (GCLK_USBB) provided by the Power Manager. 26.6.3 Interrupts The USBB interrupt request line is connected to the interrupt controller. Using the USBB interrupt requires the interrupt controller to be programmed first. 635 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7 26.7.1 26.7.1.1 Functional Description USB General Operation Introduction After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device mode or in host mode according to the ID detection. If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by the I/O Controller) and device mode is engaged. The USBSTA.ID bit is cleared when a low level has been detected on the USB_ID pin. Host mode is then engaged. 26.7.1.2 Power-On and reset Figure 26-5 on page 636 describes the USBB main states. Figure 26-5. General States Macro off: USBE = 0 Clock stopped: FRZCLK = 1 USBE = 0 Reset HW RESET USBE = 1 ID = 1 USBE = 0 USBE = 1 ID = 0 USBE = 0 Device Host After a hardware reset, the USBB is in the Reset state. In this state: • The macro is disabled. The USBB Enable bit in the General Control register (USBCON.USBE) is zero. • The macro clock is stopped in order to minimize power consumption. The Freeze USB Clock bit in USBCON (USBON.FRZCLK) is set. • The UTMI is in suspend mode. • The internal states and registers of the device and host modes are reset. • The DPRAM is not cleared and is accessible. • The USBSTA.ID bit and the VBus Level bit in the UBSTA (UBSTA.VBUS) reflect the states of the USB_ID and USB_VBUS input pins. • The OTG Pad Enable (OTGPADE) bit, the VBus Polarity (VBUSPO) bit, the FRZCLK bit, the USBE bit, the USB_ID Pin Enable (UIDE) bit, the USBB Mode (UIMOD) bit in USBCON, and the Low-Speed Mode Force bit in the Device General Control (UDCON.LS) register can be written by software, so that the user can program pads and speed before enabling the macro, but their value is only taken into account once the macro is enabled and unfrozen. 636 32072C–AVR32–2010/03 AT32UC3A3/A4 After writing a one to USBCON.USBE, the USBB enters the Device or the Host mode (according to the ID detection) in idle state. The USBB can be disabled at any time by writing a zero to USBCON.USBE. In fact, writing a zero to USBCON.USBE acts as a hardware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, UIMOD and, LS bits are not reset. 26.7.1.3 Interrupts One interrupt vector is assigned to the USB interface. Figure 26-6 on page 638 shows the structure of the USB interrupt system. 637 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 26-6. Interrupt System USBSTA.IDTI USBCON.IDTE USBSTA.VBUSTI USBCON.VBUSTE UESTAX.TXINI UECONX.TXINE UESTAX.RXOUTI UECONX.RXOUTE UESTAX.RXSTPI UECONX.RXSTPE UESTAX.UNDERFI UECONX.UNDERFE UESTAX.NAKOUTI UECONX.NAKOUTE UESTAX.HBISOINERRI UECONX.HBISOINERRE UESTAX.NAKINI UECONX.NAKINE UESTAX.HBISOFLUSHI UECONX.HBISOFLUSHE UESTAX.OVERFI UECONX.OVERFE UESTAX.STALLEDI UECONX.STALLEDE UESTAX.CRCERRI UECONX.CRCERRE UESTAX.SHORTPACKET UECONX.SHORTPACKETE UESTAX.DTSEQ=MDATA & UESTAX.RXOUTI UECONX.MDATAE UESTAX.DTSEQ=DATAX & UESTAX.RXOUTI UECONX.DATAXE UESTAX.TRANSERR UECONX.TRANSERRE UESTAX.NBUSYBK UECONX.NBUSYBKE UDINT.WAKEUP UDINTE.WAKEUPE UDINT.EORSM UDINTE.EORSME UDINT.UPRSM UDDMAX_STATUS.EOT_STA UDDMAX_CONTROL.EOT_IRQ_EN UDDMAX_STATUS.EOCH_BUFF_STA UDDMAX_CONTROL.EOBUFF_IRQ_EN UDDMAX_STATUS.DESC_LD_STA UDDMAX_CONTROL.DESC_LD_IRQ_EN UPSTAX.RXINI UPCONX.RXINE UPSTAX.TXOUTI UPCONX.TXOUTE UPSTAX.TXSTPI UPCONX.TXSTPE UPSTAX.UNDERFI UPCONX.UNDERFIE UPSTAX.PERRI UPCONX.PERRE UPSTAX.NAKEDI UPCONX.NAKEDE UPSTAX.OVERFI UPCONX.OVERFIE UPSTAX.RXSTALLDI UPCONX.RXSTALLDE UPSTAX.CRCERRI UPCONX.CRCERRE UPSTAX.SHORTPACKETI UPCONX.SHORTPACKETIE UPSTAX.NBUSYBK UPCONX.NBUSYBKE UHDMAX_STATUS.EOT_STA UHDMAX_CONTROL.EOT_IRQ_EN UHDMAX_STATUS.EOCH_BUFF_STA UHDMAX_CONTROL.EOBUFF_IRQ_EN UHDMAX_STATUS.DESC_LD_STA UHDMAX_CONTROL.DESC_LD_IRQ_EN UHINT.DMAXINT USB Host DMA Channel X Interrupt UHINT.HWUPI UHINTE.HWUPIE UHINT.PXINT UHINTE.PXINTE UHINTE.DMAXINTE USB Host Pipe X Interrupt UHINT.RSMEDI UHINTE.RSMEDIE UHINT.RXRSMI UHINTE.RXRSMIE UHINT.HSOFI UHINTE.HSOFIE USB Host Interrupt UHINT.RSTI UHINTE.RSTIE UHINT.DDISCI UHINTE.DDISCIE UHINT.DCONNI UHINTE.DCONNIE USB Device DMA Channel X Interrupt UDINT.DMAXINT UDINTE.DMAXINTE UDINTE.UPRSME UDINT.EPXINT UDINTE.EPXINTE USB Device Interrupt UDINT.EORST UDINTE.EORSTE UDINT.SOF UDINTE.SOFE USB Interrupt UDINT.SUSP UDINTE.SUSPE UDINT.MSOF UDINTE.MSOFE USB Device Endpoint X Interrupt USBSTA.SRPI USBCON.SRPE USBSTA.VBERRI USBCON.VBERRE USBSTA.BCERRI USBCON.BCERRE USBSTA.ROLEEXI USBCON.ROLEEXE USBSTA.HNPERRI USBCON.HNPERRE USBSTA.STOI USBCON.STOE USB General Interrupt Asynchronous interrupt source See Section 26.7.2.19 and Section 26.7.3.13 for further details about device and host interrupts. There are two kinds of general interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). 638 32072C–AVR32–2010/03 AT32UC3A3/A4 The processing general interrupts are: • The ID Transition Interrupt (IDTI) • The VBus Transition Interrupt (VBUSTI) • The SRP Interrupt (SRPI) • The Role Exchange Interrupt (ROLEEXI) The exception general interrupts are: • The VBus Error Interrupt (VBERRI) • The B-Connection Error Interrupt (BCERRI) • The HNP Error Interrupt (HNPERRI) • The Suspend Time-Out Interrupt (STOI) 26.7.1.4 MCU Power modes •Run mode In this mode, all MCU clocks can run, including the USB clock. •Idle mode In this mode, the CPU is halted, i.e. the CPU clock is stopped. The Idle mode is entered whatever the state of the USBB. The MCU wakes up on any USB interrupt. •Frozen mode Same as the Idle mode, except that the HSB module is stopped, so the USB DMA, which is an HSB master, can not be used. Moreover, the USB DMA must be stopped before entering this sleep mode in order to avoid erratic behavior. The MCU wakes up on any USB interrupt. •Standby, Stop, DeepStop and Static modes Same as the Frozen mode, except that the USB generic clock and other clocks are stopped, so the USB macro is frozen. Only the asynchronous USB interrupt sources can wake up the MCU in these modes. The Power Manager (PM) may have to be configured to enable asynchronous wake up from USB. •USB clock frozen In the run, idle and frozen MCU modes, the USBB can be frozen when the USB line is in the suspend mode, by writing a one to the FRZCLK bit, what reduces power consumption. In this case, it is still possible to access the following elements, but only in Run mode: • The OTGPADE, VBUSPO, FRZCLK, USBE, UIDE, UIMOD and LS bits in the USBCON register • The DPRAM (through the USB Pipe/Endpoint n FIFO Data (USBFIFOnDATA) registers, but not through USB bus transfers which are frozen) Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger the USB interrupt: 639 32072C–AVR32–2010/03 AT32UC3A3/A4 • The ID Transition Interrupt (IDTI) • The VBus Transition Interrupt (VBUSTI) • The Wake-up Interrupt (WAKEUP) • The Host Wake-up Interrupt (HWUPI) •USB Suspend mode In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the transceiver is automatically set in suspend mode to reduce the consumption.The 480MHz internal PLL is stopped. The USBSTA.CLKUSABLE bit is cleared. 26.7.1.5 Speed control •Device mode When the USB interface is in device mode, the speed selection (full-speed or high-speed) is performed automatically by the USBB during the USB reset according to the host speed capability. At the end of the USB reset, the USBB enables or disables high-speed terminations and pull-up. It is possible to restraint the USBB to full-speed or low-speed mode by handling the LS and the Speed Configuration (SPDCONF) bits in UDCON. •Host mode When the USB interface is in host mode, internal pull-down resistors are connected on both D+ and D- and the interface detects the speed of the connected device, which is reflected by the Speed Status (SPEED) field in USBSTA. 26.7.1.6 DPRAM management Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the last pipe/endpoint to be allocated). The user shall therefore configure them in the same order. The allocation of a pipe/endpoint n starts when the Endpoint Memory Allocate bit in the Endpoint n Configuration register (UECFGn.ALLOC) is written to one. Then, the hardware allocates a memory area in the DPRAM and inserts it between the n-1 and n+1 pipes/endpoints. The n+1 pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) do not slide. Disabling a pipe, by writing a zero to the Pipe n Enable bit in the Pipe Enable/Reset register (UPRST.PENn), or disabling an endpoint, by writing a zero to the Endpoint n Enable bit in the Endpoint Enable/Reset register (UERST.EPENn), resets neither the UECFGn.ALLOC bit nor its configuration (the Pipe Banks (PBK) field, the Pipe Size (PSIZE) field, the Pipe Token (PTOKEN) field, the Pipe Type (PTYPE) field, the Pipe Endpoint Number (PEPNUM) field, and the Pipe Interrupt Request Frequency (INTFRQ) field in the Pipe n Configuration (UPCFGn) register/the Endpoint Banks (EPBK) field, the Endpoint Size (EPSIZE) field, the Endpoint Direction (EPDIR) field, and the Endpoint Type (EPTYPE) field in UECFGn). To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/endpoint memory window then slides down and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) does not slide. 640 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 26-7 on page 641 illustrates the allocation and reorganization of the DPRAM in a typical example. Figure 26-7. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory Free Memory PEP5 PEP4 PEP3 PEP2 PEP5 PEP4 PEP3 (ALLOC stays at 1) PEP2 PEP5 PEP4 Lost Memory PEP4 PEP2 PEP5 PEP4 PEP3 (larger size) Conflict PEP2 PEP1 PEP0 PEP1 PEP0 PEP1 PEP0 PEP1 PEP0 U(P/E)RST.(E)PENn = 1 U(P/E)CFGn.ALLOC = 1 U(P/E)RST.(E)PEN3 = 0 U(P/E)CFG3.ALLOC = 0 U(P/E)RST.(E)PEN3 = 1 U(P/E)CFG3.ALLOC = 1 Pipes/Endpoints 0..5 Activated Pipe/Endpoint 3 Disabled Pipe/Endpoint 3 Memory Freed Pipe/Endpoint 3 Activated 1. The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order. Each pipe/endpoint then owns a memory area in the DPRAM. 2. The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller. 3. In order to free its memory, its ALLOC bit is written to zero. The pipe/endpoint 4 memory window slides down, but the pipe/endpoint 5 does not move. 4. If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller allocates a memory area after the pipe/endpoint 2 memory area and automatically slides up the pipe/endpoint 4 memory window. The pipe/endpoint 5 does not move and a memory conflict appears as the memory windows of the pipes/endpoints 4 and 5 overlap. The data of these pipes/endpoints is potentially lost. Note that: • There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as memory allocation and de-allocation may affect only higher pipes/endpoints. • Deactivating then reactivating a same pipe/endpoint with the same configuration only modifies temporarily the controller DPRAM pointer and size for this pipe/endpoint, but nothing changes in the DPRAM, so higher endpoints seem to not have been moved and their data is preserved as far as nothing has been written or received into them while changing the allocation state of the first pipe/endpoint. • When the user write a one to the ALLOC bit, the Configuration OK Status bit in the Endpoint n Status register (UESTAn.CFGOK) is set only if the configured size and number of banks are correct compared to their maximal allowed values for the endpoint and to the maximal FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory allocation conflicts. 641 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.1.7 Pad Suspend Figure 26-8 on page 642 shows the pad behavior. Figure 26-8. Pad Behavior Idle USBE = 1 & DETACH = 0 & Suspend USBE = 0 | DETACH = 1 | Suspend Active • In the Idle state, the pad is put in low power consumption mode, i.e., the differential receiver of the USB pad is off, and internal pull-down with strong value(15K) are set in both DP/DM to avoid floating lines. • In the Active state, the pad is working. Figure 26-9 on page 642 illustrates the pad events leading to a PAD state change. Figure 26-9. Pad Events SUSP Suspend detected Cleared on wake-up WAKEUP Wake-up detected Cleared by software to acknowledge the interrupt PAD State Active Idle Active The SUSP bit is set and the Wake-Up Interrupt (WAKEUP) bit in UDINT is cleared when a USB “Suspend” state has been detected on the USB bus. This event automatically puts the USB pad in the Idle state. The detection of a non-idle event sets WAKEUP, clears SUSP and wakes up the USB pad. Moreover, the pad goes to the Idle state if the macro is disabled or if the DETACH bit is written to one. It returns to the Active state when USBE is written to one and DETACH is written to zero. 642 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.1.8 Customizing of OTG timers It is possible to refine some OTG timers thanks to the Timer Page (TIMPAGE) and Timer Value (TIMVALUE) fields in USBCON, as shown by Table 26-4 on page 643. Customizing of OTG Timers TIMPAGE 0b00 AWaitVrise Time-Out (see OTG Standard(1) Section 6.6.5.1) TIMVALUE 00b 01b 10b 11b 20 ms 50 ms 70 ms 100 ms 0b01 VbBusPulsing Time-Out (see OTG Standard(1) Section5.3.4) 15 ms 23 ms 31 ms 40 ms 0b10 PdTmOutCnt Time-Out (see OTG Standard(1) Section 5.3.2) 93 ms 105 ms 118 ms 131 ms 0b11 SRPDetTmOut Time-Out (see OTG Standard(1) Section 5.3.3) 10 µs 100 µs 1 ms 11 ms Table 26-4. Note: 1. “On-The-Go Supplement to the USB 2.0 Specification Revision 1.0a”. TIMPAGE is used to select the OTG timer to access while TIMVALUE indicates the time-out value of the selected timer. TIMPAGE and TIMVALUE can be read or written. Before writing them, the user shall unlock write accesses by writing a one to the Timer Access Unlock (UNLOCK) bit in USBCON. This is not required for read accesses, except before accessing TIMPAGE if it has to be written in order to read the TIMVALUE field of another OTG timer. 26.7.1.9 Plug-In detection The USB connection is detected from the USB_VBUS pad. Figure 26-10 on page 643 shows the architecture of the plug-in detector. Figure 26-10. Plug-In Detection Input Block Diagram VDD VBus_pulsing RPU Session_valid Logic USB_VBUS RPD Va_Vbus_valid VBUS USBSTA VBUSTI USBSTA VBus_discharge GND Pad Logic The control logic of the USB_VBUS pad outputs two signals: • The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 1.4V. • The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 4.4V. In device mode, the USBSTA.VBUS bit follows the Session_valid comparator output: 643 32072C–AVR32–2010/03 AT32UC3A3/A4 • It is set when the voltage on the USB_VBUS pad is higher than or equal to 1.4V. • It is cleared when the voltage on the VBUS pad is lower than 1.4V. In host mode, the USBSTA.VBUS bit follows an hysteresis based on Session_valid and Va_Vbus_valid: • It is set when the voltage on the USB_VBUS pad is higher than or equal to 4.4V. • It is cleared when the voltage on the USB_VBUS pad is lower than 1.4V. The VBus Transition interrupt (VBUSTI) bit in USBSTA is set on each transition of the USBSTA.VBUS bit. The USBSTA.VBUS bit is effective whether the USBB is enabled or not. 26.7.1.10 ID detection Figure 26-11 on page 644 shows how the ID transitions are detected. Figure 26-11. ID Detection Input Block Diagram VDD RPU 1 USB_ID 0 ID USBSTA IDTI USBSTA UIMOD USBCON UIDE USBCON I/O Controller The USB mode (device or host) can be either detected from the USB_ID pin or software selected by writing to the UIMOD bit, according to the UIDE bit. This allows the USB_ID pin to be used as a general purpose I/O pin even when the USB interface is enabled. By default, the USB_ID pin is selected (UIDE is written to one) and the USBB is in device mode (UBSTA.ID is one), what corresponds to the case where no Mini-A plug is connected, i.e. no plug or a Mini-B plug is connected and the USB_ID pin is kept high by the internal pull-up resistor from the I/O Controller (which must be enabled if USB_ID is used). The ID Transition Interrupt (IDTI) bit in USBSTA is set on each transition of the ID bit, i.e. when a Mini-A plug (host mode) is connected or disconnected. This does not occur when a Mini-B plug (device mode) is connected or disconnected. The USBSTA.ID bit is effective whether the USBB is enabled or not. 644 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.2 26.7.2.1 USB Device Operation Introduction In device mode, the USBB supports hi- full- and low-speed data transfers. In addition to the default control endpoint, seven endpoints are provided, which can be configured with the types isochronous, bulk or interrupt, as described in .Table 26-1 on page 630. The device mode starts in the Idle state, so the pad consumption is reduced to the minimum. 26.7.2.2 Power-On and reset Figure 26-12 on page 645 describes the USBB device mode main states. Figure 26-12. Device Mode States USBE = 0 | ID = 0 USBE = 0 | ID = 0 Reset HW RESET USBE = 1 & ID = 1 Idle After a hardware reset, the USBB device mode is in the Reset state. In this state: • The macro clock is stopped in order to minimize power consumption (FRZCLK is written to one). • The internal registers of the device mode are reset. • The endpoint banks are de-allocated. • Neither D+ nor D- is pulled up (DETACH is written to one). D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written to zero and VBus is present. See “Device mode” for further details. When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode state goes to the Idle state with minimal power consumption. This does not require the USB clock to be activated. The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing a zero to USBE) or when host mode is engaged (ID is zero). 26.7.2.3 USB reset The USB bus reset is managed by hardware. It is initiated by a connected host. When a USB reset is detected on the USB line, the following operations are performed by the controller: • All the endpoints are disabled, except the default control endpoint. 645 32072C–AVR32–2010/03 AT32UC3A3/A4 • The default control endpoint is reset (see Section 26.7.2.4 for more details). • The data toggle sequence of the default control endpoint is cleared. • At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set. • During a reset, the USBB automatically switches to the Hi-Speed mode if the host is HiSpeed capable (the reset is called a Hi-Speed reset). The user should observe the USBSTA.SPEED field to know the speed running at the end of the reset (EORST is one). 26.7.2.4 Endpoint reset An endpoint can be reset at any time by writing a one to the Endpoint n Reset (EPRSTn) bit in the UERST register. This is recommended before using an endpoint upon hardware reset or when a USB bus reset has been received. This resets: • The internal state machine of this endpoint. • The receive and transmit bank FIFO counters. • All the registers of this endpoint (UECFGn, UESTAn, the Endpoint n Control (UECONn) register), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and the Data Toggle Sequence (DTSEQ) field of the UESTAn register. Note that the interrupt sources located in the UESTAn register are not cleared when a USB bus reset has been received. The endpoint configuration remains active and the endpoint is still enabled. The endpoint reset may be associated with a clear of the data toggle sequence as an answer to the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data Toggle Set bit in the Endpoint n Control Set register (UECONnSET.RSTDTS).(This will set the Reset Data Toggle (RSTD) bit in UECONn). In the end, the user has to write a zero to the EPRSTn bit to complete the reset operation and to start using the FIFO. 26.7.2.5 Endpoint activation The endpoint is maintained inactive and reset (see Section 26.7.2.4 for more details) as long as it is disabled (EPENn is written to zero). DTSEQ is also reset. The algorithm represented on Figure 26-13 on page 647 must be followed in order to activate an endpoint. 646 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 26-13. Endpoint Activation Algorithm Endpoint Activation Enable the endpoint. Configure the endpoint: - type - direction - size - number of banks Allocate the configured DPRAM banks. Test if the endpoint configuration is correct. No EPENn = 1 UECFGn EPTYPE EPDIR EPSIZE EPBK ALLOC CFGOK == 1? Yes Endpoint Activated ERROR As long as the endpoint is not correctly configured (CFGOK is zero), the controller does not acknowledge the packets sent by the host to this endpoint. The CFGOK bit is set only if the configured size and number of banks are correct compared to their maximal allowed values for the endpoint (see Table 26-1 on page 630) and to the maximal FIFO size (i.e. the DPRAM size). See Section 26.7.1.6 for more details about DPRAM management. 26.7.2.6 Address setup The USB device address is set up according to the USB protocol. • After all kinds of resets, the USB device address is 0. • The host starts a SETUP transaction with a SET_ADDRESS(addr) request. • The user write this address to the USB Address (UADD) field in UDCON, and write a zero to the Address Enable (ADDEN) bit in UDCON, so the actual address is still 0. • The user sends a zero-length IN packet from the control endpoint. • The user enables the recorded USB device address by writing a one to ADDEN. Once the USB device address is configured, the controller filters the packets to only accept those targeting the address stored in UADD. UADD and ADDEN shall not be written all at once. UADD and ADDEN are cleared: • On a hardware reset. • When the USBB is disabled (USBE written to zero). • When a USB reset is detected. When UADD or ADDEN is cleared, the default device address 0 is used. 647 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.2.7 Suspend and wake-up When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP) interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power consumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power consumption. To recover from the Suspend mode, the user shall wait for the Wake-Up (WAKEUP) interrupt bit, which is set when a non-idle event is detected, then write a zero to FRZCLK. As the WAKEUP interrupt bit in UDINT is set when a non-idle event is detected, it can occur whether the controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are thus independent of each other except that one bit is cleared when the other is set. 26.7.2.8 Detach The reset value of the DETACH bit is one. It is possible to initiate a device re-enumeration simply by writing a one then a zero to DETACH. DETACH acts on the pull-up connections of the D+ and D- pads. See “Device mode” for further details. 26.7.2.9 Remote wake-up The Remote Wake-Up request (also known as Upstream Resume) is the only one the device may send on its own initiative, but the device should have beforehand been allowed to by a DEVICE_REMOTE_WAKEUP request from the host. • First, the USBB must have detected a “Suspend” state on the bus, i.e. the Remote Wake-Up request can only be sent after a SUSP interrupt has been set. • The user may then write a one to the Remote Wake-Up (RMWKUP) bit in UDCON to send an upstream resume to the host for a remote wake-up. This will automatically be done by the controller after 5ms of inactivity on the USB bus. • When the controller sends the upstream resume, the Upstream Resume (UPRSM) interrupt is set and SUSP is cleared. • RMWKUP is cleared at the end of the upstream resume. • If the controller detects a valid “End of Resume” signal from the host, the End of Resume (EORSM) interrupt is set. 26.7.2.10 STALL request For each endpoint, the STALL management is performed using: • The STALL Request (STALLRQ) bit in UECONn to initiate a STALL request. • The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has been sent. To answer the next request with a STALL handshake, STALLRQ has to be set by writing a one to the STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOUTI, etc. will not be set) and handshaked with a STALL until the STALLRQ bit is cleared, what is done when a new SETUP packet is received (for control endpoints) or when the STALL Request Clear (STALLRQC) bit is written to one. Each time a STALL handshake is sent, the STALLEDI bit is set by the USBB and the EPnINT interrupt is set. 648 32072C–AVR32–2010/03 AT32UC3A3/A4 •Special considerations for control endpoints If a SETUP packet is received into a control endpoint for which a STALL is requested, the Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are cleared. The SETUP has to be ACKed. This management simplifies the enumeration process management. If a command is not supported or contains an error, the user requests a STALL and can return to the main task, waiting for the next SETUP request. •STALL handshake and retry mechanism The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the STALLRQ bit is set and if there is no retry required. 26.7.2.11 Management of control endpoints •Overview A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set, but not the Received OUT Data Interrupt (RXOUTI) bit. The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these endpoints. When read, their value are always zero. Control endpoints are managed using: • The RXSTPI bit which is set when a new SETUP packet is received and which shall be cleared by firmware to acknowledge the packet and to free the bank. • The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared by firmware to acknowledge the packet and to free the bank. • The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to accept a new IN packet and which shall be cleared by firmware to send the packet. •Control write Figure 26-14 on page 650 shows a control write transaction. During the status stage, the controller will not necessarily send a NAK on the first IN token: • If the user knows the exact number of descriptor bytes that must be read, it can then anticipate the status stage and send a zero-length packet after the next IN token. • Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the bytes have been sent by the host and that the transaction is now in the status stage. 649 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 26-14. Control Write SETUP USB Bus RXSTPI RXOUTI TXINI SETUP HW SW DATA OUT OUT IN NAK STATUS IN HW SW HW SW SW •Control read Figure 26-15 on page 650 shows a control read transaction. The USBB has to manage the simultaneous write requests from the CPU and the USB host. Figure 26-15. Control Read SETUP USB Bus RXSTPI RXOUTI TXINI Wr Enable HOST Wr Enable CPU SW HW DATA IN SW STATUS IN OUT NAK OUT SETUP HW HW SW SW A NAK handshake is always generated on the first status stage command. When the controller detects the status stage, all the data written by the CPU are lost and clearing TXINI has no effect. The user checks if the transmission or the reception is complete. The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the following software algorithm: set TXINI wait for RXOUTI OR TXINI if RXOUTI, then clear bit and return if TXINI, then continue Once the OUT status stage has been received, the USBB waits for a SETUP request. The SETUP request has priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO reset when a SETUP is received. The user has to take care of the fact that the byte counter is reset when a zero-length OUT packet is received. 650 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.2.12 Management of IN endpoints •Overview IN packets are sent by the USB device controller upon IN requests from the host. All the data can be written which acknowledges or not the bank when it is full. The endpoint must be configured first. The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one. TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then writes into the FIFO and write a one to the FIFO Control Clear (FIFOCONC) bit in UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are updated in accordance with the status of the next bank. TXINI shall always be cleared before clearing FIFOCON. The RWALL bit is set when the current bank is not full, i.e. the software can write further data into the FIFO. Figure 26-16. Example of an IN Endpoint with 1 Data Bank NAK IN DATA (bank 0) ACK IN HW TXINI SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 0 SW Figure 26-17. Example of an IN Endpoint with 2 Data Banks IN DATA (bank 0) ACK IN DATA (bank 1) ACK HW TXINI SW SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 1 SW write data to CPU BANK0 651 32072C–AVR32–2010/03 AT32UC3A3/A4 •Detailed description The data is written, following the next flow: • When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if TXINE is one. • The user acknowledges the interrupt by clearing TXINI. • The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data (USBFIFOnDATA) register, until all the data frame is written or the bank is full (in which case RWALL is cleared and the Byte Count (BYCT) field in UESTAn reaches the endpoint size). • The user allows the controller to send the bank and switches to the next bank (if any) by clearing FIFOCON. If the endpoint uses several banks, the current one can be written while the previous one is being read by the host. Then, when the user clears FIFOCON, the following bank may already be free and TXINI is set immediately. An “Abort” stage can be produced when a zero-length OUT packet is received during an IN stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is used to kill the last written bank. The best way to manage this abort is to apply the algorithm represented on Figure 26-18 on page 652. Figure 26-18. Abort Algorithm Endpoint Abort TXINEC = 1 Disable the TXINI interrupt. NBUSYBK == 0? Yes EPRSTn = 1 No Abort is based on the fact that no bank is busy, i.e., that nothing has to be sent KILLBKS = 1 Kill the last written bank. Yes KILLBK == 1? No Wait for the end of the procedure Abort Done 26.7.2.13 Management of OUT endpoints •Overview OUT packets are sent by the host. All the data can be read which acknowledges or not the bank when it is empty. The endpoint must be configured first. 652 32072C–AVR32–2010/03 AT32UC3A3/A4 The RXOUTI bit is set at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is one. RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear (RXOUTIC) bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are updated in accordance with the status of the next bank. RXOUTI shall always be cleared before clearing FIFOCON. The RWALL bit is set when the current bank is not empty, i.e. the software can read further data from the FIFO. Figure 26-19. Example of an OUT Endpoint with one Data Bank OUT DATA (bank 0) ACK NAK OUT DATA (bank 0) ACK HW RXOUTI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 0 Figure 26-20. Example of an OUT Endpoint with two Data Banks OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW RXOUTI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 1 •Detailed description The data is read, following the next flow: • When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT interrupt if RXOUTE is one. • The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI. 653 32072C–AVR32–2010/03 AT32UC3A3/A4 • The user can read the byte count of the current bank from BYCT to know how many bytes to read, rather than polling RWALL. • The user reads the data from the current bank by using the USBFIFOnDATA register, until all the expected data frame is read or the bank is empty (in which case RWALL is cleared and BYCT reaches zero). • The user frees the bank and switches to the next bank (if any) by clearing FIFOCON. If the endpoint uses several banks, the current one can be read while the following one is being written by the host. Then, when the user clears FIFOCON, the following bank may already be ready and RXOUTI is set immediately. In Hi-Speed mode, the PING and NYET protocol is handled by the USBB. For single bank, a NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the current packet is acknowledged but there is no room for the next one. For double bank, the USBB responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted the data successfully and has room for another data payload (the second bank is free). 26.7.2.14 Underflow This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt (UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable (UNDERFE) bit is one. An underflow can occur during IN stage if the host attempts to read from an empty bank. A zerolength packet is then automatically sent by the USBB. An underflow can not occur during OUT stage on a CPU action, since the user may read only if the bank is not empty (RXOUTI is one or RWALL is one). An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost. An underflow can not occur during IN stage on a CPU action, since the user may write only if the bank is not full (TXINI is one or RWALL is one). 26.7.2.15 Overflow This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one. An overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in. An overflow can not occur during IN stage on a CPU action, since the user may write only if the bank is not full (TXINI is one or RWALL is one). 26.7.2.16 HB IsoIn error This error exists only for high-bandwidth isochronous IN endpoints. At the end of the micro-frame, if at least one packet has been sent to the host, if less banks than expected has been validated (by clearing the FIFOCON) for this micro-frame, it set the HBISOINERRORI bit in UESTAn, what triggers an EPnINT interrupt if the High Bandwidth Isochronous IN Error Interrupt Enable (HBISOINERRORE) bit is one. For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint (NBTRANS field in UECFGn is three (three transactions per micro-frame), only two banks are 654 32072C–AVR32–2010/03 AT32UC3A3/A4 filled by the CPU (three expected) for the current micro-frame. Then, the HBISOINERRI interrupt is generated at the end of the micro-frame. Note that an UNDERFI interrupt is also generated (with an automatic zero-length-packet), except in the case of a missing IN token. 26.7.2.17 HB IsoFlush This error exists only for high-bandwidth isochronous IN endpoints. At the end of the micro-frame, if at least one packet has been sent to the host, if there is missing IN token during this micro-frame, the bank(s) destined to this micro-frame is/are flushed out to ensure a good data synchronization between the host and the device. For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token (among 3) is well received by the USBB, then the two last banks will be discarded. 26.7.2.18 CRC error This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI) bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE) bit is one. A CRC error can occur during OUT stage if the USBB detects a corrupted received packet. The OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is set). 26.7.2.19 Interrupts See the structure of the USB device interrupt system on Figure 26-6 on page 638. There are two kinds of device interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). •Global interrupts The processing device global interrupts are: • The Suspend (SUSP) interrupt • The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero) • The Micro Start of Frame (MSOF) interrupt with no CRC error. • The End of Reset (EORST) interrupt • The Wake-Up (WAKEUP) interrupt • The End of Resume (EORSM) interrupt • The Upstream Resume (UPRSM) interrupt • The Endpoint n (EPnINT) interrupt • The DMA Channel n (DMAnINT) interrupt The exception device global interrupts are: • The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one) • The Micro Start of Frame (MSOF) interrupt with a CRC error •Endpoint interrupts The processing device endpoint interrupts are: • The Transmitted IN Data Interrupt (TXINI) 655 32072C–AVR32–2010/03 AT32UC3A3/A4 • The Received OUT Data Interrupt (RXOUTI) • The Received SETUP Interrupt (RXSTPI) • The Short Packet (SHORTPACKET) interrupt • The Number of Busy Banks (NBUSYBK) interrupt • The Received OUT isochronous Multiple Data Interrupt (MDATAI) • The Received OUT isochronous DataX Interrupt (DATAXI) The exception device endpoint interrupts are: • The Underflow Interrupt (UNDERFI) • The NAKed OUT Interrupt (NAKOUTI) • The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) • The NAKed IN Interrupt (NAKINI) • The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI) • The Overflow Interrupt (OVERFI) • The STALLed Interrupt (STALLEDI) • The CRC Error Interrupt (CRCERRI) • The Transaction error (ERRORTRANS) interrupt •DMA interrupts The processing device DMA interrupts are: • The End of USB Transfer Status (EOTSTA) interrupt • The End of Channel Buffer Status (EOCHBUFFSTA) interrupt • The Descriptor Loaded Status (DESCLDSTA) interrupt There is no exception device DMA interrupt. 26.7.2.20 Test Modes When written to one, the UDCON.TSTPCKT bit switches the USB device controller in a “test packet”mode: The transceiver repeatedly transmit the packet stored in the current bank. TSTPCKT must be written to zero to exit the “test-packet” mode. The endpoint shall be reset by software after a “test-packet” mode. This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic waveform specifications. The flow control used to send the packets is as follows: • TSTPCKT=1; • Store data in an endpoint bank • Write a zero to FifoCON bit To stop the test-packet mode, just write a zero to the TSTPCKT bit. 656 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.3 26.7.3.1 USB Host Operation Description of pipes For the USBB in host mode, the term “pipe” is used instead of “endpoint” (used in device mode). A host pipe corresponds to a device endpoint, as described by the Figure 26-21 on page 657 from the USB specification. Figure 26-21. USB Communication Flow In host mode, the USBB associates a pipe to a device endpoint, considering the device configuration descriptors. 26.7.3.2 Power-On and reset Figure 26-22 on page 657 describes the USBB host mode main states. Figure 26-22. Host Mode States Macro off Clock stopped Idle Device Connection Device Disconnection Device Disconnection Ready SOFE = 0 SOFE = 1 Suspend After a hardware reset, the USBB host mode is in the Reset state. When the USBB is enabled (USBE is one) in host mode (ID is zero), its host mode state goes to the Idle state. In this state, the controller waits for device connection with minimal power con- 657 32072C–AVR32–2010/03 AT32UC3A3/A4 sumption. The USB pad should be in the Idle state. Once a device is connected, the macro enters the Ready state, what does not require the USB clock to be activated. The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when the host mode does not generate the “Start of Frame (SOF)”. In this state, the USB consumption is minimal. The host mode exits the Suspend state when starting to generate the SOF over the USB line. 26.7.3.3 Device detection A device is detected by the USBB host mode when D+ or D- is no longer tied low, i.e., when the device D+ or D- pull-up resistor is connected. To enable this detection, the host controller has to provide the VBus power supply to the device by setting the VBUSRQ bit (by writing a one to the VBUSRQS bit). The device disconnection is detected by the host controller when both D+ and D- are pulled down. 26.7.3.4 USB reset The USBB sends a USB bus reset when the user write a one to the Send USB Reset bit in the Host General Control register (UHCON.RESET). The USB Reset Sent Interrupt bit in the Host Global Interrupt register (UHINT.RSTI) is set when the USB reset has been sent. In this case, all the pipes are disabled and de-allocated. If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable (SOFE) bit in UHCON is zero), the USBB automatically switches it to the “Resume” state, the Host WakeUp Interrupt (HWUPI) bit in UHINT is set and the SOFE bit is set in order to generate SOFs or micro SOFs immediately after the USB reset. At the end of the reset, the user should check the USBSTA.SPEED field to know the speed running according to the peripheral capability (LS.FS/HS) 26.7.3.5 Pipe reset A pipe can be reset at any time by writing a one to the Pipe n Reset (PRSTn) bit in the UPRST register. This is recommended before using a pipe upon hardware reset or when a USB bus reset has been sent. This resets: • The internal state machine of this pipe • The receive and transmit bank FIFO counters • All the registers of this pipe (UPCFGn, UPSTAn, UPCONn), except its configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ in UPCFGn) and its Data Toggle Sequence field in the Pipe n Status register (UPSTAn.DTSEQ). The pipe configuration remains active and the pipe is still enabled. The pipe reset may be associated with a clear of the data toggle sequence. This can be achieved by setting the Reset Data Toggle bit in the Pipe n Control register (UPCONn.RSTDT) (by writing a one to the Reset Data Toggle Set bit in the Pipe n Control Set register (UPCONnSET.RSTDTS)). In the end, the user has to write a zero to the PRSTn bit to complete the reset operation and to start using the FIFO. 658 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.3.6 Pipe activation The pipe is maintained inactive and reset (see Section 26.7.3.5 for more details) as long as it is disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset. The algorithm represented on Figure 26-23 on page 659 must be followed in order to activate a pipe. Figure 26-23. Pipe Activation Algorithm Pipe Activation PENn = 1 UPCFGn INTFRQ PEPNUM PTYPE PTOKEN PSIZE PBK ALLOC Enable the pipe. Configure the pipe: - interrupt request frequency - endpoint number - type - size - number of banks Allocate the configured DPRAM banks. Test if the pipe configuration is correct. CFGOK == 1? Yes Pipe Activated No ERROR As long as the pipe is not correctly configured (UPSTAn.CFGOK is zero), the controller can not send packets to the device through this pipe. The UPSTAn.CFGOK bit is set only if the configured size and number of banks are correct compared to their maximal allowed values for the pipe (see Table 26-1 on page 630) and to the maximal FIFO size (i.e. the DPRAM size). See Section 26.7.1.6 for more details about DPRAM management. Once the pipe is correctly configured (UPSTAn.CFGOK is zero), only the PTOKEN and INTFRQ fields can be written by software. INTFRQ is meaningless for non-interrupt pipes. When starting an enumeration, the user gets the device descriptor by sending a GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0) and the user re-configures the size of the default control pipe with this size parameter. 26.7.3.7 Address setup Once the device has answered the first host requests with the default device address 0, the host assigns a new address to the device. The host controller has to send an USB reset to the device and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the device. Once this SETUP transaction is over, the user writes the new address into the USB Host Address for Pipe n field in the USB Host Device Address register (UHADDR.UHADDRPn). All following requests, on all pipes, will be performed using this new address. 659 32072C–AVR32–2010/03 AT32UC3A3/A4 When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the following host requests will be performed using the default device address 0. 26.7.3.8 Remote wake-up The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3ms later. The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature). When the host controller detects a non-idle state on the USB bus, it set the Host Wake-Up interrupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K state), the Upstream Resume Received Interrupt (RXRSMI) bit in UHINT is set. The user has to generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no effect. 26.7.3.9 Management of control pipes A control transaction is composed of three stages: • SETUP • Data (IN or OUT) • Status (OUT or IN) The user has to change the pipe token according to each stage. For the control pipe, and only for it, each token is assigned a specific initial data toggle sequence: • SETUP: Data0 • IN: Data1 • OUT: Data1 26.7.3.10 Management of IN pipes IN packets are sent by the USB device controller upon IN requests from the host. All the data can be read which acknowledges or not the bank when it is empty. The pipe must be configured first. When the host requires data from the device, the user has to select beforehand the IN request mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE): • When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before freezing the pipe. • When INMODE is written to one, the USBB will perform IN requests endlessly when the pipe is not frozen by the user. The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE) field in UPCONn is zero). The Received IN Data Interrupt (RXINI) bit in UPSTAn is set at the same time as the FIFO Control (FIFOCON) bit in UPCONn when the current bank is full. This triggers a PnINT interrupt if the Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one. 660 32072C–AVR32–2010/03 AT32UC3A3/A4 RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what has no effect on the pipe FIFO. The user then reads from the FIFO and clears the FIFOCON bit (by writing a one to the FIFO Control Clear (FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN pipe is composed of multiple banks, this also switches to the next bank. The RXINI and FIFOCON bits are updated in accordance with the status of the next bank. RXINI shall always be cleared before clearing FIFOCON. The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e., the software can read further data from the FIFO. Figure 26-24. Example of an IN Pipe with 1 Data Bank IN DATA (bank 0) ACK IN DATA (bank 0) ACK HW RXINI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 0 Figure 26-25. Example of an IN Pipe with 2 Data Banks IN DATA (bank 0) ACK IN DATA (bank 1) ACK HW RXINI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 1 26.7.3.11 Management of OUT pipes OUT packets are sent by the host. All the data can be written which acknowledges or not the bank when it is full. The pipe must be configured and unfrozen first. The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFOCON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data Interrupt Enable (TXOUTE) bit in UPCONn is one. 661 32072C–AVR32–2010/03 AT32UC3A3/A4 TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the pipe FIFO. The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and FIFOCON bits are updated in accordance with the status of the next bank. TXOUTI shall always be cleared before clearing FIFOCON. The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write further data into the FIFO. Note that if the user decides to switch to the Suspend state (by writing a zero to the UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and the bank is sent. Note that in High-Speed operating mode, the host controller automatically manages the PING protocol to maximize the USB bandwidth. The user can tune the PING protocol by handling the Ping Enable (PINGEN) bit and the bInterval Parameter for the Bulk-Out/Ping Transaction (BINTERVALL) field in UPCFGn. See the Section 26.8.3.12 for more details. Figure 26-26. Example of an OUT Pipe with one Data Bank OUT DATA (bank 0) ACK OUT HW TXOUTI SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 0 SW Figure 26-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW SW SW FIFOCON write data to CPU SW BANK 0 write data to CPU BANK 1 SW write data to CPU BANK0 662 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 26-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 1 SW write data to CPU BANK0 26.7.3.12 CRC error This error exists only for isochronous IN pipes. It set the CRC Error Interrupt (CRCERRI) bit, what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in UPCONn is one. A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN packet is stored in the bank as if no CRC error had occurred (RXINI is set). 26.7.3.13 Interrupts See the structure of the USB host interrupt system on Figure 26-6 on page 638. There are two kinds of host interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). •Global interrupts The processing host global interrupts are: • The Device Connection Interrupt (DCONNI) • The Device Disconnection Interrupt (DDISCI) • The USB Reset Sent Interrupt (RSTI) • The Downstream Resume Sent Interrupt (RSMEDI) • The Upstream Resume Received Interrupt (RXRSMI) • The Host Start of Frame Interrupt (HSOFI) • The Host Wake-Up Interrupt (HWUPI) • The Pipe n Interrupt (PnINT) • The DMA Channel n Interrupt (DMAnINT) There is no exception host global interrupt. •Pipe interrupts The processing host pipe interrupts are: • The Received IN Data Interrupt (RXINI) 663 32072C–AVR32–2010/03 AT32UC3A3/A4 • The Transmitted OUT Data Interrupt (TXOUTI) • The Transmitted SETUP Interrupt (TXSTPI) • The Short Packet Interrupt (SHORTPACKETI) • The Number of Busy Banks (NBUSYBK) interrupt The exception host pipe interrupts are: • The Underflow Interrupt (UNDERFI) • The Pipe Error Interrupt (PERRI) • The NAKed Interrupt (NAKEDI) • The Overflow Interrupt (OVERFI) • The Received STALLed Interrupt (RXSTALLDI) • The CRC Error Interrupt (CRCERRI) •DMA interrupts The processing host DMA interrupts are: • The End of USB Transfer Status (EOTSTA) interrupt • The End of Channel Buffer Status (EOCHBUFFSTA) interrupt • The Descriptor Loaded Status (DESCLDSTA) interrupt There is no exception host DMA interrupt. 664 32072C–AVR32–2010/03 AT32UC3A3/A4 26.7.4 26.7.4.1 USB DMA Operation Introduction USB packets of any length may be transferred when required by the USBB. These transfers always feature sequential addressing. These two characteristics mean that in case of high USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length” since the average access latency of HSB slaves can then be reduced. The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1kbyte boundary crossing. Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus bandwidth performance boost with paged memories. This is because these memories row (or bank) changes, which are very clock-cycle consuming, will then likely not occur or occur once instead of dozens of times during a single big USB packet DMA transfer in case other HSB masters address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints. This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size (PSIZE/EPSIZE) and the Channel Byte Length (CHBYTELENGTH) field in the Device DMA Channel n Control (UDDMAnCONTROL) register. The USBB average throughput may be up to nearly 53 Mbyte/s. Its average access latency decreases as burst length increases due to the zero wait-state side effect of unchanged pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by four compared to native byte access. If at least 0 wait-state word burst capability is also provided by the other DMA HSB bus slaves, each of both DMA HSB busses need less than 60% bandwidth allocation for full USB bandwidth usage at 33MHz, and less than 30% at 66MHz. 665 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 26-29. Example of DMA Chained List Transfer Descriptor USB DMA Channel X Registers (Current Transfer Descriptor) Next Descriptor Address Next Descriptor Address HSB Address Control HSB Address Control Status Transfer Descriptor Next Descriptor Address HSB Address Control Transfer Descriptor Next Descriptor Address HSB Address Control NULL Memory Area Data Buffer 1 Data Buffer 2 Data Buffer 3 26.7.4.2 DMA Channel descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer. The structure of the DMA channel transfer descriptor is defined by three parameters as described below: • Offset 0: – The address must be aligned: 0xXXXX0 – DMA Channel n Next Descriptor Address Register: DMAnNXTDESCADDR • Offset 4: – The address must be aligned: 0xXXXX4 – DMA Channel n HSB Address Register: DMAnADDR • Offset 8: – The address must be aligned: 0xXXXX8 – DMA Channel n Control Register: DMAnCONTROL 26.7.4.3 Programming a chanel: Each DMA transfer is unidirectionnal. Direction depends on the type of the associated endpoint (IN or OUT). Three registers, the UDDMAnNEXTDESC, the UDDMAnADDR and UDDMAnCONTROL need to be programmed to set up wether single or multiple transfer is used. The following example refers to OUT endpoint. For IN endpoint, the programming is symmetric. 666 32072C–AVR32–2010/03 AT32UC3A3/A4 •Single-block transfer programming example for OUT transfer : The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet. • Write the starting destination address in the UDDMAnADDR register. • There is no need to program the UDDMAnNEXTDESC register. • Program the channel byte length in the UDDMAnCONTROL register. • Program the UDDMAnCONTROL according to Row 2 as shown in Figure 26-7 on page 720 to set up a single block transfer. The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable. As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one, indicating that the DMA channel is transfering data from the endpoint to the destination address until the endpoint is empty or the channel byte length is reached. Once the endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared. Once the DMA channel is completed (i.e : the channel byte length is reached), after one or multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAnCONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an integral multiple of the endpoint size. •Programming example for single-block dma transfer with automatic closure for OUT transfer : The idea is to automatically close the DMA transfer at the end of the OUT transaction (received short packet). The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet. • Write the starting destination address in the UDDMAnADDR register. • There is no need to program the UDDMAnNEXTDESC register. • Program the channel byte length in the UDDMAnCONTROL register. • Set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register. • Program the UDDMAnCONTROL according to Row 2 as shown in Figure 26-7 on page 720 to set up a single block transfer. As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one, indicating that the DMA channel is transfering data from the endpoint to the destination address until the endpoint is empty. Once the endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared. After one or multiple processed OUT packet, the DMA channel is completed after sourcing a short packet. Then, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOTSTA bit is set indicating that the DMA was closed by a end of USB transaction. 667 32072C–AVR32–2010/03 AT32UC3A3/A4 •Programming example for multi-block dma transfer : run and link at end of buffer The idea is to run first a single block transfer followed automatically by a linked list of DMA. The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet. • Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items : channel next descriptor address, channel destination address and channel control. The last descriptor should be programmed according to row 2 as shown in Figure 26-7 on page 720. • Write the starting destination address in the UDDMAnADDR register. • Program the UDDMAnNEXTDESC register. • Program the channel byte length in the UDDMAnCONTROL register. • Optionnaly set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register. • Program the UDDMAnCONTROL according to Row 4 as shown in Figure 26-7 on page 720. The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable. As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one, indicating that the DMA channel is transfering data from the endpoint to the destination address until the endpoint is empty or the channel byte length is reached. Once the endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared. Once the first DMA channel is completed (i.e : the channel byte length is reached), after one or multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAnCONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an integral multiple of the endpoint size. Note that the UDDMAnCONTROL.LDNXTCH bit remains to one indicating that a linked descriptor will be loaded. Once the new descriptor is loaded from the UDDMAnNEXTDESC memory address, the UDDMAnSTATUS.DESCLDSTA bit is set, and the UDDMAnCONTROL register is updated from the memory. As a consequence, the UDDMAnSTATUS.CHEN bit is set, and the UDDMAnSTATUS.CHACTIVE is set as soon as the endpoint is ready to be sourced by the DMA (received OUT data packet). This sequence is repeated until a last linked descriptor is processed. The last descriptor is detected according to row 2 as shown in Figure 26-7 on page 720. At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared. •Programming example for multi-block dma transfer : load next descriptor now The idea is to directly run first a linked list of DMA. The following sequence may be used: The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet. 668 32072C–AVR32–2010/03 AT32UC3A3/A4 • Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items : channel next descriptor address, channel destination address and channel control. The last descriptor should be programmed according to row 2 as shown in Figure 26-7 on page 720. • Program the UDDMAnNEXTDESC register. • Program the UDDMAnCONTROL according to Row 3 as shown in Figure 26-7 on page 720. The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.LDNXTCHDESCEN is set indicating that the DMA channel is pending until the endpoint is ready (received OUT packet). As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit is set to one. Then after a few cycle latency, the new descriptor is loaded from the memory and the UDDMAnSTATUS.DESCLDSTA is set. At the end of this DMA (for instance when the channel byte length has reached 0), the UDDMAnCONTROL.CHEN bit is cleared, and then the UDDMAnSTATUS.CHEN bit is also cleared. If the UDDMAnCONTROL.LDNXTCH value is one, a new descriptor is loaded. This sequence is repeated until a last linked descriptor is processed. The last descriptor is detected according to row 2 as shown in Figure 26-7 on page 720. At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared. 669 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8 User Interface USBB Register Memory Map Register Device General Control Register Device Global Interrupt Register Device Global Interrupt Clear Register Device Global Interrupt Set Register Device Global Interrupt Enable Register Device Global Interrupt Enable Clear Register Device Global Interrupt Enable Set Register Endpoint Enable/Reset Register Device Frame Number Register Endpoint 0 Configuration Register Endpoint 1 Configuration Register Endpoint 2 Configuration Register Endpoint 3 Configuration Register Endpoint 4 Configuration Register Endpoint 5 Configuration Register Endpoint 6 Configuration Register Endpoint 7Configuration Register Endpoint 0 Status Register Endpoint 1 Status Register Endpoint 2 Status Register Endpoint 3 Status Register Endpoint 4 Status Register Endpoint 5 Status Register Endpoint 6 Status Register Endpoint 7Status Register Endpoint 0 Status Clear Register Endpoint 1 Status Clear Register Endpoint 2 Status Clear Register Endpoint 3 Status Clear Register Endpoint 4 Status Clear Register Endpoint 5 Status Clear Register Endpoint 6 Status Clear Register Endpoint 7 Status Clear Register Endpoint 0 Status Set Register Endpoint 1 Status Set Register Name UDCON UDINT UDINTCLR UDINTSET UDINTE UDINTECLR UDINTESET UERST UDFNUM UECFG0 UECFG1 UECFG2 UECFG3 UECFG4 UECFG5 UECFG6 UECFG7 UESTA0 UESTA1 UESTA2 UESTA3 UESTA4 UESTA5 UESTA6 UESTA7 UESTA0CLR UESTA1CLR UESTA2CLR UESTA3CLR UESTA4CLR UESTA5CLR UESTA6CLR UESTA7CLR UESTA0SET UESTA1SET Access Read/Write Read-Only Write-Only Write-Only Read-Only Write-Only Write-Only Read/Write Read-Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Reset Value 0x00000100 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 26-5. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 0x0130 0x0134 0x0138 0x013C 0x0140 0x0144 0x0148 0x014C 0x0160 0x0164 0x0168 0x016C 0x0170 0x0174 0x0178 0x017C 0x0190 0x0194 670 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 26-5. Offset 0x0198 0x019C 0x01A0 0x01A4 0x01A8 0x01AC 0x01C0 0x01C4 0x01C8 0x01CC 0x01D0 0x01D4 0x01D8 0x01DC 0x01F0 0x01F4 0x01F8 0x01FC 0x0200 0x0204 0x0208 0x020C 0x0220 0x0224 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C 0x0310 0x0314 0x0318 USBB Register Memory Map Register Endpoint 2 Status Set Register Endpoint 3 Status Set Register Endpoint 4 Status Set Register Endpoint 5 Status Set Register Endpoint 6 Status Set Register Endpoint 7 Status Set Register Endpoint 0 Control Register Endpoint 1 Control Register Endpoint 2 Control Register Endpoint 3 Control Register Endpoint 4 Control Register Endpoint 5 Control Register Endpoint 6 Control Register Endpoint 7 Control Register Endpoint 0 Control Set Register Endpoint 1 Control Set Register Endpoint 2 Control Set Register Endpoint 3 Control Set Register Endpoint 4 Control Set Register Endpoint 5 Control Set Register Endpoint 6 Control Set Register Endpoint 7 Control Set Register Endpoint 0 Control Clear Register Endpoint 1 Control Clear Register Endpoint 2 Control Clear Register Endpoint 3 Control Clear Register Endpoint 4 Control Clear Register Endpoint 5 Control Clear Register Endpoint 6 Control Clear Register Endpoint 7 Control Clear Register Device DMA Channel 1 Next Descriptor Address Register Device DMA Channel 1 HSB Address Register Device DMA Channel 1 Control Register Name UESTA2SET UESTA3SET UESTA4SET UESTA5SET UESTA6SET UESTA7SET UECON0 UECON1 UECON2 UECON3 UECON4 UECON5 UECON6 UECON7 UECON0SET UECON1SET UECON2SET UECON3SET UECON4SET UECON5SET UECON6SET UECON7SET UECON0CLR UECON1CLR UECON2CLR UECON3CLR UECON4CLR UECON5CLR UECON6CLR UECON7CLR UDDMA1 NEXTDESC UDDMA1 ADDR UDDMA1 CONTROL Access Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 671 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 26-5. Offset 0x031C 0x0320 0x0324 0x0328 0x032C 0x0330 0x0334 0x0338 0x033C 0x0340 0x0344 0x0348 0x034C 0x0350 0x0354 0x0358 0x035C 0x0360 0x0364 0x0368 0x036C 0x0370 USBB Register Memory Map Register Device DMA Channel 1 Status Register Device DMA Channel 2 Next Descriptor Address Register Device DMA Channel 2 HSB Address Register Device DMA Channel 2 Control Register Device DMA Channel 2 Status Register Device DMA Channel 3 Next Descriptor Address Register Device DMA Channel 3 HSB Address Register Device DMA Channel 3 Control Register Device DMA Channel 3 Status Register Device DMA Channel 4 Next Descriptor Address Register Device DMA Channel 4 HSB Address Register Device DMA Channel 4 Control Register Device DMA Channel 4 Status Register Device DMA Channel 5 Next Descriptor Address Register Device DMA Channel 5 HSB Address Register Device DMA Channel 5 Control Register Device DMA Channel 5 Status Register Device DMA Channel 6 Next Descriptor Address Register Device DMA Channel 6 HSB Address Register Device DMA Channel 6 Control Register Device DMA Channel 6 Status Register Device DMA Channel 7 Next Descriptor Address Register Name UDDMA1 STATUS UDDMA2 NEXTDESC UDDMA2 ADDR UDDMA2 CONTROL UDDMA2 STATUS UDDMA3 NEXTDESC UDDMA3 ADDR UDDMA3 CONTROL UDDMA3 STATUS UDDMA4 NEXTDESC UDDMA4 ADDR UDDMA4 CONTROL UDDMA4 STATUS UDDMA5 NEXTDESC UDDMA5 ADDR UDDMA5 CONTROL UDDMA5 STATUS UDDMA6 NEXTDESC UDDMA6 ADDR UDDMA6 CONTROL UDDMA6 STATUS UDDMA7 NEXTDESC Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 672 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 26-5. Offset 0x0374 0x0378 0x037C 0x0400 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 0x0041C 0x0420 0x0424 0x0428 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0518 0x051C 0x0530 0x0534 0x0538 0x053C 0x0540 0x0544 0x0548 0x054C 0x0560 0x0564 0x0568 0x056C USBB Register Memory Map Register Device DMA Channel 7 HSB Address Register Device DMA Channel 7 Control Register Device DMA Channel 7Status Register Host General Control Register Host Global Interrupt Register Host Global Interrupt Clear Register Host Global Interrupt Set Register Host Global Interrupt Enable Register Host Global Interrupt Enable Clear Register Host Global Interrupt Enable Set Register Pipe Enable/Reset Register Host Frame Number Register Host Address 1 Register Host Address 2 Register Pipe 0 Configuration Register Pipe 1 Configuration Register Pipe 2 Configuration Register Pipe 3 Configuration Register Pipe 4 Configuration Register Pipe 5 Configuration Register Pipe 6 Configuration Register Pipe 7 Configuration Register Pipe 0 Status Register Pipe 1 Status Register Pipe 2 Status Register Pipe 3 Status Register Pipe 4 Status Register Pipe 5 Status Register Pipe 6 Status Register Pipe 7Status Register Pipe 0 Status Clear Register Pipe 1 Status Clear Register Pipe 2 Status Clear Register Pipe 3 Status Clear Register Name UDDMA7 ADDR UDDMA7 CONTROL UDDMA7 STATUS UHCON UHINT UHINTCLR UHINTSET UHINTE UHINTECLR UHINTESET UPRST UHFNUM UHADDR1 UHADDR2 UPCFG0 UPCFG1 UPCFG2 UPCFG3 UPCFG4 UPCFG5 UPCFG6 UPCFG7 UPSTA0 UPSTA1 UPSTA2 UPSTA3 UPSTA4 UPSTA5 UPSTA6 UPSTA7 UPSTA0CLR UPSTA1CLR UPSTA2CLR UPSTA3CLR Access Read/Write Read/Write Read/Write Read/Write Read-Only Write-Only Write-Only Read-Only Write-Only Write-Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 673 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 26-5. Offset 0x0570 0x0574 0x0578 0x057C 0x0590 0x0594 0x0598 0x059C 0x05A0 0x05A4 0x05A8 0x05AC 0x05C0 0x05C4 0x05C8 0x05CC 0x05D0 0x05D4 0x05D8 0x05DC 0x05F0 0x05F4 0x05F8 0x05FC 0x0600 0x0604 0x0608 0x060C 0x0620 0x0624 0x0628 0x062C 0x0630 0x0634 0x0638 0x063C USBB Register Memory Map Register Pipe 4 Status Clear Register Pipe 5 Status Clear Register Pipe 6 Status Clear Register Pipe 7 Status Clear Register Pipe 0 Status Set Register Pipe 1 Status Set Register Pipe 2 Status Set Register Pipe 3 Status Set Register Pipe 4 Status Set Register Pipe 5 Status Set Register Pipe 6 Status Set Register Pipe 7 Status Set Register Pipe 0 Control Register Pipe 1 Control Register Pipe 2 Control Register Pipe 3 Control Register Pipe 4 Control Register Pipe 5 Control Register Pipe 6 Control Register Pipe 7 Control Register Pipe 0 Control Set Register Pipe 1 Control Set Register Pipe 2 Control Set Register Pipe 3 Control Set Register Pipe 4 Control Set Register Pipe 5 Control Set Register Pipe 6 Control Set Register Pipe 7 Control Set Register Pipe 0 Control Clear Register Pipe 1 Control Clear Register Pipe 2 Control Clear Register Pipe 3 Control Clear Register Pipe 4 Control Clear Register Pipe 5 Control Clear Register Pipe 6 Control Clear Register Pipe 7 Control Clear Register Name UPSTA4CLR UPSTA5CLR UPSTA6CLR UPSTA7CLR UPSTA0SET UPSTA1SET UPSTA2SET UPSTA3SET UPSTA4SET UPSTA5SET UPSTA6SET UPSTA7SET UPCON0 UPCON1 UPCON2 UPCON3 UPCON4 UPCON5 UPCON6 UPCON7 UPCON0SET UPCON1SET UPCON2SET UPCON3SET UPCON4SET UPCON5SET UPCON6SET UPCON7SET UPCON0CLR UPCON1CLR UPCON2CLR UPCON3CLR UPCON4CLR UPCON5CLR UPCON6CLR UPCON7CLR Access Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 674 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 26-5. Offset 0x0650 0x0654 0x0658 0x065C 0x0660 0x0664 0x0668 0x066C 0x0680 0x0684 0x0688 0x068C 0x0690 0x0694 0x0698 0x069C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0x072C 0x0730 0x0734 0x0738 0x073C USBB Register Memory Map Register Pipe 0 IN Request Register Pipe 1 IN Request Register Pipe 2 IN Request Register Pipe 3 IN Request Register Pipe 4 IN Request Register Pipe 5 IN Request Register Pipe 6 IN Request Register Pipe 7 IN Request Register Pipe 0 Error Register Pipe 1 Error Register Pipe 2 Error Register Pipe 3 Error Register Pipe 4 Error Register Pipe 5 Error Register Pipe 6 Error Register Pipe 7 Error Register Host DMA Channel 1 Next Descriptor Address Register Host DMA Channel 1 HSB Address Register Host DMA Channel 1 Control Register Host DMA Channel 1 Status Register Host DMA Channel 2 Next Descriptor Address Register Host DMA Channel 2 HSB Address Register Host DMA Channel 2 Control Register Host DMA Channel 2 Status Register Host DMA Channel 3 Next Descriptor Address Register Host DMA Channel 3 HSB Address Register Host DMA Channel 3 Control Register Host DMA Channel 3Status Register Name UPINRQ0 UPINRQ1 UPINRQ2 UPINRQ3 UPINRQ4 UPINRQ5 UPINRQ6 UPINRQ7 UPERR0 UPERR1 UPERR2 UPERR3 UPERR4 UPERR5 UPERR6 UPERR7 UHDMA1 NEXTDESC UHDMA1 ADDR UHDMA1 CONTROL UHDMA1 STATUS UHDMA2 NEXTDESC UHDMA2 ADDR UHDMA2 CONTROL UHDMA2 STATUS UHDMA3 NEXTDESC UHDMA3 ADDR UHDMA3 CONTROL UHDMA3 STATUS Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 675 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 26-5. Offset 0x0740 0x0744 0x0748 0x074C 0x0750 0x0754 0x0758 0x075C 0x0760 0x0764 0x0768 0x076C 0x0770 0x0774 0x0778 0x077C 0x0800 0x0804 0x0808 0x080C 0x0818 0x081C 0x0820 0x0824 0x0828 0x082C USBB Register Memory Map Register Host DMA Channel 4 Next Descriptor Address Register Host DMA Channel 4 HSB Address Register Host DMA Channel 4 Control Register Host DMA Channel 4 Status Register Host DMA Channel 5 Next Descriptor Address Register Host DMA Channel 5 HSB Address Register Host DMA Channel 5 Control Register Host DMA Channel 5 Status Register Host DMA Channel 6 Next Descriptor Address Register Host DMA Channel 6 HSB Address Register Host DMA Channel 6 Control Register Host DMA Channel 6 Status Register Host DMA Channel 7 Next Descriptor Address Register Host DMA Channel 7 HSB Address Register Host DMA Channel 7 Control Register Host DMA Channel 7 Status Register General Control Register General Status Register General Status Clear Register General Status Set Register IP Version Register IP Features Register IP PB Address Size Register IP Name Register 1 IP Name Register 2 USB Finite State Machine Status Register Name UHDMA4 NEXTDESC UHDMA4 ADDR UHDMA4 CONTROL UHDMA4 STATUS UHDMA5 NEXTDESC UHDMA5 ADDR UHDMA5 CONTROL UHDMA5 STATUS UHDMA6 NEXTDESC UHDMA6 ADDR UHDMA6 CONTROL UHDMA6 STATUS UHDMA7 NEXTDESC UHDMA7 ADDR UHDMA7 CONTROL UHDMA7 STATUS USBCON USBSTA USBSTACLR USBSTASET UVERS UFEATURES UADDRSIZE UNAME1 UNAME2 USBFSM Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-Only Write-Only Write-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x03004000 0x00000400 0x00000000 0x00000000 -(1) -(1) -(1) -(1) -(1) 0x00000009 676 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 26-6. Offset 0x00000 0x0FFFC 0x10000 0x1FFFC 0x20000 0x2FFFC 0x30000 0x3FFFC 0x40000 0x4FFFC 0x50000 0x5FFFC 0x60000 0x6FFFC 0x70000 0x7FFFC Note: USB HSB Memory Map Register Pipe/Endpoint 0 FIFO Data Register Pipe/Endpoint 1 FIFO Data Register Pipe/Endpoint 2 FIFO Data Register Pipe/Endpoint 3 FIFO Data Register Pipe/Endpoint 4 FIFO Data Register Pipe/Endpoint 5 FIFO Data Register Pipe/Endpoint 6 FIFO Data Register Pipe/Endpoint 7 FIFO Data Register Name USB FIFO0DATA USB FIFO1DATA USB FIFO2DATA USB FIFO3DATA USB FIFO4DATA USB FIFO5DATA USB FIFO6DATA USB FIFO7DATA Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 677 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1 26.8.1.1 Name: USB General Registers General Control Register USBCON Read/Write 0x0800 0x03004000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 UIMOD 24 UIDE 23 - 22 UNLOCK 21 TIMPAGE 20 19 - 18 - 17 TIMVALUE 16 15 USBE 14 FRZCLK 13 VBUSPO 12 OTGPADE 11 HNPREQ 10 SRPREQ 9 SRPSEL 8 VBUSHWC 7 STOE 6 HNPERRE 5 ROLEEXE 4 BCERRE 3 VBERRE 2 SRPE 1 VBUSTE 0 IDTE • UIMOD: USBB Mode This bit has no effect when UIDE is one (USB_ID input pin activated). 0: The module is in USB host mode. 1: The module is in USB device mode. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. • UIDE: USB_ID Pin Enable 0: The USB mode (device/host) is selected from the UIMOD bit. 1: The USB mode (device/host) is selected from the USB_ID input pin. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. • UNLOCK: Timer Access Unlock 1: The TIMPAGE and TIMVALUE fields are unlocked. 0: The TIMPAGE and TIMVALUE fields are locked. The TIMPAGE and TIMVALUE fields can always be read, whatever the value of UNLOCK. • TIMPAGE: Timer Page This field contains the page value to access a special timer register. • TIMVALUE: Timer Value This field selects the timer value that is written to the special time register selected by TIMPAGE. See Section 26.7.1.8 for details. • USBE: USBB Enable Writing a zero to this bit will reset the USBB, disable the USB transceiver and, disable the USBB clock inputs. Unless explicitly stated, all registers then will become read-only and will be reset. 1: The USBB is enabled. 0: The USBB is disabled. 678 32072C–AVR32–2010/03 AT32UC3A3/A4 This bit can be written even if FRZCLK is one. • FRZCLK: Freeze USB Clock 1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all registers then become read-only. 0: The clock inputs are enabled. This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but this freezes the clock inputs whatever its value. • VBUSPO: VBus Polarity 1: The USB_VBOF output signal is inverted (active low). 0: The USB_VBOF output signal is in its default mode (active high). To be generic. May be useful to control an external VBus power module. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. • OTGPADE: OTG Pad Enable 1: The OTG pad is enabled. 0: The OTG pad is disabled. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. • HNPREQ: HNP Request When the controller is in device mode: Writing a one to this bit will initiate a HNP (Host Negociation Protocol). Writing a zero to this bit has no effect. This bit is cleared when the controller has initiated an HNP. When the controller is in host mode: Writing a one to this bit will accept a HNP. Writing a zero to this bit will reject a HNP. SRPREQ: SRP Request Writing a one to this bit will initiate an SRP when the controller is in device mode. Writing a zero to this bit has no effect. This bit is cleared when the controller has initiated an SRP. SRPSEL: SRP Selection 1: VBus pulsing is selected as SRP method. 0: Data line pulsing is selected as SRP method. VBUSHWC: VBus Hardware Control 1: The hardware control over the USB_VBOF output pin is disabled. 0: The hardware control over the USB_VBOF output pin is enabled. The USBB resets the USB_VBOF output pin when a VBUS problem occurs. STOE: Suspend Time-Out Interrupt Enable 1: The Suspend Time-Out Interrupt (STOI) is enabled. 0: The Suspend Time-Out Interrupt (STOI) is disabled. HNPERRE: HNP Error Interrupt Enable 1: The HNP Error Interrupt (HNPERRI) is enabled. 0: The HNP Error Interrupt (HNPERRI) is disabled. ROLEEXE: Role Exchange Interrupt Enable 1: The Role Exchange Interrupt (ROLEEXI) is enabled. 0: The Role Exchange Interrupt (ROLEEXI) is disabled. BCERRE: B-Connection Error Interrupt Enable 1: The B-Connection Error Interrupt (BCERRI) is enabled. 0: The B-Connection Error Interrupt (BCERRI) is disabled. VBERRE: VBus Error Interrupt Enable 1: The VBus Error Interrupt (VBERRI) is enabled. • • • • • • • • 679 32072C–AVR32–2010/03 AT32UC3A3/A4 0: The VBus Error Interrupt (VBERRI) is disabled. • SRPE: SRP Interrupt Enable 1: The SRP Interrupt (SRPI) is enabled. 0: The SRP Interrupt (SRPI) is disabled. • VBUSTE: VBus Transition Interrupt Enable 1: The VBus Transition Interrupt (VBUSTI) is enabled. 0: The VBus Transition Interrupt (VBUSTI) is disabled. • IDTE: ID Transition Interrupt Enable 1: The ID Transition interrupt (IDTI) is enabled. 0: The ID Transition interrupt (IDTI) is disabled. 680 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.2 General Status Register Register Name: USBSTA Access Type: Offset: Reset Value: Read-Only 0x0804 0x00000400 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 CLKUSABLE 13 SPEED 12 11 VBUS 10 ID 9 VBUSRQ 8 - 7 STOI 6 HNPERRI 5 ROLEEXI 4 BCERRI 3 VBERRI 2 SRPI 1 VBUSTI 0 IDTI • CLKUSABLE: UTMI Clock Usable This bit is set when the UTMI 30MHz is usable. This bit is cleared when the UTMI 30MHz is not usable. • SPEED: Speed Status This field is set according to the controller speed mode. This field shall only be used in device mode. SPEED 0 1 0 1 0 0 1 1 Speed Status Full-Speed mode Low-Speed mode High-Speed mode Reserved • VBUS: VBus Level This bit is set when the VBus line level is high, even if USBE is zero. This bit is cleared when the VBus line level is low, even if USBE is zero. This bit can be used in device mode to monitor the USB bus connection state of the application. • ID: USB_ID Pin State This bit is cleared when the USB_ID level is low, even if USBE is zero. This bit is set when the USB_ID level is high, event if USBE is zero. • VBUSRQ: VBus Request This bit is set when the USBSTASET.VBUSRQS bit is written to one. This bit is cleared when the USBSTACLR.VBUSRQC bit is written to one or when a VBus error occurs and VBUSHWC is zero. 1: The USB_VBOF output pin is driven high to enable the VBUS power supply generation. 0: The USB_VBOF output pin is driven low to disable the VBUS power supply generation. This bit shall only be used in host mode. 681 32072C–AVR32–2010/03 AT32UC3A3/A4 • STOI: Suspend Time-Out Interrupt This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if STOE is one. This bit is cleared when the UBSTACLR.STOIC bit is written to one. This bit shall only be used in host mode. • HNPERRI: HNP Error Interrupt This bit is set when an error has been detected during a HNP negotiation. This triggers a USB interrupt if HNPERRE is one. This bit is cleared when the UBSTACLR.HNPERRIC bit is written to one. This bit shall only be used in device mode. • ROLEEXI: Role Exchange Interrupt This bit is set when the USBB has successfully switched its mode because of an HNP negotiation (host to device or device to host). This triggers a USB interrupt if ROLEEXE is one. This bit is cleared when the UBSTACLR.ROLEEXIC bit is written to one. • BCERRI: B-Connection Error Interrupt This bit is set when an error occurs during the B-connection. This triggers a USB interrupt if BCERRE is one. This bit is cleared when the UBSTACLR.BCERRIC bit is written to one. This bit shall only be used in host mode. • VBERRI: VBus Error Interrupt This bit is set when a VBus drop has been detected. This triggers a USB interrupt if VBERRE is one. This bit is cleared when the UBSTACLR.VBERRIC bit is written to one. This bit shall only be used in host mode. If a VBus problem occurs, then the VBERRI interrupt is generated even if the USBB does not go to an error state because of VBUSHWC is one. • SRPI: SRP Interrupt This bit is set when an SRP has been detected. This triggers a USB interrupt if SRPE is one. This bit is cleared when the UBSTACLR.SRPIC bit is written to one. This bit shall only be used in host mode. • VBUSTI: VBus Transition Interrupt This bit is set when a transition (high to low, low to high) has been detected on the USB_VBUS pad. This triggers an USB interrupt if VBUSTE is one. This bit is cleared when the UBSTACLR.VBUSTIC bit is written to one. This interrupt is generated even if the clock is frozen by the FRZCLK bit. • IDTI: ID Transition Interrupt This bit is set when a transition (high to low, low to high) has been detected on the USB_ID input pin. This triggers an USB interrupt if IDTE is one. This bit is cleared when the UBSTACLR.IDTIC bit is written to one. This interrupt is generated even if the clock is frozen by the FRZCLK bit. 682 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Offset: Read Value: Write-Only 0x0808 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 VBUSRQC 8 - 7 STOIC 6 HNPERRIC 5 ROLEEXIC 4 BCERRIC 3 VBERRIC 2 SRPIC 1 VBUSTIC 0 IDTIC Writing a one to a bit in this register will clear the corresponding bit in UBSTA. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 683 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.4 General Status Set Register Register Name: USBSTASET Access Type: Offset: Read Value: Write-Only 0x080C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 VBUSRQS 8 - 7 STOIS 6 HNPERRIS 5 ROLEEXIS 4 BCERRIS 3 VBERRIS 2 SRPIS 1 VBUSTIS 0 IDTIS Writing a one to a bit in this register will set the corresponding bit in UBSTA, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 684 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.5 Version Register Register Name: UVERS Access Type: Offset: Read Value: Read-Only 0x0818 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 685 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.6 Features Register Register Name: UFEATURES Access Type: Offset: Read Value: Read-Only 0x081C - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 ENHBISO7 22 ENHBISO6 21 ENHBISO5 20 ENHBISO4 19 ENHBISO3 18 ENHBISO2 17 ENHBISO1 16 DATABUS 15 BYTEWRITE DPRAM 14 13 FIFOMAXSIZE 12 11 10 9 8 DMAFIFOWORDDEPTH 7 DMABUFFE RSIZE 6 5 DMACHANNELNBR 4 3 2 EPTNBRMAX 1 0 • ENHBISOn: High Bandwidth Isochronous Feature for Endpoint n 1: The high bandwidth isochronous is supported. 1: The high bandwidth isochronous is not supported. • DATABUS: Data Bus 16-8 1: The UTMI data bus is a 16-bit data path at 30MHz. 0: The UTMI data bus is a 8-bit data path at 60MHz. • BYTEWRITEDPRAM: DPRAM Byte-Write Capability 1: The DPRAM is natively byte-write capable. 0: The DPRAM byte write lanes have shadow logic implemented in the USBB IP interface. • FIFOMAXSIZE: Maximal FIFO Size This field indicates the maximal FIFO size, i.e., the DPRAM size: FIFOMAXSIZE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Maximal FIFO Size < 256 bytes < 512 bytes < 1024 bytes < 2048 bytes < 4096 bytes < 8192 bytes < 16384 bytes >= 16384 bytes 686 32072C–AVR32–2010/03 AT32UC3A3/A4 • DMAFIFOWORDDEPTH: DMA FIFO Depth in Words This field indicates the DMA FIFO depth controller in words: DMAFIFOWORDDEPTH 0 0 0 0 0 0 0 0 1 0 1 0 DMA FIFO Depth in Words 16 1 2 ... 1 1 1 1 15 • DMABUFFERSIZE: DMA Buffer Size 1: The DMA buffer size is 24bits. 0: The DMA buffer size is 16bits. • DMACHANNELNBR: Number of DMA Channels This field indicates the number of hardware-implemented DMA channels: DMACHANNELNBR 0 0 0 0 0 1 0 1 0 Number of DMA Channels Reserved 1 2 ... 1 1 1 7 • EPTNBRMAX: Maximal Number of Pipes/Endpoints This field indicates the number of hardware-implemented pipes/endpoints: EPTNBRMAX 0 0 0 0 0 0 0 0 1 0 1 0 Maximal Number of Pipes/Endpoints 16 1 2 ... 1 1 1 1 15 687 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Offset: Read Value: Read-Only 0x0820 - 31 30 29 28 27 26 25 24 UADDRSIZE[31:24] 23 22 21 20 19 18 17 16 UADDRSIZE[23:16] 15 14 13 12 11 10 9 8 UADDRSIZE[15:8] 7 6 5 4 3 2 1 0 UADDRSIZE[7:0] • UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBB IP interface. 688 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.8 Name Register 1 Register Name: UNAME1 Access Type: Offset: Read Value: Read-Only 0x0824 - 31 30 29 28 27 26 25 24 UNAME1[31:24] 23 22 21 20 19 18 17 16 UNAME1[23:16] 15 14 13 12 11 10 9 8 UNAME1[15:8] 7 6 5 4 UNAME1[7:0] 3 2 1 0 • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBB IP. 689 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.9 Name Register 2 Register Name: UNAME2 Access Type: Offset: Read Value: Read-Only 0x0828 31 30 29 28 27 26 25 24 UNAME2[31:24] 23 22 21 20 19 18 17 16 UNAME2[23:16] 15 14 13 12 11 10 9 8 UNAME2[15:8] 7 6 5 4 UNAME2[7:0] 3 2 1 0 • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBB IP. 690 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Offset: Read Value: Read-Only 0x082C 0x00000009 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 DRDSTATE 1 0 • DRDSTATE This field indicates the state of the USBB. Refer to the OTG specification for more details. DRDSTATE 0 1 2 3 4 5 6 7 8 9 10 11 12 Description a_idle state: this is the start state for A-devices (when the ID pin is 0) a_wait_vrise: In this state, the A-device waits for the voltage on VBus to rise above the Adevice VBus Valid threshold (4.4 V). a_wait_bcon: In this state, the A-device waits for the B-device to signal a connection. a_host: In this state, the A-device that operates in Host mode is operational. a_suspend: The A-device operating as a host is in the suspend mode. a_peripheral: The A-device operates as a peripheral. a_wait_vfall: In this state, the A-device waits for the voltage on VBus to drop below the Adevice Session Valid threshold (1.4 V). a_vbus_err: In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. a_wait_discharge: In this state, the A-device waits for the data usb line to discharge (100 us). b_idle: this is the start state for B-device (when the ID pin is 1). b_peripheral: In this state, the B-device acts as the peripheral. b_wait_begin_hnp: In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. b_wait_discharge: In this state, the B-device waits for the data usb line to discharge (100 us) before becoming Host. 691 32072C–AVR32–2010/03 AT32UC3A3/A4 DRDSTATE 13 14 15 Description b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. b_host: In this state, the B-device acts as the Host. b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol. 692 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2 USB Device Registers 26.8.2.1 Device General Control Register Register Name: UDCON Access Type: Offset: Reset Value: Read/Write 0x0000 0x00000100 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 OPMODE2 15 TSTPCKT 14 TSTK 13 TSTJ 12 LS 11 SPDCONF 10 9 RMWKUP 8 DETACH 7 ADDEN 6 5 4 3 UADD 2 1 0 • OPMODE2: Specific Operational mode 1: The UTMI transceiver is in the «disable bit stuffing and NRZI encoding» operational mode for test purpose. 0: The UTMI transceiver is in normal operation mode. • TSTPCKT: Test packet mode 1: The UTMI transceiver generates test packets for test purpose. 0: The UTMI transceiver is in normal operation mode. • TSTK: Test mode K 1: The UTMI transceiver generates high-speed K state for test purpose. 0: The UTMI transceiver is in normal operation mode. • TSTJ: Test mode J 1: The UTMI transceiver generates high-speed J state for test purpose. 0: The UTMI transceiver is in normal operation mode. • LS: Low-Speed Mode Force 1: The low-speed mode is active. 0: The full-speed mode is active. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. 693 32072C–AVR32–2010/03 AT32UC3A3/A4 • SPDCONF: Speed Configuration This field contains the peripheral speed. SPDCONF 0 0 1 1 0 1 0 1 Speed Normal mode: the peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. reserved, do not use this configuration reserved, do not use this configuration Full-speed: the peripheral remains in full-speed mode whatever is the host speed capability. • RMWKUP: Remote Wake-Up Writing a one to this bit will send an upstream resume to the host for a remote wake-up. Writing a zero to this bit has no effect. This bit is cleared when the USBB receive a USB reset or once the upstream resume has been sent. • DETACH: Detach Writing a one to this bit will physically detach the device (disconnect internal pull-up resistor from D+ and D-). Writing a zero to this bit will reconnect the device. • ADDEN: Address Enable Writing a one to this bit will activate the UADD field (USB address). Writing a zero to this bit has no effect. This bit is cleared when a USB reset is received. • UADD: USB Address This field contains the device address. This field is cleared when a USB reset is received. 694 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.2 Device Global Interrupt Register Register Name: UDINT Access Type: Offset: Reset Value: Read-Only 0x0004 0x00000000 31 DMA7INT 30 DMA6INT 29 DMA5INT 28 DMA4INT 27 DMA3INT 26 DMA2INT 25 DMA1INT 24 - 23 - 22 - 21 - 20 - 19 EP7INT 18 EP6INT 17 EP5INT 16 EP4INT 15 EP3INT 14 EP2INT 13 EP1INT 12 EP0INT 11 - 10 - 9 - 8 - 7 - 6 UPRSM 5 EORSM 4 WAKEUP 3 EORST 2 SOF 1 MSOF 0 SUSP • DMAnINT: DMA Channel n Interrupt This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one. This bit is cleared when the UDDMAnSTATUS interrupt source is cleared. • EPnINT: Endpoint n Interrupt This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is one. This bit is cleared when the interrupt source is serviced. • UPRSM: Upstream Resume Interrupt This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is one. This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before). • EORSM: End of Resume Interrupt This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if EORSME is one. This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt. • WAKEUP: Wake-Up Interrupt This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is one. This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before). This bit is cleared when the Suspend (SUSP) interrupt bit is set. This interrupt is generated even if the clock is frozen by the FRZCLK bit. • EORST: End of Reset Interrupt This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one. This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt. 695 32072C–AVR32–2010/03 AT32UC3A3/A4 • SOF: Start of Frame Interrupt This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is one. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared. This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt. • MSOF: Micro Start of Frame Interrupt This bit is set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every 125 us). This triggers a USB interrupt if MSOFE is one. The MFNUM field is updated. The FNUM field is unchanged. This bit is cleared when the UDINTCLR.MSOFC bit is written to one to acknowledge the interrupt. • SUSP: Suspend Interrupt This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if SUSPE is one. This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt. This bit is cleared when the Wake-Up (WAKEUP) interrupt bit is set. 696 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Offset: Read Value: Write-Only 0x0008 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 UPRSMC 5 EORSMC 4 WAKEUPC 3 EORSTC 2 SOFC 1 MSOFC 0 SUSPC Writing a one to a bit in this register will clear the corresponding bit in UDINT. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 697 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.4 Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Offset: Read Value: Write-Only 0x000C 0x00000000 31 DMA7INTS 30 DMA6INTS 29 DMA5INTS 28 DMA4INTS 27 DMA3INTS 26 DMA2INTS 25 DMA1INTS 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 UPRSMS 5 EORSMS 4 WAKEUPS 3 EORSTS 2 SOFS 1 MSOFS 0 SUSPS Writing a one to a bit in this register will set the corresponding bit in UDINT, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 698 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.5 Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Offset: Reset Value: Read-Only 0x0010 0x00000000 31 DMA7INTE 30 DMA6INTE 29 DMA5INTE 28 DMA4INTE 27 DMA3INTE 26 DMA2INTE 25 DMA1INTE 24 - 23 - 22 - 21 - 20 - 19 EP7INTE 18 EP6INTE 17 EP5INTE 16 EP4INTE 15 EP3INTE 14 EP2INTE 13 EP1INTE 12 EP0INTE 11 - 10 - 9 - 8 - 7 - 6 UPRSME 5 EORSME 4 WAKEUPE 3 EORSTE 2 SOFE 1 MSOFE 0 SUSPE 1: The corresponding interrupt is enabled. 0: The corresponding interrupt is disabled. A bit in this register is set when the corresponding bit in UDINTESET is written to one. A bit in this register is cleared when the corresponding bit in UDINTECLR is written to one. 699 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.6 Device Global Interrupt Enable Clear Register Register Name: UDINTECLR Access Type: Offset: Read Value: Write-Only 0x0014 0x00000000 31 DMA7INTEC 30 DMA6INTEC 29 DMA5INTEC 28 DMA4INTEC 27 DMA3INTEC 26 DMA2INTEC 25 DMA1INTEC 24 - 23 - 22 - 21 - 20 - 19 EP7INTEC 18 EP6INTEC 17 EP5INTEC 16 EP4INTEC 15 EP3INTEC 14 EP2INTEC 13 EP1INTEC 12 EP0INTEC 11 - 10 - 9 - 8 - 7 - 6 UPRSMEC 5 EORSMEC 4 WAKEUPEC 3 EORSTEC 2 SOFEC 1 MSOFEC 0 SUSPEC Writing a one to a bit in this register will clear the corresponding bit in UDINTE. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 700 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.7 Device Global Interrupt Enable Set Register Register Name: UDINTESET Access Type: Offset: Read Value: Write-Only 0x0018 0x00000000 31 DMA7INTES 30 DMA6INTES 29 DMA5INTES 28 DMA4INTES 27 DMA3INTES 26 DMA2INTES 25 DMA1INTES 24 - 23 - 22 - 21 - 20 - 19 EP7INTES 18 EP6INTES 17 EP5INTES 16 EP4INTES 15 EP3INTES 14 EP2INTES 13 EP1INTES 12 EP0INTES 11 - 10 - 9 - 8 - 7 - 6 UPRSMES 5 EORSMES 4 WAKEUPES 3 EORSTES 2 SOFES 1 MSOFES 0 SUSPES Writing a one to a bit in this register will set the corresponding bit in UDINTE. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 701 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.8 Endpoint Enable/Reset Register Register Name: UERST Access Type: Offset: Reset Value: Read/Write 0x001C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 EPRST7 22 EPRST6 21 EPRST5 20 EPRST4 19 EPRST3 18 EPRST2 17 EPRST1 16 EPRST0 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 EPEN7 6 EPEN6 5 EPEN5 4 EPEN4 3 EPEN3 2 EPEN2 1 EPEN1 0 EPEN0 • EPRSTn: Endpoint n Reset Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE). All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field (DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit). The endpoint configuration remains active and the endpoint is still enabled. Writing a zero to this bit will complete the reset operation and start using the FIFO. This bit is cleared upon receiving a USB reset. • EPENn: Endpoint n Enable 1: The endpoint n is enabled. 0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE). 702 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Offset: Reset Value: Read-Only 0x0020 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 FNCERR 14 - 13 12 11 FNUM[10:5] 10 9 8 7 6 5 FNUM[4:0] 4 3 2 1 MFNUM 0 • FNCERR: Frame Number CRC Error This bit is set when a corrupted frame number (or micro-frame number) is received. This bit and the SOF (or MSOF) interrupt bit are updated at the same time. This bit is cleared upon receiving a USB reset. • FNUM: Frame Number This field contains the 11-bit frame number information. It is provided in the last received SOF packet. This field is cleared upon receiving a USB reset. FNUM is updated even if a corrupted SOF is received. • MFNUM: Micro Frame Number This field contains the 3-bit micro frame number information. It is provided in the last received MSOF packet. This field is cleared at the beginning of each start of frame (SOF interrupt) or upon receiving a USB reset. MFNUM is updated even if a corrupted MSOF is received. 703 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0100 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 NBTRANS 13 12 EPTYPE 11 10 - 9 AUTOSW 8 EPDIR 7 - 6 5 EPSIZE 4 3 EPBK 2 1 ALLOC 0 - • NBTRANS: Number of transaction per microframe for isochronous endpoint This field shall be written to the number of transaction per microframe to perform high-bandwidth isochronous transfer This field can be written only for endpoint that have this capability (see UFEATURES register, ENHBISOn bit). This field is 0 otherwise. This field is irrelevant for non-isochronous endpoint. NBTRANS 0 0 1 1 0 1 0 1 Number of transaction reserved to endpoint that does not have the high-bandwidth isochronous capability. default value: one transaction per micro-frame. 2 transactions per micro-frame. This endpoint should be configured as double-bank. 3 transactions per micro-frame. This endpoint should be configured as triple-bank. • EPTYPE: Endpoint Type This field shall be written to select the endpoint type: EPTYPE 0 0 1 1 0 1 0 1 Endpoint Type Control Isochronous Bulk Interrupt This field is cleared upon receiving a USB reset. • AUTOSW: Automatic Switch This bit is cleared upon receiving a USB reset. 704 32072C–AVR32–2010/03 AT32UC3A3/A4 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. • EPDIR: Endpoint Direction This bit is cleared upon receiving a USB reset. 1: The endpoint direction is IN (nor for control endpoints). 0: The endpoint direction is OUT. • EPSIZE: Endpoint Size This field shall be written to select the size of each endpoint bank: EPSIZE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Endpoint Size 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 256 bytes 512 bytes 1024 bytes This field is cleared upon receiving a USB reset (except for the endpoint 0). • EPBK: Endpoint Banks This field shall be written to select the number of banks for the endpoint: EPBK 0 0 1 1 0 1 0 1 Endpoint Banks 1 (single-bank endpoint) 2 (double-bank endpoint) 3 (triple-bank endpoint) Reserved For control endpoints, a single-bank endpoint (0b00) shall be selected. This field is cleared upon receiving a USB reset (except for the endpoint 0). • ALLOC: Endpoint Memory Allocate Writing a one to this bit will allocate the endpoint memory. The user should check the CFGOK bit to know whether the allocation of this endpoint is correct. Writing a zero to this bit will free the endpoint memory. This bit is cleared upon receiving a USB reset (except for the endpoint 0). 705 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x0100 0x0130 + (n * 0x04) 0x00000100 31 - 30 29 28 27 BYCT 26 25 24 23 22 BYCT 21 20 19 - 18 CFGOK 17 CTRLDIR 16 RWALL 15 CURRBK 14 13 NBUSYBK 12 11 - 10 ERRORTRANS 9 DTSEQ 8 7 SHORT PACKET 6 STALLEDI/ CRCERRI 5 OVERFI 4 NAKINI/ HBISOFLUSHI 3 NAKOUTI/ HBISOINERRI 2 RXSTPI/ UNDERFI 1 RXOUTI 0 TXINI • BYCT: Byte Count This field is set with the byte count of the FIFO. For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to the host. For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software from the endpoint. This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. • CFGOK: Configuration OK Status This bit is updated when the ALLOC bit is written to one. This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size). If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register. • CTRLDIR: Control Direction This bit is set after a SETUP packet to indicate that the following packet is an IN packet. This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet. Writing a zero or a one to this bit has no effect. • RWALL: Read/Write Allowed This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO. This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO. This bit is never set if STALLRQ is one or in case of error. This bit is cleared otherwise. This bit shall not be used for control endpoints. 706 32072C–AVR32–2010/03 AT32UC3A3/A4 • CURRBK: Current Bank This bit is set for non-control endpoints, to indicate the current bank: CURRBK 0 0 1 1 0 1 0 1 Current Bank Bank0 Bank1 Bank2 Reserved This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. • NBUSYBK: Number of Busy Banks This field is set to indicate the number of busy banks: NBUSYBK 0 0 1 1 0 1 0 1 Number of Busy Banks 0 (all banks free) 1 2 3 For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this triggers an EPnINT interrupt if NBUSYBKE is one. For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this triggers an EPnINT interrupt if NBUSYBKE is one. When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to calculate the address of the next bank. An EPnINT interrupt is triggered if: - for IN endpoint, NBUSYBKE is one and all the banks are free. - for OUT endpoint, NBUSYBKE is one and all the banks are busy. • ERRORTRANS: High-bandwidth isochronous OUT endpoint transaction error Interrupt This bit is set when a transaction error occurs during the current micro-frame (the data toggle sequencing does not respect the usb 2.0 standard). This triggers an EPnINT interrupt if ERRORTRANSE is one. This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n=1,2 or 3) transferred during the micro-frame. Shall be cleared by software by clearing (at least once) the FIFOCON bit to switch to the bank that belongs to the next n-transactions (next micro-frame). • DTSEQ: Data Toggle Sequence This field is set to indicate the PID of the current bank: DTSEQ 0 0 1 1 0 1 0 1 Data Toggle Sequence Data0 Data1 Data2 (for high-bandwidth isochronous endpoint) MData (for high-bandwidth isochronous endpoint) For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the current bank. For OUT transfers, this value indicates the last data toggle sequence received on the current bank. 707 32072C–AVR32–2010/03 AT32UC3A3/A4 By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0. For High-bandwidth isochronous endpoint, an EPnINT interrupt is triggered if: - MDATAE is one and a MData packet has been received (DTSEQ=MData and RXOUTI is one). - DATAXE is one and a Data0/1/2 packet has been received (DTSEQ=Data0/1/2 and RXOUTI is one) SHORTPACKET: Short Packet Interrupt This bit is set for non-control OUT endpoints, when a short packet has been received. This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and the Automatic Switch (AUTOSW) bit are written to one. This triggers an EPnINT interrupt if SHORTPACKETE is one. This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt. STALLEDI: STALLed Interrupt This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one. This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt. CRCERRI: CRC Error Interrupt This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one. This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt. OVERFI: Overflow Interrupt This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one. For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in. This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt. NAKINI: NAKed IN Interrupt This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT interrupt if NAKINE is one. This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt. HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the micro-frame, if less than N transaction has been completed by the USBB without underflow error. This may occur in case of a missing IN token. In this case, the bank are flushed out to ensure the data synchronization between the host and the device. This triggers an EPnINT interrupt if HBISOFLUSHE is one. This bit is cleared when the HBISOFLUSHIC bit is written to one. This will acknowledge the interrupt. NAKOUTI: NAKed OUT Interrupt This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT interrupt if NAKOUTE is one. This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt. HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the microframe, if less than N bank was written by the cpu within this micro-frame. This triggers an EPnINT interrupt if HBISOINERRE is one. This bit is cleared when the HBISOINERRIC bit is written to one. This will acknowledge the interrupt. UNDERFI: Underflow Interrupt This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if UNDERFE is one. An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then automatically sent by the USBB. An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost. • • • • • • • • • 708 32072C–AVR32–2010/03 AT32UC3A3/A4 Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt. This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints. • RXSTPI: Received SETUP Interrupt This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers an EPnINT interrupt if RXSTPE is one. Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank. This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT endpoints. • RXOUTI: Received OUT Data Interrupt This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPnINT interrupt if RXOUTE is one. Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the bank. This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if RXOUTE is one. Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of the next bank. RXOUTI shall always be cleared before clearing FIFOCON. This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints. • TXINI: Transmitted IN Data Interrupt This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt if TXINE is one. This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet. This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free. This triggers an EPnINT interrupt if TXINE is one. This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance with the status of the next bank. TXINI shall always be cleared before clearing FIFOCON. This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints. 709 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0160 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SHORT PACKETC 6 STALLEDIC/ CRCERRIC 5 OVERFIC 4 NAKINIC/ HBISOFLUSHIC 3 NAKOUTIC/ HBISOINERRIC 2 RXSTPIC/ UNDERFIC 1 RXOUTIC 0 TXINIC Writing a one to a bit in this register will clear the corresponding bit in UESTA. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 710 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0190 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 NBUSYBKS 11 - 10 - 9 8 - 7 SHORT PACKETS 6 STALLEDIS/ CRCERRIS 5 OVERFIS 4 NAKINIS/ HBISOFLUSHIS 3 NAKOUTIS/ HBISOINERRIS 2 RXSTPIS/ UNDERFIS 1 RXOUTIS 0 TXINIS Writing a one to a bit in this register will set the corresponding bit in UESTA, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 711 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x01C0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 STALLRQ 18 RSTDT 17 NYETDIS 16 EPDISHDMA 15 - 14 FIFOCON 13 KILLBK 12 NBUSYBKE 11 - 10 ERRORTRANSE 9 DATAXE 8 MDATAE 7 SHORT PACKETE 6 STALLEDE/ CRCERRE 5 OVERFE 4 NAKINE/ HBISOFLUSHE 3 NAKOUTE/ HBISOINERRE 2 RXSTPE/ UNDERFE 1 RXOUTE 0 TXINE • STALLRQ: STALL Request This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host. This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero. • RSTDT: Reset Data Toggle This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle sequence of the next sent (IN endpoints) or received (OUT endpoints) packet. This bit is cleared instantaneously. The user does not have to wait for this bit to be cleared. • NYETDIS: NYET token disable This bit is set when the NYETDISS bit is written to one. This will send a ACK handshake instead of a NYET handshake in highspeed mode. This bit is cleared when the NYETDISC bit is written to one.This will let the USBB handling the high-speed handshake following the usb 2.0 standard. • EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE). The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a one to the EPDISHDMAC bit) in order to complete the DMA transfer. In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA transfer will not start (not requested). If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may occur at any time and may immediately pause the current DMA transfer. This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a DMA transfer by software after reception of a short packet, etc. 712 32072C–AVR32–2010/03 AT32UC3A3/A4 • FIFOCON: FIFO Control For control endpoints: The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read, their value is always 0. For IN endpoints: This bit is set when the current bank is free, at the same time as TXINI. This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank. For OUT endpoints: This bit is set when the current bank is full, at the same time as RXOUTI. This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank. • KILLBK: Kill IN Bank This bit is set when the KILLBKS bit is written to one. This will kill the last written bank. This bit is cleared when the bank is killed. Caution: The bank is really cleared when the “kill packet” procedure is accepted by the USBB core. This bit is automatically cleared after the end of the procedure: The bank is really killed: NBUSYBK is decremented. The bank is not cleared but sent (IN transfer): NBUSYBK is decremented. The bank is not cleared because it was empty. The user shall wait for this bit to be cleared before trying to kill another packet. This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent on the USB line. If at least 2 banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed. • NBUSYBKE: Number of Busy Banks Interrupt Enable This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK). This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt (NBUSYBK). • ERRORTRANSE: Transaction Error Interrupt Enable This bit is set when the ERRORTRANSES bit is written to one. This will enable the transaction error interrupt (ERRORTRANS). This bit is cleared when the ERRORTRANSEC bit is written to one. This will disable the transaction error interrupt (ERRORTRANS). • DATAXE: DataX Interrupt Enable This bit is set when the DATAXES bit is written to one. This will enable the DATAX interrupt. (see DTSEQ bits) This bit is cleared when the DATAXEC bit is written to one. This will disable the DATAX interrupt. • MDATAE: MData Interrupt Enable This bit is set when the MDATAES bit is written to one. This will enable the Multiple DATA interrupt. (see DTSEQ bits) This bit is cleared when the MDATAEC bit is written to one. This will disable the Multiple DATA interrupt. • SHORTPACKETE: Short Packet Interrupt Enable This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET). This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt (SHORTPACKET). • STALLEDE: STALLed Interrupt Enable This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI). This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI). • CRCERRE: CRC Error Interrupt Enable This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI). This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI). • OVERFE: Overflow Interrupt Enable This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI). This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI). • NAKINE: NAKed IN Interrupt Enable This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI). 713 32072C–AVR32–2010/03 AT32UC3A3/A4 This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI). • HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt Enable This bit is set when the HBISOFLUSHES bit is written to one. This will enable the HBISOFLUSHI interrupt. This bit is cleared when the HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt. • NAKOUTE: NAKed OUT Interrupt Enable This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI). This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI). • HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt Enable This bit is set when the HBISOINERRES bit is written to one. This will enable the HBISOINERRI interrupt. This bit is cleared when the HBISOINERREC bit disable the HBISOINERRI interrupt. • RXSTPE: Received SETUP Interrupt Enable This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI). This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI). • UNDERFE: Underflow Interrupt Enable This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI). This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI). • RXOUTE: Received OUT Data Interrupt Enable This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT). This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT). • TXINE: Transmitted IN Data Interrupt Enable This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI). This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI). 714 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0220 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 STALLRQC 18 - 17 NYETDISC 16 EPDISHDMAC 15 - 14 FIFOCONC 13 - 12 NBUSYBKEC 11 - 10 ERRORTRANSEC 9 DATAXEC 8 MDATEC 7 SHORT PACKETEC 6 STALLEDEC/ CRCERREC 5 OVERFEC 4 NAKINEC/ HBISOFLUSHEC 3 NAKOUTEC/ HBISOINERREC 2 RXSTPEC/ UNDERFEC 1 RXOUTEC 0 TXINEC Writing a one to a bit in this register will clear the corresponding bit in UECONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 715 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x01F0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 STALLRQS 18 RSTDTS 17 NYETDISS 16 EPDISHDMAS 15 - 14 - 13 KILLBKS 12 NBUSYBKES 11 - 10 ERRORTRANSES 9 DATAXES 8 MDATES 7 SHORT PACKETES 6 STALLEDES/ CRCERRES 5 OVERFES 4 NAKINES/ HBISOFLUSHES 3 NAKOUTES/ HBISOINERRES 2 RXSTPES/ UNDERFES 1 RXOUTES 0 TXINES Writing a one to a bit in this register will set the corresponding bit in UECONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 716 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.17 Device DMA Channel n Next Descriptor Address Register Register Name: UDDMAnNEXTDESC, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0310 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 NXTDESCADDR[31:24] 23 22 21 20 19 18 17 16 NXTDESCADDR[23:16] 15 14 13 12 11 10 9 8 NXTDESCADDR[15:8] 7 6 5 4 3 - 2 - 1 - 0 - NXTDESCADDR[7:4] • NXTDESCADDR: Next Descriptor Address This field contains the bits 31:4 of the 16-byte aligned address of the next channel descriptor to be processed. This field is written either or by descriptor loading. 717 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.18 Device DMA Channel n HSB Address Register Register Name: UDDMAnADDR, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0314 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 HSBADDR[31:24] 23 22 21 20 19 18 17 16 HSBADDR[23:16] 15 14 13 12 11 10 9 8 HSBADDR[15:8] 7 6 5 4 3 2 1 0 HSBADDR[7:0] • HSBADDR: HSB Address This field determines the HSB bus current address of a channel transfer. The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e., HSBADDR[1:0] is considered as 0b00 since only word accesses are performed. Channel HSB start and end addresses may be aligned on any byte boundary. The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared. This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access byte-width. The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary. The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer. The packet end address is either the channel end address or the latest channel address accessed in the channel buffer. The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set. 718 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.19 Device DMA Channel n Control Register Register Name: UDDMAnCONTROL, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0318 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTELENGTH[15:8] 23 22 21 20 19 18 17 16 CHBYTELENGTH[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 BURSTLOCKEN 6 DESCLDIRQEN 5 EOBUFFIRQEN 4 EOTIRQEN 3 DMAENDEN 2 BUFFCLOSE INEN 1 LDNXTCH DESCEN 0 CHEN • CHBYTELENGTH: Channel Byte Length This field determines the total number of bytes to be transferred for this buffer. The maximum channel transfer size 64kB is reached when this field is zero (default value). If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero. This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is ignored. • BURSTLOCKEN: Burst Lock Enable 1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration. 0: The DMA never locks the HSB access. • DESCLDIRQEN: Descriptor Loaded Interrupt Enable 1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system bus. 0: The Descriptor Loaded interrupt is disabled. • EOBUFFIRQEN: End of Buffer Interrupt Enable 1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero. 0: The end of buffer interrupt is disabled. • EOTIRQEN: End of USB Transfer Interrupt Enable 1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set. 0: The end of usb OUT data transfer interrupt is disabled. • DMAENDEN: End of DMA Buffer Output Enable Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer. For IN endpoint, it means that a short packet (or a Zero Length Packet) will be sent to the USB line to properly closed the usb transfer at the end of the dma transfer. For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer. 719 32072C–AVR32–2010/03 AT32UC3A3/A4 • BUFFCLOSEINEN: Buffer Close Input Enable For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB OUT data transfer (received short packet). For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero. For high-speed OUT isochronous, it may make sense. In that case, if BUFFCLOSEINEN is written to one, the current DMA transfer is closed when the received PID packet is not MDATA. Writing a zero to this bit to disable this feature. • LDNXTCHDESCEN: Load Next Channel Descriptor Enable 1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit is reset. 0: no channel register is loaded after the end of the channel transfer. If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN endpoint, or endpoint is full for OUT endpoint). Table 26-7. LDNXTCHDES CEN 0 0 1 1 DMA Channel Control Command Summary CHEN 0 1 0 1 Current Bank stop now Run and stop at end of buffer Load next descriptor now Run and link at end of buffer • CHEN: Channel Enable Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both UDDMAnSTATUS.CHEN and CHACTIVE bits are zero. Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer. Then any pending request will start the transfer. This may be used to start or resume any requested transfer. This bit is cleared when the channel source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by descriptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed. If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the UDDMAnSTATUS.CHEN bit is cleared. If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 720 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.2.20 Device DMA Channel n Status Register Register Name: UDDMAnSTATUS, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x031C + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTECNT[15:8] 23 22 21 20 19 18 17 16 CHBYTECNT[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 DESCLD STA 5 EOCHBUFF STA 4 EOTSTA 3 - 2 - 1 CHACTIVE 0 CHEN • CHBYTECNT: Channel Byte Count This field contains the current number of bytes still to be transferred for this buffer. This field is decremented at each dma access. This field is reliable (stable) only if the CHEN bit is zero. • DESCLDSTA: Descriptor Loaded Status This bit is set when a Descriptor has been loaded from the HSB bus. This bit is cleared when read by the user. • EOCHBUFFSTA: End of Channel Buffer Status This bit is set when the Channel Byte Count counts down to zero. This bit is automatically cleared when read by software. • EOTSTA: End of USB Transfer Status This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if UDDMAnCONTROL.BUFFCLOSEINEN is one. This bit is automatically cleared when read by software. • CHACTIVE: Channel Active 0: the DMA channel is no longer trying to source the packet data. 1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an EOCHBUFFSTA, this bit stays set during the next channel descriptor load (if any) and potentially until USB packet transfer completion, if allowed by the new descriptor. When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is running (the endpoint is free for IN transaction, the endpoint is full for OUT transaction). • CHEN: Channel Enabled This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded. This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end. 0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN bit is zero. 721 32072C–AVR32–2010/03 AT32UC3A3/A4 1: the DMA channel is currently enabled and transfers data upon request. If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared. 722 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3 USB Host Registers 26.8.3.1 Host General Control Register Register Name: UHCON Access Type: Offset: Reset Value: Read/Write 0x0400 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 SPDCONF 12 11 - 10 RESUME 9 RESET 8 SOFE 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - • SPDCONF: Speed Configuration This field contains the host speed capability. SPDCONF 0 0 1 1 0 1 0 1 Speed Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. reserved, do not use this configuration reserved, do not use this configuration Full-speed: the host remains to full-speed mode whatever is the peripheral speed capability. • RESUME: Send USB Resume Writing a one to this bit will generate a USB Resume on the USB bus. This bit is cleared when the USB Resume has been sent or when a USB reset is requested. Writing a zero to this bit has no effect. This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one). • RESET: Send USB Reset Writing a one to this bit will generate a USB Reset on the USB bus. This bit is cleared when the USB Reset has been sent. It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset is being sent. • SOFE: Start of Frame Generation Enable Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode. Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state. This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.TXRSMI). 723 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.2 Host Global Interrupt Register Register Name: UHINT Access Type: Offset: Reset Value: Read-Only 0x0404 0x00000000 31 DMA7INT 30 DMA6INT 29 DMA5INT 28 DMA4INT 27 DMA3INT 26 DMA2INT 25 DMA1INT 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 15 P7INT 14 P6INT 13 P5INT 12 P4INT 11 P3INT 10 P2INT 9 P1INT 8 P0INT 7 - 6 HWUPI 5 HSOFI 4 RXRSMI 3 RSMEDI 2 RSTI 1 DDISCI 0 DCONNI • DMAnINT: DMA Channel n Interrupt This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if the corresponding DMAnINTE is one (UHINTE register). This bit is cleared when the UHDMAnSTATUS interrupt source is cleared. • PnINT: Pipe n Interrupt This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe interrupt enable bit is one (UHINTE register). This bit is cleared when the interrupt source is served. • HWUPI: Host Wake-Up Interrupt This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is detected. This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected. This bit is set when the host controller is in the Idle state (USBSTA.VBUSRQ is zero, no VBus is generated), and an OTG SRP event initiated by the peripheral is detected (USBSTA.SRPI is one). This interrupt is generated even if the clock is frozen by the FRZCLK bit. • HSOFI: Host Start of Frame Interrupt This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the host controller in low speed mode, this bit is also set when a keep-alive is sent. This bit is cleared when the HSOFIC bit is written to one. • RXRSMI: Upstream Resume Received Interrupt This bit is set when an Upstream Resume has been received from the Device. This bit is cleared when the RXRSMIC is written to one. • RSMEDI: Downstream Resume Sent Interrupt This bit set when a Downstream Resume has been sent to the Device. This bit is cleared when the RSMEDIC bit is written to one. • RSTI: USB Reset Sent Interrupt This bit is set when a USB Reset has been sent to the device. 724 32072C–AVR32–2010/03 AT32UC3A3/A4 This bit is cleared when the RSTIC bit is written to one. • DDISCI: Device Disconnection Interrupt This bit is set when the device has been removed from the USB bus. This bit is cleared when the DDISCIC bit is written to one. • DCONNI: Device Connection Interrupt This bit is set when a new device has been connected to the USB bus. This bit is cleared when the DCONNIC bit is written to one. 725 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.3 Host Global Interrupt Clear Register Register Name: UHINTCLR Access Type: Offset: Read Value: Write-Only 0x0408 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 HWUPIC 5 HSOFIC 4 RXRSMIC 3 RSMEDIC 2 RSTIC 1 DDISCIC 0 DCONNIC Writing a one to a bit in this register will clear the corresponding bit in UHINT. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 726 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.4 Host Global Interrupt Set Register Register Name: UHINTSET Access Type: Offset: Read Value: Write-Only 0x040C 0x00000000 31 DMA7INTS 30 DMA6INTS 29 DMA5INTS 28 DMA4INTS 27 DMA3INTS 26 DMA2INTS 25 DMA1INTS 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 HWUPIS 5 HSOFIS 4 RXRSMIS 3 RSMEDIS 2 RSTIS 1 DDISCIS 0 DCONNIS Writing a one to a bit in this register will set the corresponding bit in UHINT, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 727 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.5 Host Global Interrupt Enable Register Register Name: UHINTE Access Type: Offset: Reset Value: Read-Only 0x0410 0x00000000 31 DMA7INTE 30 DMA6INTE 29 DMA5INTE 28 DMA4INTE 27 DMA3INTE 26 DMA2INTE 25 DMA1INTE 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 P7INTE 14 P6INTE 13 P5INTE 12 P4INTE 11 P3INTE 10 P2INTE 9 P1INTE 8 P0INTE 7 - 6 HWUPIE 5 HSOFIE 4 RXRSMIE 3 RSMEDIE 2 RSTIE 1 DDISCIE 0 DCONNIE • DMAnINTE: DMA Channel n Interrupt Enable This bit is set when the DMAnINTES bit is written to one. This will enable the DMA Channel n Interrupt (DMAnINT). This bit is cleared when the DMAnINTEC bit is written to one. This will disable the DMA Channel n Interrupt (DMAnINT). • PnINTE: Pipe n Interrupt Enable This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT). This bit is cleared when the PnINTEC bit is written to one. This will disable the Pipe n Interrupt (PnINT). • HWUPIE: Host Wake-Up Interrupt Enable This bit is set when the HWUPIES bit is written to one. This will enable the Host Wake-up Interrupt (HWUPI). This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wake-up Interrupt (HWUPI). • HSOFIE: Host Start of Frame Interrupt Enable This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI). This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI). • RXRSMIE: Upstream Resume Received Interrupt Enable This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI). This bit is cleared when the RXRSMIEC bit is written to one. This will disable the Downstream Resume interrupt (RXRSMI). • RSMEDIE: Downstream Resume Sent Interrupt Enable This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI). This bit is cleared when the RSMEDIEC bit is written to one. This will disable the Downstream Resume interrupt (RSMEDI). • RSTIE: USB Reset Sent Interrupt Enable This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI). This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI). • DDISCIE: Device Disconnection Interrupt Enable This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI). This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI). • DCONNIE: Device Connection Interrupt Enable This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI). This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI). 728 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.6 Host Global Interrupt Enable Clear Register Register Name: UHINTECLR Access Type: Offset: Read Value: Write-Only 0x0414 0x00000000 31 DMA7INTEC 30 DMA6INTEC 29 DMA5INTEC 28 DMA4INTEC 27 DMA3INTEC 26 DMA2INTEC 25 DMA1INTEC 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 P7INTEC 14 P6INTEC 13 P5INTEC 12 P4INTEC 11 P3INTEC 10 P2INTEC 9 P1INTEC 8 P0INTEC 7 - 6 HWUPIEC 5 HSOFIEC 4 RXRSMIEC 3 RSMEDIEC 2 RSTIEC 1 DDISCIEC 0 DCONNIEC Writing a one to a bit in this register will clear the corresponding bit in UHINTE. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 729 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.7 Host Global Interrupt Enable Set Register Register Name: UHINTESET Access Type: Offset: Read Value: Write-Only 0x0418 0x00000000 31 DMA7INTES 30 DMA6INTES 29 DMA5INTES 28 DMA4INTES 27 DMA3INTES 26 DMA2INTES 25 DMA1INTES 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 P7INTES 14 P6INTES 13 P5INTES 12 P4INTES 11 P3INTES 10 P2INTES 9 P1INTES 8 P0INTES 7 - 6 HWUPIES 5 HSOFIES 4 RXRSMIES 3 RSMEDIES 2 RSTIES 1 DDISCIES 0 DCONNIES Writing a one to a bit in this register will set the corresponding bit in UHINT. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 730 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.8 Host Frame Number Register Register Name: UHFNUM Access Type: Offset: Reset Value: Read/Write 0x0420 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 FLENHIGH 19 18 17 16 15 - 14 - 13 12 11 FNUM[10:5] 10 9 8 7 6 5 FNUM[4:0] 4 3 2 1 MFNUM 0 • FLENHIGH: Frame Length In Full speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is 30000 to ensure a SOF generation every 1 ms). In High speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is 3750 to ensure a SOF generation every 125 us). • FNUM: Frame Number This field contains the current SOF number. This field can be written. In this case, the MFNUM field is reset to zero. • MFNUM: Micro Frame Number This field contains the current Micro Frame number (can vary from 0 to 7) updated every 125us. When operating in full-speed mode, this field is tied to zero. 731 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.9 USB Host Frame Number Register (UHADDR1) Register Name: UHADDR1 Access Type: Offset: Reset Value: Read/Write 0x0424 0x00000000 31 - 30 29 28 27 UHADDRP3 26 25 24 23 - 22 21 20 19 UHADDRP2 18 17 16 15 - 14 13 12 11 UHADDRP1 10 9 8 7 - 6 5 4 3 UHADDRP0 2 1 0 • UHADDRP3: USB Host Address This field contains the address of the Pipe3 of the USB Device. This field is cleared when a USB reset is requested. • UHADDRP2: USB Host Address This field contains the address of the Pipe2 of the USB Device. This field is cleared when a USB reset is requested. • UHADDRP1: USB Host Address This field contains the address of the Pipe1 of the USB Device. This field is cleared when a USB reset is requested. • UHADDRP0: USB Host Address This field contains the address of the Pipe0 of the USB Device. This field is cleared when a USB reset is requested. 732 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.10 Host Frame Number Register Register Name: UHADDR2 Access Type: Offset: Reset Value: Read/Write 0x0428 0x00000000 31 - 30 29 28 27 UHADDRP7 26 25 24 23 - 22 21 20 19 UHADDRP6 18 17 16 15 - 14 13 12 11 UHADDRP5 10 9 8 7 - 6 5 4 3 UHADDRP4 2 1 0 • UHADDRP7: USB Host Address This field contains the address of the Pipe7 of the USB Device. This field is cleared when a USB reset is requested. • UHADDRP6: USB Host Address This field contains the address of the Pipe6 of the USB Device. This field is cleared when a USB reset is requested. • UHADDRP5: USB Host Address This field contains the address of the Pipe5 of the USB Device. This field is cleared when a USB reset is requested. • UHADDRP4: USB Host Address This field contains the address of the Pipe4 of the USB Device. This field is cleared when a USB reset is requested. 733 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.11 Pipe Enable/Reset Register Register Name: UPRST Access Type: Offset: Reset Value: Read/Write 0x0041C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 PRST7 22 PRST6 21 PRST5 20 PRST4 19 PRST3 18 PRST2 17 PRST1 16 PRST0 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 PEN7 6 PEN6 5 PEN5 4 PEN4 3 PEN3 2 PEN2 1 PEN1 0 PEN0 • PRSTn: Pipe n Reset Writing a one to this bit will reset the Pipe n FIFO. This resets the endpoint n registers (UPCFGn, UPSTAn, UPCONn) but not the endpoint configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ). All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management. The endpoint configuration remains active and the endpoint is still enabled. Writing a zero to this bit will complete the reset operation and allow to start using the FIFO. • PENn: Pipe n Enable Writing a one to this bit will enable the Pipe n. Writing a zero to this bit will disable the Pipe n, what forces the Pipe n state to inactive and resets the pipe n registers (UPCFGn, UPSTAn, UPCONn) but not the pipe configuration (ALLOC, PBK, PSIZE). 734 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.12 Pipe n Configuration Register Register Name: UPCFGn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0500 + (n * 0x04) 0x00000000 31 30 29 28 27 26 25 24 INTFRQ/BINTERVAL 23 - 22 - 21 - 20 PINGEN 19 18 PEPNUM 17 16 15 - 14 - 13 PTYPE 12 11 - 10 AUTOSW 9 PTOKEN 8 7 - 6 5 PSIZE 4 3 PBK 2 1 ALLOC 0 - • INTFRQ: Pipe Interrupt Request Frequency This field contains the maximum value in millisecond of the polling period for an Interrupt Pipe. This value has no effect for a non-Interrupt Pipe. This field is cleared upon sending a USB reset. • BINTERVAL: bInterval parameter for the Bulk-Out/Ping transaction This field contains the Ping/Bulk-out period. If BINTERVAL>0 and PINGEN=1, one PING token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral. If BINTERVAL=0 and PINGEN=1, multiple consecutive PING token is sent in the same micro-frame until it is ACKed. If BINTERVAL>0 and PINGEN=0, one OUT token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral. If BINTERVAL=0 and PINGEN=0, multiple consecutive OUT token is sent in the same micro-frame until it is ACKed. This value must be in the range from 0 to 255. • PINGEN: Ping Enable This bit is relevant for High-speed Bulk-out transaction only (including the control data stage and the control status stage). Writing a zero to this bit will disable the ping protocol. Writing a one to this bit will enable the ping mechanism according to the usb 2.0 standard. This bit is cleared upon sending a USB reset. • PEPNUM: Pipe Endpoint Number This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 15. This field is cleared upon sending a USB reset. • PTYPE: Pipe Type This field contains the pipe type. PTYPE 0 0 Pipe Type Control 735 32072C–AVR32–2010/03 AT32UC3A3/A4 PTYPE 0 1 1 1 0 1 Pipe Type Isochronous Bulk Interrupt This field is cleared upon sending a USB reset. • AUTOSW: Automatic Switch This bit is cleared upon sending a USB reset. 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. • PTOKEN: Pipe Token This field contains the endpoint token. PTOKEN 00 01 10 11 Endpoint Direction SETUP IN OUT reserved • PSIZE: Pipe Size This field contains the size of each pipe bank. PSIZE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Endpoint Size 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 256 bytes 512 bytes 1024 bytes This field is cleared upon sending a USB reset. • PBK: Pipe Banks This field contains the number of banks for the pipe. PBK 0 0 1 1 0 1 0 1 Endpoint Banks 1 (single-bank pipe) 2 (double-bank pipe) 3 (triple-bank pipe) Reserved For control endpoints, a single-bank pipe (0b00) should be selected. This field is cleared upon sending a USB reset. 736 32072C–AVR32–2010/03 AT32UC3A3/A4 • ALLOC: Pipe Memory Allocate Writing a one to this bit will allocate the pipe memory. Writing a zero to this bit will free the pipe memory. This bit is cleared when a USB Reset is requested. Refer to the DPRAM Management chapter for more details. 737 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.13 Pipe n Status Register Register Name: UPSTAn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x0530 + (n * 0x04) 0x00000000 31 - 30 29 28 27 PBYCT[10:4] 26 25 24 23 22 PBYCT[3:0] 21 20 19 - 18 CFGOK 17 - 16 RWALL 15 CURRBK 14 13 NBUSYBK 12 11 - 10 - 9 DTSEQ 8 7 SHORT PACKETI 6 RXSTALLDI/ CRCERRI 5 OVERFI 4 NAKEDI 3 PERRI 2 TXSTPI/ UNDERFI 1 TXOUTI 0 RXINI • PBYCT: Pipe Byte Count This field contains the byte count of the FIFO. For OUT pipe, incremented after each byte written by the user into the pipe and decremented after each byte sent to the peripheral. For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user from the pipe. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. • CFGOK: Configuration OK Status This bit is set/cleared when the UPCFGn.ALLOC bit is set. This bit is set if the pipe n number of banks (UPCFGn.PBK) and size (UPCFGn.PSIZE) are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size). If this bit is cleared, the user should rewrite correct values ot the PBK and PSIZE field in the UPCFGn register. • RWALL: Read/Write Allowed For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO. For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO. This bit is cleared otherwise. This bit is also cleared when the RXSTALL or the PERR bit is one. • CURRBK: Current Bank For non-control pipe, this field indicates the number of the current bank. CURRBK 0 0 Current Bank Bank0 738 32072C–AVR32–2010/03 AT32UC3A3/A4 CURRBK 0 1 1 1 0 1 Current Bank Bank1 Bank2 Reserved This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit. • NBUSYBK: Number of Busy Banks This field indicates the number of busy bank. For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one. For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one. NBUSYBK 0 0 1 1 0 1 0 1 Number of busy bank All banks are free. 1 busy bank 2 busy banks reserved • DTSEQ: Data Toggle Sequence This field indicates the data PID of the current bank. DTSEQ 0 0 1 1 0 1 0 1 Data toggle sequence Data0 Data1 reserved reserved • • • • • For OUT pipe, this field indicates the data toggle of the next packet that will be sent. For IN pipe, this field indicates the data toggle of the received packet stored in the current bank. SHORTPACKETI: Short Packet Interrupt This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field). This bit is cleared when the SHORTPACKETIC bit is written to one. RXSTALLDI: Received STALLed Interrupt This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe. The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one. This bit is cleared when the RXSTALLDIC bit is written to one. CRCERRI: CRC Error Interrupt This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if the TXSTPE bit is one. This bit is cleared when the CRCERRIC bit is written to one. OVERFI: Overflow Interrupt This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if the OVERFIE bit is one. This bit is cleared when the OVERFIC bit is written to one. NAKEDI: NAKed Interrupt This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one. 739 32072C–AVR32–2010/03 AT32UC3A3/A4 This bit is cleared when the NAKEDIC bit written to one. • PERRI: Pipe Error Interrupt This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to the UPERRn register to determine the source of the error. This bit is cleared when the error source bit is cleared. • TXSTPI: Transmitted SETUP Interrupt This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the TXSTPE bit is one. This bit is cleared when the TXSTPIC bit is written to one. • UNDERFI: Underflow Interrupt This bit is set, for isochronous and Interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE bit is one. This bit is set, for Isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe. (the pipe can’t send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be sent instead of. This bit is set, for Isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe. i.e, the current bank of the pipe is not free whereas a new IN USB packet is received. This packet is not stored in the bank. For Interrupt pipe, the overflowed packet is ACKed to respect the USB standard. This bit is cleared when the UNDERFIEC bit is written to one. • TXOUTI: Transmitted OUT Data Interrupt This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one. This bit is cleared when the TXOUTIC bit is written to one. • RXINI: Received IN Data Interrupt This bit is set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the RXINE bit is one. This bit is cleared when the RXINIC bit is written to one. 740 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.14 Pipe n Status Clear Register Register Name: UPSTAnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0560 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SHORT PACKETIC 6 RXSTALLDI C/ CRCERRIC 5 OVERFIC 4 NAKEDIC 3 - 2 TXSTPIC/ UNDERFIC 1 TXOUTIC 0 RXINIC Writing a one to a bit in this register will clear the corresponding bit in UPSTAn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 741 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.15 Pipe n Status Set Register Register Name: UPSTAnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0590 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 NBUSYBKS 11 - 10 - 9 - 8 - 7 SHORT PACKETIS 6 RXSTALLDIS/ 5 OVERFIS 4 NAKEDIS 3 PERRIS 2 TXSTPIS/ UNDERFIS 1 TXOUTIS 0 RXINIS CRCERRIS Writing a one to a bit in this register will set the corresponding bit in UPSTAn, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 742 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.16 Pipe n Control Register Register Name: UPCONn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x05C0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 RSTDT 17 PFREEZE 16 PDISHDMA 15 - 14 FIFOCON 13 - 12 NBUSYBKE 11 - 10 - 9 - 8 - 7 SHORT PACKETIE 6 RXSTALLDE/ CRCERRE 5 OVERFIE 4 NAKEDE 3 PERRE 2 TXSTPE/ UNDERFIE 1 TXOUTE 0 RXINE • RSTDT: Reset Data Toggle This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value for the current Pipe. This bit is cleared when proceed. • PFREEZE: Pipe Freeze This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe requests generation. This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation. • PDISHDMA: Pipe Interrupts Disable HDMA Request Enable See the UECONn.EPDISHDMA bit description. • FIFOCON: FIFO Control For OUT and SETUP Pipe: This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI. This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank. For IN Pipe: This bit is set when a new IN message is stored in the current bank, at the same time than RXINI. This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank. • NBUSYBKE: Number of Busy Banks Interrupt Enable This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE). This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE). • SHORTPACKETIE: Short Packet Interrupt Enable This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT (SHORTPACKETIE). This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT (SHORTPACKETE). 743 32072C–AVR32–2010/03 AT32UC3A3/A4 • RXSTALLDE: Received STALLed Interrupt Enable This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE). This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXSTALLDE). • CRCERRE: CRC Error Interrupt Enable This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE). This bit is cleared when the CRCERREC bit is written to one. This will disable the Transmitted IN Data interrupt (CRCERRE). • OVERFIE: Overflow Interrupt Enable This bit is set when the OVERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (OVERFIE). This bit is cleared when the OVERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (OVERFIE). • NAKEDE: NAKed Interrupt Enable This bit is set when the NAKEDES bit is written to one. This will enable the Transmitted IN Data interrupt (NAKEDE). This bit is cleared when the NAKEDEC bit is written to one. This will disable the Transmitted IN Data interrupt (NAKEDE). • PERRE: Pipe Error Interrupt Enable This bit is set when the PERRES bit is written to one. This will enable the Transmitted IN Data interrupt (PERRE). This bit is cleared when the PERREC bit is written to one. This will disable the Transmitted IN Data interrupt (PERRE). • TXSTPE: Transmitted SETUP Interrupt Enable This bit is set when the TXSTPES bit is written to one. This will enable the Transmitted IN Data interrupt (TXSTPE). This bit is cleared when the TXSTPEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXSTPE). • UNDERFIE: Underflow Interrupt Enable This bit is set when the UNDERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (UNDERFIE). This bit is cleared when the UNDERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (UNDERFIE). • TXOUTE: Transmitted OUT Data Interrupt Enable This bit is set when the TXOUTES bit is written to one. This will enable the Transmitted IN Data interrupt (TXOUTE). This bit is cleared when the TXOUTEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXOUTE). • RXINE: Received IN Data Interrupt Enable This bit is set when the RXINES bit is written to one. This will enable the Transmitted IN Data interrupt (RXINE). This bit is cleared when the RXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXINE). 744 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.17 Pipe n Control Clear Register Register Name: UPCONnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0620 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 PFREEZEC 16 PDISHDMAC 15 - 14 FIFOCONC 13 - 12 NBUSYBKEC 11 - 10 - 9 - 8 - 7 SHORT PACKETIEC 6 RXSTALLDEC/ 5 OVERFIEC 4 NAKEDEC 3 PERREC 2 TXSTPEC/ UNDERFIEC 1 TXOUTEC 0 RXINEC CRCERREC Writing a one to a bit in this register will clear the corresponding bit in UPCONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 745 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.18 Pipe n Control Set Register Register Name: UPCONnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x05F0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 RSTDTS 17 PFREEZES 16 PDISHDMAS 15 - 14 - 13 - 12 NBUSYBKES 11 - 10 - 9 - 8 - 7 SHORT PACKETIES 6 RXSTALLDES/ 5 OVERFIES 4 NAKEDES 3 PERRES 2 TXSTPES/ UNDERFIES 1 TXOUTES 0 RXINES CRCERRES Writing a one to a bit in this register will set the corresponding bit in UPCONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 746 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.19 Pipe n IN Request Register Register Name: UPINRQn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0650 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 INMODE 7 6 5 4 INRQ 3 2 1 0 • INMODE: IN Request Mode Writing a one to this bit will allow the USBB to perform infinite IN requests when the Pipe is not frozen. Writing a zero to this bit will perform a pre-defined number of IN requests. This number is the INRQ field. • INRQ: IN Request Number before Freeze This field contains the number of IN transactions before the USBB freezes the pipe. The USBB will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed. This register has no effect when the INMODE bit is one (infinite IN requests generation till the pipe is not frozen). 747 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.20 Pipe n Error Register Register Name: UPERRn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0680 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 COUNTER 5 4 CRC16 3 TIMEOUT 2 PID 1 DATAPID 0 DATATGL • COUNTER: Error Counter This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL). This field is cleared when receiving a good usb packet without any error. When this field reaches 3 (i.e., 3 consecutive errors), this pipe is automatically frozen (UPCONn.PFREEZE is set). Writing 0b00 to this field will clear the counter. • CRC16: CRC16 Error This bit is set when a CRC16 error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. • TIMEOUT: Time-Out Error This bit is set when a Time-Out error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. • PID: PID Error This bit is set when a PID error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. • DATAPID: Data PID Error This bit is set when a Data PID error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. • DATATGL: Data Toggle Error This bit is set when a Data Toggle error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. 748 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.21 Host DMA Channel n Next Descriptor Address Register Register Name: UHDMAnNEXTDESC, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0710 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 NXTDESCADDR[31:24] 23 22 21 20 19 18 17 16 NXTDESCADDR[23:16] 15 14 13 12 11 10 9 8 NXTDESCADDR[15:8] 7 6 5 4 3 - 2 - 1 - 0 - NXTDESCADDR[7:4] Same as Section 26.8.2.17. 749 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.22 Host DMA Channel n HSB Address Register Register Name: UHDMAnADDR, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0714 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 HSBADDR[31:24] 23 22 21 20 19 18 17 16 HSBADDR[23:16] 15 14 13 12 11 10 9 8 HSBADDR[15:8] 7 6 5 4 3 2 1 0 HSBADDR[7:0] Same as Section 26.8.2.18. 750 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.23 USB Host DMA Channel n Control Register Register Name: UHDMAnCONTROL, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0718 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTELENGTH[15:8] 23 22 21 20 19 18 17 16 CHBYTELENGTH[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 BURSTLOC KEN 6 DESCLD IRQEN 5 EOBUFF IRQEN 4 EOTIRQEN 3 DMAENDEN 2 BUFFCLOSE INEN 1 LDNXTCHD ESCEN 0 CHEN Same as Section 26.8.2.19. (just replace the IN endpoint term by OUT endpoint, and vice-versa) 751 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.3.24 USB Host DMA Channel n Status Register Register Name: UHDMAnSTATUS, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x071C + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTECNT[15:8] 23 22 21 20 19 18 17 16 CHBYTECNT[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 DESCLD STA 5 EOCHBUFFS TA 4 EOTSTA 3 - 2 - 1 CHACTIVE 0 CHEN Same as Section 26.8.2.20. 752 32072C–AVR32–2010/03 AT32UC3A3/A4 26.8.4 USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA) The application has access to the physical DPRAM reserved for the Endpoint/Pipe through a 64KB logical address space. The application can access a 64KB buffer linearly or fixedly as the DPRAM address increment is fully handled by hardware. Byte, half-word and word access are supported. Data should be access in a big-endian way. Disabling the USBB (by writing a zero to the USBE bit) does not reset the DPRAM. 753 32072C–AVR32–2010/03 AT32UC3A3/A4 26.9 Module Configuration The specific configuration for the USBB instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 26-8. Module name USBB Module Clock Name Clock name CLK_USBB_HSB Clock name CLK_USBB_PB Table 26-9. Register UVERS UFEATURES UADDRSIZE UNAME1 UNAME2 Register Reset Values Reset Value 0x00000320 to be defined to be defined to be defined to be defined 754 32072C–AVR32–2010/03 AT32UC3A3/A4 27. Timer/Counter (TC) Rev: 2.2.3.1 27.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse width modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Internal interrupt signal • Two global registers that act on all three TC channels 27.2 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The TC block has two global registers which act upon all three TC channels. The Block Control Register (BCR) allows the three channels to be started simultaneously with the same instruction. The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing them to be chained. 755 32072C–AVR32–2010/03 AT32UC3A3/A4 27.3 Block Diagram Figure 27-1. TC Block Diagram TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIMER_CLOCK3 TCLK1 TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOA1 TIOA2 XC0 XC1 XC2 TC0XC0S SYNC Timer/Counter Channel 0 TIOA TIOB I/O Contr oller CLK0 CLK1 CLK2 A0 B0 TIOA0 TIOB0 INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC INT1 Timer/Counter Channel 1 TIOA TIOB TIOA1 TIOB1 A1 B1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOB TIOA2 TIOB2 A2 B2 SYNC INT2 Timer Count er Interrupt Controller 27.4 I/O Lines Description Table 27-1. Pin Name CLK0-CLK2 A0-A2 B0-B2 I/O Lines Description Description External Clock Input I/O Line A I/O Line B Type Input Input/Output Input/Output 27.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 27.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first program the I/O Controller to assign the TC pins to their peripheral functions. 756 32072C–AVR32–2010/03 AT32UC3A3/A4 27.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TC before disabling the clock, to avoid freezing the TC in an undefined state. 27.5.3 27.5.4 Interrupts The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt requires the interrupt controller to be programmed first. 27.5.5 Debug Operation The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps peripherals running in debug operation. 27.6 27.6.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Figure 27-3 on page 772. Channel I/O Signals As described in Figure 27-1 on page 756, each Channel has the following I/O signals. 27.6.1.1 Table 27-2. Channel I/O Signals Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture mode: Timer Counter Input Waveform mode: Timer Counter Output Capture mode: Timer Counter Input Waveform mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal Block/Channel Channel Signal TIOB INT SYNC 27.6.1.2 16-bit counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Status Register (SRn.COVFS) is set. The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 757 32072C–AVR32–2010/03 AT32UC3A3/A4 27.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 27-2 on page 758. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about the connection of these clock sources. • External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details about the connection of these clock sources. This selection is made by the Clock Selection field in the Channel n Mode Register (CMRn.TCCLKS). The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The Burst Signal Selection field in the CMRn register (CMRn.BURST) defines this signal. Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC. Figure 27-2. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 27.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 27-3 on page 759. 758 32072C–AVR32–2010/03 AT32UC3A3/A4 • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions have no effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA). • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. In Capture mode the clock can be stopped by an RB load event if the Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop commands have effect only if the clock is enabled. Figure 27-3. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 27.6.1.5 TC operating modes Each channel can independently operate in two different modes: • Capture mode provides measurement on signals. • Waveform mode provides wave generation. The TC operating mode selection is done by writing to the Wave bit in the CCRn register (CCRn.WAVE). In Capture mode, TIOA and TIOB are configured as inputs. In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 759 32072C–AVR32–2010/03 AT32UC3A3/A4 27.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.SWTRG). • SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing a one to the Synchro Command bit in the BCR register (BCR.SYNC). • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn (CMRn.CPCTRG) is written to one. The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external event can then be programmed to perform a trigger by writing a one to the External Event Trigger Enable bit in CMRn (CMRn.ENETRG). If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 27.6.2 Capture Operating Mode This mode is entered by writing a zero to the CMRn.WAVE bit. Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 27-4 on page 762 shows the configuration of the TC channel when programmed in Capture mode. 27.6.2.1 Capture registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in SRn (SRn.LOVRS). In this case, the old value is overwritten. 760 32072C–AVR32–2010/03 AT32UC3A3/A4 27.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled. 761 32072C–AVR32–2010/03 TCCLKS CLKI CLKSTA CLKEN CLKDIS 32072C–AVR32–2010/03 TIMER_CLOCK1 Q Q S R LDBSTOP BURST LDBDIS Register C Capture Register A SWTRG CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LD A R LDRB SR Edge Detector If RA is Loaded IMR CPCTRG 16-bit Counter Capture Register B S R Figure 27-4. Capture Mode TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 1 Compare RC = SYNC MTIOB TIOB CPCS COVFS LDRBS LDRAS LOVRS ETRGS MTIOA If RA is not Loaded or RB is Loaded Edge Detector TIOA Timer/Counter Channel INT AT32UC3A3/A4 762 AT32UC3A3/A4 27.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event. Figure 27-5 on page 764 shows the configuration of the TC channel when programmed in Waveform operating mode. 27.6.3.1 Waveform selection Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 763 32072C–AVR32–2010/03 O utput Contr oller EN G ETR SR TIOB Edge Detector BSWTRG IMR Timer/Counter Channel AT32UC3A3/A4 764 INT O utput Cont r oller 32072C–AVR32–2010/03 TCCLKS CLKSTA CLKDIS CLKI Q Q R CPCSTOP AEEVT S R CPCDIS S ACPA CLKEN ACPC MTIOA TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 Figure 27-5. Waveform Mode TIOA XC2 BURST Register A WAVSEL 1 16-bit Counter CLK Register B Register C ASWTRG Compare RA = Compare RB = Compare RC = SWTRG RESET OVF BCPC T rig BCPB WAVSEL E VT E BEEVT E VTEDG E CPCS CPBS CPAS ETRGS COVFS MTIOB SYNC TIOB AT32UC3A3/A4 27.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 27-6 on page 765. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 27-7 on page 766. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 27-6. WAVSEL= 0 Without Trigger Counter Value 0xFFFF RC Counter cleared by compare match with 0xFFFF RB RA Waveform Examples TIOB Time TIOA 765 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 27-7. WAVSEL= 0 With Trigger Counter Value 0xFFFF RC RB Counter cleared by trigger Counter cleared by compare match with 0xFFFF RA Waveform Examples TIOB Time TIOA 27.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 27-8 on page 767. It is important to note that CVn can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 27-9 on page 767. In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the counter clock (CMRn.CPCDIS = 1). 766 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 27-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF RC Counter cleared by compare match with RC RB RA Waveform Examples TIOB Time TIOA Figure 27-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 27.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of CVn is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 27-10 on page 768. 767 32072C–AVR32–2010/03 AT32UC3A3/A4 A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 27-11 on page 768. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 27-10. WAVSEL = 1 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 27-11. WAVSEL = 1 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Counter decremented by compare match with 0xFFFF Waveform Examples TIOB Time TIOA 768 32072C–AVR32–2010/03 AT32UC3A3/A4 27.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 27-12 on page 769. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 27-13 on page 770. RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 27-12. WAVSEL = 3 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 769 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 27-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 27.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger. The External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to zero, no external event is defined. If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by writing a one to the CMRn.ENETRG bit. As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the CMRn.WAVSEL field. 27.6.3.7 Output controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: • software trigger • external event • RC compare RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the following fields in CMRn: • RC Compare Effect on TIOB (CMRn.BCPC) 770 32072C–AVR32–2010/03 AT32UC3A3/A4 • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.ACPA) 771 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7 User Interface TC Register Memory Map Register Channel 0 Control Register Channel 0 Mode Register Channel 0 Counter Value Channel 0 Register A Channel 0 Register B Channel 0 Register C Channel 0 Status Register Interrupt Enable Register Channel 0 Interrupt Disable Register Channel 0 Interrupt Mask Register Channel 1 Control Register Channel 1 Mode Register Channel 1 Counter Value Channel 1 Register A Channel 1 Register B Channel 1 Register C Channel 1 Status Register Channel 1 Interrupt Enable Register Channel 1 Interrupt Disable Register Channel 1 Interrupt Mask Register Channel 2 Control Register Channel 2 Mode Register Channel 2 Counter Value Channel 2 Register A Channel 2 Register B Channel 2 Register C Channel 2 Status Register Channel 2 Interrupt Enable Register Channel 2 Interrupt Disable Register Channel 2 Interrupt Mask Register Block Control Register Block Mode Register Notes: Register Name CCR0 CMR0 CV0 RA0 RB0 RC0 SR0 IER0 IDR0 IMR0 CCR1 CMR1 CV1 RA1 RB1 RC1 SR1 IER1 IDR1 IMR1 CCR2 CMR2 CV2 RA2 RB2 RC2 SR2 IER2 IDR2 IMR2 BCR BMR Access Write-only Read/Write Read-only Read/Write(1) Read/Write(1) Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write Read-only Read/Write Read/Write (1) (1) Table 27-3. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x40 0x44 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x80 0x84 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xC0 0xC4 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 00x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write Read-only Read/Write(1) Read/Write(1) Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write 1. Read-only if CMRn.WAVE is zero 772 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.1 Name: Channel Control Register CCR Write-only 0x00 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 SWTRG 1 CLKDIS 0 CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started. 0: Writing a zero to this bit has no effect. • CLKDIS: Counter Clock Disable Command 1: Writing a one to this bit will disable the clock. 0: Writing a zero to this bit has no effect. • CLKEN: Counter Clock Enable Command 1: Writing a one to this bit will enable the clock if CLKDIS is not one. 0: Writing a zero to this bit has no effect. 773 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.2 Name: Channel Mode Register: Capture Mode CMR Read/Write 0x04 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 LDRB 18 17 LDRA 16 15 WAVE 14 CPCTRG 13 - 12 - 11 - 10 ABETRG 9 ETRGEDG 8 7 LDBDIS 6 LDBSTOP 5 BURST 4 3 CLKI 2 1 TCCLKS 0 • LDRB: RB Loading Selection LDRB 0 1 2 3 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • LDRA: RA Loading Selection LDRA 0 1 2 3 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • WAVE 1: Capture mode is disabled (Waveform mode is enabled). 0: Capture mode is enabled. • CPCTRG: RC Compare Trigger Enable 1: RC Compare resets the counter and starts the counter clock. 0: RC Compare has no effect on the counter and its clock. • ABETRG: TIOA or TIOB External Trigger Selection 1: TIOA is used as an external trigger. 774 32072C–AVR32–2010/03 AT32UC3A3/A4 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG 0 1 2 3 Edge none rising edge falling edge each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs. • BURST: Burst Signal Selection BURST 0 1 2 3 Burst Signal Selection The clock is not gated by an external signal XC0 is ANDed with the selected clock XC1 is ANDed with the selected clock XC2 is ANDed with the selected clock • CLKI: Clock Invert 1: The counter is incremented on falling edge of the clock. 0: The counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection TCCLKS 0 1 2 3 4 5 6 7 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 775 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.3 Name: Channel Mode Register: Waveform Mode CMR Read/Write 0x04 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 BSWTRG 30 29 BEEVT 28 27 BCPC 26 25 BCPB 24 23 ASWTRG 22 21 AEEVT 20 19 ACPC 18 17 ACPA 16 15 WAVE 14 WAVSEL 13 12 ENETRG 11 EEVT 10 9 EEVTEDG 8 7 CPCDIS 6 CPCSTOP 5 BURST 4 3 CLKI 2 1 TCCLKS 0 • BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 1 2 3 Effect none set clear toggle • BEEVT: External Event Effect on TIOB BEEVT 0 1 2 3 Effect none set clear toggle 776 32072C–AVR32–2010/03 AT32UC3A3/A4 • BCPC: RC Compare Effect on TIOB BCPC 0 1 2 3 Effect none set clear toggle • BCPB: RB Compare Effect on TIOB BCPB 0 1 2 3 Effect none set clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 1 2 3 Effect none set clear toggle • AEEVT: External Event Effect on TIOA AEEVT 0 1 2 3 Effect none set clear toggle • ACPC: RC Compare Effect on TIOA ACPC 0 1 2 3 Effect none set clear toggle 777 32072C–AVR32–2010/03 AT32UC3A3/A4 • ACPA: RA Compare Effect on TIOA ACPA 0 1 2 3 Effect none set clear toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled). • WAVSEL: Waveform Selection WAVSEL 0 1 2 3 Effect UP mode without automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare • ENETRG: External Event Trigger Enable 1: The external event resets the counter and starts the counter clock. 0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. • EEVT: External Event Selection EEVT 0 1 2 3 Note: Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • EEVTEDG: External Event Edge Selection EEVTEDG 0 1 2 3 Edge none rising edge falling edge each edge • CPCDIS: Counter Clock Disable with RC Compare 1: Counter clock is disabled when counter reaches RC. 0: Counter clock is not disabled when counter reaches RC. • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 778 32072C–AVR32–2010/03 AT32UC3A3/A4 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST 0 1 2 3 Burst Signal Selection The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock. 0: Counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection TCCLKS 0 1 2 3 4 5 6 7 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 779 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.4 Name: Channel Counter Value Register CV Read-only 0x10 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 CV[15:8] 11 10 9 8 7 6 5 4 CV[7:0] 3 2 1 0 • CV: Counter Value CV contains the counter value in real time. 780 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.5 Name: Channel Register A RA Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 0x14 + n * 0X40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RA[15:8] 11 10 9 8 7 6 5 4 RA[7:0] 3 2 1 0 • RA: Register A RA contains the Register A value in real time. 781 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.6 Name: Channel Register B RB Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 0x18 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RB[15:8] 11 10 9 8 7 6 5 4 RB[7:0] 3 2 1 0 • RB: Register B RB contains the Register B value in real time. 782 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.7 Name: Channel Register C RC Read/Write 0x1C + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RC[15:8] 11 10 9 8 7 6 5 4 RC[7:0] 3 2 1 0 • RC: Register C RC contains the Register C value in real time. 783 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.8 Name: Channel Status Register SR Read-only 0x20 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 MTIOB 17 MTIOA 16 CLKSTA 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts. • MTIOB: TIOB Mirror 1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven high. 0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven low. • MTIOA: TIOA Mirror 1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven high. 0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven low. • CLKSTA: Clock Enabling Status 1: This bit is set when the clock is enabled. 0: This bit is cleared when the clock is disabled. • ETRGS: External Trigger Status 1: This bit is set when an external trigger has occurred. 0: This bit is cleared when the SR register is read. • LDRBS: RB Loading Status 1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • LDRAS: RA Loading Status 1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • CPCS: RC Compare Status 1: This bit is set when an RC Compare has occurred. 0: This bit is cleared when the SR register is read. 784 32072C–AVR32–2010/03 AT32UC3A3/A4 • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • COVFS: Counter Overflow Status 1: This bit is set when a counter overflow has occurred. 0: This bit is cleared when the SR register is read. 785 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.9 Name: Channel Interrupt Enable Register IER Write-only 0x24 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 786 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.10 Name: Channel Interrupt Disable Register IDR Write-only 0x28 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 787 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.11 Name: Channel Interrupt Mask Register IMR Read-only 0x2C + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 788 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.12 Name: Block Control Register BCR Write-only 0xC0 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0: Writing a zero to this bit has no effect. 789 32072C–AVR32–2010/03 AT32UC3A3/A4 27.7.13 Name: Block Mode Register BMR Read/Write 0xC4 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 TC2XC2S 4 3 TC1XC1S 2 1 TC0XC0S 0 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 1 2 3 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 1 2 3 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 Signal Connected to XC0 TCLK0 790 32072C–AVR32–2010/03 AT32UC3A3/A4 1 2 3 none TIOA1 TIOA2 791 32072C–AVR32–2010/03 AT32UC3A3/A4 27.8 Module Configuration The specific configuration for each TC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 27-4. Module name TC0 TC1 Module Clock Name Clock name CLK_TC0 CLK_TC1 27.8.1 Clock Connections Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 27-5. Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Timer/Counter Internal Clock Connections Connection 32 KHz clock PBA Clock / 2 PBA Clock / 8 PBA Clock / 32 PBA Clock / 128 792 32072C–AVR32–2010/03 AT32UC3A3/A4 28. Analog-to-Digital Converter (ADC) Rev: 2.0.0.1 28.1 Features • Integrated multiplexer offering up to eight independent analog inputs • Individual enable and disable of each channel • Hardware or software trigger – External trigger pin – Timer counter outputs (corresponding TIOA trigger) • Peripheral DMA Controller support • Possibility of ADC timings configuration • Sleep mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 28.2 Overview The Analog-to-Digital Converter (ADC) is based on a Successive Approximation Register (SAR) 10-bit ADC. It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital conversions of 8 analog lines. The conversions extend from 0V to VDDANA. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the TRIGGER pin, or internal triggers from timer counter output(s) are configurable. The ADC also integrates a sleep mode and a conversion sequencer and connects with a Peripheral DMA Controller channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as startup time and sample & hold time. 793 32072C–AVR32–2010/03 AT32UC3A3/A4 28.3 Block Diagram Figure 28-1. ADC Block Diagram Timer Counter Channels ADC Trigger Selection TRIGGER Control Logic ADC Interrupt Interrupt Controller VDDANA VREF High Speed Bus (HSB) ADDedicated Analog Inputs ADUser Interface Peripheral DMA Controller AD- Peripheral Bridge Analog Inputs Multiplexed With I/O lines ADADI/O Controller Successive Approximation Register Analog-to-Digital Converter Peripheral Bus (PB) AD- GND 28.4 I/O Lines Description ADC Pins Description Description Analog power supply Analog input channels External trigger Table 28-1. Pin Name VDDANA AD[0] - AD[7] TRIGGER 28.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 28.5.1 I/O Lines The TRIGGER pin may be shared with other peripheral functions through the I/O Controller. 794 32072C–AVR32–2010/03 AT32UC3A3/A4 28.5.2 Power Management In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the ADC behavior. Clocks The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the ADC before disabling the clock, to avoid freezing the ADC in an undefined state. 28.5.3 28.5.4 Interrupts The ADC interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the interrupt controller to be programmed first. 28.5.5 Analog Inputs The analog input pins can be multiplexed with I/O lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding I/O is configured through the I/O contoller. By default, after reset, the I/O line is configured as a logic input. 28.5.6 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be non-connected. 28.6 28.6.1 Functional Description Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires sample and hold clock cycles as defined in the Sample and Hold Time field of the Mode Register (MR.SHTIM) and 10 ADC Clock cycles. The ADC Clock frequency is selected in the Prescaler Rate Selection field of the MR register (MR.PRESCAL). The ADC Clock range is between CLK_ADC/2, if the PRESCAL field is 0, and CLK_ADC/128, if the PRESCAL field is 63 (0x3F). The PRESCAL field must be written in order to provide an ADC Clock frequency according to the parameters given in the Electrical Characteristics chapter. 28.6.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage connected to VDDANA. Analog input values between these voltages are converted to digital values based on a linear conversion. Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by writing a one to the Resolution bit in the MR register (MR.LOWRES). By default, after a reset, the resolution is the highest and the Converted Data field in the Channel Data Registers (CDRn.DATA) is fully used. By writing a one to the LOWRES bit, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the Channel Data Registers (CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Register (LCDR.LDATA) will be read as zero too. 28.6.3 795 32072C–AVR32–2010/03 AT32UC3A3/A4 Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. 28.6.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the CDR register of the current channel and in the LCDR register. Channels are enabled by writing a one to the Channel n Enable bit (CHn) in the CHER register. The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY can trigger an interrupt. Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel. Figure 28-2. EOCn and DRDY Flag Behavior Write CR With START=1 Read CDRn Write CR With START=1 Read LCDR CHn(CHSR) EOCn(SR) Conversion Time Conversion Time DRDY(SR) 796 32072C–AVR32–2010/03 AT32UC3A3/A4 If the CDR register is not read before further incoming data is converted, the corresponding Overrun Error bit in the SR register (SR.OVREn) is set. In the same way, new data converted when DRDY is high sets the General Overrun Error bit in the SR register (SR.GOVRE). The OVREn and GOVRE bits are automatically cleared when the SR register is read. Figure 28-3. GOVRE and OVREn Flag Behavior Read SR TRIGGER CH0(CHSR) CH1(CHSR) LCDR CRD0 CRD1 Undefined Data Undefined Data Undefined Data Conversion Data A Data A Data B Data C Data C Data B EOC0(SR) Conversion Read CDR0 EOC1(SR) Conversion Read CDR1 GOVRE(SR) DRDY(ASR) OVRE0(SR) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in SR are unpredictable. 797 32072C–AVR32–2010/03 AT32UC3A3/A4 28.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing a one to the START bit in the Control Register (CR.START). The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger Selection field in the Mode Register (MR.TRIGSEL). The selected hardware trigger is enabled by writing a one to the Trigger Enable bit in the Mode Register (MR.TRGEN). If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (CHER) and Channel Disable (CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a Peripheral DMA Controller, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 28.6.6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by writing a one to the Sleep Mode bit in the Mode Register (MR.SLEEP). The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the Peripheral DMA Controller. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. 798 32072C–AVR32–2010/03 AT32UC3A3/A4 28.6.7 ADC Timings Each ADC has its own minimal startup time that is defined through the Start Up Time field in the Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics chapter. In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be defined through the Sample and Hold Time field in the Mode Register (MR.SHTIM). This time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier. 28.6.8 Conversion Performances For performance and electrical characteristics of the ADC, see the Electrical Characteristics chapter. 799 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7 User Interface ADC Register Memory Map Register Control Register Mode Register Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 ...(if implemented) Channel Data Register 7(if implemented) Version Register Name CR MR CHER CHDR CHSR SR LCDR IER IDR IMR CDR0 ... CDR7 VERSION Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only ... Read-only Read-only Reset State 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000C0000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ... 0x00000000 - (1) Table 28-2. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 ... 0x4C 0xFC Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 800 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.1 Name: Control Register CR Write-only 0x00 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 START 24 – 16 – 8 – 0 SWRST Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – • START: Start Conversion Writing a one to this bit will begin an analog-to-digital conversion. Writing a zero to this bit has no effect. This bit always reads zero. • SWRST: Software Reset Writing a one to this bit will reset the ADC. Writing a zero to this bit has no effect. This bit always reads zero. 801 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.2 Name: Mode Register MR Read/Write 0x04 0x00000000 30 – 22 29 – 21 28 – 20 27 26 SHTIM 19 STARTUP 11 PRESCAL 7 – 6 – 5 SLEEP 4 LOWRES 3 2 TRGSEL 1 0 TRGEN 18 17 16 25 24 Access Type: Offset: Reset Value: 31 – 23 – 15 14 13 12 10 9 8 • SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+3) / ADCClock • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock • PRESCAL: Prescaler Rate Selection ADCClock = CLK_ADC / ( (PRESCAL+1) * 2 ) • SLEEP: Sleep Mode 1: Sleep Mode is selected. 0: Normal Mode is selected. • LOWRES: Resolution 1: 8-bit resolution is selected. 0: 10-bit resolution is selected. • TRGSEL: Trigger Selection TRGSEL 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Selected TRGSEL Internal Trigger 0, depending of chip integration Internal Trigger 1, depending of chip integration Internal Trigger 2, depending of chip integration Internal Trigger 3, depending of chip integration Internal Trigger 4, depending of chip integration Internal Trigger 5, depending of chip integration External trigger • TRGEN: Trigger Enable 1: The hardware trigger selected by the TRGSEL field is enabled. 0: The hardware triggers are disabled. Starting a conversion is only possible by software. 802 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.3 Name: Channel Enable Register CHER Write-only 0x10 0x00000000 30 – 22 – 14 – 6 CH6 29 – 21 – 13 – 5 CH5 28 – 20 – 12 – 4 CH4 27 – 19 – 11 – 3 CH3 26 – 18 – 10 – 2 CH2 25 – 17 – 9 – 1 CH1 24 – 16 – 8 – 0 CH0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 CH7 • CHn: Channel n Enable Writing a one to these bits will set the corresponding bit in CHSR. Writing a zero to these bits has no effect. These bits always read a zero. 803 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.4 Name: Channel Disable Register CHDR Write-only 0x14 0x00000000 30 – 22 – 14 – 6 CH6 29 – 21 – 13 – 5 CH5 28 – 20 – 12 – 4 CH4 27 – 19 – 11 – 3 CH3 26 – 18 – 10 – 2 CH2 25 – 17 – 9 – 1 CH1 24 – 16 – 8 – 0 CH0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 CH7 • CHn: Channel n Disable Writing a one to these bits will clear the corresponding bit in CHSR. Writing a zero to these bits has no effect. These bits always read a zero. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in SR are unpredictable. 804 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.5 Name: Channel Status Register CHSR Read-only 0x18 0x00000000 30 – 22 – 14 – 6 CH6 29 – 21 – 13 – 5 CH5 28 – 20 – 12 – 4 CH4 27 – 19 – 11 – 3 CH3 26 – 18 – 10 – 2 CH2 25 – 17 – 9 – 1 CH1 24 – 16 – 8 – 0 CH0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 CH7 • CHn: Channel n Status These bits are set when the corresponding bits in CHER is written to one. These bits are cleared when the corresponding bits in CHDR is written to one. 1: The corresponding channel is enabled. 0: The corresponding channel is disabled. 805 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.6 Name: Status Register SR Read-only 0x1C 0x000C0000 30 – 22 – 14 OVRE6 6 EOC6 29 – 21 – 13 OVRE5 5 EOC5 28 – 20 – 12 OVRE4 4 EOC4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 – 23 – 15 OVRE7 7 EOC7 • RXBUFF: RX Buffer Full This bit is set when the Buffer Full signal from the Peripheral DMA is active. This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive. • ENDRX: End of RX Buffer This bit is set when the End Receive signal from the Peripheral DMA is active. This bit is cleared when the End Receive signal from the Peripheral DMA is inactive. • GOVRE: General Overrun Error This bit is set when a General Overrun Error has occurred. This bit is cleared when the SR register is read. 1: At least one General Overrun Error has occurred since the last read of the SR register. 0: No General Overrun Error occurred since the last read of the SR register. • DRDY: Data Ready This bit is set when a data has been converted and is available in the LCDR register. This bit is cleared when the LCDR register is read. 0: No data has been converted since the last read of the LCDR register. 1: At least one data has been converted and is available in the LCDR register. • OVREn: Overrun Error n These bits are set when an overrun error on the corresponding channel has occurred (if implemented). These bits are cleared when the SR register is read. 0: No overrun error on the corresponding channel (if implemented) since the last read of SR. 1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR. • EOCn: End of Conversion n These bits are set when the corresponding conversion is complete. These bits are cleared when the corresponding CDR or LCDR registers are read. 0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished. 1: Corresponding analog channel (if implemented) is enabled and conversion is complete. 806 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.7 Name: Last Converted Data Register LCDR Read-only 0x20 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 LDATA[7:0] • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 LDATA[9:8] 1 0 24 – 16 – 8 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 807 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.8 Name: Interrupt Enable Register IER Write-only 0x24 0x00000000 30 – 22 – 14 OVRE6 6 EOC6 29 – 21 – 13 OVRE5 5 EOC5 28 – 20 – 12 OVRE4 4 EOC4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 – 23 – 15 OVRE7 7 EOC7 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 808 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.9 Name: Interrupt Disable Register IDR Write-only 0x28 0x00000000 30 – 22 – 14 OVRE6 6 EOC6 29 – 21 – 13 OVRE5 5 EOC5 28 – 20 – 12 OVRE4 4 EOC4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 – 23 – 15 OVRE7 7 EOC7 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 809 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.10 Name: Interrupt Mask Register IMR Read-only 0x2C 0x00000000 30 – 22 – 14 OVRE6 6 EOC6 29 – 21 – 13 OVRE5 5 EOC5 28 – 20 – 12 OVRE4 4 EOC4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 – 23 – 15 OVRE7 7 EOC7 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is cleared when the corresponding bit in IER is written to one. 810 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.11 Name: Channel Data Register CDRx Read-only 0x2C-0x4C 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DATA[7:0] • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled. 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 DATA[9:8] 1 0 24 – 16 – 8 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 811 32072C–AVR32–2010/03 AT32UC3A3/A4 28.7.12 Name: Version Register VERSION Read-only 0xFC – 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 27 – 19 26 – 18 VARIANT 11 10 9 VERSION[11:8] 2 1 8 25 – 17 24 – 16 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 3 0 812 32072C–AVR32–2010/03 AT32UC3A3/A4 28.8 Module Configuration The specific configuration for the ADC instance is listed in the following tables. Table 28-3. Feature Module configuration ADC 8 TIOA Ouput A of the Timer Counter Channel 0 TIOB Ouput B of the Timer Counter Channel 0 TIOA Ouput A of the Timer Counter Channel 1 TIOB Ouput B of the Timer Counter Channel 1 TIOA Ouput A of the Timer Counter Channel 2 TIOB Ouput B of the Timer Counter Channel 2 ADC_NUM_CHANNELS Internal Trigger 0 Internal Trigger 1 Internal Trigger 2 Internal Trigger 3 Internal Trigger 4 Internal Trigger 5 Table 28-4. Module name ADC Module Clock Name Clock name CLK_ADC Table 28-5. Module name VERSION Register Reset Values Reset Value 0x00000200 813 32072C–AVR32–2010/03 AT32UC3A3/A4 29. HSB Bus Performance Monitor (BUSMON) Rev 1.0.0.0 29.1 Features • Allows performance monitoring of High Speed Bus master interfaces – Up to 4 masters can be monitored – Peripheral Bus access to monitor registers • The following is monitored – Data transfer cycles – Bus stall cycles – Maximum access latency for a single transfer • Automatic handling of event overflow 29.2 Overview BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB). Up to 4 device-specific masters can be measured. Each of these masters is part of a measurement channel. Which masters that are connected to a channel is device-specific. Devices may choose not to implement all channels. 29.3 Block Diagram Figure 29-1. BUSMON Block Diagram Master A Master B Master C Master D Channel 0 Slave 0 Registers Master E Master F Master G Master H Channel 1 Slave 1 Registers Master I Master J Master K Master L Channel 2 Slave 2 Registers Master M Master N Master O Master P Channel 3 Slave 3 Registers Control Peripheral Bus Interface 814 32072C–AVR32–2010/03 AT32UC3A3/A4 29.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 29.4.1 Clocks The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager. This clock is enabled at reset and can be disabled in the Power Manager. It is recommended to disable the BUSMON before disabling the clock, to avoid freezing the BUSMON in an undefined state. 29.5 Functional Description Three different parameters can be measured by each channel: • The number of data transfer cycles since last channel reset • The number of stall cycles since last channel reset • The maximum continuous number of stall cycles since last channel reset (This approximates the max latency in the transfers.) These measurements can be extracted by software and used to generate indicators for bus latency, bus load and maximum bus latency. Each of the counters have a fixed width, and may therefore overflow. When overflow is encountered in either the Channel n Data Cycles (DATAn) register or the Channel n Stall Cycles (STALLn) register of a channel, all registers in the channel are reset. This behavior is altered if the Channel n Overflow Freeze (CHnOF) bit is set in the Control (CONTROL) register. If this bit is written to one, the channel registers are frozen when either DATAn or STALLn reaches its maximum value. This simplifies one-shot readout of the counter values. The registers can also be manually reset by writing to the CONTROL register. The Channeln Max Initiation Latency (LATn) register is saturating, when its max count is reached, it will be set to its maximum value. The LATn register is reset whenever DATAn and STALLn are reset. A counter must manually be enabled by writing to the CONTROL register. 815 32072C–AVR32–2010/03 AT32UC3A3/A4 29.6 User interface BUSMON Register Memory Map Register Control register Channel0 Data Cycles register Channel0 Stall Cycles register Channel0 Max Initiation Latency register Channel1 Data Cycles register Channel1 Stall Cycles register Channel1 Max Initiation Latency register Channel2 Data Cycles register Channel2 Stall Cycles register Channel2 Max Initiation Latency register Channel3 Data Cycles register Channel3 Stall Cycles register Channel3 Max Initiation Latency register Parameter register Version register Register Name CONTROL DATA0 STALL0 LAT0 DATA1 STALL1 LAT1 DATA2 STALL2 LAT2 DATA3 STALL3 LAT3 PARAMETER VERSION Access Read/Write Read Read Read Read Read Read Read Read Read Read Read Read Read Read Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) -(1) Table 29-1. Offset 0x00 0x10 0x14 0x18 0x20 0x24 0x28 0x30 0x34 0x38 0x40 0x44 0x48 0x50 0x54 Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 816 32072C–AVR32–2010/03 AT32UC3A3/A4 29.6.1 Name: Control Register CONTROL Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 CH3RES 18 CH2RES 17 CH1RES 16 CH0RES 15 - 14 - 13 - 12 - 11 CH3OF 10 CH2OF 9 CH1OF 8 CH0OF 7 - 6 - 5 - 4 - 3 CH3EN 2 CH2EN 1 CH1EN 0 CH0EN • CHnRES: Channel Counter Reset Writting a one to this bit will reset the counter in the channel n. Writting a zero to this bit has no effect. This bit always reads as zero. • CHnOF: Channel Overflow Freeze 1: All channel n registers are frozen just before DATA or STALL overflows. 0: The channel n registers are reset if DATA or STALL overflows. • CHnEN: Channel Enabled 1: The channel n is enabled. 0: The channel n is disabled. 817 32072C–AVR32–2010/03 AT32UC3A3/A4 29.6.2 Name: Channel n Data Cycles Register DATAn Read-Only 0x10 + n*0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA: Data cycles counted since the last reset. 818 32072C–AVR32–2010/03 AT32UC3A3/A4 29.6.3 Name: Channel n Stall Cycles Register STALLn Read-Only 0x14 + n*0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 STALL[31:24] 27 26 25 24 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 • STALL: Stall cycles counted since the last reset. 819 32072C–AVR32–2010/03 AT32UC3A3/A4 29.6.4 Name: Channel n Max Transfer Initiation Cycles Register LATn Read-Only 0x18 + n*0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 LAT[31:24] 27 26 25 24 23 22 21 20 LAT[23:16] 19 18 17 16 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 • LAT: This field is cleared whenever the DATA or STALL register is reset. Maximum transfer initiation cycles counted since the last reset. This counter is saturating. 820 32072C–AVR32–2010/03 AT32UC3A3/A4 29.6.5 Name: Parameter Register PARAMETER Read-only 0x50 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 CH3IMPL 2 CH2IMPL 1 CH1IMPL 0 CH0IMPL • CHnIMP: Channel Implementation 1: The corresponding channel is implemented. 0: The corresponding channel is not implemented. 821 32072C–AVR32–2010/03 AT32UC3A3/A4 29.6.6 Name: Version Register VERSION Read-only 0x54 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 822 32072C–AVR32–2010/03 AT32UC3A3/A4 29.7 Module Configuration Table 29-2. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000100 0x0000000F 823 32072C–AVR32–2010/03 AT32UC3A3/A4 30. MultiMedia Card Interface (MCI) Rev. 4.1.0.0 30.1 Features • • • • • • • • • • • • • • Compatible with Multimedia Card specification version 4.3 Compatible with SD Memory Card specification version 2.0 Compatible with SDIO specification version 1.1 Compatible with CE-ATA specification 1.1 Cards clock rate up to master clock divided by two Boot Operation Mode support High Speed mode support Embedded power management to slow down clock rate when not used Supports 2 Slots – Each slot for either a MultiMediaCard bus (up to 30 cards) or an SD Memory Card Support for stream, block and multi-block data read and write Supports connection to DMA Controller – Minimizes processor intervention for large buffer transfers Built in FIFO (from 16 to 256 bytes) with large memory aperture supporting incremental access Support for CE-ATA completion cignal disable command Protection against unexpected modification on-the-Fly of the configuration registers 30.2 Overview The Multimedia Card Interface (MCI) supports the MultiMedia Card (MMC) specification V4.3, the SD Memory Card specification V2.0, the SDIO V1.1 specificationand CE-ATA specification V1.1. The MCI includes a Command Register (CMDR), Response Registers (RSPRn), data registers, time-out counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi block data read and write, and is compatible with the DMA Controller, minimizing processor intervention for large buffers transfers. The MCI operates at a rate of up to CLK_MCI divided by 2 and supports the interfacing of 2 Slots. Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). The SDCard/SDIO Slot Selection field in the SDCard/SDIO Register (SDCR.SDCSEL) performs this selection. The SD Memory Card communication is based on a nine-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a seven-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. MCI fully supports CE-ATA Revision 1.1, built on the MMC System specification V4.0. The module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable. 824 32072C–AVR32–2010/03 AT32UC3A3/A4 30.3 Block Diagram Figure 30-1. MCI Block Diagram Peripheral Bus Brigde DMA Controller Peripheral Bus CLK CMD MCI Interface Power Manager CLK_MCI I/O controller DATA Interrupt Control MCI Interrupt Figure 30-2. Application Block Diagram Application Layer Ex: File System, Audio, Security, etc Physical Layer MCI Interface 12 34567 1 2 3 4 5 6 78 9 910 1213 8 MMC SDCard 825 32072C–AVR32–2010/03 AT32UC3A3/A4 30.4 I/O Lines Description I/O Lines Description Pin Description Command/Response Clock Data 0..7 of Slot A Data 0..7 of Slot B Type (1) Input/Output/ PP/OD Input/Output Input/Output/PP Input/Output/PP Comments CMD of a MMC or SDCard/SDIO CLK of a MMC or SD Card/SDIO DAT[0..7] of a MMC DAT[0..3] of a SD Card/SDIO DAT[0..7] of a MMC DAT[0..3] of a SD Card/SDIO Table 30-1. Pin Name CMD[1:0] CLK DATA[7:0] DATA[15:8] 1. PP: Push/Pull, OD: Open Drain 30.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 30.5.1 Power Management If the CPU enters a sleep mode that disables clocks used by the MCI, the MCI will stop functioning and resume operation after the system wakes up from sleep mode. I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with GPIO lines. User must first program the I/O controller to assign the peripheral functions to MCI pins. 30.5.2 30.5.3 Clocks The clock for the MCI bus interface (CLK_MCI) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the MCI before disabling the clock, to avoid freezing the MCI in an undefined state. 30.5.4 Interrupt The MCI interrupt request line is connected to the interrupt controller. Using the MCI interrupt requires the interrupt controller to be programmed first. 30.6 30.6.1 Functional Description Bus Topology Figure 30-3. Multimedia Memory Card Bus Topology 12 34567 910 1213 8 MMC 826 32072C–AVR32–2010/03 AT32UC3A3/A4 The MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 30-2. Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Notes: Bus Topology Name DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] DAT[4] DAT[5] DAT[6] DAT[7] Type(1) I/O/PP I/O/PP/OD S S I/O S I/O/PP I/O/PP I/O/PP I/O/PP I/O/PP I/O/PP I/O/PP Description Data Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 Data 1 Data 2 Data 4 Data 5 Data 6 Data 7 MCI Pin Name(2) (Slot z) DATAz[3] CMDz VSS VDD CLK VSS DATAz[0] DATAz[1] DATAz[2] DATAz[4] DATAz[5] DATAz[6] DATAz[7] 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. Figure 30-4. MMC Bus Connections (One Slot) MCI CMD DATA[0] CLK 12 34567 91011 1213 8 MMC1 12 34567 91011 1213 8 MMC2 12 34567 91011 1213 8 MMC3 Figure 30-5. SD Memory Card Bus Topology 12345678 9 SDCARD 827 32072C–AVR32–2010/03 AT32UC3A3/A4 The SD Memory Card bus includes the signals listed in Table 30-3 on page 828. Table 30-3. Pin Number 1 2 3 4 5 6 7 8 9 Notes: SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type (1) Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2 MCI Pin Name(2) (Slot z) DATAz[3] CMDz VSS VDD CLK VSS DATAz[0] DATAz[1] DATAz[2] I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP 1. I: input, O: output, PP: Push Pull, OD: Open Drain. Figure 30-6. SD Card Bus Connections with One Slot DATA[3:0] CLK CMD 12345678 SDCARD Figure 30-7. SD Card Bus Connections with Two Slots DATA[3:0] CLK CMD[0] 1 234 5678 1 234 5678 DATA[7:4] CMD[1] 9 9 SDCARD2 9 SDCARD1 828 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 30-8. Mixing MultiMedia and SD Memory Cards with Two Slots DATA[7:0] CMD[0] CLK 12 34567 91011 1213 8 MMC1 12 34567 91011 1213 8 MMC2 12 34567 91011 1213 8 MMC3 12 345 678 DATA[11:8] SDCARD CMD[1] When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the SDCard /SDIO Bus Width field in the SDCR register (SDCR.SDCBUS). See Section “30.7.4” on page 850. for details. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent GPIOs. 30.6.2 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: a command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the CMD line. • Response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. Refer also to Table 30-5 on page 831. MultiMediaCard bus data transfers are composed of these tokens. 9 829 32072C–AVR32–2010/03 AT32UC3A3/A4 There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the MCI clock (CLK). Two types of data transfer commands are defined: • Sequential commands: these commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands: these commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See Section “30.6.3” on page 832.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 30.6.2.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the Multi-Media Interface Enable bit in the Control Register (CR.MCIEN). The Power Save Mode Enable bit in the CR register (CR.PWEN) saves power by dividing the MCI clock (CLK) by 2PWSDIV + 1 when the bus is inactive. The Power Saving Divider field locates in the Mode Register (MR.PWSDIV). The two bits, Read Proof Enable and Write Proof Enable in the MR register (MR.RDPROOF and MR.WRPROOF) allow stopping the MCI Clock (CLK) during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the Command Register (CMDR). The CMDR register allows a command to be carried out. For example, to perform an ALL_SEND_CID command Table 30-4. ALL_SEND_CID command Host Command NID Cycles E Z ****** Z S T CID Content Z Z Z CMD S T Content CRC 830 32072C–AVR32–2010/03 AT32UC3A3/A4 The command ALL_SEND_CID and the fields and values for CMDR register are described in Table 30-5 on page 831 and Table 30-6 on page 831. Table 30-5. CMD Index ALL_SEND_CID Command Description Type Argument Resp Abbreviation Command Description Asks all cards to send their CID numbers on the CMD line CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Note: bcr means broadcast command with response. Table 30-6. Field Fields and Values for the CMDR register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command) The Argument Register (ARGR) contains the argument field of the command. To send a command, the user must perform the following steps: • Set the ARGR register with the command argument. • Set the CMDR register (see Table 30-6 on page 831). The command is sent immediately after writing the command register. As soon as the command register is written, then the Command Ready bit in the Status Register (SR.CMDRDY) is cleared. It is released and the end of the card response. If the command requires a response, it can be read in the Response Registers (RSPRn). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the Interrupt Enable Register (IER) allows using an interrupt method. 831 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 30-9. Command/Response Functional Flow Diagram Set the command argument ARGR = Argument(1) Set the command CMD = Command Read the SR register Wait for SR.CMDRY bit set to one 0 SR.CMDRDY 1 Check error bits in the SR register(1) Yes Status error bits? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error bit is always present (refer to R3 response in the MultiMedia Card specification). 30.6.3 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type field in the CMDR register (CMDR.TRTYP). These operations can be done using the features of the DMA Controller. In all cases, the Data Block Length must be defined either in the Data Block Length field in the MR register (MR.BLKLEN)), or in the Block Register (BLKR). This field determines the size of the data block. 832 32072C–AVR32–2010/03 AT32UC3A3/A4 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly set the BLKR register. Otherwise the card will start an openended multiple block read. The MMC/SDIO Block Count - SDIO Byte Count field in the BLKR register (BLKR.BCNT) defines the number of blocks to transfer (from 1 to 65535 blocks). Writing zero to this field corresponds to an infinite block transfer. 30.6.4 Read/Write Operation The following flowchart shows how to read a single block with or without use of DMA Controller facilities. In this example (see Figure 30-10 on page 834), a polling method is used to wait for the end of read. Similarly, the user can configure the IER register to trigger an interrupt at the end of read. 833 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 30-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) No Read with DMA Yes Write a zero in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Send READ_SINGLE_BLOCK command(1) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.BLKLEN)/4 for Transfer Size in the DMA Controller Number of words to read = (MR.BLKLEN)/4 Send READ_SINGLE_BLOCK command(1) Yes Number of words to read = 0 ? Read the SR register No Read the SR register Yes SR.XFRDONE = 0 ? SR.RXRDY = 0 ? Yes No No Read data in the RDR register Number of words to read = Number of words to read -1 RETURN RETURN Note: 1. It is assumed that this command has been correctly sent (see Figure 30-9 on page 832). 2. This field is also accessible in the BLKR register. 834 32072C–AVR32–2010/03 AT32UC3A3/A4 In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00 value is used when padding data, otherwise 0xFF is used. Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register (DMA.DMAEN) enables DMA transfer. The following flowchart shows how to write a single block with or without use of DMA facilities (see Figure 30-11 on page 836). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (IMR). 835 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 30-11. Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) No Write using DMA Yes Write a zero in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Send WRITE_SINGLE_BLOCK command(1) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.BLKLEN)/4 for Transfer Size in the DMA Controller Number of words to write = BlockLength/4 Send WRITE_SINGLE_BLOCK command(1) Enable the DMA channel X Yes Number of words to write = 0 ? Read the SR register No Read the SR register Yes SR.NOTBUSY = 0 ? SR.TXRDY = 0 ? Yes No No Write Data to transmit in the TDR register Number of words to write = Number of words to write - 1 RETURN RETURN Note: 1. It is assumed that this command has been correctly sent (see Figure 30-9 on page 832). 2. This field is also accessible in BLKR register. 836 32072C–AVR32–2010/03 AT32UC3A3/A4 The following flowchart shows how to manage a multiple write block transfer with the DMA Controller (see Figure 30-12 on page 838). Polling or interrupt method can be used to wait for the end of write according to the contents of the IMR register. 837 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 30-12. Multiple Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command (1) Write a zero in the DMA.DMAEN bit Write the block lenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.BLKLEN)/4 for Transfer Size in the DMA Controller Send WRITE_MULTIPLE_BLOCK command(1) Enable the DMA channel X Read the SR register Yes SR.BLKE = 0 ? No Send STOP_TRANSMISSION command(1) Yes SR.NOTBUSY = 0 ? No RETURN Note: 1. It is assumed that this command has been correctly sent (see Figure 30-9 on page 832). 2. This field is also accessible in BLKR register. 838 32072C–AVR32–2010/03 AT32UC3A3/A4 30.6.4.1 WRITE_SINGLE_BLOCK operation using DMA Controller 1. Wait until the current command execution has successfully terminated. c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Configure the DMA Channel in the DMA Controller. 5. Write the DMA register with the following fields: – Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET). – Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE). – Write a one to he DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the DMA Transfer done bit in IER register (IER.DMADONE). 7. Issue a WRITE_SINGLE_BLOCK command. 8. Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set. 30.6.4.2 READ_SINGLE_BLOCK operation using DMA Controller 1. Wait until the current command execution has successfully terminated. d. Check that the SR.XFRDONE bit is set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Configure the DMA Channel in the DMA Controller. 5. Write the DMA register with the following fields: – Write zero to the DMA.OFFSET field. – Write the DMA.CHKSIZE field. – Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the IER.DMADONE bit. 7. Issue a READ_SINGLE_BLOCK command. 8. Wait for SR.DMADONE bit is set. 30.6.4.3 WRITE_MULTIPLE_BLOCK 1. Wait until the current command execution has successfully terminated. a. Check that the SR.XFRDONE bit is set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one block of data. 5. Program the DMA register with the following fields: – Write the dma_offset in the DMA.OFFSET field. – Write the DMA.CHKSIZE field. – Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the IER.DMADONE bit. 7. Issue a WRITE_MULTIPLE_BLOCK command. 8. Wait for DMA chained buffer transfer complete interrupt. 839 32072C–AVR32–2010/03 AT32UC3A3/A4 30.6.4.4 READ_MULTIPLE_BLOCK 1. Wait until the current command execution has successfully terminated. a. Check that the SR.CMDRDY and the SR.NOTBUSY are set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Program the DMA Controller to use a list of descriptors. 5. Write the DMA register with the following fields: – Write zero to the DMA.OFFSET. – Write the DMA.CHKSIZE. – Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the IER.DMADONE bit. 7. Issue a READ_MULTIPLE_BLOCK command. 8. Wait for DMA end of chained buffer transfer interrupt. 30.6.5 SD/SDIO Card Operation The MCI allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the MultiMedia Card with some additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cameras and more. SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital Card Association. The SD/SDIO Card communication is based on a nine-pin interface (Clock, Command, four Data and three Power lines). The communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and the MultiMedia Card is the initialization process. The SD/SDIO Card Register (SDCR) allows selection of the Card Slot (SDCSEL) and the data bus width (SDCBUS). The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the SD/SDIO Card uses only DAT[0] for data transfer. After initialization, the host can change the bus width (number of active data lines). 30.6.5.1 SDIO Data Transfer Type SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The CMDR.TRTYP field allows to choose between SDIO Byte or SDIO Block transfer. The number of bytes/blocks to transfer is set through the BCNT field in the BLKR register. In SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode. 840 32072C–AVR32–2010/03 AT32UC3A3/A4 An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field in CMDR register (CMDR.IOSPCMD). 30.6.5.2 SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled in the IER register. The SDIO interrupt is sampled regardless of the currently selected slot. 30.6.6 CE-ATA Operation CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC register space. CE-ATA utilizes five MMC commands: • GO_IDLE_STATE (CMD0): used for hard reset. • STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted. • FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, eight bit access only. • RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the control/status registers. • RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command. CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC devices. 30.6.6.1 Executing an ATA Polling Command 1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of DATA. 2. Read the ATA status register until DRQ is set. 3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. 4. Read the ATA status register until DRQ && BSY are set to 0. 30.6.6.2 Executing an ATA Interrupt Command 1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of DATA with the IEN field written to zero to enable the command completion signal in the device. 2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. 3. Wait for Completion Signal Received Interrupt. 30.6.6.3 Aborting an ATA Command If the host needs to abort an ATA command prior to the completion signal it must send a special command to avoid potential collision on the command line. The Special Command field of 841 32072C–AVR32–2010/03 AT32UC3A3/A4 CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal Disable Command. 30.6.6.4 CE-ATA Error Recovery Several methods of ATA command failure may occur, including: • No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60). • CRC is invalid for an MMC command or response. • CRC16 is invalid for an MMC data packet. • ATA Status register reflects an error by setting the ERR bit to one. • The command completion signal does not arrive within a host specified time out period. Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism may be used for each error event. The recommended error recovery procedure after a time-out is: • Issue the command completion signal disable if IEN was cleared to zero and the RW_MULTIPLE_BLOCK (CMD61) response has been received. • Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response. • Issue a software reset to the CE-ATA device using FAST_IO (CMD39). If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the error recovery procedure does not work as expected or there is another time-out, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states. Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA command itself failed implying that the device could not complete the action requested, however, there was no communication or protocol failure. After the device signals an error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command. 30.6.7 MCI Boot Operation Mode In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line low after power-on before issuing CMD1. The data can be read from either boot area or user area depending on register setting. Boot Procedure, processor mode 1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR register. The BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly. 2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writing BLKLEN and BCNT fields of the MCI_BLKR Register. 3. Issue the Boot Operation Request command by writing to the MCI_CMDR register with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”. 4. The BOOT_ACK field located in the MCI_CMDR register must be set to one, if the BOOT_ACK field of the MMC device located in the Extended CSD register is set to one. 5. Host processor can copy boot data sequentialy as soon as the RXRDY flag is asserted. 30.6.7.1 842 32072C–AVR32–2010/03 AT32UC3A3/A4 6. When Data transfer is completed, host processor shall terminate the boot stream by writing the MCI_CMDR register with SPCMD field set to BOOTEND. 30.6.7.2 Boot Procedure, dma mode 1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set accordingly. 2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writing BLKLEN and BCNT fields of the MCI_BLKR Register. 3. Enable DMA transfer in the MCI_DMA register. 4. Configure DMA controller, program the total amount of data to be transferred and enable the relevant channel. 5. Issue the Boot Operation Request command by writing to the MCI_CMDR register with SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”. 6. DMA controller copies the boot partition to the memory. 7. When DMA transfer is completed, host processor shall terminate the boot stream by writing the MCI_CMDR register with SPCMD field set to BOOTEND. 30.6.8 30.6.8.1 MCI Transfer Done Timings Definition The SR.XFRDONE bit indicates exactly when the read or write sequence is finished. 30.6.8.2 Read Access During a read access, the SR.XFRDONE bit behaves as shown in Figure 30-13 on page 843. Figure 30-13. SR.XFRDONE During a Read Access CMD line MCI read CMD Card response CMDRDY flag The CMDRDY flag is released 8 tbit lafter the end of the card response. Data 1st Block Not busy flag Last Block XFRDONE flag 843 32072C–AVR32–2010/03 AT32UC3A3/A4 30.6.8.3 Write Access During a write access, the SR.XFRDONE bit behaves as shown in Figure 30-14 on page 844. Figure 30-14. SR.XFRDONE During a Write Access CMD line MCI writeCMD Card response CMDRDY flag The CMDRDY flag is released 8 tbit lafter the end of the card response. D0 1st Block Data bus - D0 1st Block Not busy flag Last Block Last Block D0 is tied by the card D0 is released XFRDONE flag 30.7 User Interface MCI Register Memory Map Register Control Register Mode Register Data Time-out Register SD/SDIO Card Register Argument Register Command Register Block Register Completion Signal Time-out Register Response Register Response Register Response Register Response Register Receive Data Register Transmit Data Register Status Register Name CR MR DTOR SDCR ARGR CMDR BLKR CSTOR RSPR RSPR1 RSPR2 RSPR3 RDR TDR SR Access Write-only Read-write Read-write Read-write Read-write Write-only Read-write Read-write Read-only Read-only Read-only Read-only Read-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0C000025 Table 30-7. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x040 844 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 30-7. Offset 0x044 0x048 0x04C 0x050 0x054 0x0E4 0x0E8 0x0FC 0x200-0x3FFC 1. MCI Register Memory Map Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register DMA Configuration Register Configuration Register Write Protection Mode Register Write Protection Status Register Version Register FIFO Memory Aperture Name IER IDR IMR DMA CFG WPMR WPSR VERSION – Access Write-only Write-only Read-only Read-write Read-write Read-write Read-only Read-only Read-write Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - (1) 0x00000000 The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter. 845 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.1 Name: Control Register CR Write-only 0x000 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SWRST 6 - 5 IOWAITDIS 4 IOWAITEN 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • SWRST: Software Reset Writing a one to this bit will reset the MCI interface. Writing a zero to this bit has no effect. • IOWAITDIS: SDIO Read Wait Disable Writing a one to this bit will disable the SDIO Read Wait Operation. Writing a zero to this bit has no effect. • IOWAITEN: SDIO Read Wait Enable Writing a one to this bit will enable the SDIO Read Wait Operation. Writing a zero to this bit has no effect. • PWSDIS: Power Save Mode Disable Writing a one to this bit will disable the Power Saving Mode. Writing a zero to this bit has no effect. • PWSEN: Power Save Mode Enable Writing a one to this bit and a zero to PWSDIS will enable the Power Saving Mode. Writing a one to this bit and a one to PWSDIS will disable the Power Saving Mode. Writing a zero to this bit has no effect. Warning: Before enabling this mode, the user must write a value different from 0 to the PWSDIV field. • MCIDIS: Multi-Media Interface Disable Writing a one to this bit will disable the Multi-Media Interface. Writing a zero to this bit has no effect. • MCIEN: Multi-Media Interface Enable Writing a one to this bit and a zero to MCIDIS will enable the Multi-Media Interface. Writing a one to this bit and a one to MCIDIS will disable the Multi-Media Interface. Writing a zero to this bit has no effect. 846 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.2 Name: Mode Register MR Read-write 0x004 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 BLKLEN[15:8] 23 22 21 20 BLKLEN[7:0] 19 18 17 16 15 - 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 CLKDIV 3 2 1 0 • BLKLEN[15:0]: Data Block Length This field determines the size of the data block. This field is also accessible in the BLKR register. If FBYTE bit is zero, the BLKEN[1:0] field must be written to 0b00 Notes: 1. In SDIO Byte mode, BLKLEN field is not used. 2. BLKLEN should be written to one before sending the data transfer command. Otherwise, Overrun may occur even if RDPROOF bit is one. • PADV: Padding Value 0: 0x00 value is used when padding data in write transfer. 1: 0xFF value is used when padding data in write transfer. PADV is used only in manual transfer. • FBYTE: Force Byte Transfer Enabling Force Byte Transfer allows byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. Warning: BLKLEN value depends on FBYTE. Writing a one to this bit will enable the Force Byte Transfer. Writing a zero to this bit will disable the Force Byte Transfer. • WRPROOF Write Proof Enable Enabling Write Proof allows to stop the MCI Clock (CLK) during write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. Writing a one to this bit will enable the Write Proof mode. Writing a zero to this bit will disable the Write Proof mode. • RDPROOF Read Proof Enable Enabling Read Proof allows to stop the MCI Clock (CLK) during read access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. Writing a one to this bit will enable the Read Proof mode. Writing a zero to this bit will disable the Read Proof mode. 847 32072C–AVR32–2010/03 AT32UC3A3/A4 • PWSDIV: Power Saving Divider Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode. Warning: This value must be different from zero before enabling the Power Save Mode in the CR register (CR.PWSEN). • CLKDIV: Clock Divider The Multimedia Card Interface Clock (CLK) is CLK_MCI divided by (2*(CLKDIV+1)). 848 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.3 Name: Data Time-out Register DTOR Read/Write 0x008 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 DTOMUL 4 3 2 DTOCYC 1 0 These two fields determine the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. It is equal to (DTOCYC x Multiplier). If the data time-out defined by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error bit in the SR register (SR.DTOE) is set. • DTOMUL: Data Time-out Multiplier Multiplier is defined by DTOMUL as shown in the following table DTOMUL 0 1 2 3 4 5 6 7 Multiplier 1 16 128 256 1024 4096 65536 1048576 • DTOCYC: Data Time-out Cycle Number 849 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.4 Name: SDCard/SDIO Register SDCR Read/Write 0x00C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SDCBUS 6 5 – 4 – 3 – 2 – 1 SDCSEL 0 • SDCBUS: SDCard/SDIO Bus Width SDCBUS 0 1 2 3 BUS WIDTH 1 bit Reserved 4 bits 8 bits • SDCSEL: SDCard/SDIO Slot SDCSEL 0 1 2 3 SDCard/SDIO Slot Slot A is selected. Slot B is selected. Reserved. Reserved. 850 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.5 Name: Argument Register ARGR Read/Write 0x010 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 ARG[31:24] 27 26 25 24 23 22 21 20 ARG[23:16] 19 18 17 16 15 14 13 12 ARG[15:8] 11 10 9 8 7 6 5 4 ARG[7:0] 3 2 1 0 • ARG[31:0]: Command Argument this field contains the argument field of the command. 851 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.6 Name: Command Register CMDR Write-only 0x014 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 BOOTACK 26 ATACS 25 IOSPCMD 24 23 - 22 - 21 20 TRTYP 19 18 TRDIR 17 TRCMD 16 15 - 14 - 13 - 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 7 RSPTYP 6 5 4 3 CMDNB 2 1 0 This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an interrupt response (SPCMD field). This means that the current command execution cannot be interrupted or modified. • BOOT_ACK: Boot Operation Acknowledge The master can choose to receive the boot acknowledge from the slave when a Boot Request command is isssued. Writing a one to this bit indicates that a Boot acknolwedge is expected within a programmable amount of time defined with DTOMUL and DTOCYC fields located in the DTOR register. If the acknowledge pattern is not received then an acknowledge timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set. • ATACS: ATA with Command Completion Signal Writing a one to this bit will configure ATA completion signal within a programmed amount of time in Completion Signal Time-out Register (CSTOR). Writing a zero to this bit will configure no ATA completion signal. • IOSPCMD: SDIO Special Command IOSPCMD 0 1 2 3 SDIO Special Command Type Not a SDIO Special Command SDIO Suspend Command SDIO Resume Command Reserved 852 32072C–AVR32–2010/03 AT32UC3A3/A4 • TRTYP: Transfer Type TRTYP 0 1 2 3 4 5 others Transfer Type MMC/SDCard Single Block MMC/SDCard Multiple Block MMC Stream Reserved SDIO Byte SDIO Block Reserved • TRDIR: Transfer Direction Writing a zero to this bit will configure the transfer direction as write transfer. Writing a one to this bit will configure the transfer direction as read transfer. • TRCMD: Transfer Command TRCMD 0 1 2 3 Transfer Type No data transfer Start data transfer Stop data transfer Reserved • MAXLAT: Max Latency for Command to Response Writing a zero to this bit will configure a 5-cycle max latency. Writing a one to this bit will configure a 64-cycle max latency. • OPDCMD: Open Drain Command Writing a zero to this bit will configure the push-pull command. Writing a one to this bit will configure the open-drain command. • SPCMD: Special Command SPCMD 0 1 2 Command Not a special CMD. Initialization CMD: 74 clock cycles for initialization sequence. Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. Interrupt command: Corresponds to the Interrupt Mode (CMD40). Interrupt response: Corresponds to the Interrupt Mode (CMD40). Reserved 3 4 5 others 853 32072C–AVR32–2010/03 AT32UC3A3/A4 • RSPTYP: Response Type RSP 0 1 2 3 Response Type No response. 48-bit response. 136-bit response. R1b response type • CMDNB: Command Number The Command Number to transmit. 854 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.7 Name: Block Register BLKR Read/Write 0x018 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 BLKLEN[15:8] 23 22 21 20 BLKLEN[7:0] 19 18 17 16 15 14 13 12 BCNT[15:8] 11 10 9 8 7 6 5 4 BCNT[7:0] 3 2 1 0 • BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MR register. If MR.FBYTE bit is zero, the BLKEN[17:16] field must be written to 0b00 1. In SDIO Byte mode, BLKLEN field is not used. 2. BLKLEN should be specified before sending the data transfer command. Otherwise, Overrun may occur (even if MR.RDPROOF bit is set). • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by CMDR.TRTYP field: TRTYP 0 2 3 Others Type of Transfer MMC/SDCard Multiple Block SDIO Byte SDIO Block BCNT Authorized Values From 1 to 65535: Value 0 corresponds to an infinite block transfer. From 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer. Values from 0x200 to 0xFFFF are forbidden. From 1 to 511 blocks: Value 0 corresponds to an infinite block transfer. Values from 0x200 to 0xFFFF are forbidden. Reserved. Notes: Warning: In SDIO Byte and Block modes, writing to the seven last bits of BCNT field is forbidden and may lead to unpredictable results. 855 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.8 Name: Completion Signal Time-out Register CSTOR Read-write 0x01C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 CSTOMUL 4 3 2 CSTOCYC 1 0 These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. Its value is calculated by (CSTOCYC x Multiplier). These two fields also determine the maximum number of CLK_MCI cycles that the MCI waits between the end of the data transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a non-DATA ATA command is issued, the MCI starts waiting immediately after the end of the response until the completion signal. If the data time-out defined by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error bit in the SR register (SR.CSTOE) is set. • CSTOMUL: Completion Signal Time-out Multiplier Multiplier is defined by CSTOMUL as shown in the following table: CSTOMUL 0 1 2 3 4 5 6 7 Multiplier 1 16 128 256 1024 4096 65536 1048576 • CSTOCYC: Completion Signal Time-out Cycle Number 856 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.9 Name: Response Register n RSPRn Read-only 0x020 + 0*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 RSP[31:24] 27 26 25 24 23 22 21 20 RSP[23:16] 19 18 17 16 15 14 13 12 RSP[15:8] 11 10 9 8 7 6 5 4 RSP[7:0] 3 2 1 0 • RSP[31:0]: Response The response register can be read by N access(es) at the same RSPRn or at consecutive addresses (0x20 + n*0x04). N depends on the size of the response. 857 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.10 Name: Receive Data Register RDR Read-only 0x030 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA[31:0]: Data to Read The last data received. 858 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.11 Name: Transmit Data Register TDR Write-only 0x034 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA[31:0]: Data to Write The data to send. 859 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.12 Name: Status Register SR Read-only 0x040 0x0C000025 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • ACKRCVE: Boot Operation Acknowledge Error This bit is set when a corrupted Boot Acknowlegde signal has been received. This bit is cleared by reading the SR register. • ACKRCV: Boot Operation Acknowledge Received This bit is set when a Boot acknowledge signal has been received. This bit is cleared by reading the SR register. • UNRE: Underrun Error This bit is set when at least one eight-bit data has been sent without valid information (not written). This bit is cleared when sending a new data transfer command if the Flow Error bit reset control mode in Configuration Register (CFG.FERRCTRL) is zero or when reading the SR register if CFG.FERRCTRL is one. • OVRE: Overrun Error This bit is set when at least one 8-bit received data has been lost (not read). This bit is cleared when sending a new data transfer command if CFG.FERRCTRL is zero, or when reading the SR register if CFG.FERRCTRL is one. • XFRDONE: Transfer Done This bit is set when the CR register is ready to operate and the data bus is in the idle state. This bit is cleared when a transfer is in progress. • FIFOEMPTY: FIFO empty This bit is set when the FIFO is empty. This bit is cleared when the FIFO contains at least one byte. • DMADONE: DMA Transfer done This bit is set when the DMA buffer transfer is completed. This bit is cleared when reading the SR register. • BLKOVRE: DMA Block Overrun Error This bit is set when a new block of data is received and the DMA controller has not started to move the current pending block. This bit is cleared when reading the SR register. 860 32072C–AVR32–2010/03 AT32UC3A3/A4 • CSTOE: Completion Signal Time-out Error This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is reached. This bit is cleared when reading the SR register. • DTOE: Data Time-out Error This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached. This bit is cleared when reading the SR register. • DCRCE: Data CRC Error This bit is set when a CRC16 error is detected in the last data block. This bit is cleared when reading the SR register. • RTOE: Response Time-out Error This bit is set when the response time-out defined by the CMDR.MAXLAT bit is reached. This bit is cleared when writing the CMDR register. • RENDE: Response End Bit Error This bit is set when the end bit of the response is not detected. This bit is cleared when writing the CMDR register. • RCRCE: Response CRC Error This bit is set when a CRC7 error is detected in the response. This bit is cleared when writing the CMDR register. • RDIRE: Response Direction Error This bit is set when the direction bit from card to host in the response is not detected. This bit is cleared when writing the CMDR register. • RINDE: Response Index Error This bit is set when a mismatch is detected between the command index sent and the response index received. This bit is cleared when writing the CMDR register. • TXBUFE: TX Buffer Empty Status This bit is set when the DMA Tx Buffer is empty. This bit is cleared when the DMA Tx Buffer is not empty. • RXBUFF: RX BUffer Full Status This bit is set when the DMA Rx Buffer is full. This bit is cleared when the DMA Rx Buffer is not full. • CSRCV: CE-ATA Completion Signal Received This bit is set when the device issues a command completion signal on the command line. This bit is cleared when reading the SR register. • SDIOWAIT: SDIO Read Wait Operation Status This bit is set when the data bus has entered IO wait state. This bit is cleared when normal bus operation. • SDIOIRQB: SDIO Interrupt for Slot B This bit is cleared when reading the SR register. This bit is set when a SDIO interrupt on Slot B occurs. • SDIOIRQA: SDIO Interrupt for Slot A This bit is set when a SDIO interrupt on Slot A occurs. This bit is cleared when reading the SR register. • ENDTX: End of RX Buffer This bit is set when the DMA Controller transmission is finished. This bit is cleared when the DMA Controller transmission is not finished. • ENDRX: End of RX Buffer This bit is set when the DMA Controller reception is finished. This bit is cleared when the DMA Controller reception is not finished. • NOTBUSY: MCI Not Busy This bit must be used only for write operations. 861 32072C–AVR32–2010/03 AT32UC3A3/A4 A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. The NOTBUSY bit allows to deal with these different states. 1: MCI is ready for new data transfer. 0: MCI is not ready for new data transfer. This bit is cleared at the end of the card response. This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. DTIP: Data Transfer in Progress This bit is set when the current data transfer is in progress. This bit is cleared at the end of the CRC16 calculation 1: The current data transfer is still in progress. 0: No data transfer in progress. BLKE: Data Block Ended This bit must be used only for Write Operations. This bit is set when a data block transfer has ended. This bit is cleared when reading SR. 1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status. 0: A data block transfer is not yet finished. Refer to the MMC or SD Specification for more details concerning the CRC Status. TXRDY: Transmit Ready This bit is set when the last data written in the TDR register has been transferred. This bit is cleared the last data written in the TDR register has not yet been transferred. RXRDY: Receiver Ready This bit is set when the data has been received since the last read of the RDR register. This bit is cleared when the data has not yet been received since the last read of the RDR register. CMDRDY: Command Ready This bit is set when the last command has been sent. This bit is cleared when writing the CMDR register • • • • • 862 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.13 Name: Interrupt Enable Register IER Write-only 0x044 0x00000000 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFF 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 863 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.14 Name: Interrupt Disable Register IDR Write-only 0x048 0x00000000 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFF 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 864 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.15 Name: Interrupt Mask Register IMR Read-only 0x04C 0x00000000 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFF 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 865 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.16 Name: DMA Configuration Register DMA Read/Write 0x050 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 DAMEN 7 - 6 5 CHKSIZE 4 3 - 2 - 1 OFFSET 0 • DMAEN: DMA Hardware Handshaking Enable 1: DMA Interface is enabled. 0: DMA interface is disabled. To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed. To avoid data losses, the DMA register should be initialized before sending the data transfer command. This is also illustrated in Figure 30-10 on page 834 or Figure 30-11 on page 836 • CHKSIZE: DMA Channel Read and Write Chunk Size The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted. CHKSIZE value 0 1 2 3 4 others Number of data transferred 1 4 8 16 32 Only available if FIFO_SIZE>= 16 bytes Only available if FIFO_SIZE>= 32 bytes Only available if FIFO_SIZE>= 64 bytes Only available if FIFO_SIZE>= 128 bytes Only available if FIFO_SIZE>= 256 bytes Reserved • OFFSET: DMA Write Buffer Offset This field indicates the number of discarded bytes when the DMA writes the first word of the transfer. 866 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.17 Name: Configuration Register CFG Read/Write 0x054 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 LSYNC 11 - 10 - 9 - 8 HSMODE 7 - 6 - 5 - 4 FERRCTRL 3 - 2 - 1 - 0 FIFOMODE • LSYNC: Synchronize on the last block 1: The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be different from zero) 0: The pending command is sent at the end of the current data block. This register needs to configured before sending the data transfer command. • HSMODE: High Speed Mode 1: The host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the high speed support in the card registers. 0: Default bus timing mode. • FERRCTRL: Flow Error bit reset control mode 1: When an underflow/overflow condition bit is set, reading SR resets the bit. 0: When an underflow/overflow condition bit is set, a new Write/Read command is needed to reset the bit. • FIFOMODE: MCI Internal FIFO control mode 1: A write transfer starts as soon as one data is written into the FIFO. 0: A write transfer starts when a sufficient amount of data is written into the FIFO. When the block length is greater than or equal to 3/4 of the MCI internal FIFO size, then the write transfer starts as soon as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the internal FIFO. 867 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.18 Name: Write Protect Mode Register WPMR Read/Write 0x0E4 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 WPKEY[23:16] 23 22 21 20 WPKEY[15:8] 19 18 17 16 15 14 13 12 WPKEY[7:0] 11 10 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 WPEN • WPKEY[23:0]: Write Protection Key password This field should be written at value 0x4D4349 (ASCII code for “MCI”). Writing any other value in this field has no effect. • WPEN: Write Protection Enable 1: This bit enables the Write Protection if WPKEY corresponds. 0: This bit disables the Write Protection if WPKEY corresponds. 868 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.19 Name: Write Protect Status Register WPSR Read-only 0x0E8 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 WPVSRC[15:8] 15 14 13 12 11 10 9 8 WPVSRC[7:0] 7 - 6 - 5 - 4 - 3 2 WPVS 1 0 • WPVSRC[15:0]: Write Protection Violation Source This field contains address where the violation access occurs. • WPVS: Write Protection Violation Status WPVS 0 1 2 3 others Definition No Write Protection Violation occurred since the last read of this register (WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) Software reset had been performed while Write Protection was enabled (since the last read). Both Write Protection violation and software reset with Write Protection enabled had occurred since the last read. Reserved 869 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.20 Name: Access: Offset: Reset Value: Version Register VERSION Read-only 0x0FC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 17 VARIANT 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associate 870 32072C–AVR32–2010/03 AT32UC3A3/A4 30.7.21 Name: Access: Offset: Reset Value: FIFO Memory Aperture Read/Write 0x200 - 0x3FFC 0x000000000 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA[31:0]:Data to read or Data to write 871 32072C–AVR32–2010/03 AT32UC3A3/A4 30.8 Module Configuration The specific configuration for the MCI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 30-8. Module name Module Clock Name Clock name CLK_MCI MCI Table 30-9. Name Parameter Value Value FIFO_SIZE 128 Table 30-10. Register Reset Values Register Reset Value VERSION 0x00000410 872 32072C–AVR32–2010/03 AT32UC3A3/A4 31. Memory Stick Interface (MSI) Rev: 2.1.0.0 31.1 Features • • • • • • Memory Stick ver. 1.x & Memory Stick PRO support Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.) Data transmit/receive FIFO of 64 bits x 4 16 bits CRC circuit DMACA transfer support Card insertion/removal detection 31.2 Overview The Memory Stick Interface (MSI) is a host controller that supports Memory Stick Version 1.X and Memory Stick PRO. The communication protocol with the Memory Stick is started by write from the CPU to the command register. When the protocol finishes, the CPU is notified that the protocol has ended by an interrupt request. When the protocol is started and enters the data transfer state, data is requested by issuing a DMA transfer request (via DMACA) or an interrupt request to the CPU. The RDY time out time when the handshake state (BS2 in read protocol, BS3 for write protocol) is established in communication with the Memory Stick can be designated as the number of Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has ended due to a time out error by an interrupt request. CRC circuit can be set off for test mode purpose. When CRC is off, CRC is not added to the data transmitted to the Memory Stick. An interrupt request can also be issued to the CPU when a Memory Stick is inserted or removed. Figure 31-1. Read packet BS BS0 Memory Stick BS1 Host TPC RDY/BSY BS2 BS3 Memory Stick DATA CRC INT BS0 SDIO / DATA[3:0] INT SCLK 873 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 31-2. Write packet BS BS0 Memory Stick BS1 BS2 Host TPC DATA CRC BS3 BS0 Memory Stick RDY/BSY INT SDIO / DATA[3:0] INT SCLK 31.3 Block Diagram Figure 31-3. MSI block diagram CLK_MSI INS SDIO / DATA0 DATA1 DATA2 DATA3 SCLK BS ÷ Registers PB FIFO 64 x 4 MS I/F Data buffer 31.4 31.4.1 Product Dependencies GPIO SCLK, DATA[3..0], BS & INS are I/O lines, multiplexed with other I/O lines. The I/O controller must be configured so that MSI can drive these I/O lines. 31.4.2 Power Manager MSI is clocked through the Power Manager (PM), thus programmer must first configure the PM to enable the CLK_MSI clock. 874 32072C–AVR32–2010/03 AT32UC3A3/A4 31.4.3 Interrupt Controller MSI interrupt line is connected to the Interrupt Controller. In order to handle interrupts, Interrupt Controller(INTC) must be programmed before configuring MSI. DMA Controller (DMACA) Handshake signals are connected to DMACA. In order to accelerate transfer from/to flash card, DMACA must be programmed before using MSI. 31.4.4 31.5 Connection to a Memory Stick The Memory Stick serial clock (SCLK) is maximum 20 MHz in serial mode, and maximum 40 MHz in parallel mode. SCLK is derived from peripheral clock (CLK_MSI) : f_SCLK = f_CLK_MSI / [2*(CLKDIV+1)] where CLKDIV = {0..255}. Pin DATA[1] is a power supply for some Memory Stick version, so leaving the pull-down resistor connected may result in wasteful current consumption. User should leave the DATA[1] pin pulldown open when Memory Stick Ver. 1.x is inserted. Table 31-1. Memory Stick pull-down configuration Memory Stick 1.x Memory Stick PRO Pull-down enabled Pull-down enabled Memory Stick inserted Memory Stick removed Pull-down open Pull-down enabled Figure 31-4. Memory Stick pull-down overview 875 32072C–AVR32–2010/03 AT32UC3A3/A4 31.6 31.6.1 Functional Description Reset Operation An internal reset (initialization of the internal registers and operating sequence) is performed when PB reset is active or by setting SYS.RST=1. RST bit is cleared to 0 after the internal reset is completed. The protocol currently being executed stops, and the internal operating sequence is initialized. In addition, the FIFO is set to the empty state (SR.EMP=1, SR.FUL=0). However, when the host controller is reset during communication with the Memory Stick, the resulting bus state may differ from the Memory Stick. Therefore, when reset is performed during communication, also power-on-reset the Memory Stick. Internal registers are initialized to their initial value. However, some bits in following registers are not affected by RST bit : • SYS : CLKDIV[7:0], •ISR : all bits but DRQ, •SR : ISTA, •IMR : all bits. 31.6.2 Communication with the Memory Stick An example of communication with the Memory Stick is shown below. This example shows the case when Transfer Protocol Command (TPC) SET_CMD is executed. – Enable PEND and MSINT interrupt requests (write PEND=1, MSINT=1 in IER). – Set FIFO direction to “CPU to MS” (write FDIR=1 in SYS). – Write the command data to the FIFO (write DAT). – Write the TPC and the data transfer size to the command register to start the protocol (write CMD). – After the protocol ends, an interrupt request is output from the host controller (PEND=1 in ISR). To acknowledge this interrupt request, CPU must clear the source of interrupt by writing PEND=1 in ISCR. – Some TPC commands require additional time to be executed by Memory Stick therefore INT can appear later after protocol end. After INT generation, an interrupt request is output from the host controller (MSINT=1 in ISR). To acknowledge this interrupt request, CPU must clear the source of interrupt by writing MSINT=1 in ISCR. When the command register is written, the communication protocol with the Memory Stick starts and data transmit/receive is performed. The data transfer direction is determined from TPC[3]. When TPC[3]=0, the read protocol is performed, and when TPC[3]=1, the write protocole is performed. When TPC[3] and FDIR bit differ, the TPC[3] value is reflected to system register bit FDIR when the protocol starts. FIFO can be written after protocol start therefore data must be written each time ISR.DRQ=1. Even when the data is less than 8 bytes, always read and write 8 bytes of data. All interrupt 876 32072C–AVR32–2010/03 AT32UC3A3/A4 sources can be cleared by setting corresponding bit in ISCR but DRQ which is cleared once FIFO has been read/written. Figure 31-5. Communication example CPU PEND=1, MSINT=1 MSI Interrupt enable MSIER register FIFO direction setting Write to FIFO TPC setting Interrupt wait FDIR=1 MSSYS register MSDAT register MSCMD register Protocol start Communication with Memory Stick CMD TPC = SET_CMD MSISR.PEND=1 Protocol end MSISCR register MS INT wait INT from Memory Stick Interrupt clear Interrupt wait PEND=1 MSISR.MSINT=1 INT received MSISCR register Interrupt clear MSINT=1 31.6.3 Parallel Interface Mode Setting Procedure Host controller supports parallel mode and must be set to parallel interface mode after the Memory Stick. – Identify the Memory Stick media and confirm it is a Memory Stick PRO. For Memory stick media identification, see “Memory Stick Standard Format Specifications ver. 1.X Appendix D” or “Memory Stick Standard Format Specifications ver. 2.0 Application Notes 1.3 Media Identification Process”. – Set the Memory Stick to parallel interface mode by executing TPC commands SET_R/W_REG_ADRS then WRITE_REG to set System Parameter bit PAM=1. – Write SRAC=0 and REI=0 to the system register (SYS) to switch host controller to parallel interface mode. – Change serial clock (SCLK) while communication is not being performed with the Memory Stick. 877 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 31-6. Interface mode switching sequence Serial Interface Mode (MSSYS.SRAC=1, MSSYS.REI=1) SET_R/W_REG_ADRS TPC WRITE_REG TPC system parameter (PAM bit) Error OK Set Parallel Interface Mode (MSSYS.SRAC=0, MSSYS.REI=0) Change SCLK (MSSYS.CLKDIV[7:0]=X) 31.6.4 Data transfer requests After the communication protocol with the Memory Stick starts, a data transfer request is asserted to the CPU (DRQ bit in ISR) and to DMACA (internal signals), until data transfer of the amount indicated by DSZ (CMD) is finished. However, the data transfer request stops when the internal FIFO becomes either empty or full. Like CPU, DMACA uses Peripheral Bus to access FIFO so it is not recommended to access MSI registers during transfer. It is also not recommended to enable DRQ interrupt because ISR.DRQ bit is automatically cleared when FIFO is accessed. DMACA channel should be configured first and the data size should be a multiple of 64 bits (FIFO size is 4 * 64bits). 31.6.5 Interrupts The interrupt sources of MSI are : • • • • • • PEND : protocol command ended without error. DRQ : data request, FIFO is full or empty. MSINT : interrupt received from Memory Stick. CRC : protocol ended with CRC error. TOE : protocol ended with time out error. CD : card detected (inserted or removed). Each interrupt source can be enabled in Interrupt Enable register (IER) and disabled in Interrupt Disable register (IDR). The enable status is read in Interrupt Mask register (IMR). The status of the interrupt source, even if the interrupt is masked, can be read in ISR. 878 32072C–AVR32–2010/03 AT32UC3A3/A4 DRQ interrupt request is cleared by reading (reception) or writing (transmission) FIFO, other interrupt requests are cleared by writing 1 to the corresponding bit in Interrupt Status Clear Register (ISCR). 31.6.6 OCD mode There is no OCD mode for MSI. 31.7 User Interface MSI Register Memory Map Register Name Access Reset State Table 31-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 Command register Data register Status register System register Interrupt Status register Interrupt Status Clear register Interrupt Enable register Interrupt Disable register Interrupt Mask register Version register CMD DAT SR SYS ISR ISCR IER IDR IMR VERSION Read/Write Read/Write Read Only Read/Write Read Only Write Only Write Only Write Only Read Only Read Only 0x00000000 0x4C004C00 0x00001020 0x00004015 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000210 879 32072C–AVR32–2010/03 AT32UC3A3/A4 31.7.1 Name : Command register CMD Read/Write 0x00 0x00000000 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 TPC 13 12 11 - 10 DSL 9 DSZ 8 7 6 5 4 DSZ 3 2 1 0 • TPC : Transfer Protocol Code. code (dec) 2 3 4 7 8 9 11 12 13 14 other TPC Description READ_LONG_DATA READ_SHORT_DATA READ_REG GET_INT SET_R/W_REG_ADRS EX_SET_CMD WRITE_REG WRITE_SHORT_DATA WRITE_LONG_DATA SET_CMD - Transfer data from Data Buffer (512 bytes) Transfer data from Data Buffer (32~256 bytes) Read from a register Read from an INT register Set an address of READ_REG/WRITE_REG Set command and parameters Write to a register Transfer data to Data Buffer (32~256 bytes) Transfer data to Data Buffer (512 bytes) Set command Banned for use TPC[3] indicates the transfer direction of data (1:write packet, 0:read packet) • DSL : Data Select. 0 : Data is transmitted to and received from Memory Stick using the internal FIFO. 1 : Reserved. 880 32072C–AVR32–2010/03 AT32UC3A3/A4 • DSZ : Data size. Length can be set from 1 byte to 1024 bytes. However, 1024 bytes is set when DSZ=0. 881 32072C–AVR32–2010/03 AT32UC3A3/A4 31.7.2 Name : Data register DAT Read/Write 0x04 0x4C004C00 Access Type : Offset : Reset Value : 31 30 29 28 DATA 27 26 25 24 23 22 21 20 DATA 19 18 17 16 15 14 13 12 DATA 11 10 9 8 7 6 5 4 DATA 3 2 1 0 This register is used to acces internal FIFO. Even when the data is less than 8 bytes, always read and write 8 bytes of data. 882 32072C–AVR32–2010/03 31.7.3 Name : Status register SR Read Only 0x08 0x00001020 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 ISTA 15 - 14 - 13 - 12 RDY 11 - 10 - 9 - 8 - 7 - 6 - 5 EMP 4 FUL 3 CED 2 ERR 1 BRQ 0 CNK • ISTA : Insertion Status. It reflects the Memory Stick card presence. This is the inverse of INS pin. 0 : No card. 1 : Card is inserted. • RDY : Ready. RDY goes to 1 when the protocol ends. This bit bit is cleared to 0 by write to the command register. 0 : Command receive disabled due to communication with the Memory Stick. 1 : Command received or protocol ended. • EMP : FIFO Empty. This bit is set to 1 by writing system register bit FCLR=1. 0 : FIFO contains data. 1 : FIFO is empty. • FUL : FIFO Full. This bit is cleared to 0 by writing system register bit FCLR=1. 0 : FIFO has empty space. 1 : FIFO is full. • CED : MS Command End. In parallel mode, this bit reflects the CED bit in the status register of a Memory Stick (INT). Indicates the end of a command executed with SET_CMD TPC. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD). • ERR : Memory Stick Error. In parallel mode, this bit reflects the ERR bit in the status register of a Memory Stick (INT). It indicates the occurence of an error. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD). AT32UC3A3/A4 • BRQ : MS Data Buffer Request. In parallel mode, this bit reflects the BREQ bit in the status register of a Memory Stick (INT). It indicates that a host has requested to access a Memory Sticks page buffer.In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD). • CNK : MS Command No Acknowledge. In parallel mode, this bit reflects the CMDNK bit in the status register of a Memory Stick (INT). It indicates that the command cannot be executed. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD). 884 32072C–AVR32–2010/03 31.7.4 Name : System register SYS Read/Write 0x0C 0x00004015 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 CLKDIV 19 18 17 16 15 RST 14 SRAC 13 - 12 NOCRC 11 - 10 - 9 FCLR 8 FDIR 7 - 6 - 5 - 4 REI 3 REO 2 1 BSY 0 • CLKDIV : Clock Division. Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)). • RST : Reset. When RST is written, internal synchronous reset is performed. 0 : This bit is cleared to 0 after the internal reset is completed. 1 : Writing a 1 starts reset operation. • SRAC : Serial Access Mode. The SRAC cannot be changed during protocol execution. 0 : Write this bit to 0 to set parallel mode. 1 : Write this bit to 1 to set serial mode. • NOCRC : No CRC computation. 0 : Write 0 to enable CRC output. During read protocol, the CRC check is performed as usual regardless of NOCRC. 1 : Write 1 to disable CRC output. When NOCRC=1, the write protocol is executed without adding the CRC data. • FCLR : FIFO clear. Write 1 to initialize FIFO data. This bit is cleared after the FIFO is initialized. • FDIR : FIFO direction. 0 : Write 0 to set the FIFO direction to transmit. 1 : Write 1 to set the FIFO direction to receive. • REI : Rising Edge Input. When setting parallel mode, set REI=0. This setting cannot be changed during protocol execution. 0 : Write 0 to sample data at the falling edge of SCLK. 1 : Write 1 to sample data at the rising edge of SCLK. AT32UC3A3/A4 • REO : Rising Edge output. This bit is used when not fixed hold time by the side of the Memory Stick in parallel communication. This setting cannot be changed during protocol execution. 0 : Write 0 to synchronize outputs with the falling edge of SCLK. 1 : Write 1 to synchronize outputs with the rising edge of SCLK. • BSY : Busy Count. This is the maximum BSY wait time until the RDY signal is output from the Memory Stick. 0 : Write a value to configure time out = BSY * 4 SCLK. 1 : Write 0 to disable time out detection. 886 32072C–AVR32–2010/03 31.7.5 Name : Interrupt Status register ISR Read Only 0x10 0x00000000 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 CD 4 TOE 3 CRC 2 MSINT 1 DRQ 0 PEND • CD : Card Detection. 0 : No card detected. This bit is cleared when the correponding bit in ISCR is set to 1. 1 : This bit is set to 1 when a Memory Stick card is inserted or removed. • TOE : Time Out Error. 0 : This bit is cleared to 0 when the corresponding bit in ISCR it set to 1. 1 : This bit is set to 1 when protol ended with time out error. • CRC : CRC error. 0 : No CRC error. This bit is cleared when the corresponding bit in ISCR is set to 1. 1 : This bit is set when protocol ends with CRC error. • MSINT : Memory Stick interruption. 0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1. 1 : This bit is set to 1 when an interrupt request INT is received from Memory Stick. • DRQ : Data request, FIFO is full (reception) or empty (transmission). 0 : This bit is cleared to 0 when data access is no more required. 1 : This bit is set to 1 when data access is required (read or write). • PEND : Protocol End. 0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1. 1 : This bit is set to 1 when protol ended witout error. AT32UC3A3/A4 31.7.6 Name : Interrupt Status Clear register ISCR Write Only 0x14 0x00000000 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 CD 4 TOE 3 CRC 2 MSINT 1 - 0 PEND • CD : Card Detection clear bit. 0 : Writing 0 has no effect. 1 : Writing 1 clears corresponding bit in ISR. • TOE : Time Out Error clear bit. 0 : Writing 0 has no effect. 1 : Writing 1 clears corresponding bit in ISR. • CRC : CRC error clear bit. 0 : Writing 0 has no effect. 1 : Writing 1 clears corresponding bit in ISR. • MSINT : Memory Stick interruption clear bit. 0 : Writing 0 has no effect. 1 : Writing 1 clears corresponding bit in ISR. • PEND : Protocol End clear bit. 0 : Writing 0 has no effect. 1 : Writing 1 clears corresponding bit in ISR. 888 32072C–AVR32–2010/03 31.7.7 Name : Interrupt Enable register IER Write Only 0x18 0x00000000 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 CD 4 TOE 3 CRC 2 MSINT 1 DRQ 0 PEND • CD : Card Detection interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR. • TOE : Time Out Error interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR. • CRC : CRC error interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR. • MSINT : Memory Stick interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR. • DRQ : Data Request interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR. • PEND : Protocol End interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR. AT32UC3A3/A4 31.7.8 Name : Interrupt Disable register IDR Write Only 0x1C 0x00000000 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 CD 4 TOE 3 CRC 2 MSINT 1 DRQ 0 PEND • CD : Card Detection interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR. • TOE : Time Out Error interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR. • CRC : CRC error interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR. • MSINT : Memory Stick interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR. • DRQ : Data Request interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR. • PEND : Protocol End interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR. 890 32072C–AVR32–2010/03 31.7.9 Name : Interrupt Mask register IMR Read Only 0x20 0x00000000 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 CD 4 TOE 3 CRC 2 MSINT 1 DRQ 0 PEND • CD : Card Detection interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. • TOE : Time Out Error interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. • CRC : CRC error interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. • MSINT : Memory Stick interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. • DRQ : Data Request interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. • PEND : Protocol End interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. AT32UC3A3/A4 31.7.10 Name : Version Register VERSION Read Only 0x24 0x00000210 Access Type : Offset : Reset Value : 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 VERSION[11:8] 9 8 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION : Version Number Version number of the module. No functionality associated. 892 32072C–AVR32–2010/03 AT32UC3A3/A4 32. Advanced Encryption Standard (AES) Rev: 1.2.3.1 32.1 Features • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit/192-bit/256-bit cryptographic key • 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key • Support of the five standard modes of operation specified in the NIST Special Publication 80038A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques: – Electronic Code Book (ECB) – Cipher Block Chaining (CBC) – Cipher Feedback (CFB) – Output Feedback (OFB) – Counter (CTR) 8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode Last output data mode allows optimized Message Authentication Code (MAC) generation Hardware counter measures against differential power analysis attacks Connection to DMA Controller capabilities optimizes data transfers for all operating modes • • • • 32.2 Overview The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 80038A Recommendation. It is compatible with all these modes via DMA Controller, minimizing processor intervention for large buffer transfers. The 128-bit/192-bit/256-bit key is stored in write-only four/six/eight 32-bit KEY Word Registers (KEYWnR) which are all write-only registers. The 128-bit input data and initialization vector (for some modes) are each stored in 32-bit Input Data Registers (IDATAnR) and in Initialization Vector Registers (VnR) which are all write-only registers. As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data is ready to be read out on the four 32-bit Output Data Registers (ODATAnR) or through the DMA Controller. 32.3 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 32.3.1 Power Management If the CPU enters a sleep mode that disables clocks used by the AES, the AES will stop functioning and resume operation after the system wakes up from sleep mode. 893 32072C–AVR32–2010/03 AT32UC3A3/A4 32.3.2 Clocks The clock for the AES bus interface (CLK_AES) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the AES before disabling the clock, to avoid freezing the AES in an undefined state. 32.3.3 Interrupts The AES interrupt request line is connected to the interrupt controller. Using the AES interrupt requires the interrupt controller to be programmed first. 32.4 Functional Description The AES specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext. The Processing Mode bit in the Mode Register (MR.CIPHER) allows selection between the encryption and the decryption processes. The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. This 128-bit/192-bit/256-bit key is defined in the KEYWnR Registers (KEYWnR). The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector, which must be writing in the Initialization Vector Registers (IVnR). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The IVRnR registers are also used in the CTR mode to set the counter value. 32.4.1 Operation Modes The AES supports the following modes of operation: • ECB: Electronic Code Book • CBC: Cipher Block Chaining • OFB: Output Feedback • CFB: Cipher Feedback – CFB8 (CFB where the length of the data segment is 8 bits) – CFB16 (CFB where the length of the data segment is 16 bits) – CFB32 (CFB where the length of the data segment is 32 bits) – CFB64 (CFB where the length of the data segment is 64 bits) – CFB128 (CFB where the length of the data segment is 128 bits) • CTR: Counter The data pre-processing, post-processing and chaining for the concerned modes are automatically performed. Refer to the NIST Special Publication 800-38A Recommendation for more complete information. These modes are selected by writing the Operation Mode field in the Mode Register (MR.OPMOD). In CFB mode, five data size are possible (8 bits, 16 bits, 32 bits, 64 bits or 128 bits). 894 32072C–AVR32–2010/03 AT32UC3A3/A4 These sizes are selected by writing the Cipher Feedback Data Size field in the MR register (MR.CFDS). 32.4.2 Start Modes The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or decryption) start mode. 32.4.2.1 Manual mode The sequence is as follows: • Write the 128-bit/192-bit/256-bit key in the KEYWnR registers. • Write the initialization vector (or counter) in the IVnR registers. Note: The Initialization Vector Registers concern all modes except ECB. • Write the Data Ready bit in the Interrupt Enable Register (IER.DATRDY), depending on whether an interrupt is required or not at the end of processing. • Write the data to be encrypted/decrypted in the authorized Input Data Registers (IDATAnR). Table 32-1. Authorized Input Data Registers IDATAnR to Write All All All All IDATA1R and IDATA2R IDATA1R IDATA1R IDATA1R All Operation Mode ECB CBC OFB 128-bit CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit CFB CTR Note: Note: In 64-bit CFB mode, writing to IDATA3R and IDATA4R registers is not allowed and may lead to errors in processing. In 32-bit, 16-bit and 8-bit CFB modes, writing to IDATA2R, IDATA3R and IDATA4R registers is not allowed and may lead to errors in processing. • Write the START bit in the Control Register (CR.START) to begin the encryption or the decryption process. • When the processing completes, the DATRDY bit in the Interrupt Status Register (ISR.DATRDY) is set. • If an interrupt has been enabled by writing the IER.DATRDY bit, the interrupt line of the AES is activated. • When the software reads one of the Output Data Registers (ODATAxR), the ISR.DATRDY bit is cleared. 32.4.2.2 Automatic mode The automatic mode is similar to the manual one, except that in this mode, as soon as the correct number of IDATAnR Registers is written, processing is automatically started without any action in the CR register. 895 32072C–AVR32–2010/03 AT32UC3A3/A4 32.4.2.3 DMA mode The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without any action by the software during processing. In this starting mode, the type of the data transfer (byte, halfword or word) depends on the operation mode. Table 32-2. Data Transfer Type for the Different Operation Modes Data Transfer Type (DMA) word word word word word word halfword byte word Operation Mode ECB CBC OFB CFB 128-bit CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit CTR The sequence is as follows: • Write the 128-bit/192-bit/256-bit key in the KEYWnR registers. • Write the initialization vector (or counter) in the IVnR registers. Note: The Initialization Vector Registers concern all modes except ECB. • Configure a channel of the DMA Controller with source address (data buffer to encrypt/decrypt) and destination address set to register IDATA1R (index is automatically incremented and rolled over to write IDATAnR). Then configure a second channel with source address set to ODATA1R (index is automatically incremented and rolled over to read ODATAnR) and destination address to write processed data. Note: Transmit and receive buffers can be identical. • Enable the DMA Controller in transmission and reception to start the processing. • The processing completion should be monitored with the DMA Controller. 32.4.3 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption algorithm (CBC-MAC algorithm for example). After each end of encryption/decryption, the output data is available either on the ODATAnR registers for manual and automatic mode or at the address specified in the receive buffer pointer for DMA mode. The Last Output Data bit in the Mode Register (MR.LOD) allows retrieval of only the last data of several encryption/decryption processes. Therefore, there is no need to define a read buffer in DMA mode. This data is only available on the Output Data Registers (ODATAnR). 896 32072C–AVR32–2010/03 AT32UC3A3/A4 32.4.3.1 Manual and automatic modes • When MR.LOD is zero The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read. Figure 32-1. Manual and Automatic Modes when MR.LOD is zero Write CR.START (Manual mode) Or Write IDATAnR register(s) (Auto mode) Read ODATAnR register(s) ISR.DATRDY Encryption or Decryption Process If the user does not want to read the output data registers between each encryption/decryption, the ISR.DATRDY bit will not be cleared. If the ISR.DATRDY bit is not cleared, the user cannot know the end of the following encryptions/decryptions. • When MR.LOD is one The ISR.DATRDY bit is cleared when at least one IDATAnR register is written, so before the start of a new transfer. No more ODATAnR register reads are necessary between consecutive encryptions/decryptions. Figure 32-2. Manual and Automatic Modes when MR.LOD is one Write CR.START(Manual mode) or Write IDATAnR register(s) (Auto mode) Write IDATAnR register(s) ISR.DATRDY Encryption or Decryption Process 32.4.3.2 DMA mode • when MR.LOD is zero The end of the encryption/decryption should be monitored with the DMA Controller. 897 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 32-3. DMA Mode when MR.LOD is zero E n a b le D M A C o n tro lle r C h a n n e ls (R e ce ive a n d T ra n sm it C h a n n e ls ) M u ltip le e n cryp tio n o r d e c ryp tio n p ro ce ss e s D M A C o n tro lle r In te rru p t • when MR.LOD is one The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that the encryption/decryption is completed. In this case, no receive buffers are required. The output data is only available in ODATAnR registers. Figure 32-4. DMA Mode when MR.LOD is one Enable DMA Controller Channels (only Transmit Channel) ISR.DATRDY Multiple Encryption or Decryption Processes DMA Controller Interrupt Following table summarizes the different cases. Table 32-3. Last Output Mode Behavior versus Start Modes Manual and Automatic Modes MR.LOD = 0 MR.LOD = 1 At least one IDATAnR register must be written MR.LOD = 0 Not used At the address specified in the configuration of DMA Mode MR.LOD = 1 Managed by the DMA ISR.DATRDY bit Clearing Condition(1) Encrypted/Decrypted Data Result Location At least one ODATAnR register must be read Controller In ODATAnR registers In ODATAnR registers In ODATAnR registers DMA Controller End of Encryption/Decryption Note: ISR.DATRDY ISR.DATRDY DMA Controller Interrupt DMA Controller Interrupt then DATRDY.ISR 1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR) definition. Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results. 898 32072C–AVR32–2010/03 AT32UC3A3/A4 32.4.4 32.4.4.1 Security Features Countermeasures The AES also features hardware countermeasures that can be useful to protect data against Differential Power Analysis (DPA) attacks. These countermeasures can be enabled through the Countermeasure Type field in the MR register (MR.CTYPE). This field is write-only, and all changes to it are taken into account if, at the same time, the Countermeasure Key field in the Mode Register (MR.CKEY) is correctly written (see the Mode Register (MR) description in Section 32.5.2). Note: Enabling countermeasures has an impact on the AES encryption/decryption throughput. By default, all the countermeasures are enabled. The best throughput is achieved with all the countermeasures disabled. On the other hand, the best protection is achieved with all of them enabled. The Random Number Generator Seed Loading bit in the CR register (CR.LOADSEED) allows a new seed to be loaded in the embedded random number generator used for the different countermeasures. 32.4.4.2 Unspecified register access detection When an unspecified register access occurs, the Unspecified Register Detection Status bit in the ISR register (ISR.URAD) is set to one. Its source is then reported in the Unspecified Register Access Type field in the ISR register (ISR.URAT). Only the last unspecified register access is available through the ISR.URAT field. Several kinds of unspecified register accesses can occur when: • Writing the IDATAnR registers during the data processing in DMA mode • Reading the ODATAnR registers during data processing • Writing the MR register during data processing • Reading the ODATAnR registers during sub-keys generation • Writing the MR register during sub-keys generation • Reading an write-only register The ISR.URAD bit and the ISR.URAT field can only be reset by the Software Reset bit in the CR register (CR.SWRST). 899 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5 User Interface AES Register Memory Map Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Key Word 1 Register Key Word 2 Register Key Word 3 Register Key Word 4 Register Key Word 5 Register Key Word 6 Register Key Word 7 Register Key Word 8 Register Input Data 1 Register Input Data 2 Register Input Data 3 Register Input Data 4 Register Output Data 1 Register Output Data 2 Register Output Data 3 Register Output Data 4 Register Initialization Vector 1 Register Initialization Vector 2 Register Initialization Vector 3 Register Initialization Vector 4 Register Version Register Register Name CR MR IER IDR IMR ISR KEYW1R KEYW2R KEYW3R KEYW4R KEYW5R KEYW6R KEYW7R KEYW8R IDATA1R IDATA2R IDATA3R IDATA4R ODATA1R ODATA2R ODATA3R ODATA4R IV1R IV2R IV3R IV4R VR Access Write-only Read/Write Write-only Write-only Read-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Read-only Read-only Read-only Write-only Write-only Write-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000001E 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xC01F0000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) Table 32-4. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0xFC Note: 1. The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter. 900 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.1 Name: Control Register CR Write-only 0x00 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 LOADSEED 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 SWRST 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 START • LOADSEED: Random Number Generator Seed Loading Writing a one to this bit will load a new seed in the embedded random number generator used for the different countermeasures. writing a zero to this bit has no effect. • SWRST: Software Reset Writing a one to this bit will reset the AES. writing a zero to this bit has no effect. • START: Start Processing Writing a one to this bit will start manual encryption/decryption process. writing a zero to this bit has no effect. 901 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.2 Name: Mode Register MR Read/Write 0x04 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 27 26 CTYPE 25 24 23 22 CKEY 21 20 19 - 18 17 CFBS 16 15 LOD 14 13 OPMOD 12 11 KEYSIZE 10 9 SMOD 8 7 6 PROCDLY 5 4 3 - 2 - 1 - 0 CIPHER • CTYPE: Countermeasure Type CTYPE X X X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X X X Description Countermeasure type 1 is disabled Add random spurious power consumption during some configuration settings Countermeasure type 2 is disabled Add randomly 1 cycle to processing. Countermeasure type 3 is disabled Add randomly 1 cycle to processing (other version) Countermeasure type 4 is disabled Add randomly up to /13/15 cycles (for /192/256-bit key) to processing Countermeasure type 5 is disabled Add random spurious power consumption during processing (recommended with DMA access) All the countermeasures are enabled by default. CTYPE field is write-only and can only be modified if CKEY is correctly set. 902 32072C–AVR32–2010/03 AT32UC3A3/A4 • CKEY: Countermeasure Key Writing the value 0xE to this field allows the CTYPE field to be modified. Writing another value to this field has no effect. This bit always reads as zero. • CFBS: Cipher Feedback Data Size CFBS 0 1 2 3 4 Others Description 128-bit 64-bit 32-bit 16-bit 8-bit Reserved • LOD: Last Output Data Mode Writing a one to this bit will enabled the LOD mode. Writing a zero to this bit will disabled the LOD mode. These mode is described in the Table 32-3 on page 898. • OPMOD: Operation Mode OPMOD 0 1 2 3 4 Others Description ECB: Electronic Code Book mode CBC: Cipher Block Chaining mode OFB: Output Feedback mode CFB: Cipher Feedback mode CTR: Counter mode Reserved • KEYSIZE: Key Size KEYSIZE 0 1 Others Description AES Key Size is 128 bits AES Key Size is 192 bits AES Key Size is 256 bits 903 32072C–AVR32–2010/03 AT32UC3A3/A4 • SMOD: Start Mode SMOD 0 1 Description Manual mode Automatic mode DMA mode 2 • LOD = 0: The encrypted/decrypted data are available at the address specified in the configuration of DMA Controller. • LOD = 1: The encrypted/decrypted data are available in the ODATAnR registers. Reserved 3 • PROCDLY: Processing Delay The processing time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption with no countermeasures activated: Processing Time = 12 × ( PROCDLY + 1 ) The best performance is achieved with PROCDLY equal to 0. Writing a value to this field will update the processing time. Reading this field will give the current processing delay. • CIPHER: Processing Mode 0: Decrypts data is enabled. 1: Encrypts data is enabled. 904 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.3 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 905 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.4 Name: Interrupt Disable Register IDR Write-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 906 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.5 Name: Interrupt Mask Register IMR Read-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 907 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.6 Name: Interrupt Status Register ISR Read-only 0x1C 0x0000001E Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 URAT 13 12 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY • URAT: Unspecified Register Access Type: URAT 0 1 2 3 4 5 Others Description The IDATAnR register during the data processing in DMA mode. The ODATAnR register read during the data processing. The MR register written during the data processing. The ODATAnR register read during the sub-keys generation. The MR register written during the sub-keys generation. Write-only register read access. Reserved Only the last Unspecified Register Access Type is available through the URAT field. This field is reset to 0 when SWRST bit in the Control Register is written to one. • URAD: Unspecified Register Access Detection Status This bit is set when at least one unspecified register access has been detected since the last software reset. This bit is cleared when SWRST bit in the Control Register is set to one. • • • • 908 32072C–AVR32–2010/03 AT32UC3A3/A4 • DATRDY: Data Ready This bit is set/clear as described in the Table 32-3 on page 898. This bit is also cleared when SWRST bit in the Control Register is set to one. 909 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.7 Name: Key Word n Register KEYWnR Write-only 0x20 +(n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 KEYWn[31:24] 23 22 21 20 19 18 17 16 KEYWn[23:16] 15 14 13 12 KEYWn[15:8] 11 10 9 8 7 6 5 4 KEYWn[7:0] 3 2 1 0 • KEYWn[31:0]: Key Word n Writing the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption in the four/six/eight 32-bit Key Word registers. KEYW1 corresponds to the first word of the key and respectively KEYW4/KEYW6/KEYW8 to the last one. This field always read as zero to prevent the key from being read by another application. 910 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.8 Name: Input Data n Register IDATAnR Write-only 0x40 + (n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 IDATAn[31:24] 23 22 21 20 19 18 17 16 IDATAn[23:16] 15 14 13 12 IDATAn[15:8] 11 10 9 8 7 6 5 4 IDATAn[7:0] 3 2 1 0 • IDATAn[31:0]: Input Data Word n Writing the 128-bit data block used for encryption/decryption in the four 32-bit Input Data registers. IDATA1 corresponds to the first word of the data to be encrypted/decrypted, and IDATA4 to the last one. This field always read as zero to prevent the input data from being read by another application. 911 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.9 Name: Output Data n Register ODATAnR Read-only 0x50 + (n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 ODATAn[31:24] 23 22 21 20 19 18 17 16 ODATAn[23:16] 15 14 13 12 ODATAn[15:8] 11 10 9 8 7 6 5 4 ODATAn[7:0] 3 2 1 0 • ODATAn[31:0]: Output Data n Reading the four 32-bit ODATAnR give the 128-bit data block that has been encrypted/decrypted. ODATA1 corresponds to the first word, ODATA4 to the last one. 912 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.10 Name: Initialization Vector n Register IVnR Write-only 0x60 + (n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 IVn[31:24] 27 26 25 24 23 22 21 20 IVn[23:16] 19 18 17 16 15 14 13 12 IVn[15:8] 11 10 9 8 7 6 5 4 IVn[7:0] 3 2 1 0 • IVn[31:0]: Initialization Vector n The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input: MODE(OPMODE. CBC,OFB, CFB CTR ECB Description initialization vector counter value not used, must not be written IV1 corresponds to the first word of the Initialization Vector, IV4 to the last one. This field is always read as zero to prevent the Initialization Vector from being read by another application. 913 32072C–AVR32–2010/03 AT32UC3A3/A4 32.5.11 Name: Version Register VERSION Read-only 0xFC - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION[11:0] Version number of the module. No functionality associated. 914 32072C–AVR32–2010/03 AT32UC3A3/A4 32.6 Module Configuration The specific configuration for each AES instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 32-5. Module name Module clock name Clock name CLK_AES AES Table 32-6. Register Register Reset Values Reset Value VERSION 0x00000123 915 32072C–AVR32–2010/03 AT32UC3A3/A4 33. Audio Bitstream DAC (ABDAC) Rev: 1.0.1.1 33.1 Features • Digital Stereo DAC • Oversampled D/A conversion architecture – Oversampling ratio fixed 128x – FIR equalization filter – Digital interpolation filter: Comb4 – 3rd Order Sigma-Delta D/A converters • Digital bitstream outputs • Parallel interface • Connected to DMA Controller for background transfer without CPU intervention 33.2 Overview The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average value proportional to the sample value. Two channels are supported, making the Audio Bitstream DAC particularly suitable for stereo audio. Each channel has a pair of complementary digital outputs, DATAn and DATANn, which can be connected to an external high input impedance amplifier. The output DATAn and DATANn should be as ideal as possible before filtering, to achieve the best SNR and THD quality. The outputs can be connected to a class D amplifier output stage to drive a speaker directly, or it can be low pass filtered and connected to a high input impedance amplifier. A simple 1st order low pass filter that filters all the frequencies above 50kHz should be adequate when applying the signal to a speaker or a bandlimited amplifier, as the speaker or amplifier will act as a filter and remove high frequency components from the signal. In some cases high frequency components might be folded down into the audible range, and in that case a higher order filter is required. For performance measurements on digital equipment a minimum of 4th order low pass filter should be used. This is to prevent aliasing in the measurements. For the best performance when not using a class D amplifier approach, the two outputs DATAn and DATANn, should be applied to a differential stage amplifier, as this will increase the SNR and THD. 916 32072C–AVR32–2010/03 AT32UC3A3/A4 33.3 Block Diagram Figure 33-1. ABDAC Block Diagram Audio Bitstream DAC PM GCLK_ABDAC Clock Generator sample_clk bit_clk CHANNEL0[15:0] Equalization FIR COMB (INT=128) COMB (INT=128) Sigma-Delta DA-MOD Sigma-Delta DA-MOD DATA0 User Interface CHANNEL1[15:0] Equalization FIR DATA1 33.4 I/O Lines Description I/O Lines Description Pin Description Output from Audio Bitstream DAC Channel 0 Output from Audio Bitstream DAC Channel 1 Inverted output from Audio Bitstream DAC Channel 0 Inverted output from Audio Bitstream DAC Channel 1 Type Output Output Output Output Table 33-1. Pin Name DATA0 DATA1 DATAN0 DATAN1 33.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 33.5.1 I/O Lines The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed with IO lines. Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode. 917 32072C–AVR32–2010/03 AT32UC3A3/A4 33.5.2 Clocks The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is enabled in the Power Manager. The ABDAC needs a separate clock for the D/A conversion operation. This clock, GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its frequency must be as follow: f GCLK = 256 × f S where fs is the samping rate of the data stream to convert. For fs= 48 kHz this means that the GCLK_ABDAC clock must have a frequency of 12.288MHz. The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other. 33.5.3 Interrupts The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC interrupt requires the interrupt controller to be programmed first. 33.6 33.6.1 Functional Description How to Initialize the Module In order to use the Audio Bitstream DAC the product dependencies given in Section 33.5 on page 917 must be resolved. Particular attention should be given to the configuration of clocks and I/O lines in order to ensure correct operation of the Audio Bitstream DAC. The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream DAC Control Register (CR.EN). The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be set whenever the ABDAC is ready to receive a new sample. A new sample value should be written to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writing one to the corresponding bits in the Interrupt Clear Register (ICR). 33.6.2 Data Format The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can be written to the least and most significant halfword of the Sample Data Register (SDR), respectively. An input value of 0x7FFF will result in an output voltage of approximately: 3838V OUT ( 0 x 7 FFF ) ≈ --------- ⋅ VDDIO = --------- ⋅ 3, 3 ≈ 0, 98 V 128 128 An Input value of 0x8000 will result in an output value of approximately: 9090V OUT ( 0 x 8000 ) ≈ --------- ⋅ VDDIO = --------- ⋅ 3, 3 ≈ 2, 32 V 128 128 918 32072C–AVR32–2010/03 AT32UC3A3/A4 If one want to get coherence between the sign of the input data and the output voltage one can use the DATAN signal or invert the sign of the input data by software. 33.6.3 Data Swapping When the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the Sample Data Register (SDR) will cause the values written to the CHANNEL0 and CHANNEL1 fields to be swapped. Peripheral DMA Controller The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA Controller can be programmed to automatically transfer samples to the Audio Bitstream DAC Sample Data Register (SDR) when the Audio Bitstream DAC is ready for new samples. In this case only the CR.EN bit needs to be set in the Audio Bitstream DAC module. This enables the Audio Bitstream DAC to operate without any CPU intervention such as polling the Interrupt Status Register (ISR) or using interrupts. See the Peripheral DMA Controller documentation for details on how to setup Peripheral DMA transfers. Construction The Audio Bitstream DAC is constructed of two 3rd order Sigma-Delta D/A converter with an oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter (Comb4) before being applied to the Sigma-Delta Modulator. In order to compensate for the pass band frequency response of the interpolation filter and flatten the overall frequency response, the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total frequency response of the Equalization FIR filter and the interpolation filter is given in Figure 332 on page 920. The digital output bitstreams from the Sigma-Delta Modulators should be lowpass filtered to remove high frequency noise inserted by the modulation process. 33.6.4 33.6.5 33.6.6 Equalization Filter The equalization filter is a simple 3-tap FIR filter. The purpose of this filter is to compensate for the pass band frequency response of the sinc interpolation filter. The equalization filter makes the pass band response more flat and moves the -3dB corner a little higher. Interpolation Filter The interpolation filter interpolates from fs to 128fs. This filter is a 4thorder Cascaded IntegratorComb filter, and the basic building blocks of this filter is a comb part and an integrator part. Sigma-Delta Modulator This part is a 3rdorder Sigma-Delta Modulator consisting of three differentiators (delta blocks), three integrators (sigma blocks) and a one bit quantizer. The purpose of the integrators is to shape the noise, so that the noise is reduced in the band of interest and increased at the higher frequencies, where it can be filtered. 33.6.7 33.6.8 919 32072C–AVR32–2010/03 AT32UC3A3/A4 33.6.9 Frequency Response Figure 33-2. Frequency Response, EQ-FIR+COMB4 10 0 [dB ] A m p li t u d e -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 0 1 2 3 4 5 F re q u e n c y 6 [F s ] 7 8 9 x 10 10 4 920 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7 User Interface ABDAC Register Memory Map Register Sample Data Register Control Register Interrupt Mask Register Interrupt Enable Register Interrupt Disable Register Interrupt Clear Register Interrupt Status Register Register Name SDR CR IMR IER IDR ICR ISR Access Read/Write Read/Write Read-only Write-only Write-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 33-2. Offset 0x00 0x08 0x0C 0x10 0x14 0x18 0x1C 921 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7.1 Name: Sample Data Register SDR Read/Write 0x00 0x00000000 30 29 28 27 CHANNEL1[15:8] 20 19 CHANNEL1[7:0] 12 11 CHANNEL0[15:8] 4 3 CHANNEL0[7:0] 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 • CHANNEL1: Sample Data for Channel 1 signed 16-bit Sample Data for channel 1. • CHANNEL0: Signed 16-bit Sample Data for Channel 0 signed 16-bit Sample Data for channel 0. 922 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7.2 Name: Control Register CR Read/Write 0x08 0x00000000 30 SWAP 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 EN 23 15 7 - • EN: Enable Audio Bitstream DAC 1: The module is enabled. 0: The module is disabled. • SWAP: Swap Channels 1: The swap of CHANNEL0 and CHANNEL1 samples is enabled. 0: The swap of CHANNEL0 and CHANNEL1 samples is disabled. 923 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7.3 Name: Interrupt Mask Register IMR Read-only 0x0C 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - 1: The corresponding interrupt is enabled. 0: The corresponding interrupt is disabled. A bit in this register is set when the corresponding bit in IER is written to one. A bit in this register is cleared when the corresponding bit in IDR is written to one. 924 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7.4 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - Writing a one to a bit in this register will set the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 925 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7.5 Name: Interrupt Disable Register IDR Write-only 0x14 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - Writing a one to a bit in this register will clear the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 926 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7.6 Name: Interrupt Clear Register ICR Write-only 0x18 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. Writing a zero to a bit in this register has no effect. 927 32072C–AVR32–2010/03 AT32UC3A3/A4 33.7.7 Name: Interrupt Status Register ISR Read-only 0x1C 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - • TXREADY: TX Ready Interrupt Status This bit is set when the Audio Bitstream DAC is ready to receive a new data in SDR. This bit is cleared when the Audio Bitstream DAC is not ready to receive a new data in SDR. • UNDERRUN: Underrun Interrupt Status This bit is set when at least one Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or by writing in ICR). This bit is cleared when no Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or by writing in ICR). 928 32072C–AVR32–2010/03 AT32UC3A3/A4 34. Programming and Debugging 34.1 Overview General description of programming and debug features, block diagram and introduction of main concepts. 34.2 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG port through a bus master module, which also handles synchronization between the debugger and SAB clocks. When accessing the SAB through the debugger there are no limitations on debugger frequency compared to chip frequency, although there must be an active system clock in order for the SAB accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger will restart the system clock automatically, without waking the device from sleep. Debuggers may optimize the transfer rate by adjusting the frequency in relation to the system clock. This ratio can be measured with debug protocol specific instructions. The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared. 34.2.1 SAB address map The Service Access Bus (SAB) gives the user access to the internal address space and other features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32 LSBs are decoded within the slave’s address space. The SAB slaves are shown in Table 34-1 on page 929. Table 34-1. Slave Unallocated OCD HSB HSB Memory Service Unit Reserved SAB Slaves, addresses and descriptions. Address [35:32] 0x0 0x1 0x4 0x5 0x6 Other Description Intentionally unallocated OCD registers HSB memory space, as seen by the CPU Alternative mapping for HSB space, for compatibility with other 32-bit AVR devices. Memory Service Unit registers Unused 34.2.2 SAB security restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below. 929 32072C–AVR32–2010/03 AT32UC3A3/A4 34.2.2.1 Security measure and control location A security measure is a mechanism to either block or allow SAB access to a certain address or address range. A security measure is enabled or disabled by one or several control signals. This is called the control location for the security measure. These security measures can be used to prevent an end user from reading out the code programmed in the flash, for instance. Table 34-2. SAB Security measures. Control Location FLASHC security bit set FLASHC UPROT + security bit set Description Programming and debugging not possible, very restricted access. Restricts all access except parts of the flash and the flash controller for programming user code. Debugging is not possible unless an OS running from the secure part of the flash supports it. Security measure Security bit User code programming Below follows a more in depth description of what locations are accessible when the security measures are active. Table 34-3. Name Security bit SAB restrictions Address start 0x100000110 0x580800000 Address end 0x100000118 0x581000000 Access Read/Write Read Blocked OCD DCCPU, OCD DCEMU, OCD DCSR User page Other accesses Table 34-4. Name User code programming SAB restrictions Address start 0x100000110 0x580800000 0x5FFFE0000 0x580000000 + BOOTPROT size Address end 0x100000118 0x581000000 0x5FFFE0400 Access Read/Write Read Read/Write OCD DCCPU, OCD DCEMU, OCD DCSR User page FLASHC PB interface FLASH pages outside BOOTPROT Other accesses 0x580000000 + Flash size - Read/Write Blocked 930 32072C–AVR32–2010/03 AT32UC3A3/A4 34.3 On-Chip Debug (OCD) Rev: 1.4.2.1 34.3.1 Features • • • • • • • • Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ JTAG access to all on-chip debug functions Advanced program, data, ownership, and watchpoint trace supported NanoTrace JTAG-based trace access Auxiliary port for high-speed trace information Hardware support for 6 program and 2 data breakpoints Unlimited number of software breakpoints supported Automatic CRC check of memory regions 34.3.2 Overview Debugging on the AT32UC3A3 is facilitated by a powerful On-Chip Debug (OCD) system. The user accesses this through an external debug tool which connects to the JTAG port and the Auxiliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based debugger is sufficient for basic debugging. The debug system is based on the Nexus 2.0 standard, class 2+, which includes: • Basic run-time control • Program breakpoints • Data breakpoints • Program trace • Ownership trace • Data trace In addition to the mandatory Nexus debug features, the AT32UC3A3 implements several useful OCD features, such as: • Debug Communication Channel between CPU and JTAG • Run-time PC monitoring • CRC checking • NanoTrace • Software Quality Assurance (SQA) support The OCD features are controlled by OCD registers, which can be accessed by JTAG when the NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical Reference Manual. 931 32072C–AVR32–2010/03 AT32UC3A3/A4 34.3.3 Block Diagram Figure 34-1. On-Chip Debug Block Diagram JTAG JTAG AUX On-Chip Debug Service Access Bus Memory Service Unit Transmit Queue Watchpoints Debug PC Debug Instruction Breakpoints Program Trace Data Trace Ownership Trace CPU Internal SRAM HSB Bus Matrix Memories and peripherals 34.3.4 JTAG-based Debug Features A debugger can control all OCD features by writing OCD registers over the JTAG interface. Many of these do not depend on output on the AUX port, allowing a JTAG-based debugger to be used. A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector as described in the AVR32UC Technical Reference Manual. 932 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 34-2. JTAG-based Debugger PC JTAG-based debug tool 10-pin IDC JTAG AVR32 34.3.4.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange data between the CPU and the JTAG master, both runtime as well as in debug mode. breakpoints One of the most fundamental debug features is the ability to halt the CPU, to examine registers and the state of the system. This is accomplished by breakpoints, of which many types are available: • Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU immediately. • Program breakpoints halt the CPU when a specific address in the program is executed. • Data breakpoints halt the CPU when a specific memory address is read or written, allowing variables to be watched. • Software breakpoints halt the CPU when the breakpoint instruction is executed. When a breakpoint triggers, the CPU enters debug mode, and the D bit in the Status Register is set. This is a privileged mode with dedicated return address and return status registers. All privileged instructions are permitted. Debug mode can be entered as either OCD mode, running instructions from JTAG, or monitor mode, running instructions from program memory. 34.3.4.2 933 32072C–AVR32–2010/03 AT32UC3A3/A4 34.3.4.3 OCD mode When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g. read out the register file by issuing mtdr instructions to the CPU, writing each register to the Debug Communication Channel OCD registers. 34.3.4.4 monitor mode Since the OCD registers are directly accessible by the CPU, it is possible to build a softwarebased debugger that runs on the CPU itself. Setting the Monitor Mode bit in the Development Control register causes the CPU to enter monitor mode instead of OCD mode when a breakpoint triggers. Monitor mode is similar to OCD mode, except that instructions are fetched from the debug exception vector in regular program memory, instead of issued by JTAG. program counter monitoring Normally, the CPU would need to be halted for a JTAG-based debugger to examine the current PC value. However, the AT32UC3A3 provides a Debug Program Counter OCD register, where the debugger can continuously read the current PC without affecting the CPU. This allows the debugger to generate a simple statistic of the time spent in various areas of the code, easing code optimization. 34.3.4.5 34.3.5 Memory Service Unit The Memory Service Unit (MSU) is a block dedicated to test and debug functionality. It is controlled through a dedicated set of registers addressed through the MEMORY_SERVICE JTAG command. Cyclic Redundancy Check (CRC) The MSU can be used to automatically calculate the CRC of a block of data in memory. The OCD will then read out each word in the specified memory block and report the CRC32-value in an OCD register. NanoTrace The MSU additionally supports NanoTrace. This is an AVR32-specific feature, in which trace data is output to memory instead of the AUX port. This allows the trace data to be extracted by JTAG MEMORY_ACCESS, enabling trace features for JTAG-based debuggers. The user must write MSU registers to configure the address and size of the memory block to be used for NanoTrace. The NanoTrace buffer can be anywhere in the physical address range, including internal and external RAM, through an EBI, if present. This area may not be used by the application running on the CPU. 34.3.5.1 34.3.5.2 34.3.6 AUX-based Debug Features Utilizing the Auxiliary (AUX) port gives access to a wide range of advanced debug features. Of prime importance are the trace features, which allow an external debugger to receive continuous information on the program execution in the CPU. Additionally, Event In and Event Out pins allow external events to be correlated with the program flow. The AUX port contains a number of pins, as shown in Table 34-5 on page 935. These are multiplexed with I/O Controller lines, and must explicitly be enabled by writing OCD registers before the debug session starts. The AUX port is mapped to two different locations, selectable by OCD Registers, minimizing the chance that the AUX port will need to be shared with an application. 934 32072C–AVR32–2010/03 AT32UC3A3/A4 Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mictor-38 connector, as described in the AVR32UC Technical Reference manual. This connector includes the JTAG signals and the RESET_N pin, giving full access to the programming and debug features in the device. Table 34-5. Signal MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Auxiliary Port Signals Direction Output Output Output Input Output Description Trace data output clock Trace data output Trace frame control Event In Event Out Figure 34-3. AUX+JTAG based Debugger PC T ra c e b u ffe r A U X +JTA G d e b u g to o l M ic t o r 3 8 AUX h ig h s p e e d JTA G AVR 32 34.3.6.1 trace operation Trace features are enabled by writing OCD registers by JTAG. The OCD extracts the trace information from the CPU, compresses this information and formats it into variable-length messages according to the Nexus standard. The messages are buffered in a 16-frame transmit queue, and are output on the AUX port one frame at a time. 935 32072C–AVR32–2010/03 AT32UC3A3/A4 The trace features can be configured to be very selective, to reduce the bandwidth on the AUX port. In case the transmit queue overflows, error messages are produced to indicate loss of data. The transmit queue module can optionally be configured to halt the CPU when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program. 34.3.6.2 program trace Program trace allows the debugger to continuously monitor the program execution in the CPU. Program trace messages are generated for every branch in the program, and contains compressed information, which allows the debugger to correlate the message with the source code to identify the branch instruction and target address. data trace Data trace outputs a message every time a specific location is read or written. The message contains information about the type (read/write) and size of the access, as well as the address and data of the accessed location. The AT32UC3A3 contains two data trace channels, each of which are controlled by a pair of OCD registers which determine the range of addresses (or single address) which should produce data trace messages. 34.3.6.4 ownership trace Program and data trace operate on virtual addresses. In cases where an operating system runs several processes in overlapping virtual memory segments, the Ownership Trace feature can be used to identify the process switch. When the O/S activates a process, it will write the process ID number to an OCD register, which produces an Ownership Trace Message, allowing the debugger to switch context for the subsequent program and data trace messages. As the use of this feature depends on the software running on the CPU, it can also be used to extract other types of information from the system. watchpoint messages The breakpoint modules normally used to generate program and data breakpoints can also be used to generate Watchpoint messages, allowing a debugger to monitor program and data events without halting the CPU. Watchpoints can be enabled independently of breakpoints, so a breakpoint module can optionally halt the CPU when the trigger condition occurs. Data trace modules can also be configured to produce watchpoint messages instead of regular data trace messages. Event In and Event Out pins The AUX port also contains an Event In pin (EVTI_N) and an Event Out pin (EVTO_N). EVTI_N can be used to trigger a breakpoint when an external event occurs. It can also be used to trigger specific program and data trace synchronization messages, allowing an external event to be correlated to the program flow. When the CPU enters debug mode, a Debug Status message is transmitted on the trace port. All trace messages can be timestamped when they are received by the debug tool. However, due to the latency of the transmit queue buffering, the timestamp will not be 100% accurate. To improve this, EVTO_N can toggle every time a message is inserted into the transmit queue, allowing trace messages to be timestamped precisely. EVTO_N can also toggle when a breakpoint module triggers, or when the CPU enters debug mode, for any reason. This can be used to measure precisely when the respective internal event occurs. 34.3.6.3 34.3.6.5 34.3.6.6 936 32072C–AVR32–2010/03 AT32UC3A3/A4 34.3.6.7 Software Quality Analysis (SQA) Software Quality Analysis (SQA) deals with two important issues regarding embedded software development. Code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. Performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized. Program trace must be used to accomplish these tasks without instrumenting (altering) the code to be examined. However, traditional program trace cannot reconstruct the current PC value without correlating the trace information with the source code, which cannot be done on-the-fly. This limits program trace to a relatively short time segment, determined by the size of the trace buffer in the debug tool. The OCD system in AT32UC3A3 extends program trace with SQA capabilities, allowing the debug tool to reconstruct the PC value on-the-fly. Code coverage and performance analysis can thus be reported for an unlimited execution sequence. 937 32072C–AVR32–2010/03 AT32UC3A3/A4 34.4 JTAG and Boundary-Scan (JTAG) Rev: 2.0.0.4 34.4.1 Features • IEEE1149.1 compliant JTAG Interface • Boundary-Scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface 34.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing. Figure 34-4 on page 939 shows how the JTAG is connected in an 32-bit AVR device. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (shift register) between the TDI-input and TDO-output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The Device Identification Register, Bypass Register, and the boundary-scan chain are the Data Registers used for board-level testing. The Reset Register can be used to keep the device reset during test or programming. The Service Access Bus (SAB) interface contains address and data registers for the Service Access Bus, which gives access to On-Chip Debug, programming, and other functions in the device. The SAB offers several modes of access to the address and data registers, as described in Section 34.4.10. Section 34.5 lists the supported JTAG instructions, with references to the description in this document. 938 32072C–AVR32–2010/03 AT32UC3A3/A4 34.4.3 Block Diagram Figure 34-4. JTAG and Boundary-Scan Access 32-bit AVR device JTAG JTAG master TMS TCK TDO TDI TAP Controller Boundary scan enable JTAG Pins TCK TMS TDI TDO Instruction register scan enable Data register scan enable Instruction Register TMS TCK TDO TDI JTAG data registers 2nd JTAG device Device Identification Register By-pass Register Pins and analog blocks Boundary Scan Chain Internal I/O lines Reset Register Part specific registers ... Service Access Bus interface SAB 34.4.4 I/O Lines Description I/O Line Description Pin Description Test Clock Input. Fully asynchronous to system clock frequency. Test Mode Select, sampled on rising TCK. Test Data In, sampled on rising TCK. Test Data Out, driven on falling TCK. Type Input Input Input Output Active Level Table 34-6. Pin Name TCK TMS TDI TDO 34.4.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 939 32072C–AVR32–2010/03 AT32UC3A3/A4 34.4.5.1 Power Management When an instruction that accesses the SAB is loaded in the instruction register, before entering a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This can lead to a program behaving differently when debugging. Clocks The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by the JTAG master. Instructions that use the SAB bus requires the internal main clock to be running. 34.4.5.2 34.4.6 JTAG Interface The JTAG Interface is accessed through the dedicated JTAG pins shown in Table 34-6 on page 939. The TMS control line navigates the TAP controller, as shown in Figure 34-5 on page 941. The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data is scanned into the selected instruction or data register on TDI, and out of the register on TDO, in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is highZ in other states than Shift-IR and Shift-DR. The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions defined by the JTAG standard are supported, as described in Section 34.5.2, as well as a number of 32-bit AVR-specific private JTAG instructions described in Section 34.5.3. Each instruction selects a specific data register for the Shift-DR path, as described for each instruction. 940 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 34-5. TAP Controller State Diagram 1 Test-LogicReset 0 1 1 Select-DR Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 1 Update-DR 0 1 0 1 0 0 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 0 1 0 0 Run-Test/ Idle 1 1 941 32072C–AVR32–2010/03 AT32UC3A3/A4 34.4.7 How to Initialize the Module Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied at the start of a JTAG session to bring the TAP Controller into a defined state before applying JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the RunTest/Idle state, which is the starting point for JTAG operations. 34.4.8 Typical Sequence Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG Interface follows. Scanning in JTAG Instruction At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register (Shift-IR) state. While in this state, shift the 5 bits of the JTAG instructions into the JTAG instruction register from the TDI input at the rising edge of TCK. During shifting, the JTAG outputs status bits on TDO, refer to Section 34.5 for a description of these. The TMS input must be held low during input of the 4 LSBs in order to remain in the Shift-IR state. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. 34.4.8.1 Figure 34-6. Scanning in JTAG Instruction TCK TAP State TMS TDI TDO 34.4.8.2 TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI Instruction ImplDefined Scanning in/out Data At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register (Shift-DR) state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin. 942 32072C–AVR32–2010/03 AT32UC3A3/A4 Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using Data Registers. 34.4.9 Boundary-Scan The boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long shift register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, boundary-scan provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the 4 TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the data register path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the 32-bit AVR device in reset during test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external RESETn pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. When using the JTAG Interface for boundary-scan, the JTAG TCK clock is independent of the internal chip clock. The internal chip clock is not required to run during boundary-scan operations. NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one using boundary-scan, as this will create a current flowing from the 3,3V driver to the 5V pull-up on the line. Optionally a series resistor can be added between the line and the pin to reduce the current. Details about the boundary-scan chain can be found in the BSDL file for the device. This can be found on the Atmel website. 34.4.10 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG through a bus master module, which also handles synchronization between the TCK and SAB clocks. 943 32072C–AVR32–2010/03 AT32UC3A3/A4 For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 34.4.10.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus. MEMORY_WORD_ACCESS is a shorthand instruction for 32-bit accesses to any 36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruction for accessing the 32-bit OCD registers in the 7-bit address space reserved for these. These instructions require two passes through the Shift-DR TAP state: one for the address and control information, and one for data. Block Transfer To increase the transfer rate, consecutive memory accesses can be accomplished by the MEMORY_BLOCK_ACCESS instruction, which only requires a single pass through Shift-DR for data transfer only. The address is automatically incremented according to the size of the last SAB transfer. Canceling a SAB Access It is possible to abort an ongoing SAB access by the CANCEL_ACCESS instruction, to avoid hanging the bus due to an extremely slow slave. Busy Reporting As the time taken to perform an access may vary depending on system activity and current chip frequency, all the SAB access JTAG instructions can return a busy indicator. This indicates whether a delay needs to be inserted, or an operation needs to be repeated in order to be successful. If a new access is requested while the SAB is busy, the request is ignored. The SAB becomes busy when: • Entering Update-DR in the address phase of any read operation, e.g., after scanning in a NEXUS_ACCESS address with the read bit set. • Entering Update-DR in the data phase of any write operation, e.g., after scanning in data for a NEXUS_ACCESS write. • Entering Update-DR during a MEMORY_BLOCK_ACCESS. • Entering Update-DR after scanning in a counter value for SYNC. • Entering Update-IR after scanning in a MEMORY_BLOCK_ACCESS if the previous access was a read and data was scanned after scanning the address. The SAB becomes ready again when: • A read or write operation completes. • A SYNC countdown completed. • A operation is cancelled by the CANCEL_ACCESS instruction. What to do if the busy bit is set: • During Shift-IR: The new instruction is selected, but the previous operation has not yet completed and will continue (unless the new instruction is CANCEL_ACCESS). You may continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting data, you must be prepared that the data shift may also report busy. • During Shift-DR of an address: The new address is ignored. The SAB stays in address mode, so no data must be shifted. Repeat the address until the busy bit clears. 34.4.10.2 34.4.10.3 34.4.10.4 944 32072C–AVR32–2010/03 AT32UC3A3/A4 • During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears. • During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat scanning until the busy bit clears. 34.4.10.5 Error Reporting The Service Access Bus may not be able to complete all accesses as requested. This may be because the address is invalid, the addressed area is read-only or cannot handle byte/halfword accesses, or because the chip is set in a protected mode where only limited accesses are allowed. The error bit is updated when an access completes, and is cleared when a new access starts. What to do if the error bit is set: • During Shift-IR: The new instruction is selected. The last operation performed using the old instruction did not complete successfully. • During Shift-DR of an address: The previous operation failed. The new address is accepted. If the read bit is set, a read operation is started. • During Shift-DR of read data: The read operation failed, and the read data is invalid. • During Shift-DR of write data: The previous write operation failed. The new data is accepted and a write operation started. This should only occur during block writes or stream writes. No error can occur between scanning a write address and the following write data. • While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not have actually completed. • After power-up: The error bit is set after power up, but there has been no previous SAB instruction so this error can be discarded. 34.4.10.6 Protected Reporting A protected status may be reported during Shift-IR or Shift-DR. This indicates that the security bit in the Flash Controller is set and that the chip is locked for access, according to Section 34.5.1. The protected state is reported when: • The Flash Controller is under reset. This can be due to the AVR_RESET command or the RESET_N line. • The Flash Controller has not read the security bit from the flash yet (This will take a a few ms). Happens after the Flash Controller reset has been released. • The security bit in the Flash Controller is set. What to do if the protected bit is set: • Release all active AVR_RESET domains, if any. • Release the RESET_N line. • Wait a few ms for the security bit to clear. It can be set temporarily due to a reset. • Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the non-volatile memory. 945 32072C–AVR32–2010/03 AT32UC3A3/A4 34.5 JTAG Instruction Summary The implemented JTAG instructions in the 32-bit AVR are shown in the table below. JTAG Instruction Summary Instruction IDCODE SAMPLE_PRELOAD EXTEST INTEST CLAMP AVR_RESET CHIP_ERASE NEXUS_ACCESS MEMORY_WORD_ACCESS MEMORY_BLOCK_ACCESS CANCEL_ACCESS MEMORY_SERVICE MEMORY_SIZED_ACCESS SYNC HALT BYPASS N/A Description Select the 32-bit Device Identification register as data register. Take a snapshot of external pin values without affecting system operation. Select boundary-scan chain as data register for testing circuitry external to the device. Select boundary-scan chain for internal testing of the device. Bypass device through Bypass register, while driving outputs from boundaryscan register. Apply or remove a static reset to the device Erase the device Select the SAB Address and Data registers as data register for the TAP. The registers are accessed in Nexus mode. Select the SAB Address and Data registers as data register for the TAP. Select the SAB Data register as data register for the TAP. The address is auto-incremented. Cancel an ongoing Nexus or Memory access. Select the SAB Address and Data registers as data register for the TAP. The registers are accessed in Memory Service mode. Select the SAB Address and Data registers as data register for the TAP. Synchronization counter Halt the CPU for safe programming. Bypass this device through the bypass register. Acts as BYPASS Table 34-7. Instruction OPCODE 0x01 0x02 0x03 0x04 0x06 0x0C 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x17 0x1C 0x1F Others 34.5.1 Security Restrictions When the security fuse in the Flash is programmed, the following JTAG instructions are restricted: • NEXUS_ACCESS • MEMORY_WORD_ACCESS • MEMORY_BLOCK_ACCESS • MEMORY_SIZED_ACCESS For description of what memory locations remain accessible, please refer to the SAB address map. Full access to these instructions is re-enabled when the security fuse is erased by the CHIP_ERASE JTAG instruction. Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. 946 32072C–AVR32–2010/03 AT32UC3A3/A4 Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 34.5.1.1 Notation Table 34-9 on page 947 shows bit patterns to be shifted in a format like "peb01". Each character corresponds to one bit, and eight bits are grouped together for readability. The least significantbit is always shifted first, and the most significant bit shifted last. The symbols used are shown in Table 34-8. Table 34-8. Symbol 0 1 a b d e Symbol Description Description Constant low value - always reads as zero. Constant high value - always reads as one. An address bit - always scanned with the least significant bit first A busy bit. Reads as one if the SAB was busy, or zero if it was not. See Section 34.4.10.4 for details on how the busy reporting works. A data bit - always scanned with the least significant bit first. An error bit. Reads as one if an error occurred, or zero if not. See Section 34.4.10.5 for details on how the error reporting works. The chip protected bit. Some devices may be set in a protected state where access to chip internals are severely restricted. See the documentation for the specific device for details. On devices without this possibility, this bit always reads as zero. A direction bit. Set to one to request a read, set to zero to request a write. A size bit. The size encoding is described where used. A don’t care bit. Any value can be shifted in, and output data should be ignored. p r s x In many cases, it is not required to shift all bits through the data register. Bit patterns are shown using the full width of the shift register, but the suggested or required bits are emphasized using bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is 34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar". The following describes how to interpret the fields in the instruction description tables: Table 34-9. Instruction Instruction Description Description Shows the bit pattern to shift into IR in the Shift-IR state in order to select this instruction. The pattern is show both in binary and in hexadecimal form for convenience. Example: 10000 (0x10) Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is active. Example: peb01 IR input value IR output value 947 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 34-9. Instruction DR Size Instruction Description (Continued) Description Shows the number of bits in the data register chain when this instruction is active. Example: 34 bits Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes. Example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx Shows the bit pattern shifted out of the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes. Example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR input value DR output value 34.5.2 Public JTAG Instructions The JTAG standard defines a number of public JTAG instructions. These instructions are described in the sections below. IDCODE This instruction selects the 32 bit Device Identification register (DID) as Data Register. The DID register consists of a version number, a device number, and the manufacturer code chosen by JEDEC. This is the default instruction after a JTAG reset. Details about the DID register can be found in the module configuration section at the end of this chapter. Starting in Run-Test/Idle, the Device Identification register is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The IDCODE value is latched into the shift register. 7. In Shift-DR: The IDCODE scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. 34.5.2.1 Table 34-10. IDCODE Details Instructions IR input value IR output value DR Size DR input value DR output value Details 00001 (0x01) p0001 32 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Device Identification Register 34.5.2.2 SAMPLE_PRELOAD This instruction takes a snap-shot of the input/output pins without affecting the system operation, and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is selected as Data Register. Starting in Run-Test/Idle, the Device Identification register is accessed in the following way: 948 32072C–AVR32–2010/03 AT32UC3A3/A4 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. Table 34-11. SAMPLE_PRELOAD Details Instructions IR input value IR output value DR Size DR input value DR output value Details 00010 (0x02) p0001 Depending on boundary-scan chain, see BSDL-file. Depending on boundary-scan chain, see BSDL-file. Depending on boundary-scan chain, see BSDL-file. 34.5.2.3 EXTEST This instruction selects the boundary-scan chain as Data Register for testing circuitry external to the 32-bit AVR package. The contents of the latched outputs of the boundary-scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction. Starting in Run-Test/Idle, the EXTEST instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the output pins. 5. Return to Run-Test/Idle. 6. Select the DR Scan path. 7. In Capture-DR: The data on the external pins is sampled into the boundary-scan chain. 8. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 9. In Update-DR: The data from the scan chain is applied to the output pins. 10. Return to Run-Test/Idle. Table 34-12. EXTEST Details Instructions IR input value IR output value DR Size DR input value DR output value Details 00011 (0x03) p0001 Depending on boundary-scan chain, see BSDL-file. Depending on boundary-scan chain, see BSDL-file. Depending on boundary-scan chain, see BSDL-file. 949 32072C–AVR32–2010/03 AT32UC3A3/A4 34.5.2.4 INTEST This instruction selects the boundary-scan chain as Data Register for testing internal logic in the device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the INTEST instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the internal logic inputs. 5. Return to Run-Test/Idle. 6. Select the DR Scan path. 7. In Capture-DR: The data on the internal logic is sampled into the boundary-scan chain. 8. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 9. In Update-DR: The data from the boundary-scan chain is applied to internal logic inputs. 10. Return to Run-Test/Idle. Table 34-13. INTEST Details Instructions IR input value IR output value DR Size DR input value DR output value Details 00100 (0x04) p0001 Depending on boundary-scan chain, see BSDL-file. Depending on boundary-scan chain, see BSDL-file. Depending on boundary-scan chain, see BSDL-file. 34.5.2.5 CLAMP This instruction selects the Bypass register as Data Register. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the output pins. 5. Return to Run-Test/Idle. 6. Select the DR Scan path. 7. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register. 8. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register. 950 32072C–AVR32–2010/03 AT32UC3A3/A4 9. Return to Run-Test/Idle. Table 34-14. CLAMP Details Instructions IR input value IR output value DR Size DR input value DR output value Details 00110 (0x06) p0001 1 x x 34.5.2.6 BYPASS This instruction selects the 1-bit Bypass Register as Data Register. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register. 7. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register. 8. Return to Run-Test/Idle. Table 34-15. BYPASS Details Instructions IR input value IR output value DR Size DR input value DR output value Details 11111 (0x1F) p0001 1 x x 34.5.3 Private JTAG Instructions The 32-bit AVR defines a number of private JTAG instructions, not defined by the JTAG standard. Each instruction is briefly described in text, with details following in table form. NEXUS_ACCESS This instruction allows Nexus-compliant access to the On-Chip Debug registers through the SAB. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through the JTAG port. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. 34.5.3.1 NOTE: The polarity of the direction bit is inverse of the Nexus standard. 951 32072C–AVR32–2010/03 AT32UC3A3/A4 Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the OCD register. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-16. NEXUS_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details 10000 (0x10) peb01 34 bits aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx dddddddd dddddddd dddddddd dddddddd xx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb eb dddddddd dddddddd dddddddd dddddddd xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.5.3.2 MEMORY_SERVICE This instruction allows access to registers in an optional Memory Service Unit. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through the JTAG port. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_SERVICE instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, Memory Service registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the Memory Service register. 952 32072C–AVR32–2010/03 AT32UC3A3/A4 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-17. MEMORY_SERVICE Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details 10100 (0x14) peb01 34 bits aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx dddddddd dddddddd dddddddd dddddddd xx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb eb dddddddd dddddddd dddddddd dddddddd xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.5.3.3 MEMORY_SIZED_ACCESS This instruction allows access to the entire Service Access Bus data area. Data is accessed through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units mapped on the SAB bus may support all sizes of accesses, e.g., some may only support word accesses. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. 953 32072C–AVR32–2010/03 AT32UC3A3/A4 The size field is encoded as i Table 34-18. Table 34-18. Size Field Semantics Size field value Access size Data alignment Address modulo 4 : data alignment 0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx 1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx 2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx 3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd Address modulo 4 : data alignment 0: dddddddd dddddddd xxxxxxxx xxxxxxxx 1: Not allowed 2: xxxxxxxx xxxxxxxx dddddddd dddddddd 3: Not allowed Address modulo 4 : data alignment 0: dddddddd dddddddd dddddddd dddddddd 1: Not allowed 2: Not allowed 3: Not allowed N/A 00 Byte (8 bits) 01 Halfword (16 bits) 10 Word (32 bits) 11 Reserved Starting in Run-Test/Idle, SAB data is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write), 2-bit access size, and the 36-bit address of the data to access. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a write operation, scan in the new contents of the area. 9. Return to Run-Test/Idle. For any operation, the full 36 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-19. MEMORY_SIZED_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) Details 10101 (0x15) peb01 39 bits aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx dddddddd dddddddd dddddddd dddddddd xxxxxxx 954 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 34-19. MEMORY_SIZED_ACCESS Details (Continued) Instructions DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb xxxxxeb dddddddd dddddddd dddddddd dddddddd xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.5.3.4 MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area. Data is accessed through the 34 MSB of the SAB address, a direction bit, and 32 bits of data. This instruction is identical to MEMORY_SIZED_ACCESS except that it always does word sized accesses. The size field is implied, and the two lowest address bits are removed and not scanned in. Note: This instruction was previously known as MEMORY_ACCESS, and is provided for backwards compatibility. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, SAB data is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 34-bit address of the data to access. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a write operation, scan in the new contents of the area. 9. Return to Run-Test/Idle. For any operation, the full 34 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-20. MEMORY_WORD_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) Details 10001 (0x11) peb01 35 bits aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx dddddddd dddddddd dddddddd dddddddd xxx 955 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 34-20. MEMORY_WORD_ACCESS Details (Continued) Instructions DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb xeb dddddddd dddddddd dddddddd dddddddd xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.5.3.5 MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area. Up to 32 bits of data is accessed at a time, while the address is sequentially incremented from the previously used address. In this mode, the SAB address, size, and access direction is not provided with each access. Instead, the previous address is auto-incremented depending on the specified size and the previous operation repeated. The address must be set up in advance with MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS. It is allowed, but not required, to shift data after shifting the address. This instruction is primarily intended to speed up large quantities of sequential word accesses. It is possible to use it also for byte and halfword accesses, but the overhead in this is case much larger as 32 bits must still be shifted for each access. The following sequence should be used: 1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the first location. 2. Return to Run-Test/Idle. 3. Select the IR Scan path. 4. In Capture-IR: The IR output value is latched into the shift register. 5. In Shift-IR: The instruction register is shifted by the TCK input. 6. Return to Run-Test/Idle. 7. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corresponding to the next byte, halfword, or word location). 8. In Shift-DR: For a read operation, scan out the contents of the next addressed location. For a write operation, scan in the new contents of the next addressed location. 9. Go to Update-DR. 10. If the block access is not complete, return to Select-DR Scan and repeat the access. 11. If the block access is complete, return to Run-Test/Idle. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-21. MEMORY_BLOCK_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Data read phase) Details 10010 (0x12) peb01 34 bits xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx 956 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 34-21. MEMORY_BLOCK_ACCESS Details (Continued) Instructions DR input value (Data write phase) DR output value (Data read phase) DR output value (Data write phase) Details dddddddd dddddddd dddddddd dddddddd xx eb dddddddd dddddddd dddddddd dddddddd xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% transfer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency. 34.5.3.6 CANCEL_ACCESS If a very slow memory location is accessed during a SAB memory access, it could take a very long time until the busy bit is cleared, and the SAB becomes ready for the next operation. The CANCEL_ACCESS instruction provides a possibility to abort an ongoing transfer and report a timeout to the JTAG master. When the CANCEL_ACCESS instruction is selected, the current access will be terminated as soon as possible. There are no guarantees about how long this will take, as the hardware may not always be able to cancel the access immediately. The SAB is ready to respond to a new command when the busy bit clears. Starting in Run-Test/Idle, CANCEL_ACCESS is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. Table 34-22. CANCEL_ACCESS Details Instructions IR input value IR output value DR Size DR input value DR output value Details 10011 (0x13) peb01 1 x 0 34.5.3.7 SYNC This instruction allows external debuggers and testers to measure the ratio between the external JTAG clock and the internal system clock. The SYNC data register is a 16-bit counter that counts down to zero using the internal system clock. The busy bit stays high until the counter reaches zero. Starting in Run-Test/Idle, SYNC instruction is used in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 957 32072C–AVR32–2010/03 AT32UC3A3/A4 6. Scan in an 16-bit counter value. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7. 9. Calculate an approximation to the internal clock speed using the elapsed time and the counter value. 10. Return to Run-Test/Idle. The full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined. When reading status, shifting may be terminated once the required number of bits have been acquired. Table 34-23. SYNC_ACCESS Details Instructions IR input value IR output value DR Size DR input value DR output value Details 10111 (0x17) peb01 16 bits dddddddd dddddddd xxxxxxxx xxxxxxeb 34.5.3.8 AVR_RESET This instruction allows a debugger or tester to directly control separate reset domains inside the chip. The shift register contains one bit for each controllable reset domain. Setting a bit to one resets that domain and holds it in reset. Setting a bit to zero releases the reset for that domain. The AVR_RESET instruction can be used in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the value corresponding to the reset domains the JTAG master wants to reset into the data register. 7. Return to Run-Test/Idle. 8. Stay in run test idle for at least 10 TCK clock cycles to let the reset propagate to the system. See the device specific documentation for the number of reset domains, and what these domains are. For any operation, all bits must be provided or the result will be undefined. Table 34-24. AVR_RESET Details Instructions IR input value IR output value Details 01100 (0x0C) p0001 958 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 34-24. AVR_RESET Details (Continued) Instructions DR Size DR input value DR output value Details Device specific. Device specific. Device specific. 34.5.3.9 CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In devices without non-volatile memories this instruction does nothing, and appears to complete immediately. The erasing of non-volatile memories starts as soon as the CHIP_ERASE instruction is selected. The CHIP_ERASE instruction selects a 1 bit bypass data register. A chip erase operation should be performed as: 1. Reset the system and stop the CPU from executing. 2. Select the IR Scan path. 3. In Capture-IR: The IR output value is latched into the shift register. 4. In Shift-IR: The instruction register is shifted by the TCK input. 5. Check the busy bit that was scanned out during Shift-IR. If the busy bit was set goto 2. 6. Return to Run-Test/Idle. Table 34-25. CHIP_ERASE Details Instructions IR input value IR output value DR Size DR input value DR output value Details 01111 (0x0F) p0b01 Where b is the busy bit. 1 bit x 0 34.5.3.10 HALT This instruction allows a programmer to easily stop the CPU to ensure that it does not execute invalid code during programming. This instruction selects a 1-bit halt register. Setting this bit to one resets the device and halts the CPU. Setting this bit to zero resets the device and releases the CPU to run normally. The value shifted out from the data register is one if the CPU is halted. The HALT instruction can be used in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 959 32072C–AVR32–2010/03 AT32UC3A3/A4 6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution. 7. Return to Run-Test/Idle. Table 34-26. HALT Details Instructions IR input value IR output value DR Size DR input value DR output value Details 11100 (0x1C) p0001 1 bit d d 960 32072C–AVR32–2010/03 AT32UC3A3/A4 34.5.4 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. Device Identification Register The Device Identification Register contains a unique identifier for each product. The register is selected by the IDCODE instruction, which is the default instruction after a JTAG reset. MSB Bit Device ID 31 28 27 Part Number 34.5.4.1 LSB 12 11 Manufacturer ID 1 0 1 Revision 4 bits 16 bits 11 bits 1 bit Revision Part Number Manufacturer ID This is a 4 bit number identifying the revision of the component. Rev A = 0x0, B = 0x1, etc. The part number is a 16 bit code identifying the component. The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is 0x01F. •Device specific ID codes The different device configurations have different JTAG ID codes, as shown in Table 34-27. Note that if the flash controller is statically reset, the ID code will be undefined. Table 34-27. Device and JTAG ID Device name AT32UC3A3256S AT32UC3A3128S AT32UC3A364S AT32UC3A3256 AT32UC3A3128 AT32UC3A364 AT32UC3A4256S AT32UC3A4128S AT32UC3A464S AT32UC3A4256 AT32UC3A128 AT32UC3A64 JTAG ID code (r is the revision number) 0xr202003F 0xr202103F 0xr202203F 0xr202603F 0xr202703F 0xr202803F 0xr202903F 0xr202a03F 0xr202b03F 0xr202c03F 0xr202d03F 0xr202e03F 961 32072C–AVR32–2010/03 AT32UC3A3/A4 34.5.4.2 Reset register The reset register is selected by the AVR_RESET instruction and contains one bit for each reset domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared. LSB Bit Device ID 4 OCD 3 APP 2 RESERVED 1 RESERVED 0 CPU CPU APP OCD RSERVED CPU HSB and PB buses On-Chip Debug logic and registers No effect Note: This register is primarily intended for compatibility with other 32-bit AVR devices. Certain operations may not function correctly when parts of the system are reset. It is generally recommended to only write 0x11111 or 0x00000 to these bits to ensure no unintended side effects occur. 34.5.4.3 Boundary-Scan Chain The Boundary-Scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the internal logic. Typically, output value, output enable, and input data are all available in the boundary scan chain. The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file available at the Atmel web site. 962 32072C–AVR32–2010/03 AT32UC3A3/A4 35. Electrical Characteristics 35.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V Total DC Output Current on all I/O Pin for TQFP144 package ................................................. 370 mA for TFBGA144 package ............................................... 370 mA 35.2 DC Characteristics The following characteristics are applicable to the operating temperature range: T A = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up toTJ = 100°C. Table 35-1. Symbol VVDDCORE VVDDIO VIL VIH DC Characteristics Parameter DC Supply Core DC Supply Peripheral I/Os Input Low-level Voltage Input High-level Voltage IOL = -2mA for Pin drive x1 IOL = -4mA for Pin drive x2 IOL = -8mA for Pin drive x3 IOL = 2mA for Pin drive x1 IOL = 4mA for Pin drive x2 IOL = 8mA for Pin drive x3 Pullup resistors disabled 7 9 15 25 2.0 4.0 8.0 On VVDDIN = 3.3V, CPU in static mode TA = 25°C TA = 85°C 30 175 VVDDIO -0.4 1 Conditions Min. 1.65 3.0 -0.3 2.0 Typ. Max. 1.95 3.6 +0.8 VVDDIO +0.3 0.4 Unit V V V V VOL Output Low-level Voltage V VOH ILEAK CIN RPULLUP Output High-level Voltage Input Leakage Current Input Capacitance Pull-up Resistance Output Current Pin drive 1x Pin drive 2x Pin drive 3x See Table 35-2 Static Current V µA pF KΩ IO mA µA µA ISC 963 32072C–AVR32–2010/03 AT32UC3A3/A4 Table 35-2. PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 Pins Drive Capabilities Drive 3x 1x 1x 1x 1x 1x 1x 1x 3x 2x 2x 2x 1x 1x 1x 1x 1x 1x 1x 1x 1x 1x PIN PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 Drive 1x 1x 1x 1x 1x 2x 1x 1x 1x 1x 1x 1x 1x 1x 1x 3x 1x 3x 2x 2x 2x 1x PIN PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 P1x0 P1x1 P1x2 P1x3 P1x4 P1x5 Drive 1x 1x 1x 1x 1x 1x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x PIN P1x6 P1x7 P1x8 P1x9 P2x0 P21x P2x2 P2x3 P2x4 P2x5 P2x6 P2x7 P2x8 P2x9 P3x0 P31x P32x P3x3 P3x4 P3x5 P3x6 P3x7 Drive 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x PIN P3x8 P3x9 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 Drive 2x 2x 2x 2x 2x 2x 2x 3x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 964 32072C–AVR32–2010/03 AT32UC3A3/A4 35.3 Regulator characteristics Electrical Characteristics Parameter Supply voltage (input) Supply voltage (output) Conditions Min. 2.7 1.81 Typ. 3.3 1.85 Max. 3.6 1.89 Unit V V Table 35-3. Symbol VVDDIN VVDDCORE Table 35-4. Symbol CIN1 CIN2 COUT1 COUT2 Decoupling Requirements Parameter Input Regulator Capacitor 1 Input Regulator Capacitor 2 Output Regulator Capacitor 1 Output Regulator Capacitor 2 Conditions Typ. 1 4.7 470 2.2 Technology NPO X7R NPO X7R Unit nF µF pF µF 35.4 35.4.1 Analog characteristics ADC Electrical Characteristics Parameter Analog Power Supply Conditions Min. 3.0 Typ. Max. 3.6 Unit V Table 35-5. Symbol VVDDANA Table 35-6. Symbol CVDDANA Decoupling Requirements Parameter Power Supply Capacitor Conditions Typ. 100 Technology NPO Unit nF 35.4.2 BOD BOD Level Values Parameter Value 00 1111b 01 0111b Conditions Min. Typ. 1.78 1.69 1.60 1.51 Max. Unit V V V V Table 35-7. Symbol BODLEVEL 01 1111b 10 0111b Table 35-7 describes the values of the BODLEVEL field in the flash FGPFR register. Table 35-8. Symbol TBOD BOD Timing Parameter Minimum time with VDDCORE < VBOD to detect power failure Conditions Falling VDDCORE from 1.8V to 1.1V Min. Typ. 300 Max. 800 Unit ns 965 32072C–AVR32–2010/03 AT32UC3A3/A4 35.4.3 Reset Sequence Electrical Characteristics Parameter VDDCORE rise rate to ensure poweron-reset VDDCORE fall rate to ensure poweron-reset Rising threshold voltage: voltage up to which device is kept under reset by POR on rising VDDCORE Falling threshold voltage: voltage when POR resets device on falling VDDCORE On falling VDDCORE, voltage must go down to this value before supply can rise again to ensure reset signal is released at VPOR+ Minimum time with VDDCORE < VPORTime for reset signal to be propagated to system Time for Cold System Startup: Time for CPU to fetch its first instruction (RCosc not calibrated) Time for Hot System Startup: Time for CPU to fetch its first instruction (RCosc calibrated) 480 Rising VDDCORE: VRESTART -> VPOR+ Conditions Min. 0.01 0.01 400 Typ. Max. Unit V/ms V/ms Table 35-9. Symbol VDDRR VDDFR VPOR+ 1.35 1.5 1.6 V VPOR- Falling VDDCORE: 1.8V -> VPOR+ 1.25 1.3 1.4 V VRESTART Falling VDDCORE: 1.8V -> VRESTART -0.1 0.5 V TPOR TRST Falling VDDCORE: 1.8V -> 1.1V 15 200 400 µs µs TSSU1 960 µs TSSU2 420 µs 966 32072C–AVR32–2010/03 AT32UC3A3/A4 Figure 35-1. MCU Cold Start-Up RESET_N tied to VDDIN VDDCORE VPORVRESTART VPOR+ RESET_N Internal POR Reset TPOR Internal MCU Reset TRST TSSU1 Figure 35-2. MCU Cold Start-Up RESET_N Externally Driven VDDCORE VPORVRESTART VPOR+ RESET_N Internal POR Reset TPOR Internal MCU Reset TRST TSSU1 Figure 35-3. MCU Hot Start-Up VDDCORE RESET_N BOD Reset WDT Reset TSSU2 Internal MCU Reset 967 32072C–AVR32–2010/03 AT32UC3A3/A4 35.4.4 RESET_N Characteristics Table 35-10. RESET_N Waveform Parameters Symbol tRESET Parameter RESET_N minimum pulse width Conditions Min. 10 Typ. Max. Unit ns 968 32072C–AVR32–2010/03 AT32UC3A3/A4 35.5 Power Consumption The values in Table 35-11 and Table 35-12 on page 970 are measured values of power consumption with operating conditions as follows: •VDDIO = 3.3V •TA = 25°C •I/Os are configured in input, pull-up enabled. Figure 35-4. Measurement Setup VDDANA Amp0 VDDIO Amp1 VDDIN Internal Voltage Regulator VDDCORE GNDCORE GNDPLL 969 32072C–AVR32–2010/03 AT32UC3A3/A4 These figures represent the power consumption measured on the power supplies. Table 35-11. Power Consumption for Different Modes Mode Conditions(1) CPU running from flash CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0: external clock (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated GPIOs on internal pull-up JTAG unconnected with ext pull-up TA = 25 °C CPU is in static mode GPIOs on internal pull-up All peripheral clocks de-activated DM and DP pins connected to ground XIN0, Xin1 and XIN32 are stopped f = 12 MHz f = 24 MHz f = 36 MHz f = 50 MHz f = 60 MHz Typ. 10 18 27 34 42 Unit mA mA mA mA mA Active on Amp0 0 µA Static on Amp1