ACPL-336J
2.5 Amp Gate Drive Optocoupler with Integrated (VCE)
Desaturation Detection, Active Miller Clamping, Fault and UVLO Status Feedback
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Avago’s ACPL-336J gate drive optocoupler features fast
propagation delay with excellent timing skew performance. Smart features that are integrated to protect
the IGBT include IGBT desaturation detection with softshutdown protection and fault feedback, undervoltage
lockout and feedback, and active Miller current clamping.
This full-featured and easy-to-implement IGBT gate drive
optocoupler comes in a compact, surface-mountable
SO-16 package for space-savings. It is suitable for driving
IGBTs and power MOSFETs used in motor control and
inverter applications.
• 2.5 A maximum peak output current
Avago isolation products provide reinforced insulation
and reliability that deliver safe signal isolation critical in
high voltage and noisy industrial applications.
VE
- Desaturation detection, “Soft” IGBT turn-off and
fault feedback
- UnderVoltage LockOut (UVLO) Protection with
feedback
• Integrated input LED driver
• 250 ns maximum propagation delay over temperature
• 30 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 1500 V
• SO-16 package with 8 mm clearance and creepage
VLED
Input LED Driver
VCC1
UVLO
UVLO
Fault
Decoder
• Integrated fail-safe IGBT protection
• Wide operating temperature range: -40 °C to 105 °C
VCC2
VIN+
FAULT
• 2.5 A Miller Clamp
• Wide operating voltage: 15 V to 30 V
Functional Diagram
VLEDDRV
• Rail-to-rail output voltage
DESAT
LED2
DESAT
Output
Driver
Applications
• Isolated IGBT/Power MOSFET gate drive
VEE1
VOUT
Soft
Shut
ANODE
V CLAMP
CATHODE
• Regulatory approvals:
– UL 1577, VISO = 5000 VRMS for 1 min
– CSA
– IEC/EN/DIN EN 60747-5-5 VIORM = 1414 VPEAK
LED1
VEE2 V EE2
• Renewable energy inverters
• AC and brushless DC motor drives
VCLAMP
• Industrial Inverters
• Switching power supplies
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Product Overview Description
The ACPL-336J is a highly integrated power control device that incorporates all the necessary components for a
complete, isolated IGBT gate drive circuit. It features IGBT desaturation detection with soft-shutdown protection and
fault feedback, undervoltage lockout and feedback, and active Miller current clamping in a SO-16 package. Direct LED
input with or without integrated LED driver allows flexible logic configuration and differential current mode driving with
low input impedance, greatly increasing its noise immunity.
Pin Description
Pin
Symbol
Description
1
VEE1
Input common
1
VEE1
VEE2 16
2
VIN+
Non inverting voltage control input.
2
VIN+
VLED 15
3
VCC1
Input power supply (4.5 V to 5.5 V)
3
VCC1
DESAT 14
4
VLEDDRV
Integrated LED driver output.
4
VLEDDRV
5
UVLO
VCC2 undervoltage lockout feedback
6
FAULT
DESAT fault feedback
VE 13
5
UVLO
VCC2 12
7
ANODE
Input LED anode
6
FAULT
VOUT 11
8
CATHODE
Input LED cathode
VCLAMP 10
9
VEE2
Negative power supply
10
VCLAMP
Miller current clamping output
11
VOUT
Driver output to IGBT gate
12
VCC2
Positive power supply
13
VE
Common (IGBT emitter) output supply voltage.
14
DESAT
Desaturation voltage input. When the voltage on DESAT
exceeds an internal reference voltage of 7 V while the IGBT is
on, VOUT will soft shut down and FAULT will change from High
impedance to Low logic state
15
VLED
No connection, for testing only
16
VEE2
Negative power supply
7
ANODE
8
CATHODE
VEE2
9
Ordering Information
ACPL-336J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Option
Part number
RoHS Compliant
Package
Surface Mount
ACPL-336J
-000E
SO-16
X
-500E
X
Tape & Reel
X
IEC/EN/DIN EN 60747-5-5
Quantity
X
45 per tube
X
850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-336J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-5 Safety Approval in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
ACPL-336J 16-Lead Surface Mount Package
0.018
(0.457)
16 15 14 13 12 11 10 9
A 336J
AVAGO
LEAD-FREE
YYWW
EEE
LAND PATTERN RECOMMENDATION
0.025 (0.64 )
0.050
(1.270)
TYPE NUMBER
DATE CODE
0.295 ± 0.010
(7.493 ± 0.254)
0.458 (11.63)
LOT ID
0.085 (2.16)
9°
1 2 3 4 5 6 7 8
0.406 ± 0.10
(10.312 ± 0.254)
0.018
(0.457)
0.345 ± 0.010
(8.763 ± 0.254)
0.138 ± 0.005
(3.505 ± 0.127)
0-8°
0.025 MIN.
0.408 ± 0.010
(10.363 ± 0.254)
ALL LEADS
TO BE
COPLANAR
± 0.002
0.008 ± 0.003
(0.203 ± 0.076)
STANDOFF
Dimensions in inches (millimeters)
Notes: Initial and continued variation in the color of the ACPL-336J’s white mold compound is normal and does note affect device performance or
reliability.
Lead coplanarity = 0.1 mm (0.004 inches)
Floating Lead Protrusion is 0.25 mm (10 mils) max.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used.
Regulatory Information
The ACPL-336J is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5
Maximum working insulation voltage VIORM = 1414 VPEAK
UL
Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
3
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*
Description
Symbol
Characteristic
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 VRMS
for rated mains voltage ≤ 300 VRMS
for rated mains voltage ≤ 600 VRMS
for rated mains voltage ≤ 1000 VRMS
I – IV
I – IV
I – IV
I – III
Climatic Classification
40/105/21
Pollution Degree (DIN VDE 0110/39)
2
Unit
Maximum Working Insulation Voltage
VIORM
1414
Vpeak
Input to Output Test Voltage, Method b**
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC
VPR
2652
Vpeak
Input to Output Test Voltage, Method a**
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC
VPR
2262
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
8000
Vpeak
Case Temperature
TS
175
°C
Input Current
IS, INPUT
400
mA
Output Power
PS, OUTPUT
1200
mW
RS
>109
W
Safety-limiting values – maximum values allowed in the event of a failure.
Insulation Resistance at TS, VIO = 500 V
* Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-336J
Units
Conditions
Minimum External Air Gap
(Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(102)
8.3
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.5
mm
Through insulation distance conductor to conductor,
usually the straight line distance thickness between the
emitter and detector.
>175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
4
CTI
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
105
°C
Output IC Junction Temperature
TJ
125
°C
Average Input Current
IF(AVG)
20
mA
Peak Transient Input Current
(< 1 µs pulse width, 300 pps)
IF(TRAN)
1
A
Reverse Input Voltage
VR
5
V
Peak Output Current
|IO(PEAK)|
2.5
A
FAULT Output Current
IFAULT
10
mA
FAULT Pin Voltage
VFAULT
VCC1
V
UVLO Output Current
IUVLO
10
mA
UVLO Pin Voltage
VUVLO
-0.5
VCC1
V
Non Inverting Voltage Control Input Voltage
VIN+
-0.5
VCC1
V
Integrated LED Driver Output Current
ILEDDRV
20
mA
Integrated LED Driver Output Voltage
VLEDDRV
-0.5
VCC1
V
Positive Input Supply Voltage
VCC1
-0.5
7.0
V
Total Output Supply Voltage
VCC2 – VEE2
-0.5
35
V
Negative Output Supply Voltage
VE – VEE2
-0.5
15
V
Positive Output Supply Voltage
VCC2 – VE
-0.5
35 – (VE – VEE)
V
Gate Drive Output Voltage
VO(PEAK)
-0.5
VCC2
V
Peak Clamping Sinking Current
ICLAMP
2.5
A
Miller Clamping Pin Voltage
VCLAMP
-0.5
VCC2
V
DESAT Voltage
VDESAT
VE – 0.5
(VCC2 + 0.5)
V
Output IC Power Dissipation
PO
600
mW
4
Input LED Power Dissipation
PI
150
mW
5
-0.5
Note
1
2
3
2
Notes:
1. Derate linearly above 70 °C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs
3. This supply is optional and is required only when negative gate drive is implemented.
4. Derate linearly above 95 °C free-air temperature at a rate of 20 mW/°C.
5. Derate linearly above 95 °C free-air temperature at a rate of 5 mW/°C. The maximum LED junction temperature should not exceed 125 °C.
Table 4. Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Operating Temperature
TA
-40
105
°C
Note
Input supply voltage
VCC1
4.5
5.5
V
1
Total Output Supply Voltage
VCC2 – VEE2
15
30
V
2
Negative Output Supply Voltage
(VE – VEE)
0
13.5
V
3
Positive Output Supply Voltage
VCC2 – VE
15
30 – (VE – VEE)
V
Input LED Current
IF(ON)
9
16
mA
Input Voltage (OFF)
VF(OFF)
-3.6
0.8
V
Notes:
1. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the
IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that input remains low until VCC1 reaches the proper operating
voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
2. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 13.7 V.
3. This supply is optional and is required only when negative gate drive is implemented.
5
Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values at TA = 25 °C, VCC1 = 5 V, VCC2 – VEE2 = 30 V, VE – VEE2 = 0 V; all Minimum/
Maximum specifications are at Recommended Operating Conditions.
Parameter
Symbol
Logic Low Input Voltage
Logic High Input Voltage
Logic High LED Driver Output RDS(ON)
Logic Low LED Driver Output Voltage
Input Low Supply Current
Input High Supply Current
VIN+L
VIN+H
RLEDDRVH
VLEDDRVL
ICC1L
ICC1H
Output Low Supply Current
Output High Supply Current
LED Forward Voltage
Temperature Coefficient of Input
Forward Voltage
LED Reverse Breakdown Voltage
Input Capacitance
LED Turn on Current Threshold Low
to High
LED Turn on Current Threshold High
to Low
LED Turn on Current Hysteresis
High Level Output Current
Low Level Output Current
High Output Transistor RDS(ON)
Low Output Transistor RDS(ON)
Low Level Output Current During
Fault Condition
High Level Output Voltage
Low Level Output Voltage
Clamp Threshold Voltage
Clamp Low Level Sinking Current
Clamp Output Transistor RDS(ON)
VCC2 UVLO Threshold Low to High
VCC2 UVLO Threshold High to Low
VCC2 UVLO Hysteresis
DESAT Detection Threshold
DESAT Charging Current
DESAT Discharging Current
FAULT Logic Low Output Current
FAULT Logic High Output Current
UVLO Logic Low Output Current
UVLO Logic High Output Current
ICC2L
ICC2H
VF
ΔVF/ΔTA
Min.
2
5.5
0.2
1.2
VBR
CIN
ITH+
5
Typ.
13.5
0.4
3
3
13
4.3
5.4
1.55
-1.7
Max.
Units
Test Conditions
0.8
V
V
Ω
V
mA
mA
mA
mA
mA
V
mV/°C
23
23
ILEDDRV = -10 mA, VIN+ = 5 V 23
ILEDDRV = 2.4 mA, VIN+ = 0 V 23
IF = 0 mA, VIN+ = 0 V
1
IF = 10 mA, VIN+=0 V
1
ILEDDRV = 10 mA , VIN+=5 V
IF = 0 mA
2, 3
IF = 10 mA
2, 3
IF =10 mA
4
IF = 10 mA
IF = 10 µA
24
0.8
6
6
16
6.5
7.5
1.95
Fig. Note
0.25
70
2
6
V
pF
mA
ITH-
0.15
1.5
5.5
mA
VOUT = 5 V
ITH_HYS
IOH
IOL
RDS,OH
RDS,OL
IOLF
-2
2
0.5
0.2
55
0.5
-3.5
3.0
2.5
1.8
115
5.0
4.0
170
mA
A
A
Ω
Ω
mA
VCC2 - VOUT =15 V
VOUT - VEE = 15 V
IOH = -2 A
IOL = 2 A
VOUT - VEE = 14 V
7
IOUT = -100 mA
IOUT = 100 mA
5
6
VOH
VOL
VTH_CLAMP
ICLAMP
RDS,CLAMP
VUVLO+
VUVLOVUVLO_HYS
VDESAT
ICHG
IDSCHG
IFAULT_L
IFAULT_H
IUVLO_L
IUVLO_H
VCC2– 0.5 VCC2 – 0.15
0.1
2
0.75
1.9
1.1
11
12.5
10.1
11.3
0.4
1.2
6.2
7
0.6
1.0
20
58
4
9.0
0.5
3
3.5
13.7
12.8
7.8
1.2
20
4
9.0
20
V
V
V
A
Ω
V
V
V
V
mA
mA
mA
µA
mA
µA
VOUT = 5 V
VCLAMP = VEE + 2.5
ICLAMP = 1 A
VOUT > 5 V
VOUT < 5 V
VDESAT = 2 V
VDESAT = 8 V
VFAULT = 0.4 V
VFAULT = 5 V
VUVLO = 0.4 V
VUVLO = 5 V
1
1
2
2
3
4, 5, 6
4, 6, 7
4, 6, 8
8
9
10
6
6, 9
Notes:
1. Maximum pulse width = 10 μs.
2. Output is sourced at -2.0 A/2.0 A with a maximum pulse width = 10 μs.
3. For further details, see the description of operation during DESAT fault condition section in the application notes.
4. 15 V is the recommended minimum operating positive supply voltage (VCC2 – VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 13.7 V. For High Level Output Voltage testing, VOH is measured with a DC load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero.
5. Maximum pulse width = 1.0 ms.
6. Once VOUT of ACPL-336J is allowed to go High (VCC2 – VE > VUVLO+), the DESAT detection feature of the ACPL-336J will be
the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 exceeds VUVLO+ threshold,
DESAT will remain functional until VCC2 is below VUVLO- threshold. Thus, the DESAT detection and UVLO features of the
ACPL-336J work in conjunction to ensure constant IGBT protection.
7. This is the “increasing” (i.e., turn-on or “positive going” direction) of VCC2 – VE.
8. This is the “decreasing” (i.e., turn-off or “negative going” direction) of VCC2 – VE.
9. For further details, see the DESAT fault detection blanking time section in the applications notes.
6
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values at TA = 25 °C, VCC1 = 5 V, VCC2 – VEE2 = 30 V, VE – VEE2 = 0 V; all Minimum/
Maximum specifications are at Recommended Operating Conditions.
Parameter
Symbol
Min.
Typ.* Max.
Units Test Conditions
Input LED to High Level Output
Propagation Delay Time
tPLH
50
130
220
ns
11, 12, 1
RG = 10 Ω, CG = 10 nF,
f = 10 kHz, Duty Cycle = 50% 13
Input LED to Low Level Output
Propagation Delay Time
tPHL
50
155
250
ns
11, 12, 2
13
Pulse Width Distortion
PWD
25
120
ns
3, 4
Propagation Delay Difference
Between Any 2 Parts (tPHL-tPLH)
PDD
150
ns
4, 5
Propagation Delay Skew
tPSK
100
ns
4,6
10% to 90% Rise Time
tR
80
ns
90% to 10% Fall Time
tF
45
ns
DESAT Blanking Time
tDESAT(BLANKING)
0.6
1.1
µs
DESAT Sense to 90% VOUT Delay
tDESAT(90%)
1.3
2
µs
DESAT Sense to 10% VOUT Delay
tDESAT(10%)
4.8
6.5
DESAT Sense to DESAT Low
Propagation Delay
tDESAT(LOW)
0.25
DESAT Sense to Low Level FAULT
Signal Delay
tDESAT(FAULT)
2.2
5
µs
Output Mute Time due to DESAT
tDESAT(MUTE)
2.3
3.0
4.2
ms
Time Input Kept Low Before Fault
Reset to High
tDESAT(RESET)
2.3
3.0
4.2
ms
VCC2 to UVLO High Delay
tPLH_UVLO
10
VCC2 to UVLO Low Delay
tPHL_UVLO
10
VCC2 UVLO to VOUT High Delay
tUVLO_ON
VCC2 UVLO to VOUT Low Delay
tUVLO_OFF
Output High Level Common Mode
Transient Immunity
|CMH|
30
Output Low Level Common Mode
Transient Immunity
|CML|
30
>50
-150
Fig.
Note
24
7
24
8
µs
24
9
µs
24
10
24
11
24
12
24
13
µs
22
14
µs
22
15
5.3
µs
22
16
1
µs
22
17
>50
kV/µs TA = 25 °C, IF = 10 mA,
VCM = 1500 V, VCC2 = 30 V
14,
16,18
18, 20
kV/µs TA = 25 °C, IF = 0 mA,
VCM = 1500 V, VCC2 = 30 V,
15, 17, 19, 20
19
RG = 10 Ω, CG= 10 nF
RF = 10 kΩ, CF = Open
RF = 10 kΩ, CF = Open
Notes:
1. tPLH is defined as propagation delay from 50% of LED input IF to 50% of High level output.
2. tPHL is defined as propagation delay from 50% of LED input IF to 50% of Low level output.
3. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
4. As measured from IF to VOUT.
5. The difference between tPHL and tPLH between any two ACPL-336J parts under the same test conditions.
6. tPSK is equal to the worst-case difference in tPHL and tPLH that will be seen between units under the same test condition.
7. The ACPL-336J internal delay time to respond to a DESAT fault condition without any external DESAT capacitor.
8. The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions.
9. The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions.
10. The amount of time from when DESAT threshold is exceeded to DESAT Low voltage, 0.7 V.
11. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of VCC1 voltage.
12. The amount of time when DESAT threshold is exceeded, output is muted to LED input.
13. The amount of time when DESAT mute time is expired, LED input must be kept low for FAULT status to return to High.
14. The delay time when VCC2 exceeds UVLO+ threshold to UVLO high – 50% of UVLO positive-going edge.
15. The delay time when VCC2 exceeds UVLO- threshold to UVLO low – 50% of UVLO negative-going edge.
16. The delay time when VCC2 exceeds UVLO+ threshold to 50% of high level output.
17. The delay time when VCC2 exceeds UVLO- threshold to 50% of low level output.
18. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VOUT > 15 V or FAULT > 2 V or UVLO > 2 V). A 330 pF and a 10 kΩ pull-up resistor are needed in FAULT and UVLO
detection mode.
19. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VOUT < 1.0 V or FAULT < 0.8 V or UVLO < 0.8 V).
20. Split resistor network in the ratio 1:1 at the anode and cathode. For further details, see description of input LED driver and split resistors circuit
section in the application notes.
7
Table 7. Package Characteristics
Parameter
Symbol
Min.
Input-Output Momentary
Withstand Voltage
VISO
5000
Resistance (Input-Output)
RI-O
Capacitance (Input-Output)
Thermal Coefficient Between
LED and Input IC
LED and Output IC
Input IC and Output IC
LED and Ambient
Input IC and Ambient
Output IC and Ambient
Typ.
Max.
Units
Test Conditions
Note
VRMS
RH < 50%,
1, 2, 3
t = 1 min., TA = 25 °C
> 109
W
VI-O = 500 VDC
CI-O
1.3
pF
freq =1 MHz
AEI
AEO
AIO
AEA
AIA
AOA
35.4
33.1
25.6
176.1
92
76.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
3
4
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
-40
7.0
I F = 10 mA for I CC1H
I F = 0 mA for I CC1L
VCC = 30 V
VEE = 0 V
ICC2 - OUTPUT SUPPLY CURRENT - mA
I CC1 - INPUT SUPPLY CURRENT - mA
Notes
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 VRMS for 1 second. This test is performed
before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table, if applicable.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating, refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Table.
3. Device considered a two-terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
4. For further details, see thermal calculation section in the application notes.
ICC1L
ICC1H
-20
0
20
40
60
TA - TEMPERATURE - °C
80
5.0
4.5
4.0
ICC2L
ICC2H
3.5
-20
0
20
40
60
TA - TEMPERATURE - °C
80
100
Figure 2. ICC2 vs. temperature
100
6.0
5.5
I F - LED1 FORWARD CURRENT - mA
IF = 10 mA for I CC2H
IF = 10 mA for I CC2L
T A = 25 ° C
V EE = 0 V
6.5
ICC2- SUPPLY CURRENT - mA
I F = 10 mA for I CC2H
I F = 0 mA for I CC2L
V CC = 30 V
V EE = 0 V
5.5
3.0
-40
7.0
5.0
10
4.5
4.0
ICC2L
ICC2H
3.5
15
Figure 3. ICC vs.VCC
8
6.0
100
Figure 1. ICC1 vs. temperature
3.0
6.5
17
19
21
VCC - SUPPLY VOLTAGE - V
23
25
1
1.4
1.5
1.6
1.7
VF - LED1 FORWARD VOLTAGE - V
Figure 4. LED1 Input Current vs. forward voltage
1.8
VOL - LOW OUTPUT VOLTAGE - V
VOH - HIGH OUTPUT VOLTAGE DROP - V
30
29.95
29.9
29.85
29.8
29.75
29.7
29.65
29.6
29.55
29.5
I F = 10 mA
I OUT = -100 mA
VCC2 = 30 V
VEE2 = 0 V
-40
-20
0
Figure 5. VOH vs. temperature
20
40
60
TA - TEMPERATURE - °C
80
100
VDESAT - DESAT THRESHOLD - V
IOLF - LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITION - mA
140
120
100
80
60
40
-40
25
105
20
0
10
20
VOUT - VEE - OUTPUT LOW VOLTAGE - V
30
Figure 7. IOLF vs. output voltage
IDSCHG - DESAT DISCHARGING CURRENT - mA
ICHG - DESAT CHARGING CURRENT - mA
-0.85
-0.90
-0.95
-1.00
-1.05
-1.10
-1.15
-20
0
Figure 9. ICHG vs. temperature
9
20
40
60
TA - TEMPERATURE - °C
-20
0
20
40
60
TA - TEMPERATURE - °C
80
100
7.5
7.4
7.3
7.2
7.1
7
6.9
6.8
6.7
6.6
6.5
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
80
100
Figure 8. VDESAT vs. temperature
-0.80
-1.20
-40
I F = 0 mA
I OUT = -100 mA
VCC = 30 V
VEE = 0 V
Figure 6. VOL vs. temperature
160
0
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40
80
100
80
70
60
50
40
30
20
10
0
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
Figure 10. IDSCHG vs. temperature
80
100
tp - PROPAGATION DELAY - ns
250
100
I F = 10 mA
CG = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
150
100
50
t PLH
t PHL
0
10
20
30
LOAD RESISTANCE - Ω
Figure 13. Propagation delay vs. load resistance
10
t PLH
t PHL
80
40
250
I = 10 mA
230 RF = 10 Ω, C = 10 nF
G
G
210 DUTY CYCLE = 50%
f = 10 kHz
190
170
150
130
110
90
70
50
15
20
25
VCC - SUPPLY VOLTAGE - V
Figure 12. Propagation delay vs. supply voltage
tp - PROPAGATION DELAY - ns
tp - PROPAGATION DELAY - ns
200
180
160
140
120
100
80
60
I = 10 mA
40 RF = 10 Ω, C = 10 nF
G
G
20 DUTY CYCLE = 50%
f = 10 kHz
0
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
Figure 11. Propagation delay vs. temperature
50
t PLH
t PHL
30
1 VEE1
VEE2 16
2 VIN+
VLED 15
3 VCC1
DESAT 14
4 VLEDDRV
VE 13
5 UVLO
150 Ω
5V
+
_
150 Ω
1 µF
VCC2 12
6 FAULT
VOUT 11
7 ANODE
VCLAMP 10
8 CATHODE
VEE2
Scope
10 Ω
30 V
10 nF +
_
9
VCM = 1500 V
Figure 14. CMR VOUT High test circuit
1 VEE1
VEE2 16
2 VIN+
VLED 15
3 VCC1
DESAT 14
4 VLEDDRV
VE 13
5 UVLO
150 Ω
150 Ω
1 µF
VCC2 12
6 FAULT
VOUT 11
7 ANODE
VCLAMP 10
8 CATHODE
VEE2
Scope
10 Ω
30 V
10 nF +
_
9
VCM = 1500 V
Figure 15. CMR VOUT Low test circuit
VLED 15
3 VCC1
DESAT 14
Scope
5V
+
_
150 Ω
150 Ω
VE 13
5 UVLO
VCC2 12
6 FAULT
VOUT 11
7 ANODE
VCLAMP 10
8 CATHODE
Figure 16. CMR FAULT High test circuit
11
VEE2 16
4 VLEDDRV
10 kΩ
330 pF
1 VEE1
1 µF
2 VIN+
VEE2
VCM = 1500 V
9
1 µF
10 Ω
30 V
10 nF +
_
VLED 15
3 VCC1
DESAT 14
VEE2 16
4 VLEDDRV
10 kΩ
Scope
330 pF
1 VEE1
1 µF
2 VIN+
5V
+
_
150 Ω
150 Ω
VE 13
5 UVLO
VCC2 12
6 FAULT
VOUT 11
7 ANODE
VCLAMP 10
8 CATHODE
1 µF
10 Ω
30 V
10 nF +
_
9
VEE2
VCM = 1500 V
Figure 17. CMR FAULT Low test circuit
10 kΩ
VLED 15
3 VCC1
DESAT 14
VEE2 16
4 VLEDDRV
Scope
330 pF
1 VEE1
1 µF
2 VIN+
5V
+
_
150 Ω
150 Ω
VE 13
5 UVLO
VCC2 12
6 FAULT
VOUT 11
7 ANODE
VCLAMP
10
VEE2
9
8 CATHODE
1 µF
10 Ω
30 V
10 nF +
_
VCM = 1500 V
Figure 18. CMR UVLO High test circuit
10 kΩ
VLED 15
3 VCC1
DESAT 14
VEE2 16
4 VLEDDRV
Scope
330 pF
1 VEE1
1 µF
2 VIN+
5V
+
_
150 Ω
150 Ω
VE 13
5 UVLO
VCC2 12
6 FAULT
VOUT 11
7 ANODE
VCLAMP 10
8 CATHODE
VEE2
VCM = 1500 V
Figure 19. CMR UVLO Low test circuit
12
9
1 µF
10 Ω
10 nF
Applications Information
Recommended Application Circuit
1 µF
+
_
10 k Ω
10 k Ω
UVLO
FAULT
330 pF
330 pF
150 Ω
150 Ω
1
VEE1
VEE2 16
2
VIN+
VLED 15
3
VCC1
DESAT 14
4
VLEDDRV
5
UVLO
VCC2 12
6
FAULT
VOUT 11
7
ANODE
VCLAMP 10
8
CATHODE
VE 13
1 µF
1kΩ
DDESAT
CBLANK =220 pF
1 µF
1 µF
RG
+
_
Q1
+
VCE
-
+
_
VEE2 9
Q2
Figure 20. Typical gate drive circuits with DESAT detection
1 µF
+
_
10 k Ω
10 k Ω
UVLO
FAULT
330 pF
330 pF
150 Ω
150 Ω
1
VEE1
VEE2 16
2
VIN+
VLED 15
3
VCC1
DESAT 14
4
VLEDDRV
5
UVLO
6
FAULT
VOUT 11
7
ANODE
VCLAMP 10
8
CATHODE
VE 13
VCC2 12
VEE2 9
1 µF
1kΩ
DDESAT
CBLANK =220 pF
1 µF
1 µF ROUT
RG
+
_
RC
+
_
Figure 21. Typical parallel IGBT gate drive circuits with DESAT detection
The ACPL-336J has non-inverting gate control inputs, and an open drain FAULT and UVLO outputs suitable for wired
‘OR’ applications. The two supplies bypass capacitors (1 µF) provide the large transient currents necessary during a
switching transition. The DESAT diode and 220 pF blanking capacitor are the necessary external components for the
fault detection circuitry. The gate resistor (RG) serves to limit gate charge current and indirectly control the IGBT collector
voltage rise and fall times. The open drain FAULT and UVLO outputs have passive 10kΩ pull-up resistors and a 330 pF
filtering capacitor.
13
Introduction to DESAT Detection
The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are potentially
destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply
short circuits due to user misconnect or bad wiring, control signal failures due to noise or computational errors, overload
conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions,
the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become
damaged when the current load approaches the saturation current of the device, and the collector to emitter voltage
rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power
device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turn-off the
IGBTs during a fault condition.
A circuit providing fast local DESAT detection and shutdown is an ideal solution, but the number of required components, board space consumed, cost, and complexity have until now limited its use to high performance drives. The
features that this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. The
ACPL-336J satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation
between the input and output, local IGBT desaturation detection and shut down, and optically isolated fault and UVLO
status feedback signal into a single 16-pin surface mount package.
The fault detection method, which is adopted in the ACPL-336J, is to monitor the saturation (collector) voltage of the
IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small
gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before
the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect
circuitry is simply disabled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit
capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only
partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-336J limits the power dissipation in the
IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method
is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold
to predict the safe limit of operation. Therefore, an overly-conservative overcurrent threshold is not needed to protect
the IGBT.
Output Control
The outputs (VOUT, FAULT and UVLO) of the ACPL-336J are controlled by the combination of VCC1, VCC2(UVLO), LED
current IF and IGBT desaturation condition. The following table shows the logic truth table for these outputs.
VCC1
VCC2 (UVLO)
IF
DESAT
VOUT
Fault
UVLO
Low
Low
X
Not Active
Low
Low
Low
Low
High
Low
Not Active
Low
Low
Low
Low
High
High
Active (no DESAT fault)
High
Low
Low
Low
High
High
Active (DESAT fault)
Low
Low
Low
High
Low
X
Not Actve
Low
High
Low
High
High
High
Active (DESAT fault)
Low
Low
High
High
High
Low
Not Active
Low
High
High
High
High
High
Active (no DESAT fault)
High
High
High
The logic level is defined by the respective threshold of each function pin.
14
Description of UnderVoltage LockOut
Insufficient gate voltage to IGBT can increase turn-on resistance of IGBT, resulting in large power loss and IGBT damage
due to high heat dissipation. ACPL-336J monitors the output power supply constantly. When output power supply is
lower than undervoltage lockout (UVLO) threshold, the gate driver output will shut off to protect IGBT from low voltage
bias. The low output power supply fault will be reported via the UVLO feedback. In this way, the UVLO feedback can also
serve as a READY signal to the controller during power up.
VCC1
VUVLO–
VCC2
VUVLO+
LED1 IF
tUVLO_OFF
VOUT
tUVLO_ON
FAULT
UVLO
tPHL_UVLO
tPLH_UVLO
Figure 22. UVLO and feedback behaviors and timing diagram
Description of Input LED Driver and Split Resistors Circuit
The ACPL-336J has integrated an input LED driver that with high impedance input(VIN+) for interfacing with the controller. The LED driver’s output(VLEDDRV) has to be connected with the recommended split resistors circuit to the LED1
anode to achieve the rated high CMR performance. The LED current can be calculated by ILEDDRV = (VCC1- VF)/(RLEDDRVH
+2R). Alternatively, if the LED driver is not used, LED1 can still be driven directly by other means of discrete driver configuration.
It is recommended that the two resistors (R) connected to input LED’s anode and cathode are split in the ratio 1:1. They
will help to balance the common mode impedances at the LED’s anode and cathode. This helps to equalize the common
mode voltage changes at the anode and cathode to give high CMR performance.
1
5V
1 µF
2
5V
+
_
3
4
ILEDDRV
R
R
VEE1
VIN+
VCC1
5
UVLO
6
FAULT
7
8
ANODE
CATHODE
Figure 23. Input LED driver functional diagram
15
RLEDDRVH
VLEDDRV
LED1
ILEDDRV = (VCC1 - VF)/(RLEDDRVH+2R)
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to
allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor.
The nominal blanking time is calculated in terms of external capacitance (CBLANK, see Figure 20 and Figure 21),
FAULT threshold voltage (VDESAT), and DESAT charge current (ICHG) in addition to an internal DESAT blanking time
(tDESAT(BLANKING)).
tBLANK = CBLANK × (VDESAT/ICHG) + tDESAT(BLANKING)
Description of Operation during DESAT Fault Condition
1. DESAT terminal monitors IGBT’s VCE voltage.
2. When the voltage on the DESAT terminal exceeds 7 V, a weak pull-down in the output stage(IOLF) will turn on to ‘softly’
turn off the IGBT. When the gate voltage falls below VEE+2 V, the Miller Clamp will turn on to clamp the IGBT gate to
VEE.
3. FAULT output goes low, notifying the microcontroller of the fault condition.
4. Microcontroller takes appropriate action.
5. When tDESAT(MUTE) expires, LED input needs to be kept low for tDESAT(RESET) before fault condition is cleared. FAULT
status will return to high.
6. Output (VOUT) starts to respond to LED input after fault condition is cleared.
tDESAT(MUTE)
LED1 IF
tDESAT(90%)
90%
VOUT
10%
tDESAT(10%)
7V
VDESAT
FAULT
tDESAT(BLANKING)
tDESAT(BLANKING)
tDESAT(LOW)
50%
t DESAT(RESET)
t DESAT(FAULT)
Figure 24. DESAT fault state timing diagram
Selecting the Gate Resistor (RG)
Step 1: Calculate RG minimum from the IO(PEAK) specification. The IGBT and RG in Figure 20 can be analyzed as a simple
RC circuit with a voltage supplied by ACPL-336J.
RG ≥
V CC − V EE
− R DS ,OH(MIN )
I O(PEAK)
= 30 − 0 V − 0 . 5 Ω
2 .5 A
= 11. 5 Ω
RG ≥
or
V CC − V EE
− R DS ,OL (MIN )
I O(PEAK)
= 30 − 0 V − 0 . 2 Ω
2 .5 A
= 11. 8 Ω
The external gate resistor, RG and internal minimum turn-on resistance, RDSON will ensure the output current will not
exceed the device absolute maximum rating of 2.5 A. In this case, we will use worst-case RG ≥ 11.8 Ω.
16
Step 2: Check the ACPL-336J power dissipation and increase RG if necessary. The ACPL-336J total power dissipation (PT)
is equal to the sum of the LED power (PE), input IC power(PI) and the output IC power (PO).
PT = PE + PI + PO
Assuming operation conditions of IF(worst case) = 16 mA, RG = 11.8 Ω, Max Duty Cycle = 80%, QG = 1 µC, f = 10 kHz and
TA max = 95 °C.
Calculation of LED Power Dissipation
PE = IF • VF • Duty Cycle
= 16 mA • 1.95 V • 0.8 = 25 mW
Calculation of Input IC Power Dissipation
PI = ICC1(Max) * VCC1(Recommended Max)
= 6 mA * 5.5 V = 33 mW
Calculation of Input IC Power Dissipation
PO = PO(BIAS) + PO(SWITCHING)
= ICC2 • (VCC2-VEE2) + PHS + PLS
PHS = (VCC2*QG*f ) * RDS,OH(MAX) / (RDS,OH(MAX)+RG) / 2
PLS = (VCC2*QG*f ) * RDS,OL(MAX) / (RDS,OL(MAX)+RG) / 2
PHS = (30 V • 1µC • 10 kHz) • 4.5 Ω/(4.5 Ω +7.3 Ω)/2 = 44.6 mW
PLS = (30 V • 1µC • 10 kHz) • 3.6 Ω/(3.6 Ω+7.3 Ω)/2 = 38.0 mW
PO = 7.5 mA • 30 V + 44.6 mW +38.0 mW
= 307.6 mW < 600 mW (PO(MAX) @ 95 °C)
The value of 7.5 mA for ICC2 in the previous equation is the maximum ICC2 over the entire operating temperature range.
Since PO is less than PO(MAX), RG = 11.8 Ω is all right for the power dissipation.
Thermal Calculation
Application and environmental design for ACPL-336J needs to ensure that the junction temperature of the internal
ICs and LED within the gate driver optocoupler do not exceed 125 °C. The following equations calculate the maximum
power dissipation effect on junction temperatures.
LED Junction Temperature, TE = AEA*PE + AEI*PI + AEO*PO + TA
= 176.1 °C/W *25 mW + 35.4 °C/W *33 mW + 33.1 °C/W *307.6 mW + 95 °C
= 110.7 °C
Input IC Junction Temperature, TI = AEI*PE + AIA*PI + AIO*PO + TA
= 35.4 °C/W *25 mW + 92 °C/W *33 mW + 25.6*307.6 mW + 95 °C
= 106.8 °C
Output IC Junction Temperature, TO = AEO*PE + AIO*PI + AOA*PO + TA
= 33.1 °C/W *25 mW + 25.6 °C/W *33 mW + 76.7*307.6 mW + 95 °C
= 120.3 °C
17
DESAT Diode and DESAT Threshold
The DESAT diode's function is to conduct forward current, allowing sensing of the IGBT's saturated collector-to-emitter
voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off").
When the IGBT is switching off and toward the end of the forward conduction of the DESAT diode, a reverse current
will flow for short time. This reverse recovery effect prevents the diode from achieving its blocking capability until the
mobile charge in the junction is depleted. During this time, there is commonly a very high dVCE/dt voltage ramp rate
across the IGBT’s collector-to-emitter. This results in ICHARGE = CD-DESAT x dVCE/dt charging current which will charge
the blanking capacitor, CBLANK. To minimize this charging current and avoid false DESAT triggering, it is best to use fastresponse diodes.
In the recommended application circuit shown in Figure 20, the voltage on pin 14 (DESAT) is VDESAT = VF + VCE, where VF
is the forward ON voltage of DDESAT and VCE is the IGBT collector-to-emitter voltage. The value of VCE that triggers DESAT
to signal a FAULT condition is nominally 7 V – VF. If desired, this DESAT threshold voltage can be decreased by using
multiple DESAT diodes or low-voltage Zener diode in series. If n is the number of DESAT diodes, the nominal threshold
value becomes VCE,FAULT(TH) = 7 V – n × VF. If a Zener diode is used, the nominal threshold value becomes VCE,FAULT(TH) = 7
V – VF – VZ. When using two diodes instead of one, then diodes with half of the total required maximum reverse-voltage
rating may be chosen.
VEE2 16
VEE2 16
VLED 15
VLED 15
1 kΩ
D ZENER
D DESAT
DESAT 14
10 V Zener
1N5925A
1 kΩ
D DESAT
DESAT 14
CBLANK
VE 13
Q1
+
V CE
-
Figure 25. DESAT diode and DESAT threshold
CBLANK
VE 13
Schottky
Diode
MBR0540
Q1
+
V CE
-
Figure 26. False fault prevention diodes
DESAT Pin Protection Resistor
The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients
that greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the
DESAT pin, which will draw substantial current out of the driver if protection is not used. To limit this current to levels that
will not damage the driver IC, make sure a 1 kΩ resistor is inserted in series with the DESAT diode.
False Fault Prevention Diodes
A situation that may cause the driver to generate a false fault signal is if the substrate diode of the driver becomes
forward biased. This can happen if the reverse recovery spikes coming from the IGBT freewheeling diodes bring the
DESAT pin below Ground. Therefore, the DESAT pin voltage will be ‘brought’ above the threshold voltage. This negative
going voltage spikes are typically generated by inductive loads or reverse recovery spikes of the IGBT/MOSFETs freewheeling diodes. To prevent a false fault signal, it is highly recommended that you connect a Zener diode and a Schottky
diode across the DESAT pin and VE pin
Figure 26 shows this circuit solution. The Schottky diode will prevent the substrate diode of the gate driver optocoupler
from being forward biased while the Zener diode (10 V) is used to prevent any positive high transient voltage from
affecting the DESAT pin.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved.
AV02-4391EN - May 9, 2014
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