PI6ULS5V9627A
4 Channel Level Translating Fast-Mode Plus I2C-bus/SMbus Repeater
Features
Description
4 channel, bidirectional buffer isolates capacitance and
allows 540pF on either side of the device at 1 MHz and
up to 4000 pF at lower speeds
Voltage level translation from 0.6V to 5.5V and from
2.2V to 5.5V
Port A operating supply voltage range of 0.6V to 5.5V
with normal levels( 0.4VCC(A) + 0.8 V ≤ VCC(B) )
Port B operating supply voltage range of 2.2V to 5.5V
with static offset level
5V tolerant I2C-bus and enable pins
0 Hz to 1 MHz clock frequency (the maximum system
operating frequency may be less than 1MHz because of
the delays added by the repeater)
Active HIGH repeater enable input referenced to VCC(B)
Open-drain input/outputs
Latching free operation
Supports arbitration and clock stretching across the
repeater
Accommodates Standard-mode, Fast-mode and Fastmode Plus I2C-bus devices, SMBus (standard and high
power mode), PMBus and multiple masters
Powered-off high-impedance I2C-bus pins
ESD protection exceeds 8000V HBM per JESD22-A114
Package: TQFN-16L 4x4 and QSOP-16L
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
The PI6ULS5V9627A is a CMOS integrated circuit intended
for Fast-mode Plus (Fm+) I2C-bus or SMBus applications. It
can provide level shifting between low voltage (down to 0.6V)
and higher voltage (2.2V to 5.5V) in mixed-mode applications.
The PI6ULS5V9627A enables the system designer to isolate
two halves of a bus for both voltage and capacitance,
accommodating more I2C devices or longer trace length. It
also permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock
(SCL) lines, thus enabling two buses of 540 pF at 1 MHz or up
to 4000 pF at lower speeds. The SDA and SCL pins are
overvoltage tolerant and are high-impedance when the
PI6ULS5V9627A is unpowered.
The 2.2V to 5.5V bus port B drivers have the static level offset,
while the adjustable voltage bus port A drivers eliminate the
static offset voltage. This results in a LOW on the port B
translating into a nearly 0V LOW on the port A which
accommodates the smaller voltage swings of lower voltage
logic. The EN pin is referenced to VCC(B) and can also be used
to turn the drivers on and off under system control.
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PI6ULS5V9627A
Pin Configuration
SCLA1 VCCA VCCB SCLB1
SDAA1
SDAB1
GND
EN1
TQFN
QSOP
VCCA
VCCB
SCLA2
SCLB2
SDAA2
QSOP-16L(Top View)
GND
EN2 SDAB2
TQFN4x4-16L(Top View)
Pin Description
Pin No.
QSOP
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
TQFN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
SDAA1
GND(1)
VCCA(2)
SCLA2
SDAA2
GND(1)
EN2
SDAB2
SCLB2
VCCB(3)
EN1
SDAB1
SCLB1
VCCB(3)
VCCA(2)
SCLA1
Description
serial data port A bus 1
supply ground (0 V)
port A supply voltage (0.6 V to 5.5V)
serial clock port A bus 2
serial data port A bus 2
supply ground (0 V)
active HIGH repeater enable input 2
serial data port B bus 2
serial clock port B bus 2
port B supply voltage (2.2 V to 5.5 V)
active HIGH repeater enable input 1
serial data port B bus 1
serial clock port B bus 1
port B supply voltage (2.2 V to 5.5 V)
port A supply voltage (0.6 V to 5.5 V)
serial clock port A bus 1
Note:
(1) The two GND pins need to be connected to the ground, can’t be floating.
(2) The two VCCA pins need to be connected to the power supply, can’t be floating.
(3) The two VCCB pins need to be connected to the power supply, can’t be floating.
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
Block Diagram
EN1
EN2
H
X
X
H
L
L
Function
SCLA1 = SCLB1
SDAA1= SDAB1
SCLA2 = SCLB2
SDAA2=SDAB2
disabled
Figure 1: Block Diagram
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
Maximum Ratings
Storage Temperature ...................................................................................... -55oC to +125oC
Supply Voltage port B ........................................................................................-0.5V to +6.0V
Supply Voltage port A .........................................................................................-0.5V to+6.0V
DC Input Voltage.................................................................................................-0.5V to +6.0V
Control Input Voltage (EN)......................................................................-0.5V to+6.0V
Total Power Dissipation...................................................................................... 100mW
Input /Output Current (port A&B) .........................................................................50mA
Input current (EN, VCCA, VCCB, GND) ...........................................................50mA
ESD: HBM Mode ................................................................................................ 8000V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
DC Electrical Characteristics
VCC(A) = 0.6V to 5.5V(1); VCC(B) = 2.2V to 5.5V; GND = 0V; TA = -40°C to +85°C; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
VCC(B)
supply voltage port B
2.2
VCC(A)
supply voltage port A
0.6
VCC(A)= 0.95V
supply current on pin
ICC(A)
VCC(A)
VCC(A)= 5.5V
port B HIGH-level
VCC(B) = 5.5 V
ICCH(B)
3
supply current
SDAn = SCLn = VCC(n)
VCC(B) = 5.5 V; one SDA and one SCL = GND;
port B LOW-level
other SDA and SCL open (with pull-up
3.4
ICCL(B)
supply current
resistors)
Quiescent current on
IQVC(B)
0.8
EN=GND;VCC(B)=5.5V
VCC(B)
Max
5.5
5.5
16
100
Unit
V
V
5
mA
5.8
mA
1
mA
μA
Note:
(1)
VCC(A) may be as high as 5.5 V for over voltage tolerance but 0.4VCC(A) + 0.8 V ≤ VCC(B) for the channels to be enabled and functional normally.
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
DC Electrical Characteristics
VCC(A) = 0.6V to 5.5V(5); VCC(B) = 2.2V to 5.5V; GND = 0V; TA = -40°C to +85°C; Typical values measured with VCC(A) = 0.95V
and VCC(B) = 2.5V, unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Input and output SDAB and SCLB
VIH
HIGH-level input voltage
-
0.7VCC(B)
-
5.5
V
VIL
LOW-level input voltage
-
-0.5
-
+0.4
V
VIK
Input clamping voltage
II = -18 mA
-1.2
-
-
V
ILI
Input leakage current
VI = 5.5V
-
-
±1
μA
IIL
LOW-level input current
SDA, SCL; VI = 0.2 V
VOL
VOL - VIL
Cio
LOW-level output voltage
Difference between LOW-level output
and LOW-level input voltage contention
Input/output capacitance
-
-
10
μA
(1)
0.47
-
-
V
(2]
-
0.54
0.60
V
60
90
160
mV
-
7
10
pF
-
7
10
pF
-
5.5
IOL = 150μA at VCC(B) = 2.2V
IOL = 13mA at VCC(B) = 2.2V
VOL at IOL = 1 mA;
guaranteed by design
VI = 3V or 0V; VCC(B) = 3.3V;
EN = LOW
VI = 3V or 0V; VCC(B) = 0V
Input and output SDAA and SCLA
VIH
HIGH-level input voltage
-
0.7VCC(A)
VIL
LOW-level input voltage
-
-0.5
VIK
Input clamping voltage
II = -18 mA
ILI
Input leakage current
IIL
(3)
-
+0.25VCC(A)
V
(4)
V
-1.2
-
-
V
VI = 5.5V
-
-
±1
μA
LOW-level input current
SDA, SCL; VI = 0.2 V
-
-
10
μA
VOL
LOW-level output voltage
-
0.1
0.2
V
Cio
Input/output capacitance
IOL = 13mA at VCC(B) = 2.2V
VI = 3V or 0V; VCC(B) = 3.3V;
EN = LOW
VI = 3V or 0V; VCC(B) = 0V
-
7
10
pF
-
7
10
pF
Enable
VIH
HIGH-level input voltage
-
0.7VCC(B)
-
5.5
V
VIL
LOW-level input voltage
-
-0.5
-
+0.3VCC(B)
V
ILI
Input leakage current
VI = VCC(B)
-1
-
+1
μA
IIL
LOW-level input current
VI = 0.2V, EN; VCC(B) = 2.2V;
-18
-7
-
μA
Ci
Input capacitance
VI = VCC(B)
-
6
-
pF
Note:
(1)
(2)
(3)
(4)
(5)
Pull-up should result in IOL ≥ 150μA.
Guaranteed by design and characterization.
VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.
When VCC(A) is less than 1V, care is required to make certain that the system ground offset and noise is minimized such that there is reasonable difference
between the VIL present at the PI6ULS5V9627 A-side input and the 0.25VCC(A) input threshold.
VCC(A) may be as high as 5.5 V for over-voltage tolerance but 0.4VCC(A) + 0.8 V ≤ VCC(B) for the channels to be enabled and functional normally.
PI6ULS5V9627A
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PI6ULS5V9627A
Dynamic characteristics
VCC(A) = 0.6V to 5.5V(8); VCC(B) = 2.2V to 5.5V; GND = 0V; TA = -40°C to +85°C; Typical values measured with VCC(A) = 0.95V
and VCC(B) = 2.5V, unless otherwise noted.(1)(2)
Min
Typ[3]
Max
Unit
B-side to A-side
B-side to A-side
B-side to A-side
A-side
-
-52
94
76
60
-103
130
152
-
ns
ns
ns
ns
Falling slew rate
port A; 0.7VCC(A) to 0.3VCC(A)
-
0.037
-
V/ns
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
LOW-to-HIGH transition time
A-side to B-side
A-side to B-side
B-side
-
45
50
60
102
173
-
ns
ns
ns
tTHL
HIGH-to-LOW transition time
B-side
-
5
-
ns
ten[7]
Enable time
-
-
100
ns
tdis[7]
Disable time
-
-
100
ns
Symbol
Parameter
tPLH
tPLH2[4]
tPHL
tTLH[5]
LOW-to-HIGH propagation delay
LOW-to-HIGH propagation delay2
HIGH-to-LOW propagation delay
LOW-to-HIGH transition time
SRf
[6]
tPLH
tPHL[6]
tTLH
Conditions
Quiescent -0.3 V; EN HIGH to
enable;
quiescent + 0.3 V;
EN LOW to disable;
Note:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Times are specified with loads of 1.35 kΩ pull-up resistance and 50 pF load capacitance on port A and port B, and a falling edge slew rate of 0.05 V/ns
input signals.
Pull-up voltages are VCC(A) on port A and VCC(B) on port B.
Typical values were measured with VCC(A) = 0.95 V,VCC(B)=2.5V at TA = 25°C, unless otherwise noted.
The tPLH2 delay data from port B to port A is measured at 0.45 V on port B to 0.5VCC(A) on port A.
The tTLH of the bus is determined by the pull-up resistance (1.35 k Ω) and the total capacitance (50 pF).
The proportional delay data from port A to port B is measured at 0.5VCC(A) on port A to 0.5VCC(B) on port B.
The enable pin EN, should only change state when the global bus and the repeater port are in an idle state.
VCC(A) may be as high as 5.5 V for over-voltage tolerance but 0.4VCC(A) + 0.8 V ≤ VCC(B) for the channels to be enabled and functional normally.
Figure 2: Propagation Delay and Transition Times BA
Figure 3: Propagation Delay and Transition Times A→B
Figure4: Propagation Delay and Enable and disable time
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
RL = load resistor; 1.35 kΩ on port B
CL = load capacitance includes jig and probe capacitance; 50 pF
RT = termination resistance should be equal to Z0 of pulse generators
Figure 5: Test Circuit
Functional Description
The PI6ULS5V9627A enables I2C-bus or SMBus translation down to VCC(A) as low as 0.6 V without degradation of system
performance. The PI6ULS5V9627A contains two bidirectional open-drain buffers specifically designed to support
up-translation/down-translation between the low voltage (as low as 0.6 V) and a 2.5 V, 3.3 V or 5 V I2C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCC(B) and/or VCC(A) = 0 V).
The PI6ULS5V9627A includes a power-up circuit that keeps the output drivers turned off until VCC(B) is above 2.2 V and until after
the internal reference circuits have settled at about 400 μs, and the VCC(A) is above 0.6 V. VCC(B) and VCC(A) can be applied in any
sequence at power-up.
The PCA9627A includes a VCC(A) over-voltage disable that turns the channel off if 0.4VCC(A) + 0.8 V > VCC(B).
The PCA9627A logic and all I/Os are powered by the VCC(B) pins.
The B-side drivers operate from 2.2V to 5.5V. The output low level of port B internal buffer is approximately 0.55 V, while the
input voltage must be 90mV lower (0.45V) or even more lower. The nearly 0.5V low signal is called a buffered low. When the
B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from
occurring when the input low condition is released. This type of design on B port prevents it from being used in series with
another PI6ULS5V9627A (B side) or similar devices, because they don’t recognize buffer low signals as a valid low .
The A-side drivers operate from 0.6V to 5.5V. The output low level of port A internal buffer is nearly 0V, while the input low level
is set at 0.35VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low
as 0.6 V. Port A of two or more PI6ULS5V9627As can be connected together to allow a star topography with port A on the
common bus. And port A can be connected directly to any other buffer with static or dynamic offset voltage. Multiple
PI6ULS5V9627As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to
consider.
After power-up and with the EN HIGH, a LOW level on port A (below 0.3VCC(A)) turns the corresponding port B driver (either
SDA or SCL) on and drives port B down to about 0.55V. When port A rises above 0.3VCC(A), the port B pull-down driver is turned
off and the external pull-up resistor pulls the pin HIGH. When port B falls first and goes below 0.4 V, the port A driver is turned
on and port A pulls down to about 0 V. The port A pull-down is not enabled unless the port B voltage goes below 0.4V. If the port
B low voltage goes below 0.4 V, the port B pull-down driver is enabled and port B will only be able to rise to 0.55 V until port A
rises above 0.3VCC(A), then port B will continue to rise being pulled up by the external pull-up resistor. The VCC(A) is only used to
provide the 0.35VCC(A) reference to the port A input comparators and for the power good detect circuit. The PI6ULS5V9627A logic
and all I/Os are powered by the VCC(B) pin.
The EN pin is active HIGH with thresholds referenced to VCC(B) and an internal pull-up to VCC(B) that maintains the device active
unless the user selects to disable the repeater to isolate a badly behaved slave on power-up until after the system power-up reset. It
should never change state during an I2C-bus operation because disabling during a bus operation will hang the bus and enabling
part way through a bus cycle could confuse the I2C-bus parts being enabled. The enable does not switch the internal reference
circuits so the 400μs delay is only seen when VCC(B) comes up. The enable pin should only change state when the global bus and the
repeater port are in an idle state to prevent system failures.
As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the buffered bus (standard
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
open-collector configuration of the I2C-bus). The size of these pull-up resistors depends on the system, but each side of the
repeater must have a pull-up resistor. This part designed to work with Standard mode, Fast-mode and Fast-mode Plus I2C-bus
devices in addition to SMBus devices. Standard mode and Fast-mode I2C-bus devices only specify 3mA output drive; this limits the
termination current to 3mA in a generic I2C-bus system where Standard-mode devices, Fast-mode devices and multiple masters
are possible. When only Fast-mode Plus devices are used with 30mA at 5V drive strength, then lower value pull-up resistors can be
used. The B-side RC should not be less than 67.5ns because shorter RCs increase the turnaround bounce when the B-side
transitions from being externally driven to pulled down by its offset buffer.
Application Information
A typical application is shown in Figure 6. In this example, the system master is running on a 3.3V I2C-bus while the slave is
connected to a 1.2V bus. Both buses run at 1MHz. Master devices can be placed on either bus.
The PI6ULS5V9627A is 5V tolerant, so it does not require any additional circuitry to translate between 0.6V to 5.5V bus voltages
and 2.2V to 5.5V bus voltages.
Figure 6: Typical Application
When port A of the PI6ULS5V9627A is pulled LOW by a driver on the I2C-bus, a comparator detects the falling edge when it goes
below 0.3VCC(A) and causes the internal driver on port B to turn on, causing port B to pull down to about 0.5 V. When port B of the
PI6ULS5V9627A falls, first a CMOS hysteresis type input detects the falling edge and causes the internal driver on port A to turn
on and pull the port A pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 9 and
Figure 10. If the bus master in Figure 6 were to write to the slave through the PI6ULS5V9627A, waveforms shown in Figure 9
would be observed on the A bus. This looks like a normal I2C-bus transmission except that the HIGH level may be as low as 0.6 V,
and the turn on and turn off of the acknowledge signals are slightly delayed.
On the B bus side of the PI6ULS5V9627A, the clock and data lines would have a positive offset from ground equal to the VOL of the
PI6ULS5V9627A. After the eighth clock pulse, the data line will be pulled to the VOL of the slave device which is very close to
ground in this example. At the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PI6ULS5V9627A for a short delay while the A bus side rises above 0.3VCC(A) then it continues HIGH. It is important to note that
any arbitration or clock stretching events require that the LOW level on the B bus side at the input of the PI6ULS5V9627A (VIL) be
at or below 0.4 V to be recognized by the PI6ULS5V9627A and then transmitted to the A bus side.
Multiple PI6ULS5V9627A port A sides can be connected in a star configuration (Figure 7), allowing all nodes to communicate
with each other.
Multiple PI6ULS5V9627As can be connected in series as long as port A is connected to port B (Figure 8). I2C-bus slave devices can
be connected to any of the bus segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
PI6ULS5V9627A
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PI6ULS5V9627A
PI6ULS5V9627A
Figure 7: Typical Star Application
PI6ULS5V9627A
PI6ULS5V9627A
Figure 8: Typical Series Application
Figure 9: Bus A (0.6V to 5.5V Bus) Waveform
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
PI6ULS
5V9627A
Figure:10: Bus B (2.2V to 5.5V Bus) Waveform
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
Mechanical Information
TQFN (ZY16)
PI6ULS5V9627A
Document Number DS40171 Rev 1-2
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PI6ULS5V9627A
QSOP-16L
For latest package info.
please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/
Ordering Information
Part No.
PI6ULS5V9627AZYEX
PI6ULS5V9627AQEX
Package Code
ZY
Q
Package
16-pin, 4x4 (TQFN), Tape & Reel
16-pin, 150mil Wide (QSOP), Tape & Reel
Notes:
Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/
E = Pb-free and Green
X suffix = Tape/Reel
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PI6ULS5V9627A
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