PI74AVC16834KE

PI74AVC16834 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 18-Bit Universal Bus Driver with 3-State Outputs Product Features Product Description • Very high-speed, low-noise universal bus driver with embedded resistor outputs • Meets PC133 SDRAM Registered DIMM specification • Implements output impedance control for low-noise and heavy-load applications • Fast Propagation Delay: 2.5ns max. for 50pF test load • VCC = 3.3V or 2.5V or 1.8V The 18-bit PI74AVC16834 universal bus driver is designed for 1.8V to 3.6V VCC operation. Data flow from A to Y is controlled by Output Enable (OE). The device operates in the transparent mode when LE is LOW. The A data is latched if CLK is held at a high or low logic level. If LE is HIGH, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the outputs are in the high-impedance state. The PI74AVC16834 bus driver is designed to drive an array of 133 MHz synchronous memory chips, with minimal undershoot/ overshoot noise, and to meet the input signal rise/fall time requirement of memory chips. • Packaging (Pb-free & Green available): – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 173 mil wide plastic TVSOP (K) The output drivers of this part have an embedded series-resistor. For DIMM module design, no external series termination resistors near the buffer drivers or any other termination resistors are required. This feature simplifies DIMM module layout design, and results in cost savings. Product Pin Configuration NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE 06-0205 1 2 56 55 GND NC 3 4 5 54 53 52 A1 6 7 8 51 50 49 9 10 48 47 A5 11 12 13 46 45 44 GND 14 15 16 43 42 41 A9 17 18 40 39 19 20 21 38 37 36 A12 GND A13 22 23 35 GND A2 A3 VCC A4 A6 A7 A8 A10 A11 A14 A15 VCC A16 24 34 33 25 26 32 31 GND A18 27 28 30 29 CLK A17 GND 1 PS8378F 09/15/06 PI74AVC16834 18-Bit Universal Bus Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Logic Block Diagram Inputs OE CLK 27 30 28 LE A1 54 1D C1 3 Y1 OE LE CLK A Outputs Y H X X X Z L L X L L L L X H H L H ↑ L L L H ↑ H H L H H X Yo(2) L H L X Yo(3) Notes: 1 H = High Signal Level L = Low Signal Level Z = High Impedance ↑ = Transition LOW-to-HIGH X = Irrelevant 2. Output level before the indicated steady-state input conditions were established, provided that CLK is HIGH before LE goes HIGH. 3. Output level before the indicated steady-state input conditions were established. CLK TO 17 OTHER CHANNELS Product Pin Description Pin Name Description OE LE CLK A Output Enable Input (Active LOW) Latch Enable (Active LOW) Clock Input Data Input Y GND VCC Data Output Ground 06-0205 Power 2 PS8378E 06/02/06 PI74AVC16834 18-Bit Universal Bus Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................................................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................................................ –40°C to +85°C Supply Voltage Range, VCC ............................................................................................................................................................................... –0.5V to +4.6V Input Voltage Range, VI(1) .................................................................................................................................................................................... –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........... –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ............................... –0.5V to VCC +0.5V Input clamp current, IIK (VI