PI7C9X440SL
PCI EXPRESS TO USB 2.0 HOST CONTROLLER
DATASHEET
REVISION 3
January 2018
1545 Barber Lane Milpitas, CA 95035
Telephone: 408-232-9100
FAX: 408-434-1040
Internet: http://www.diodes.com
Document Number DS40394 Rev 3-2
PI7C9X440SL
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without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
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Copyright © 2016, Diodes Incorporated
www.diodes.com
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 2 of 102
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PI7C9X440SL
REVISION HISTORY
Date
Revision Number
Description
06/30/09
10/20/09
0.2
0.3
06/18/10
0.4
06/23/10
0.5
08/27/10
0.6
11/18/10
0.7
12/23/10
0.8
04/29/11
1.0
06/10/11
1.1
07/15/11
11/07/11
11/23/11
1.2
1.3
1.4
02/13/11
1.5
08/13/13
1.6
09/25/13
1.7
01/05/16
01/17/17
1.8
1.9
03/22/17
2.0
01/11/18
3
Preliminary datasheet
Added Section 6 EEPROM Interface and System Management Bus
Added Section 7 Register Description
Updated Table 11-3 DC Electrical Characteristics
Updated Section 6.1.3 EEPROM Space Address Map and 6.1.4 Mapping EEPROM Contents to
Configuration Registers (Offset – C0h Physical Layer Control 3)
Updated Section 7.2 PCI Express Configuration Registers (Offset – C0h, C4h, C8h)
Added Section 14 Recommended Components
Updated Section 3 Pin Definition and Section 4 Pin Assignments (VDDCAUX to ADDC, VAUX to
VDDR)
Updated Figure 12-1 Package outline drawing
Updated Section 1 Features (Industrial Temperature Range)
Updated Section 3.3 USB Interface Signals (OCI and POE pins)
Updated Section 3.5 Miscellaneous Signals (NC pins)
Updated Section 13 Ordering Information (Industrial Temperature Range)
Updated Table 11-1 (Ambient Temperature with power applied)
Updated Section 3.3 USB Interface Signals (PME_L pin)
Updated Section 3.5 Miscellaneous Signals (MAIN_DETECT, GPIO and SMBCLK pins)
Corrected Section 4.1 Pin List (Pin 30)
Updated Section 6.1.4 Mapping EEPROM Contents to Configuration Registers (24h, 3Eh)
Updated Section 7.3.17 Serial Bus Release Number Register and 7.3.18 Miscellaneous Register
Updated 7.3.10 Base Address Register 0, 7.3.11 Base Address Register 0, 7.3.17 Serial Bus Release
Number Register, 7.3.18 Frame Length Adjustment Register, 7.3.19 Port Wake Capability Register,
7.3.22 Power Management Data Register, 7.3.27 Message Signaled Interrupt Capability ID Register,
7.3.29 Message Control Register, 7.3.30 Message Address Register, 7.3.31 Message Data Register,
7.3.40 Device Control Register, 7.3.42 Link Capabilities Register, 7.3.43 Link Control Register
Updated Table 9-3 JTAG boundary scan register definition
Updated 7.3.24 Power Management Data Register (bit 15)
Production PI7X9X440SL datasheet revision 1.0 released
Updated Section 8.2 USB Interface
Updated Section 10.1 Express Power States
Updated Section 11.3 DC Specification
Update Section 7.2.46, 7.2.53. 7.2.55. 7.2.57, 7.2.58 and 7.3.40.
Added Table 8.2 Input Clock Requirements for USB Interface
Added Table 11-4 DC electrical characteristics for Digital I/O
Updated Table 11-7 USB Interface Characteristics
Updated Section 5.1.1.3 Receiver Equalization
Updated Section 5.1.1.6 Driver Amplitude
Updated Section 7.2.53 Physical Layer Control 0 - Offset B4h (Upstream Port)
Updated Section 7.2.55 Physical Layer Control 0 - Offset B4h (Downstream Port)
Updated Section 1 Features (Power Dissipation)
Updated Section 3.5 Miscellaneous Signals (GPIO)
Updated Section 11.2 Power Consumption
Updated Section 3.6 Power Pins (Added pin 129 to VSS)
Updated Section 4.1 Pin Assignments (Added pin 129)
Updated Section 13 Ordering Information
Updated Table 11-4 DC Electrical Characteristics for Digital I/O
Updated Logo
Updated Section 11.1 Absolute Maximum Ratings
Added Section 11.2 Operating Ambient Temperature
Updated Section 3.4 JTAG Boundary Scan Signals
Updated Figure 12-1 Package Outline Drawing
Updated Section 11.1 Absolute Maximum Ratings
Remove Section 14 Recommended Components
Revision numbering system changed to whole number
Updated Section 13 Ordering Information
Added Figure 12-2 Part Marking
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
TABLE OF CONTENTS
1
FEATURES ......................................................................................................................................................... 10
2
GENERAL DESCRIPTION .............................................................................................................................. 11
3
PIN DEFINITION .............................................................................................................................................. 13
3.1
3.2
3.3
3.4
3.5
3.6
4
PIN ASSIGNMENTS ......................................................................................................................................... 16
4.1
5
SIGNAL TYPES ......................................................................................................................................... 13
PCI EXPRESS INTERFACE SIGNALS .................................................................................................... 13
USB INTERFACE SIGNALS .................................................................................................................... 13
JTAG BOUNDARY SCAN SIGNALS ...................................................................................................... 14
MISCELLANEOUS SIGNALS.................................................................................................................. 15
POWER PINS ............................................................................................................................................. 15
PIN LIST OF 128-PIN LQFP ....................................................................................................................... 16
FUNCTIONAL DESCRIPTION ....................................................................................................................... 17
5.1
PCI EXPRESS INTERFACE FUNCTIONALITIES .................................................................................. 17
5.1.1
PHYSICAL LAYER CIRCUIT ............................................................................................................. 17
5.1.1.1
5.1.1.2
5.1.1.3
5.1.1.4
5.1.1.5
5.1.1.6
5.1.1.7
5.1.1.8
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
RECEIVER DETECTION ............................................................................................................................... 18
RECEIVER SIGNAL DETECTION ............................................................................................................... 18
RECEIVER EQUALIZATION ....................................................................................................................... 18
TRANSMITTER SWING................................................................................................................................ 18
DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS ............................................................................. 19
DRIVE AMPLITUDE ..................................................................................................................................... 20
DRIVE DE-EMPHASIS .................................................................................................................................. 20
TRANSMITTER ELECTRICAL IDLE LATENCY ....................................................................................... 21
DATA LINK LAYER (DLL) ................................................................................................................. 21
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ............................................ 21
ROUTING ........................................................................................................................................... 21
TC/VC MAPPING ............................................................................................................................... 22
QUEUE ............................................................................................................................................... 22
5.1.6.1
5.1.6.2
5.1.6.3
5.1.6.4
5.1.6.5
PH .................................................................................................................................................................... 22
PD .................................................................................................................................................................... 22
NPHD .............................................................................................................................................................. 22
CPLH ............................................................................................................................................................... 22
CPLD ............................................................................................................................................................... 23
5.1.7
TRANSACTION ORDERING .............................................................................................................. 23
5.1.8
FLOW CONTROL ............................................................................................................................... 24
5.1.9
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) ............................................. 24
5.2
USB HOST CONTROLLER FUNCTIONALITIES .................................................................................. 25
5.2.1
OHCI HOST CONTROLLER .............................................................................................................. 25
5.2.1.1
5.2.2
5.2.3
OHCI LEGACY SUPPORT ............................................................................................................................ 25
EHCI HOST CONTROLLER .............................................................................................................. 25
PHYSICAL LAYER CIRCUIT ............................................................................................................. 26
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
5.2.3.6
5.2.3.7
5.2.3.8
5.2.3.9
5.2.3.10
HS DRIVER TIMING CONTROL.................................................................................................................. 26
HS DRIVER AMPLITUDE ............................................................................................................................. 26
HS DRIVER SLOPE CONTROL .................................................................................................................... 27
REFERENCE VOLTAGE FOR DISCONNECT CIRCUIT ........................................................................... 27
REFERENCE VOLTAGE FOR SQUELCH CIRCUIT .................................................................................. 27
REFERENCE VOLTAGE FOR CALIBRATION CIRCUIT .......................................................................... 28
CHARGE PUMP CURRENT FOR PLL ......................................................................................................... 28
FS RISE/FALL TIME CONTROL .................................................................................................................. 28
LS RISE/FALL TIME CONTROL .................................................................................................................. 28
HS DRIVER PRE-EMPHASIS ................................................................................................................... 29
PI7C9X440SL
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6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS.................................................................. 30
6.1
EEPROM INTERFACE.............................................................................................................................. 30
6.1.1
AUTO MODE EERPOM ACCESS...................................................................................................... 30
6.1.2
EEPROM MODE AT RESET .............................................................................................................. 30
6.1.3
EEPROM SPACE ADDRESS MAP .................................................................................................... 30
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS .......................................... 32
6.2
SMBUS INTERFACE ................................................................................................................................. 40
7
REGISTER DESCRIPTION ............................................................................................................................. 42
7.1
REGISTER TYPES .................................................................................................................................... 42
7.2
PCI EXPRESS CONFIGURATION REGISTERS ..................................................................................... 42
7.2.1
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 43
7.2.2
DEVICE ID REGISTER – OFFSET 00h ............................................................................................. 44
7.2.3
COMMAND REGISTER – OFFSET 04h ............................................................................................ 44
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................. 44
7.2.5
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 45
7.2.6
CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 45
7.2.7
CACHE LINE REGISTER – OFFSET 0Ch ......................................................................................... 45
7.2.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................ 46
7.2.9
HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................................... 46
7.2.10
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ...................................................................... 46
7.2.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................ 46
7.2.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................ 46
7.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................................... 46
7.2.14
I/O BASE ADDRESS REGISTER – OFFSET 1Ch .............................................................................. 46
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ............................................................................. 47
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch .......................................................................... 47
7.2.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h ................................................................... 47
7.2.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .................................................................. 48
7.2.19
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ..................................... 48
7.2.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h .................................... 48
7.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ......... 48
7.2.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ....... 49
7.2.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ................................................... 49
7.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.................................................. 49
7.2.25
CAPABILITY POINTER REGISTER – OFFSET 34h ......................................................................... 49
7.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................. 49
7.2.27
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 49
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch .............................................................................. 50
7.2.29
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ........................................... 50
7.2.30
NEXT ITEM POINTER REGISTER – OFFSET 80h ........................................................................... 51
7.2.31
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ............................................. 51
7.2.32
POWER MANAGEMENT DATA REGISTER – OFFSET 84h ............................................................ 51
7.2.33
PPB SUPPORT EXTENSIONS – OFFSET 84h .................................................................................. 52
7.2.34
DATA REGISTER – OFFSET 84h ...................................................................................................... 52
7.2.35
MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) .................................... 52
7.2.36
NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) ................................. 52
7.2.37
MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only) .................................. 52
7.2.38
MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only) .................................... 52
7.2.39
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream Port Only) ...................... 53
7.2.40
MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) ........................................... 53
7.2.41
VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only) ........................................ 53
7.2.42
NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only) ...................................... 53
7.2.43
VPD REGISTER – OFFSET 9Ch (Upstream Port Only) .................................................................... 53
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PI7C9X440SL
7.2.44
7.2.45
7.2.46
7.2.47
7.2.48
7.2.49
7.2.50
7.2.51
7.2.52
7.2.53
7.2.54
7.2.55
7.2.56
7.2.57
7.2.58
7.2.59
7.2.60
7.2.61
7.2.62
7.2.63
7.2.64
7.2.65
7.2.66
7.2.67
7.2.68
7.2.69
7.2.70
7.2.71
7.2.72
7.2.73
7.2.74
7.2.75
7.2.76
7.2.77
7.2.78
7.2.79
7.2.80
7.2.81
7.2.82
7.2.83
7.2.84
7.2.85
7.2.86
7.2.87
7.2.88
7.2.89
7.2.90
7.2.91
7.2.92
7.2.93
7.2.94
7.2.95
7.2.96
7.2.97
VPD DATA REGISTER – OFFSET A0h (Upstream Port Only) ......................................................... 54
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h .................................................. 54
NEXT ITEM POINTER REGISTER – OFFSET A4h .......................................................................... 54
LENGTH REGISTER – OFFSET A4h ................................................................................................ 54
XPIP CSR0 – OFFSET A8h (Test Purpose Only) ............................................................................... 54
XPIP CSR1 – OFFSET ACh (Test Purpose Only) .............................................................................. 54
REPLAY TIME-OUT COUNTER – OFFSET B0h (Upstream Port)................................................... 54
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h ....................................................................... 55
SWITCH OPERATION MODE – OFFSET B4h (Upstream Port) ...................................................... 55
PHYSICAL LAYER CONTROL 0 – OFFSET B4h (Upstream Port) ................................................... 56
SWITCH OPERATION MODE – OFFSET B4h (Downstream Port) ................................................. 56
PHYSICAL LAYER CONTROL 0 – OFFSET B4h (Downstream Port) .............................................. 57
XPIP CSR2 / TL CSR – OFFSET B8h (Test Purpose Only) ............................................................... 57
PHYSICAL LAYER CONTROL 1 – OFFSET B8h (Test Purpose Only) ............................................. 57
PHYSCIAL LAYER CONTROL 2 – OFFSET BCh ............................................................................. 57
PHYSICAL LAYER CONTROL 3 REGISTER – OFFSET C0h ........................................................... 58
SSID/SSVID CAPABILITY ID REGISTER – OFFSET C4h ................................................................ 58
NEXT ITEM POINTER REGISTER – OFFSET C4h .......................................................................... 58
SUBSYSTEM VENDOR ID REGISTER – OFFSET C8h .................................................................... 58
SUBSYSTEM ID REGISTER – OFFSET C8h ..................................................................................... 58
GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only) ............................................... 58
EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only) ........................................ 60
EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only) ......................................... 60
EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only) ................................................ 61
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ............................................................ 61
NEXT ITEM POINTER REGISTER – OFFSET E0h .......................................................................... 61
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h .............................................................. 61
DEVICE CAPABILITIES REGISTER – OFFSET E4h ....................................................................... 61
DEVICE CONTROL REGISTER – OFFSET E8h............................................................................... 62
DEVICE STATUS REGISTER – OFFSET E8h ................................................................................... 63
LINK CAPABILITIES REGISTER – OFFSET ECh ............................................................................ 63
LINK CONTROL REGISTER – OFFSET F0h .................................................................................... 64
LINK STATUS REGISTER – OFFSET F0h ........................................................................................ 65
SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h ................................... 66
SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h ........................................... 66
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h ............................................... 67
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h . 68
CAPABILITY VERSION – OFFSET 100h .......................................................................................... 68
NEXT ITEM POINTER REGISTER – OFFSET 100h ......................................................................... 68
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 68
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 69
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................. 70
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h ...................................................... 71
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ......................................................... 71
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ......................... 72
HEADER LOG REGISTER – OFFSET From 11Ch to 128h .............................................................. 72
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET 140h (Upstream Only)
72
CAPABILITY VERSION – OFFSET 140h (Upstream Only) .............................................................. 72
NEXT ITEM POINTER REGISTER – OFFSET 140h (Upstream Only) ............................................. 72
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h (Upstream Only) ........................................ 73
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h (Upstream Only) ........................................ 73
PORT VC CONTROL REGISTER – OFFSET 14Ch (Upstream Only)............................................... 73
PORT VC STATUS REGISTER – OFFSET 14Ch (Upstream Only) ................................................... 74
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h (Upstream Only) ............................ 74
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7.2.98
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h (Upstream Only) .............................. 74
7.2.99
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h (Upstream Only) .................................... 75
7.2.100
PORT ARBITRATION TABLE REGISTER (0) – OFFSET 180h-1BCh (Upstream Only) .............. 75
7.2.101
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER – OFFSET 20Ch ................ 76
7.2.102
CAPABILITY VERSION – OFFSET 20Ch ...................................................................................... 76
7.2.103
NEXT ITEM POINTER REGISTER – OFFSET 20Ch .................................................................... 76
7.2.104
DATA SELECT REGISTER – OFFSET 210h ................................................................................. 76
7.2.105
POWER BUDGETING DATA REGISTER – OFFSET 214h .......................................................... 76
7.2.106
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ..................................................... 77
7.3
USB DEVICE CONFIGURATION REGISTERS (FUNC0/FUNC1/FUNC2) .......................................... 78
7.3.1
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 78
7.3.2
DEVICE ID REGISTER – OFFSET 00h ............................................................................................. 79
7.3.3
COMMAND REGISTER – OFFSET 04h ............................................................................................ 79
7.3.4
STATUS REGISTER – OFFSET 04h .................................................................................................. 79
7.3.5
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 80
7.3.6
CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 80
7.3.7
CACHE LINE REGISTER – OFFSET 0Ch ......................................................................................... 80
7.3.8
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 81
7.3.9
HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................................... 81
7.3.10
BASE ADDRESS REGISTER 0 – OFFSET 10h (Func 0 and Func 1) ................................................ 81
7.3.11
BASE ADDRESS REGISTER 0 – OFFSET 10h (Func 2 Only) .......................................................... 81
7.3.12
SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ......................................................................... 81
7.3.13
SUBSYSTEM ID REGISTER – OFFSET 2Ch ..................................................................................... 81
7.3.14
CAPABILITIES POINTER REGISTER – OFFSET 34h...................................................................... 81
7.3.15
INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................. 82
7.3.16
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 82
7.3.17
SERIAL BUS RELEASE NUMBER REGISTER – OFFSET 60h (Func 2 Only) ................................. 82
7.3.18
FRAME LENGTH ADJUSTMENT REGISTER – OFFSET 60h (Func 2 Only) .................................. 82
7.3.19
PORT WAKE CAPABILITY REGISTER – OFFSET 60h (Func 2 Only) ............................................ 82
7.3.20
MISCELLANEOUS REGISTER – OFFSET 68h (Func 2 Only) ......................................................... 83
7.3.21
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ........................................... 83
7.3.22
NEXT ITEM POINTER REGISTER – OFFSET 80h ........................................................................... 83
7.3.23
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ............................................. 84
7.3.24
POWER MANAGEMENT DATA REGISTER – OFFSET 84h ............................................................ 84
7.3.25
PPB SUPPORT EXTENSIONS – OFFSET 84h .................................................................................. 85
7.3.26
PM DATA REGISTER – OFFSET 84h ............................................................................................... 85
7.3.27
MESSAGE SIGNALED INTERRUPT (MSI) Capability ID Register 8Ch .......................................... 85
7.3.28
MESSAGE SIGNALED INTERRUPT (MSI) NEXT ITEM POINTER 8Ch ......................................... 85
7.3.29
MESSAGE CONTROL REGISTER – OFFSET 8Ch ........................................................................... 85
7.3.30
MESSAGE ADDRESS REGISTER – OFFSET 90h............................................................................. 85
7.3.31
MESSAGE DATA REGISTER – OFFSET 94h .................................................................................... 86
7.3.32
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 1) – OFFSET A0h ............................. 86
7.3.33
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 2) – OFFSET A4h ............................. 86
7.3.34
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 3) – OFFSET A8h ............................. 87
7.3.35
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 4) – OFFSET ACh ............................ 87
7.3.36
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ............................................................ 88
7.3.37
NEXT ITEM POINTER REGISTER – OFFSET E0h .......................................................................... 88
7.3.38
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h .............................................................. 88
7.3.39
DEVICE CAPABILITIES REGISTER – OFFSET E4h ....................................................................... 88
7.3.40
DEVICE CONTROL REGISTER – OFFSET E8h............................................................................... 89
7.3.41
DEVICE STATUS REGISTER – OFFSET E8h ................................................................................... 90
7.3.42
LINK CAPABILITIES REGISTER – OFFSET ECh ............................................................................ 90
7.3.43
LINK CONTROL REGISTER – OFFSET F0h .................................................................................... 91
7.3.44
LINK STATUS REGISTER – OFFSET F0h ........................................................................................ 91
8
CLOCK SCHEME ............................................................................................................................................. 93
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PI7C9X440SL
8.1
8.2
9
PCI EXPRESS INTERFACE ...................................................................................................................... 93
USB INTERFACE ...................................................................................................................................... 93
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .................................................................................... 94
9.1
9.2
9.3
9.4
9.5
INSTRUCTION REGISTER ...................................................................................................................... 94
BYPASS REGISTER ................................................................................................................................. 94
DEVICE ID REGISTER ............................................................................................................................. 94
BOUNDARY SCAN REGISTER ............................................................................................................... 95
JTAG BOUNDARY SCAN REGISTER ORDER ...................................................................................... 95
10 POWER MANAGEMENT ................................................................................................................................ 97
10.1
10.2
PCI EXPRESS POWER STATES .............................................................................................................. 97
USB POWER STATES .............................................................................................................................. 97
11 ELECTRICAL AND TIMING SPECIFICATIONS ....................................................................................... 98
11.1
11.2
11.3
11.4
11.5
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 98
OPERATING AMBIENT TEMPERATURE ......................................................................................................... 98
POWER CONSUMPTION ......................................................................................................................... 98
DC SPECIFICATIONS .............................................................................................................................. 98
AC SPECIFICATIONS .............................................................................................................................. 99
12 PACKAGE INFORMATION.......................................................................................................................... 101
13 ORDERING INFORMATION........................................................................................................................ 102
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
TABLE OF FIGURES
FIGURE 2-1 PI7C9X440SL TOPOLOGY ....................................................................................................................... 12
FIGURE 5-1 DRIVER OUTPUT WAVEFORM ................................................................................................................... 19
FIGURE 6-1 SMBUS ARCHITECTURE IMPLEMENTATION ON PI7C9X440SL ................................................................ 41
FIGURE 12-1 PACKAGE OUTLINE DRAWING .............................................................................................................. 101
FIGURE 12-2 PART MARKING .................................................................................................................................... 101
LIST OF TABLES
TABLE 5-1 RECEIVER DETECTION THRESHOLD SETTINGS ........................................................................................... 18
TABLE 5-2 RECEIVER SIGNAL DETECT THRESHOLD .................................................................................................... 18
TABLE 5-3 TRANSMITTER SWING SETTINGS ................................................................................................................ 19
TABLE 5-4 DRIVE AMPLITUDE BASE LEVEL REGISTERS ............................................................................................. 20
TABLE 5-5 DRIVE AMPLITUDE BASE LEVEL SETTINGS................................................................................................ 20
TABLE 5-6 DRIVE DE-EMPHASIS BASE LEVEL REGISTER ............................................................................................ 20
TABLE 5-7 DRIVE DE-EMPHASIS BASE LEVEL SETTINGS ............................................................................................ 20
TABLE 5-8 SUMMARY OF PCI EXPRESS ORDERING RULES .......................................................................................... 23
TABLE 5-9 HS DRIVER TIMING CONTROL FOR PMOS ................................................................................................. 26
TABLE 5-10 HS DRIVER TIMING CONTROL FOR NMOS .............................................................................................. 26
TABLE 5-11 HS DRIVER AMPLITUDE CONTROL .......................................................................................................... 26
TABLE 5-12 HS DRIVER SLOPE CONTROL ................................................................................................................... 27
TABLE 5-13 REFERENCE VOLTAGE FOR DISCONNECT CIRCUIT ................................................................................... 27
TABLE 5-14 REFERENCE VOLTAGE FOR SQUELCH CIRCUIT......................................................................................... 27
TABLE 5-15 REFERENCE VOLTAGE FOR CALIBRATION CIRCUIT.................................................................................. 28
TABLE 5-16 CHARGE PUMP CURRENT CONTROL......................................................................................................... 28
TABLE 5-17 FS RISE/FALL T IME CONTROL ................................................................................................................. 28
TABLE 5-18 LS RISE/FALL T IME CONTROL ................................................................................................................. 29
TABLE 5-19 HS DRIVER PRE-EMPHASIS CONTROL ..................................................................................................... 29
TABLE 6-1 SMBUS ADDRESS PIN CONFIGURATION .................................................................................................... 41
TABLE 7-1 TABLE ENTRY SIZE IN 4 BITS ..................................................................................................................... 75
TABLE 8-1 INPUT CLOCK REQUIREMENTS FOR PCI EXPRESS INTERFACE .................................................................... 93
TABLE 8-2 INPUT CLOCK REQUIREMENTS FOR USB INTERFACE ................................................................................. 93
TABLE 9-1 INSTRUCTION REGISTER CODES ................................................................................................................. 94
TABLE 9-2 JTAG DEVICE ID REGISTER ...................................................................................................................... 94
TABLE 9-3 JTAG BOUNDARY SCAN REGISTER DEFINITION ........................................................................................ 95
TABLE 11-1 ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 98
TABLE 11-2 OPERATING AMBIENT TEMPERATURE ...................................................................................................... 98
TABLE 11-3 PI7C9X440SL POWER DISSIPATION ........................................................................................................ 98
TABLE 11-4 DC ELECTRICAL CHARACTERISTICS ........................................................................................................ 98
TABLE 11-5 DC ELECTRICAL CHARACTERISTICS FOR DIGITAL I/O ............................................................................. 99
TABLE 11-6 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT CHARACTERISTICS ................... 99
TABLE 11-7 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT CHARACTERISTICS ............................. 99
TABLE 11-8 USB INTERFACE CHARACTERISTICS ...................................................................................................... 100
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
1 Features
General Features
PCI Express to four USB 2.0 host controller ports
Strapped pins configurable with optional EEPROM or SMBus
SMBus interface support
Low Power Dissipation at 432 mW typical in L0 normal mode
Industrial Temperature Range -40oC to 85oC
128-pin LQFP 14mm x 14mm package
Industrial Compliance
Compliant with PCI Express Base Specification Revision 1.1
Compliant with PCI Express CEM Specification Revision 1.1
Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
Compliant with Advanced Configuration Power Interface (ACPI) Specification
Compliant with Universal Serial Bus Specification Revision 2.0 (data rate 1.5/12/480 Mbps)
Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
Compliant with System Management (SM) Bus, Version 1.0
PCI Express Interface
One x1 PCIe 1.1 port
Advanced Power Saving
- Link Power Management
- Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power state
- Active state power management for L0s and L1 state
- PME# support in L2 state
- Device State Power Management
- Supports D0, D3Hot and D3Cold device power state
- 3.3V Aux Power support in D3Cold power state
Supports up to 256-byte maximum payload size
Programmable driver current and de-emphasis level at the PCIe port
Reliability, Availability and Serviceability
USB Host Controller
USB Root Hub with 4 downstream facing ports shared by OHCI and EHCI host controllers
All USB downstream facing ports are able to handle high-speed (480 Mbps), full-speed (12 Mbps) and lowspeed (1.5 Mbps) transactions
PCI Express to USB bridging through PCI Express multi-functional core of PI7C9X440SL
Two OHCI host controllers for full-speed and low-speed and one EHCI host controller for high-speed
Programmable PHY parameters for each USB port
Operational registers of the USB Host Controller are directly mapped to PCI memory space
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
2 GENERAL DESCRIPTION
The PI7C9X440SL PCI Express-to-USB 2.0 Host Controller complies with PCI Express Base Specification
Revision 1.1, Open Host Controller Interface Specification Revision 1.0a, and Enhanced Host Controller Interface
Specification Revision 1.0. The high-performance architecture of the PI7C9X440SL is capable of bridging from one
PCIe x1 upstream port to four USB 2.0 ports. The device allows simultaneous access to multiple USB devices from
system host processor, and therefore expands the connectivity domain of the system. The USB ports of the device
can support all the available speeds including High-Speed (HS), Full-Speed (FS) and Low-Speed (LS). The PCIeto-USB2.0 bridge function of the device is implemented by two types of host controllers, the Enhanced Host
Controller Interface (EHCI) and Open Host Controller Interface (OHCI). There are one EHCI controller and two
OHCI controllers residing in PI7C9X440SL. The EHCI controller handles High-Speed USB transaction while the
OHCI controllers handle Full-Speed or Low-Speed USB transaction.
From the perspective of system model, the device contains two cascaded virtual PCI-to-PCI bridges, where the
upstream-port bridge sits upon the downstream-port bridge over a virtual PCI Bus, and three USB controllers are
attached to the downstream PCI Express port. During enumeration, the internal PCIe upstream and downstream
ports are given unique bus numbers, device number and function number that are logically formed as a destination
ID. The USB host controllers are viewed as a multi-functional device by the bootstrapping procedures. The EHCI
controller is assigned function #2 and the two OHCI controllers are assigned function #0 and #1, and all the
controllers are assigned the same device number. The memory-map and IO address ranges are exclusively allocated
to each port and USB host controller. After the software enumeration is completed, the transaction packets are
routed to the dedicated PCIe port or USB host controller based on the embedded contents of address or destination
ID.
For the PCIe-to-USB bridging function, the four USB ports are first served in a host-centric manner by EHCI or
OHCI host controllers, which then interface with the PCIe port to transfer packets to/from the upstream port through
switch fabric. At High-Speed mode, all the USB ports are handled by ECHI controller with function #2. At FullSpeed and Low-Speed modes, USB port #1 and port #2 are handled by OHCI controller with function #0 and USB
port #3 and port #4 are handled by OHCI controller with function #1. The Root Hub resides between the USB ports
and host controllers and handles connection sessions from the host controller cores to USB ports.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
PCIe x1 Link
x1 PCIe
Upstream Port
Virtual PCI Bus
PCIe Downstream Port
EHCI Host
Controller
OHCI Host
Controller
OHCI Host
Controller
Root Hub
USB Port 1
USB Port 2
USB Port 3
USB Port 4
Figure 2-1 PI7C9X440SL Topology
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
3 PIN DEFINITION
3.1
SIGNAL TYPES
TYPE OF SIGNAL
I
O
P
DESCRIPTION
Input
Output
Power
“_L” in signal name indicates Active LOW signal
3.2
PCI EXPRESS INTERFACE SIGNALS
NAME
REFCLKP
REFCLKN
3.3
PIN
51, 52
TYPE
I
PERP
PERN
PETP
PETN
PERST_L
37
38
41
42
104
I
I
O
O
I
REXT
57
I
REXT_GND
56
I
DESCRIPTION
Reference Clock Input Pairs: Connect to external 100MHz
differential clock.
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled interface so that only the AC information of
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in the AC-coupling.
PCI Express Data Serial Input Pair: Differential data receive
signals.
PCI Express Data Serial Output Pairs: Differential data transmit
signals.
System Reset (Active LOW): When PERST_L is asserted, the
internal states of whole chip except sticky logics are initialized.
External Reference Resistor: Connect an external resistor (1.43K
Ohm +/- 1%) to REXT_GND to provide a reference to both the bias
currents and impedance calibration circuitry.
External Reference Resistor Ground: Connect to an external resistor
to REXT.
USB INTERFACE SIGNALS
NAME
DP [4:1]
PIN
85, 93, 117, 124
TYPE
I/O
DM [4:1]
84, 92, 116, 123
I/O
OCI [4:1]
7, 6, 5, 4
I
POE [4:1]
13, 12, 11, 10
O
RREF[4:1]
87, 95, 119, 126
I/O
XI
XO
PME_L
102
103
113
I
O
O
LEG_EMU_EN
20
O
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
USB D+ Signal: USB D+ analog signal covering HS/FS/LS. DP [x] is
correspondent to Portx, where x=1,2,3,4.
USB D- Signal: USB D- analog signal covering HS/FS/LS. DP [x] is
correspondent to Portx, where x=1,2,3,4.
Over Current Input (Active LOW): These signals are asserted low to
indicate that an over-current condition has occurred. OCI [x] is
correspondent to Portx, where x=1,2,3,4.
Power Output Enable (Active LOW): Power supply control output
for USB Root Hub Port. When these signals are asserted low, they
enable an external power switch to turn on the power supply. POE [x]
is correspondent to Portx, where x=1,2,3,4.
External Resistor Connection for Current Reference: This analog
signal is the connection to the external resistor. It sets the reference
current. No external capacitor should be connected. The recommended
value for the resistor is 6.04 kohm and accuracy of +/- 1%.
Crystal Oscillator Input: A 12MHz crystal oscillator is required.
Crystal Oscillator Output
Power Management Event (Low Active): This signal is asserted
whenever the USB power state is resumed to Operational State from
Suspend State.
OHCI Legacy Emulation Enable: This signal indicates that Legacy
emulation support is enabled for the OHCI controller, and the
application can read or write to I/O ports 60h/64h when I/O access for
the OHCI controller is enabled. See section 5.2.1.1 for details of the
Legacy Mode.
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PI7C9X440SL
3.4
NAME
SMI_O
PIN
14
TYPE
O
IO_HIT_I
3
I
IRQ1_I
16
I
IRQ1_O
18
O
IRQ12_I
17
I
IRQ12_O
19
O
DESCRIPTION
System Management Interrupt: This signal is used to indicate that an
interrupt condition has occurred. The signal is used only when OHCI
Legacy support is enabled. See section 5.2.1.1 for details of the Legacy
Mode.
Application I/O Hit: This signal indicates a PCI I/O cycle strobe. See
section 5.2.1.1 for details of the Legacy Mode.
External Interrupt 1: This external keyboard controller interrupt 1
causes an emulation interrupt. See section 5.2.1.1 for details of the
Legacy Mode.
OHCI Legacy IRQ1: This signal is asserted when an emulation
interrupt condition exists and OutputFull, IRQEn, and AuxOutputFull
are asserted. See section 5.2.1.1 for details of the Legacy Mode.
External Interrupt 12: This external keyboard controller interrupt 12
causes an emulation interrupt. See section 5.2.1.1 for details of the
Legacy Mode.
OHCI Legacy IRQ12: This signal is asserted when an emulation
interrupt condition exists, OutputFull and IRQEn are asserted, and
AuxOutputFull is de-asserted. See section 5.2.1.1 for details of the
Legacy Mode.
JTAG BOUNDARY SCAN SIGNALS
NAME
TCK
PIN
26
TMS
27
I
TDO
25
O
TDI
28
I
TRST_L
29
I
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
I
DESCRIPTION
Test Clock: TCK is the test clock to synchronize the state information
and data during boundary scan operation. When JTAG boundary scan
function is not implemented, this pin should be left open (NC).
Test Mode Select: TMS controls the state of the Test Access Port
(TAP) controller. When JTAG boundary scan function is not
implemented, this pin should be pulled low through a 5.1K pull-down
resistor.
Test Data Output: TDO is the test data output and connects to the
end of the JTAG scan chain. When JTAG boundary scan function is
not implemented, this pin should be left open (NC).
Test Data Input: TDI is the test data input and connects to the
beginning of the JTAG scan chain. It allows the test instructions and
data to be serially shifted into the Test Access Port. When JTAG
boundary scan function is not implemented, this pin should be left open
(NC).
Test Reset (Active LOW): TRST_L is the test reset to initialize the
Test Access Port (TAP) controller. When JTAG boundary scan
function is not implemented, this pin should be pulled low through a
5.1K pull-down resistor.
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PI7C9X440SL
3.5
3.6
MISCELLANEOUS SIGNALS
NAME
EECLK
EEPD
PIN
99
98
TYPE
O
I/O
SMBCLK
SMBDATA
SCAN_EN
21
64
15
I
I/O
I/O
GPIO[7:0]
76, 75, 74, 73,
72, 71, 70, 69
I/O
MAIN_DETECT
24
I
TEST1/3/4/5/6
1, 65, 77, 114,
66
I
NC
2, 30, 31, 32, 43,
44, 47, 48, 55,
58, 59, 62, 63,
78, 79, 80, 88,
107, 108
DESCRIPTION
EEPROM Clock: Clock signal to the EEPROM interface.
EEPROM Data: Bi-directional serial data interface to and from the
EEPROM. The pin is set to 1 by default.
SMBus Clock: System management Bus Clock.
SMBus Data: Bi-Directional System Management Bus Data.
Full-Scan Enable Control: For normal operation, SCAN_EN is an
output with a value of “0”. SCAN_EN becomes an input during
manufacturing testing.
General Purpose input and output: These eight general-purpose pins
are programmed as either input-only or bi-directional pins by writing
the GPIO output enable control register.
Main Power Detect: MAIN_DETECT should be tied to the Aux
Power of the system through a 4.7K ohm pull-up resistor if the USB
remote wakeup function is to be supported. Otherwise, this signal
should be tied to the Main Power of the system through a 4.7K ohm
pull-up resistor.
Test Pins: For testing purposes only. TEST1 and TEST4 should be tied
to ground, and TEST3, TEST5, and TEST6 should be tied to high for
normal operation. The suggested value for the pull-up and pull-down
resistor is 5.1K.
Not Connected: These pins can be left floating.
POWER PINS
NAME
VDDC
VDDR
VDDA
AVDD
AVDDH
VSS
PIN
22, 35, 81, 100,
109, 111
8, 33, 67, 105,
112
83, 90, 91, 97,
115, 121, 122,
128
40, 46, 49, 60,
54
TYPE
P
DESCRIPTION
VDDC Supply (1.0V): Used as digital core power pins.
P
VDDR Supply (3.3V): Used as digital I/O power pins.
P
VDDA Supply (3.3V): Used as USB analog power pins.
P
P
9, 23, 34, 36, 39,
45, 50, 53, 61,
68, 82, 86, 89,
94, 96, 101, 106,
110, 118, 120,
125, 127, 129
P
AVDD Supply (1.0V): Used as PCI Express analog power pins.
AVDDH Supply (3.3V): Used as PCI Express analog high voltage
power pins.
VSS Ground: Used as ground pins.
PI7C9X440SL
Document Number DS40394 Rev 3-2
GND: The central thermal pad underneath the package should be
connected to ground.
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PI7C9X440SL
4 PIN ASSIGNMENTS
4.1
PIN LIST of 128-PIN LQFP
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NAME
TEST1
NC
IO_HIT_I
OCI[1]
OCI[2]
OCI[3]
OCI[4]
VDDR
VSS
POE[1]
POE[2]
POE[3]
POE[4]
SMI_O
SCAN_EN
IRQ1_I
IRQ12_I
IRQ1_O
IRQ12_O
LEG_EMU_EN
SMBCLK
VDDC
VSS
MAIN_DETECT
TDO
TCK
TMS
TDI
TRST_L
NC
NC
NC
PI7C9X440SL
Document Number DS40394 Rev 3-2
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NAME
VDDR
VSS
VDDC
VSS
PERP
PERN
VSS
AVDD
PETP
PETN
NC
NC
VSS
AVDD
NC
NC
AVDD
VSS
REFCLKP
REFCLKN
VSS
AVDDH
NC
REXT_GND
REXT
NC
NC
AVDD
VSS
NC
NC
SMBDATA
PIN
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
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NAME
TEST3
TEST6
VDDR
VSS
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
TEST4
NC
NC
NC
VDDC
VSS
VDDA
DM[4]
DP[4]
VSS
RREF[4]
NC
VSS
VDDA
VDDA
DM[3]
DP[3]
VSS
RREF[3]
VSS
PIN
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
NAME
VDDA
EEPD
EECLK
VDDC
VSS
XI
XO
PERST_L
VDDR
VSS
NC
NC
VDDC
VSS
VDDC
VDDR
PME_L
TEST5
VDDA
DM[2]
DP[2]
VSS
RREF[2]
VSS
VDDA
VDDA
DM[1]
DP[1]
VSS
RREF[1]
VSS
VDDA
E_PAD
January 2018
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PI7C9X440SL
5 FUNCTIONAL DESCRIPTION
The PCI Express-to-USB Bridge contains two virtual PCI-to-PCI Bridges (VPPB) connected by a virtual PCI bus.
One of the VPPB is implemented as the upstream port, and the other VPPB is implemented as the downstream port
to connect to the USB Host Controllers (OHCI and EHCI). The upstream PCIe port encompasses complete PCIe
architecture with the physical, data link, and transaction layers. One VPPB represents a single PCIe Port, which
handles the transmission and reception of PCIe packets. The USB Host Controller is able to handle operational
registers and descriptor link list, which provide a communication channel for Host Controller Driver (HCD) to
initiate USB packet transactions to and from USB devices.
The operation of the PCIe to USB bridging functions are depicted as follows. The HCD first prepares the data
structure of the USB commands or data. Then, the host controllers are notified to fetch the commands or data,
which are eventually converted from PCIe into USB packet format. Depending on the direction of transfer, the host
controller moves and converts the packet to/from USB devices. When the transfer is complete, an interrupt message
will notify the HCD to process the data stored in the system memory the descriptor points to.
5.1
PCI EXPRESS INTERFACE FUNCTIONALITIES
5.1.1 PHYSICAL LAYER CIRCUIT
The physical layer circuit design is based on the PHY Interface for PCI Express Architecture (PIPE). It contains
Physical Media Attachment (PMA) and Physical Coding Sub-layer (PCS) blocks. PMA includes Serializer/
Deserializer (SERDES), PLL1, Clock Recovery module, receiver detection circuits, beacon transmitter, electrical
idle detector, and input/output buffers. PCS consists of framer, 8B/10B encoder/decoder, receiver elastic buffer, and
PIPE PHY control/status circuitries. To provide the flexibility for port configuration, each lane has its own control
and status signals for MAC to access individually. In addition, a pair of PRBS generator and checker is included for
PHY built-in self test. The main functions of physical layer circuits include the conversion between serial-link and
parallel bus, provision of clock source for the interface, resolving clock difference in receiver end, and detection of
physical layer errors.
In order to meet the needs of different application, the drive amplitude, de-emphasis and equalization of each
transmitting channels can be adjusted using EEPROM individually. De-emphasis of -3.5 db is implemented by the
transmitters when full swing signaling is used, while an offset can be individually applied to each channel.
1
Multiple lanes could share the PLL.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
5.1.1.1 RECEIVER DETECTION
The physical layer circuits implement receiver detection, which detects the presence of an attached 50 ohm to
ground termination as per PCI Express Specification. The detect circuits determine if the voltage levels of the
receiver have crossed the internal threshold after a configurable time determined by the Receiver Detection
Threshold field in the Physical Layer Control Register 2 (offset BCh, bit[6:4]) as listed in Table 5-1.
Table 5-1 Receiver Detection Threshold Settings
Receiver Detection
Threshold
000
001
010
011
100
101
110
111
Threshold
1.0 us
2.0 us
4.0 us (Recommended)
5.0 us
7.0 us
Reserved
Reserved
Reserved
5.1.1.2 RECEIVER SIGNAL DETECTION
Receiver signal idling is detected with levels above a programmable threshold specified by Receiver Signal Detect
field in the Physical Layer Control Register 2 (Offset BCh, bit[22:21]) as listed in Table 5-2, and can be configured
on a per-port basis via EEPROM settings.
Table 5-2 Receiver Signal Detect Threshold
Receiver Signal Detect
00
01 (Recommended)
10
11
Min (mV ppd)
50
65
75
120
Max (mV ppd)
150
175
200
240
5.1.1.3 RECEIVER EQUALIZATION
The receiver implements programmable equalizer via the Receiver Equalization field in the Physical Layer Control
Register 2 (Offset BCh, bit[25:22]). There are 16 possible settings. It is recommended that customers determine the
optimal equalization settings based on their environment to and their application.
5.1.1.4 TRANSMITTER SWING
The PCI Express transmitters support implementations of both full voltage swing and half (low) voltage swing. In
full swing signaling mode, the transmitters implement de-emphasis, while in half swing mode, the transmitters do
not. The Transmitter Swing field in the Physical Layer Control Register 2 (offset BCh, Bit[30]) is used for the
selection of full swing signaling or half swing signaling.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
Table 5-3 Transmitter Swing Settings
Transmitter Swing
0
1
Mode
Full Voltage Swing
Half Voltage Swing
De-emphasis
Implemented
Not implemented
5.1.1.5 DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS
Depending on the operation condition (voltage swing and de-emphasis condition), one of the Drive Amplitude Base
Level fields in the Physical Layer Control Register 0 (offset B4h) and one of the Drive De-Emphasis Base Level
fields in the Physical Layer Control Register 1 (offset B8h) are active for configuration of the amplitude and
de-emphasis.
In addition, optional offset values can be added to the drive amplitude and drive de-emphasis on a per-port basis via
EEPROM settings (EEPROM offset 70h, bit[3:0]). The final drive amplitude and drive de-emphasis are the
summation of the base level value and the offset value. The offset value for drive amplitude is 25 mV pd, and 6.25
mV pd for drive de-emphasis.
The driver output waveform is the synthesis of amplitude and de-emphasis as shown in Figure 5-1. The driver
amplitude without de-emphasis is specified as a peak differential voltage level (mVpd), and the driver de-emphasis
modifies the driver amplitude.
Amplitude + De-Emphasis
Amplitude – De-Emphasis
1
1
1
1
0
0
0
0
- (Amplitude) + De-Emphasis
- (Amplitude) – De-Emphasis
Input digital wave form
Output analog waveform
Figure 5-1 Driver Output Waveform
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5.1.1.6 DRIVE AMPLITUDE
Only one of the Drive Amplitude Level field in the Physical Control Register 0 (offset B4h, bit[20:16], bit[25:21]
and bit[30:26]) listed in Table 5-4 is active depending on the de-emphasis and swing condition. The settings and the
corresponding values of the amplitude level are listed in Table 5-5
Table 5-4 Drive Amplitude Base Level Registers
Active Register
Drive Amplitude Level (3P5
Nom)
De-Emphasis Condition
-3.5 db
Swing Condition
Full
Table 5-5 Drive Amplitude Base Level Settings
Setting
Amplitude
(mV pd)
0
25
50
75
100
125
150
Setting
Amplitude
(mV pd)
175
200
225
250
275
300
325
Setting
Amplitude
(mV pd)
350
375
400
425
450
475
Reserved
00000
00111
01110
00001
01000
01111
00010
01001
10000
00011
01010
10001
00100
01011
10010
00101
01100
10011
00110
01101
Others
Note:
1. Nominal levels. Actual levels will vary with temperature, voltage and board effects.
2. The maximum nominal amplitude of the output driver is 475 mV pd. Combined values of driver amplitude and de-emphasis greater
than 475 mV pd should be avoided.
5.1.1.7 DRIVE DE-EMPHASIS
The Drive De-Emphasis Level field in the Physical Control Register 1 (Offset B8h, bit[20:16]) listed in Table 5-6
controls the de-emphasis base level. The settings and the corresponding values of the de-emphasis level are listed in
Table 5-7
Table 5-6 Drive De-Emphasis Base Level Register
Register
Drive De-Emphasis Level
De-Emphasis Condition
-3.5 db
Table 5-7 Drive De-Emphasis Base Level Settings
Setting
De-Emphasis
(mV pd)
0.0
6.25
12.5
18.75
25.0
31.25
37.5
43.75
50.0
56.25
62.5
Setting
De-Emphasis
(mV pd)
68.75
75.0
81.25
87.5
93.75
100.0
106.25
112.5
118.75
125.0
131.25
Setting
De-Emphasis
(mV pd)
137.5
143.75
150.0
156.25
162.5
168.75
175.0
181.25
187.5
194.75
-
00000
01011
10110
00001
01100
10111
00010
01101
11000
00011
01110
11001
00100
01111
11010
00101
10000
11011
00110
10001
11100
00111
10010
11101
01000
10011
11110
01001
10100
11111
01010
10101
Note:
1. Nominal levels. Actual levels will vary with temperature, voltage and board effects.
2. The maximum nominal amplitude of the output driver is 475 mV pd. Combined values of driver amplitude and de-emphasis greater
than 475 mV pd should be avoided.
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5.1.1.8 TRANSMITTER ELECTRICAL IDLE LATENCY
After the last character of the PCI Express transmission, the output current is reduced, and a differential voltage of
less than 20 mV with common mode of VTX-CM-DC is established within 20 UI. This delay time is programmable
via Transmitter PHY Latency field in the Physical Layer Control Register 2 (Offset BCh, bit[3:0]).
5.1.2 DATA LINK LAYER (DLL)
The Data Link Layer (DLL) provides a reliable data transmission between two PCI Express points. An ACK/NACK
protocol is employed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is
protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calculation to determine if the
incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter would issue a NACK
data link layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be
sent out to acknowledge on reception of a good TLP.
In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding ACK/NACK
DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller
than that carried in the ACK would be flushed out from the buffer. If a NACK is received or no ACK/NACK is
returned from the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is
triggered to re-transmit the corresponding packet that receives NACK or time-out and any other TLP transmitted
after that packet.
Meanwhile, the DLL is also responsible for the initialization, updating, and monitoring of the flow-control credit.
All of the flow control information is carried by DLLP to the other end of the link. Unlike TLP, DLLP is guarded
by 16-bit CRC to detect if data corruption occurs.
In addition, the Media Access Control (MAC) block, which is consisted of LTSSM, multiple lanes deskew,
scrambler/de-scrambler, clock correction from inserting skip order-set, and PIPE-related control/status circuits, is
implemented to interface physical layer with data link layer.
5.1.3 TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION)
The receiving end of the transaction layer performs header information retrieval and TC/VC mapping, and it
validates the correctness of the transaction type and format. If the TLP is found to contain illegal header or the
indicated packet length mismatches with the actual packet length, then a Malformed TLP is reported as an error
associated with the receiving port. To ensure end-to-end data integrity, a 32-bit ECRC is checked against the TLP at
the receiver if the digest bit is set in header.
5.1.4 ROUTING
The transaction layer implements three types of routing protocols: ID-based, address-based, and implicit routing.
For configuration reads, configuration writes, transaction completion, and user-defined messages, the packets are
routed by their destination ID constituted of bus number, device number, and function number. Address routing is
employed to forward I/O or memory transactions to the destination port, which is located within the address range
indicated by the address field carried in the packet header. The packet header indicates the packet types including
memory read, memory write, IO read, IO write, Message Signaling Interrupt (MSI) and user-defined message.
Implicit routing is mainly used to forward system message transactions such as virtual interrupt line, power
management, and so on. The message type embedded in the packet header determines the routing mechanism.
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If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or
targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI
protocol.
5.1.5 TC/VC MAPPING
The 3-bit TC field defined in the header identifies the traffic class of the incoming packets. To enable the
differential service, a TC/VC mapping table at destination port that is pre-programmed by system software or
EEPROM pre-load is utilized to cast the TC labeled packets into the desired virtual channel. Note that all the traffic
classes are mapped to VC0, since only VC0 is available on the interface. After the TC/VC mapping, the receive
block dispatches the incoming request, completion, or data into the VC0 queues.
5.1.6 QUEUE
In PCI Express, it defines six different packet types to represent request, completion, and data. They are respectively
Posted Request Header (PH), Posted Request Data payload (PD), Non-Posted Request Header (NPH), Non-Posted
Data Payload (NPD), Completion Header (CPLH) and Completion Data payload (CPLD). Each packet with
different type would be put into a separate queue in order to facilitate the following ordering processor. Since NPD
usually contains one DW, it can be merged with the corresponding NPH into a common queue named NPHD.
5.1.6.1 PH
PH queue provides TLP header spaces for posted memory writes and various message request headers. Each header
space occupies sixteen bytes to accommodate 3 DW or 4 DW headers.
5.1.6.2 PD
PD queue is used for storing posted request data. If the received TLP is of the posted request type and is determined
to have payload coming with the header, the payload data would be put into PD queue.
5.1.6.3 NPHD
NPHD queue provides TLP header spaces for non-posted request packets, which include memory read, IO read, IO
write, configuration read, and configuration write. Each header space takes twenty bytes to accommodate a 3-DW
header, s 4-DW header, s 3-WD header with 1-DW data, and a 4-DW header with 1-DW data.
5.1.6.4 CPLH
CPLH queue provides TLP header space for completion packets. Each header space takes twelve bytes to
accommodate a 3-DW header. Please note that there is no 4-DW completion headers.
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5.1.6.5 CPLD
CPLD queue is used for storing completion data. If the received TLP is of the completion type and is determined to
have payload coming with the header, the payload data would be put into CPLD queue.
5.1.7 TRANSACTION ORDERING
Within a VPPB, a set of ordering rules is defined to regulate the transactions on the PCI Express interface including
Memory, IO, Configuration and Messages, in order to avoid deadlocks and to support the Producer-Consumer
model. The ordering rules defined in table 5-4 apply within a single Traffic Class (TC). There is no ordering
requirement among transactions within different TC labels.
Table 5-8 Summary of PCI Express Ordering Rules
Row Pass Column
Posted Request
Read Request
Non-posted Write Request
Read Completion
Non-Posted Write
Completion
Posted
Request
Yes/No1
No2
No2
Yes/No3
Yes4
Read
Request
Yes5
Yes
Yes
Yes
Yes
Non-posted Write
Request
Yes5
Yes
Yes
Yes
Yes
Read
Completion
Yes5
Yes
Yes
Yes
Yes
Non-posted Write
Completion
Yes5
Yes
Yes
Yes
Yes
1. When the Relaxed Ordering Attribute bit is cleared, the Posted Request transactions including memory write and
message request must complete on the egress bus of VPPB in the order in which they are received on the ingress
bus of VPPB. If the Relaxed Ordering Attribute bit is set, the Posted Request is permitted to pass over other Posted
Requests occurring before it.
2. A Read Request transmitting in the same direction as a previously queued Posted Request transaction must push
the posted write data ahead of it. The Posted Request transaction must complete on the egress bus before the Read
Request can be attempted on the egress bus. The Read transaction can go to the same location as the Posted data.
Therefore, if the Read transaction were to pass the Posted transaction, it would return stale data.
3. When the Relaxed Ordering Attribute bit is cleared, a Read completion must ‘‘pull’’ ahead of previously queued
posted data transmitting in the same direction. In this case, the read data transmits in the same direction as the
posted data, and the requestor of the read transaction is on the same side of the VPPB as the completer of the posted
transaction. The posted transaction must deliver to the completer before the read data is returned to the requestor. If
the Relaxed Ordering Attribute bit is set, then a read completion is permitted to pass a previously queued Memory
Write or Message Request.
4. Non-Posted Write Completions are permitted to pass a previous Memory Write or Message Request transaction.
Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship.
5. Posted Request transactions must be given opportunities to pass Non-posted Read and Write Requests as well as
Completions. Otherwise, deadlocks may occur when some older Bridges that do not support delayed transactions
are mixed with PCIe interface in the same system. A fairness algorithm is used to arbitrate between the Posted
Write queue and the Non-posted transaction queue.
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5.1.8 FLOW CONTROL
PCI Express employs Credit-Based Flow Control mechanism to make buffer utilization more efficient.
The transaction layer transmitter ensures that it does not transmit a TLP to an opposite receiver unless the receiver
has enough buffer space to accept the TLP. The transaction layer receiver has the responsibility to advertise the free
buffer space to an opposite transmitter to avoid packet stale. In this device, each port has separate queues for
different traffic types and the credits are on the fly sent to data link layer, which compares the current available
credits with the monitored one and reports the updated credit to the counterpart. If no new credit is acquired, the
credit reported is scheduled for every 30 us to prevent from link entering retrain. On the other hand, the receiver at
each egress port gets the usable credits from the opposite end in a link. It would broadcast them to all the other
ingress ports for gating the packet transmission.
5.1.9 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION)
The transmit portion of transaction layer performs the following functions. They are to construct the all types of
forwarded TLP generated from VC arbiter, respond with the completion packet when the local resource (i.e.
configuration register) is accessed and regenerate the message that terminated at receiver to RC if acts as an
upstream port.
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5.2
USB HOST CONTROLLER FUNCTIONALITIES
5.2.1 OHCI HOST CONTROLLER
The OHCI Host Controller (HC) is responsible for communications between Host Controller Driver (HCD)
software and USB Full Speed/Low Speed devices. The OHCI/HC and HCD exchange the information via
operational registers, bulk transfer descriptors, control transfer descriptors and Host Controller Communication
Area (HCCA), which are for interrupt and isochronous transfer types.
When communicating with operational registers, the OHCI/HC acts as a PCI target device to accept the commands
provided by HCD and reports the status requested by HCD. The operational register contains the pointers that
indicate the locations of HCCA and descriptors for bulk and control within the system memory. The HCD receives
the IO Request Packet (IRP) from USB driver software and prepares the data structure of Endpoint Descriptor (ED)
and Transfer Descriptor (TD) in the format of linked list in the system memory. After ED and TD are prepared, the
HC is notified and acts as a PCI master to fetch the ED and TD and move data between the USB devices and
memory area by following the instructions described in the descriptors.
An ED is comprised of the information including endpoint address, speed, data flow direction and maximum packet
size, etc. A TD contains the information of data toggle, buffer position in system memory, complete status code and
data buffer size. The EDs are linked together based on their transfer type, and each ED points to a list of TD queue
that is used to transfer the data or command associated with a specific endpoint.
5.2.1.1 OHCI LEGACY SUPPORT
The OHCI host controller implements legacy support for emulation of PS/2 mouse and/or keyboard in operating
systems, applications, and drivers that do not support USB functions. The emulation code translates the standard
USB compliant keyboard/mouse data and transfers the data to/from PS/2 compatible legacy keyboard interface at
I/O addresses 60h and 64h.
The legacy support interface is consisted of 7 hardware pins, LEG_EN, SMI_O, IO_HIT_I, IRQ_1_I, IRQ1_O,
IRQ12_I and IRQ12_O, and 4 operational registers, HceControl, HceInput, HceOutput and HceStatus (offset 100h,
104h, 108h and 10Ch). When EmulationEnable bit in HceControl register is set to 1, legacy emulation is enabled.
The host controller decodes accesses to I/O registers 60h and 64h, and generates IRQ1 and/or IRQ12 when
appropriate.
When legacy emulation is enabled, reads and writes of the I/O register 60h and 64h are captured in HceInput,
HceOutput, and HceStatus operational registers.
For details, refer to OpenHCI Specification 1.0, Appendix B.
5.2.2 EHCI HOST CONTROLLER
The EHCI Host Controller (HC) is responsible for communications between HC Driver software and USB High
Speed devices. Similar to OHCI/HC, the EHCI/HC and HCD exchange the information via operational registers as
well as data structure arranged in periodic schedule and asynchronous schedule traversals in the system memory.
The periodic schedule traversal is used for time-sensitive isochronous and interrupts transfer types while the
asynchronous schedule traversal is for less time-sensitive control and bulk transfer types. The handling of EHCI
data structure is similar to that in OHCI. However, EHCI data is more complicated due to micro-frame scheduling
and split transaction support. For isochronous and interrupt transactions, the data structure contains High Speed
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device isochronous transfer descriptors (iTD), Full Speed device split-transaction isochronous transfer descriptors
(siTD) and queue head structure queue element descriptors (qTD) for interrupt devices. For bulk and control
transactions, the HC utilizes the qTD to represent the asynchronous data transfer types for High Speed bulk and
control devices.
5.2.3 PHYSICAL LAYER CIRCUIT
The USB physical layer circuit design is based on USB 2.0 Specification. The design contains PLL, bias current
generator, voltage bandgap, clock and data recovery, sync detector, NRZI Encoder / Decoder, Serializer /
De-Serializer, VBUS pulsing and discharge SRP circuit, and VBUS threshold comparators.
The USB physical layer parameters can be configured by setting the USB Physical Layer Control Register (Offset
A0h for port 1, A4h for port 2, A8h for port 3, and ACh for port 4) and EEPROM. Each of the USB port has its own
set of physical layer control parameters, and the configuration of the parameters is performed on a per-port basis.
5.2.3.1 HS DRIVER TIMING CONTROL
The timing of the HS Driver can be adjusted by changing the ratio of PMOS/NMOS strength. The PMOS Strength
for HS Driver Timing and the PMOS Strength for HS Driver Timing fields (bit[0] and bit[2:1]) in the USB Physical
Layer Control Register control the PMOS and NMOS strength respectively.
Table 5-9 HS Driver Timing Control for PMOS
PMOS Strength for HS Driver Timing
0 (default)
1
HS Driver Timing for PMOS
2x
8x
Table 5-10 HS Driver Timing Control for NMOS
NMOS Strength for HS Driver Timing
00 (default)
01
10
11
HS Driver Timing for NMOS
2x
4x
6x
8x
5.2.3.2 HS DRIVER AMPLITUDE
The amplitude of the HS driver current can be adjusted by setting the HS Driver Amplitude field (bit[4:3]) in the
USB Physical Layer Control Register.
Table 5-11 HS Driver Amplitude Control
HS Driver Amplitude
00 (default)
01
10
11
Note: I=17.78mA
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HS Driver Current
I
I + 2.5%
I + 5%
I + 7.5%
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5.2.3.3 HS DRIVER SLOPE CONTROL
The rise/fall times of the HS Driver can be adjusted by setting the HS Driver Slope Control field (bit[8:5]) in the
USB Physical Layer Control Register. The field controls the injection of additional charge and changes the RC
constant.
Table 5-12 HS Driver Slope Control
HS Driver Slope Control
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Rise/Fall Time
Actual values depend on boards,
ambient temperatures, etc.
5.2.3.4 REFERENCE VOLTAGE FOR DISCONNECT CIRCUIT
The reference voltage of the disconnect circuit can be adjusted by setting the Reference Voltage for Disconnect
Circuit field (bit[10:9]) in the USB Physical Layer Control Register.
Table 5-13 Reference Voltage for Disconnect Circuit
Reference Voltage for Disconnect Circuit
00
01
10 (default)
11
Vref575m
(46 + 2) / 100 * vbg
(46 + 3) / 100 * vbg
(46 + 4) / 100 * vbg
(46 + 5) / 100 * vbg
5.2.3.5 REFERENCE VOLTAGE FOR SQUELCH CIRCUIT
The reference voltage of the squelch circuit can be adjusted by setting the Reference Voltage for Squelch Circuit
field (bit[12:11]) in the USB Physical Layer Control Register.
Table 5-14 Reference Voltage for Squelch Circuit
Reference Voltage for Squelch Circuit
00
01
10 (default)
11
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Differential Reference Voltage
9 / 100 * vbg
(9 + 1) / 100 * vbg
(9 + 2) / 100 * vbg
(9 + 3) / 100 * vbg
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5.2.3.6 REFERENCE VOLTAGE FOR CALIBRATION CIRCUIT
The reference voltage of the calibration circuit can be adjusted by setting the Reference Voltage for Calibration
Circuit field (bit[15:13]) in the USB Physical Layer Control Register.
Table 5-15 Reference Voltage for Calibration Circuit
Reference Voltage for Calibration Circuit
000
001
010
011
100 (default)
101
110
111
Vref575mtune
(46) / 100 * vbg
(46 + 1) / 100 * vbg
(46 + 2) / 100 * vbg
(46 + 3) / 100 * vbg
(46 + 4) / 100 * vbg
(46 + 5) / 100 * vbg
(46 + 6) / 100 * vbg
(46 + 7) / 100 * vbg
5.2.3.7 CHARGE PUMP CURRENT FOR PLL
The charge pump current can be adjusted by setting the Charge Pump Current for PLL field (bit[17:16]) in the USB
Physical Layer Control Register.
Table 5-16 Charge Pump Current Control
Charge Pump Current for PLL
00 (default)
01
10
11
Note: Icp=40uA
Charge Pump Current (mA)
Icp
Icp * 0.5
Icp * 1.5
Icp * 2
5.2.3.8 FS RISE/FALL TIME CONTROL
The rise/fall times for FS can be adjusted by setting the FS Rise/Fall Time Control field (bit[19:18]) in the USB
Physical Layer Control Register.
Table 5-17 FS Rise/Fall Time Control
FS Rise/Fall Time Control
00
01 (default)
10
11
Rise/Fall Time
Normal FS rise time - 30%
Normal FS rise time
Normal FS rise time
Normal FS rise time +30%
5.2.3.9 LS RISE/FALL TIME CONTROL
The rise/fall times for LS can be adjusted by setting the LS Rise/Fall Time Control field (bit[21:20]) in the USB
Physical Layer Control Register.
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Table 5-18 LS Rise/Fall Time Control
LS Rise/Fall Time Control
00
01 (default)
10
11
5.2.3.10
Rise/Fall Time
Normal LS rise time - 30%
Normal LS rise time
Normal LS rise time
Normal LS rise time +30%
HS DRIVER PRE-EMPHASIS
The amplitude of the HS Driver can be adjusted by setting the HS Driver Pre-Emphasis field (bit[23:22]) in the
USB Physical Layer Control Register.
Table 5-19 HS Driver Pre-Emphasis Control
HS Driver Pre-Emphasis
00 (default)
01
10
11
Note: I=17.78mA
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HS Drive Current
I
I + 10%
I
I + 20%
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6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS
The EEPROM interface consists of two pins: EECLK (EEPROM clock output) and EEPD (EEPROM
bi-directional serial data). The Switch may control an ISSI IS24C04 or compatible parts using into 512x8 bits.
The EEPROM is used to initialize a number of registers before enumeration. This is accomplished after PRST# is
de-asserted, at which time the data from the EEPROM is loaded. The EEPROM interface is organized into a 16-bit
base, and the Switch supplies a 7-bit EEPROM word address. The Switch does not control the EEPROM address
input. It can only access the EEPROM with address input set to 0.
The System Management Bus interface consists of two pins: SMBCLK (System Management Bus Clock input) and
SMBDATA (System Management Bus Data input/ output).
6.1
EEPROM INTERFACE
6.1.1 AUTO MODE EERPOM ACCESS
The Swidge may access the EEPROM in a WORD format by utilizing the auto mode through a hardware sequencer.
The EEPROM start-control, address, and read/write commands can be accessed through the configuration register.
Before each access, the software should check the Autoload Status bit before issuing the next start.
6.1.2 EEPROM MODE AT RESET
During a reset, the Switch will automatically load the information/data from the EEPROM if the automatic load
condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload
initiates right after the reset.
During the autoload, the Bridge will read sequential words from the EEPROM and write to the appropriate registers.
Before the Bridge registers can be accessed through the host, the autoload condition should be verified by reading
bit [3] offset DCh (EEPROM Autoload Status). The host access is allowed only after the status of this bit is set to '0'
which indicates that the autoload initialization sequence is complete.
6.1.3 EEPROM SPACE ADDRESS MAP
15 – 8
7–0
EEPROM Signature (1516h)
Vendor ID for Port 0 ~ 3
Device ID for Port 0 ~ 3
Extended VC Count / Link Capability / Switch Mode Operation / Interrupt pin
for Port 1 ~ 2
Subsystem Vender ID for Port 0 ~ 3
Subsystem ID for Port 0 ~ 3
Misc Configuration for Port 0 ~ 3
Reserved
Revision ID for Port 0 ~ 3
FTS / RefClk ppm Difference / Scramble Control for Port 0
FTS / RefClk ppm Difference / Scramble Control for Port 1
FTS / RefClk ppm Difference / Scramble Control for Port 2
Reserved
Physical Layer Control 0 for Port 0 ~ 2
Physical Layer Control 1 for Port 0 ~ 2
Physical Layer Control 2, Bit[6:0] for Port 0 ~ 2
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BYTE OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
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15 – 8
7–0
Reserved
TC/VC Map for Port 0 (VC0)
Slot Clock / LPVC Count / Port Num, Port 0
TC/VC Map for Port 1(VC0)
Slot Implemented / Slot Clock / LPVC Count
/ Port Num, Port 1
TC/VC Map for Port 2 (VC0)
Slot Implemented / Slot Clock / LPVC Count
/ Port Num, Port 2
Reserved
Vendor ID for Func 0
Vendor ID for Func 1
Vendor ID for Func 2
Device Control for Func 0
Reserved
Slot Capability 0 for Port 1
Slot Capability 0 for Port 2
Reserved
Device ID for Func 0
Device ID for Func 1
Device ID for Func 2
Miscellaneous Register for Func 2
Reserved
Slot Capability 1 for Port 1
Slot Capability 1 for Port 2
Reserved
Revision ID / Programming Interface for Func 0
Revision ID / Programming Interface for Func 1
Revision ID / Programming Interface for Func 2
USB Physical Layer Control Register (USB Port 1), Bit[15:0]
PM Data for Port 0
PM Capability for Port 0
PM Data for Port 1
PM Capability for Port 1
PM Data for Port 2
PM Capability for Port 2
PM Data for Port 3
PM Capability for Port 3
Class Code for Func 0
Class Code for Func 1
Class Code for Func 2
USB Physical Layer Control Register (USB Port 2), Bit[15:0]
Power Budgeting Capability Register for Port 0
Power Budgeting Capability Register for Port 1
Power Budgeting Capability Register for Port 2
Reserved
Subsystem Vendor ID for Func 0
Subsystem Vendor ID for Func 1
Subsystem Vendor ID for Func 2
Device Control for Func 1
Physical Layer Control 2, Bit[30:16] for Port 0
Physical Layer Control 2, Bit[30:16] for Port 1
Physical Layer Control 2, Bit[30:16] for Port 2
Reserved
Subsystem ID for Func 0
Subsystem ID for Func 1
Subsystem ID for Func 2
Reserved
Physical Layer Control 2, Bit[12:8] for Port 0
Physical Layer Control 2, Bit[12:8] for Port 1
Physical Layer Control 2, Bit[12:8] for Port 2
Reserved
Reserved
Capability Pointer for Func 0
Reserved
Capability Pointer for Func 1
Reserved
Capability Pointer for Func 2
USB Physical Layer Control Register (USB Port 3), Bit[15:0]
PM Control Parameter / Rx Polarity for Port 0
PM Control Parameter / Rx Polarity for Port 1
PM Control Parameter / Rx Polarity for Port 2
Reserved
PM Capability for Func 0
Next Pointer Item for Func 0
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 31 of 102
www.diodes.com
BYTE OFFSET
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
90h
92h
94h
96h
98h
January 2018
© Diodes Incorporated
PI7C9X440SL
15 – 8
7–0
PM Capability for Func 1
Next Pointer Item for Func 1
PM Capability for Func 2
Next Pointer Item for Func 2
USB Physical Layer Control Register (USB Port 4), Bit[15:0]
Replay Time-out Counter for Port 0
Replay Time-out Counter for Port 1
Replay Time-out Counter for Port 2
Reserved
PM Capability / PM Data / Next Pointer Item for Func 0
PM Capability / PM Data / Next Pointer Item for Func 1
PM Capability / PM Data / Next Pointer Item for Func 2
Device Control for Func 0
Acknowledge Latency Timer for Port 0
Acknowledge Latency Timer for Port 1
Acknowledge Latency Timer for Port 2
Reserved
Next Pointer Item for Func 0
Capability ID for Func 0
Next Pointer Item for Func 1
Capability ID for Func 1
Next Pointer Item for Func 2
Capability ID for Func 2
Reserved
Physical Layer Control 3 for Port 0
Reserved
Reserved
Reserved
PCI Express Capability for Func 0
PCI Express Capability for Func 1
PCI Express Capability for Func 2
USB Physical Layer Control Register (USB
USB Physical Layer Control Register
Port 2), Bit[23:16]
(USB Port 1), Bit[23:16]
Reserved
Reserved
Reserved
Reserved
Device Capability 0 for Func 0
Device Capability 0 for Func 1
Device Capability 0 for Func 2
USB Physical Layer Control Register (USB
USB Physical Layer Control Register
Port 4), Bit[23:16]
(USB Port 3), Bit[23:16]
Reserved
Reserved
Reserved
Reserved
Device Capability 1 for Func 0
Device Capability 1 for Func 1
Device Capability 1 for Func 2
BYTE OFFSET
9Ah
9Ch
9Eh
A0h
A2h
A4h
A6h
A8h
AAh
ACh
AEh
B0h
B2h
B4h
B6h
B8h
BAh
BCh
BEh
C0h
C2h
C4h
C6h
C8h
CAh
CCh
CEh
D0h
D2h
D4h
D6h
D8h
DAh
DCh
DEh
E0h
E2h
E4h
E6h
E8h
EAh
ECh
6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS
ADDRESS
00h
02h
04h
PCI CFG OFFSET
00h ~ 01h
02h ~ 03h
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
EEPROM signature – 1516h
Vendor ID for Port 0~3
Device ID for Port 0~3
Page 32 of 102
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January 2018
© Diodes Incorporated
PI7C9X440SL
ADDRESS
06h
08h
0Ah
0Ch
0Eh
10h
PCI CFG OFFSET
ECh (Port 0~2)
ECh – Bit[14:12]
ECh – Bit[17:15]
DESCRIPTION
Link Capability for Port 0~2
Bit[3:1]: It represents L0s Exit Latency for all ports
Bit[6:4]: It represents L1 Exit Latency for all ports
B4h (Port 0~2)
B4h – Bit[5]
Bit[6]
Bit[0]
Bit[2:1]
Bit[3]
Bit[4]
Switch Mode Operation for Port 0~2
Bit[8]: Ordering on Different Egress Port Mode
Bit[9]: Ordering on Different Tag of Completion Mode
Bit[10]: Store and Forward
Bit[12:11]: Cut-through Threshold
Bit[13]: Port Arbitration Mode
Bit[14]: Credit Update Mode
3Ch (Port 1~2)
3Ch – Bit[8]
Interrupt pin for Port 1~2
Bit[15]: Set when INTA is requested for interrupt
resource
Subsystem Vender ID
Subsystem ID
Max_Payload_Size Support for Port 0~3
Bit[0]: Indicated the maximum payload size that the
device can support for the TLP
C4h ~ C5h
C6h ~ C7h
E4h (Port 0~3)
E4h – Bit[0]
ECh (Port 0~3)
ECh – Bit[11 :10]
ASPM Support for Port 0~3
Bit[2:1]: Indicate the level of ASPM supported on the
PCIe link
E4h (Port 0~3)
E4h – Bit[15]
Role_Base Error Reporting for Port 0~3
Bit[3]: Indicate implement the role-base error reporting
B0h (Port 0~3)
B0h – Bit[14]
B0h – Bit[15]
MSI/AER Capability Disable for Port 0~3
Bit[4]: Disable MSI capability
Bit[5]: Disable AER capability
B4h (Port 0~3)
B4h – Bit[15]
Compliance Pattern Parity Control Disable for Port 0~3
Bit[6]: Compliance Pattern Parity Control Disable
B0h (Port 0~3)
B0h – Bit[13]
Power Management Capability Disable for Port 0~3
Bit[7]: Disable Power Management Capability
B4h (Port 0~3)
B4h – Bit[7]
Ordering Frozen for Port 0~3
Bit[10]: Freeze the ordering feature
B8h (Port 0~3)
B8h – Bit[12]
TX SOF Latency Mode for Port 0~3
Bit[11]: Set to zero to shorten latency
ECh (Port 1~3)
ECh – Bit[19]
Surprise Down Capability Enable for for Port 1~3
Bit[12]: Enable Surprise Down Capability
B8h (Port 0~3)
B8h – Bit[13]
Power Management’s Data Select Register R/W Capability for
Port 0~3
Bit[13]: Enable Data Select Register R/W
B8h (Port 0~3)
B8h – Bit[14]
Flow Control Update Type for Port 0~3
Bit[14]: Select Flow Control Update Type
B8h (Port 0~3)
B8h – Bit[15]
08h (Port 0~3)
08h – Bit[7:0]
B8h (Port 0)
B8h – Bit[7 :0]
4KB Boundary Check Enable for Port 0~3
Bit[15]: Enable 4KB Boundary Check
Revision ID for Port 0~3
Bit [7:0]: Indicates the Revision ID of chip.
FTS Number for Port 0
Bit[7:0]: FTS number at receiver side
A8h (Port 0)
A8h – Bit[14:13]
RefClk ppm Difference for Port 0
Bit[9:8]: It represents RefClk ppm difference between the
two ends in one link; 00: 0 ppm, 01: 100 ppm,
10: 200 ppm, 11: 300 ppm
B8h (Port 0)
Scrambler Control for Port 0
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 33 of 102
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January 2018
© Diodes Incorporated
PI7C9X440SL
ADDRESS
12h
14h
18h
1Ah
1Ch
20h
22h
PCI CFG OFFSET
B8h – Bit[11:10]
B8h – Bit[12]
B8h (Port 1)
B8h – Bit[7 :0]
DESCRIPTION
Bit[11:10]: Scrambler Control
Bit[12]: L0s
FTS Number for Port 1
Bit[7:0]: FTS number at receiver side
A8h (Port 1)
A8h – Bit[14:13]
RefClk ppm Difference for Port 1
Bit[9:8]: It represents RefClk ppm difference between the
two ends in one link; 00: 0 ppm, 01: 100 ppm,
10: 200 ppm, 11: 300 ppm
B8h (Port 1)
B8h – Bit[9:8]
B8h – Bit[10]
B8h (Port 2)
B8h – Bit[7:0]
Scrambler Control for Port 1
Bit[11:10]: Scrambler Control
Bit[12]: L0s
FTS Number for Port 2
Bit[7:0]: FTS number at receiver side
A8h (Port 2)
A8h – Bit [14:13]
RefClk ppm Difference for Port 2
Bit[9:8]: It represents RefClk ppm difference between the
two ends in one link; 00: 0 ppm, 01: 100 ppm,
10: 200 ppm, 11: 300 ppm
B8h (Port 2)
B8h – Bit[9:8]
B8h – Bit[10]
B4h (Port 0~2)
B4h – Bit[20 :16]
B4h – Bit[25 :21]
B4h – Bit[30 :26]
B8h (Port 0~2)
B8h – Bit[20 :16]
B8h – Bit[25 :21]
B8h – Bit[30 :26]
BCh (Port 0~2)
BCh – Bit[3 :0]
BCh – Bit[6 :4]
F0h (Port 0)
F0h – Bit[28]
Scrambler Control for Port 2
Bit[11:10]: Scrambler Control
Bit[12]: L0s
Physical Layer Control 0 for Port 0~2
Bit[4:0]: Drive Amplitude Level (3P5 Nom)
Bit[9:5]: Drive Amplitude Level (6P0 Nom)
Bit[14:10]: Drive Amplitude Level (Half)
Physical Layer Control 1 for Port 0~2
Bit[4:0]: Drive De-Emphasis Level
Bit[9:5]: Reserved
Bit[14:10]: Reserved
Physical Layer Control 2 for Port 0~2
Bit[3:0]: Transmitter PHY Latency
Bit[6:4]: Receiver Detection Threshold
Slot Clock Configuration for Port 0
Bit[1]: When set, the component uses the clock provided
on the connector
80h (Port 0)
80h – Bit[21]
Device specific Initialization for Port 0
Bit[2]: When set, the DSI is required
ECh (Port 0)
ECh – Bit[25:24]
Port Number for Port 0
Bit[5:4]: It represents the logic port numbering for
physical port 0
84h (Port 0)
84h – Bit[14:13]
154h (Port 0)
154h – Bit[7:1]
PMCSR Data Scale for Port 0
Bit[7:6]: It represents the PMCSR Data Scale for physical port 0
VC0 TC/VC Map for Port 0
Bit[15:9]: When set, it indicates the corresponding TC is
mapped into VC0
PCIe Capability Slot Implemented for Port 1
Bit[0]: When set, the slot is implemented for Port 1
E0h (Port1)
E0h – Bit[24]
F0h (Port 1)
F0h – Bit[28]
Slot Clock Configuration for Port 1
Bit[1]: When set, the component uses the clock provided
on the connector
80h (Port 1)
80h – Bit[21]
Device specific Initialization for Port 1
Bit[2]: When set, the DSI is required
ECh (Port 1)
ECh – Bit[25:24]
Port Number for Port 1
Bit[5:4]: It represents the logic port numbering for
physical port 1
84h (Port 1)
84h – Bit[14:13]
PMCSR Data Scale for Port 1
Bit[7:6]: It represents the PMCSR Data Scale for physical port 1
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 34 of 102
www.diodes.com
January 2018
© Diodes Incorporated
PI7C9X440SL
ADDRESS
24h
PCI CFG OFFSET
154h (Port 1)
154h – Bit[7:1]
E0h (Port 2)
E0h – Bit[24]
F0h (Port 2)
F0h – Bit[28]
Slot Clock Configuration for Port 2
Bit[1]: When set, the component uses the clock provided
on the connector
80h (Port 2)
80h – Bit[21]
Device specific Initialization for Port 2
Bit[2]: When set, the DSI is required
ECh (Port 2)
ECh – Bit[25:24]
Port Number for Port 2
Bit[5:4]: It represents the logic port numbering for
physical port 2
PMCSR Data Scale for Port 2
Bit[7:6]: It represents the PMCSR Data Scale for physical port 2
VC0 TC/VC Map for Port 2
Bit[15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Vendor ID for Func 0
Vendor ID for Func 1
Vendor ID for Func 2
PCI Express Capability for Func 0
Bit[0]: Correctable Error Reporting Enable
Bit[1]: Non-Fatal Error Reporting Enable
Bit[2]: Fatal Error Reporting Enable
Bit[3]: Unsupported Request Reporting Enable
Bit[4]: Enable Relaxed Ordering
Bit[7:5]: Max_Payload_Size
Bit[8]: Extended Tag Field Enable
Bit[9]: Phantom Function Enable
Bit[10]: Auxiliary (AUX) Power PM Enable
Bit[11]: Enable No Snoop
Bit[14:12]: Max_Read_ Request_Size
Slot Capability 0 of Port 1
Bit[15:0]: Mapping to the low word of slot capability
register
Slot Capability 0 of Port 2
Bit[15:0]: Mapping to the low word of slot capability
register
Device ID for Func 0
Device ID for Func 1
Device ID for Func 2
Miscellaneous Register for Func 2
Bit[0]: Enable Basic Mode
Bit[1]: Enable Boundary 64-byte
Bit[2]: Enable EHCI Prefetch
Bit[3]: Reserved. Must to be 0b.
Bit[4]: Enable User Max_Read_Request_Size
Bit[6:5]: User Max_Read_Request_Size
Bit[14:8]: Prefetch DW Size (Unit: DW)
Slot Capability 1 of Port 1
Bit[15:0]: Mapping to the high word of slot capability
register
Slot Capability 1 of Port 2
Bit[15:0]: Mapping to the high word of slot capability
register
Revision ID and Class Code for Func 0
Bit[7:0]: Revision ID
Bit[15:8]: Programming Interface
Revision ID and Class Code for Func 1
Bit[7:0]: Revision ID
Bit[15:8]: Programming Interface
84h (Port 2)
84h – Bit[14:13]
154h (Port 2)
154h – Bit[7:1]
28h
2Ah
2Ch
2Eh
32h
00h ~ 01h (Func 0)
00h ~ 01h (Func 1)
00h ~ 01h (Func 2)
E8h (Func 0)
E8h – Bit[0]
E8h – Bit[1]
E8h – Bit[2]
E8h – Bit[3]
E8h – Bit[4]
E8h – Bit[7 :5]
E8h – Bit[8]
E8h – Bit[9]
E8h – Bit[10]
E8h – Bit[11]
E8h – Bit[14 :12]
F4h (Port 1)
F4h – Bit[15:0]
34h
F4h (Port 2)
F4h – Bit[15:0]
38h
3Ah
3Ch
3Eh
02h ~ 03h (Func 0)
02h ~ 03h (Func 1)
02h ~ 03h (Func 2)
68h (Func 2)
68h – Bit[0]
68h – Bit[1]
68h – Bit[2]
68h – Bit[3]
68h – Bit[4]
68h – Bit[6:5]
68h – Bit[14:8]
F4h (Port 1)
F4h – Bit[31:16]
42h
44h
F4h (Port 2)
F4h – Bit[31:16]
48h
08h (Func 0)
08h – Bit[7:0]
08h – Bit[15:8]
08h (Func 1)
08h – Bit[7:0]
08h – Bit[15:8]
4Ah
DESCRIPTION
VC0 TC/VC Map for Port 1
Bit[15:9]: When set, it indicates the corresponding TC is
mapped into VC0
PCIe Capability Slot Implemented for Port 2
Bit[0]: When set, the slot is implemented for Port 2
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 35 of 102
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January 2018
© Diodes Incorporated
PI7C9X440SL
ADDRESS
4Ch
4Eh
50h
PCI CFG OFFSET
08h (Func 2)
08h – Bit[7:0]
08h – Bit[15:8]
A0h (Func 0~2)
A0h – Bit[15 :0]
84h (Port 0)
84h – Bit[3]
80h (Port 0)
80h – Bit[24:22]
80h – Bit[25]
80h – Bit[26]
51h
52h
80h – Bit[29:28]
84h (Port 0)
84h – Bit[31:24]
84h (Port 1)
84h – Bit[3]
80h (Port 1)
80h – Bit[24:22]
80h – Bit[25]
80h – Bit[26]
53h
54h
80h – Bit[29:28]
84h (Port 1)
84h – Bit[31:24]
84h (Port 2)
84h – Bit[3]
80h (Port 2)
80h – Bit[24:22]
80h – Bit[25]
80h – Bit[26]
55h
56h
80h – Bit[29:28]
84h (Port 2)
84h – Bit[31:24]
84h (Port 3)
84h – Bit[3]
80h (Port 3)
80h – Bit[24:22]
80h – Bit[25]
80h – Bit[26]
57h
58h
5Ah
5Ch
5Eh
80h – Bit[29:28]
84h (Port 3)
84h – Bit[31:24]
08h (Func 0)
08h – Bit[23:16]
08h – Bit[31:24]
08h (Func 1)
08h – Bit[23:16]
08h – Bit[31:24]
08h (Func 2)
08h – Bit[23:16]
08h – Bit[31:24]
A4h (Func 0~2)
A4h – Bit[15 :0]
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
Revision ID and Class Code for Func 2
Bit[7:0]: Revision ID
Bit[15:8]: Programming Interface
USB Physical Layer Control Register (USB Port 1), Bit[15:0]
Bit[15:0]: USB Physical Layer Control Register (USB
Port 1), Bit[15:0]
No_Soft_Reset for Port 0
Bit[0]: No_Soft_Reset.
Power Management Capability for Port 0
Bit[3:1]: AUX Current
Bit[4]: read only as 1 to indicate Bridge supports the D1
power management state
Bit[5]: read only as 1 to indicate Bridge supports the D2
power management state
Bit[7:6]: PME Support for D2 and D1 states
Power Management Data for Port 0
Bit[15:8]: read only as Data register
No_Soft_Reset for Port 1
Bit[0]: No_Soft_Reset.
Power Management Capability for Port 1
Bit[3:1]: AUX Current
Bit[4]: read only as 1 to indicate Bridge supports the D1
power management state
Bit[5]: read only as 1 to indicate Bridge supports the D2
power management state
Bit[7:6]: PME Support for D2 and D1 states
Power Management Data for Port 1
Bit[15:8]: read only as Data register
No_Soft_Reset for Port 2
Bit[0]: No_Soft_Reset.
Power Management Capability for Port 2
Bit[3:1]: AUX Current
Bit[4]: read only as 1 to indicate Bridge supports the D1
power management state
Bit[5]: read only as 1 to indicate Bridge supports the D2
power management state
Bit[7:6]: PME Support for D2 and D1 states
Power Management Data for Port 2
Bit[15:8]: read only as Data register
No_Soft_Reset for Port 3
Bit[0]: No_Soft_Reset.
Power Management Capability for Port 3
Bit[3:1]: AUX Current
Bit[4]: read only as 1 to indicate Bridge supports the D1
power management state
Bit[5]: read only as 1 to indicate Bridge supports the D2
power management state
Bit[7:6]: PME Support for D2 and D1 states
Power Management Data for Port 3
Bit[15:8]: read only as Data register
Class Code for Func 0
Bit[7:0]: Sub-Class Code
Bit[15:8]: Base Class Code
Class Code for Func 1
Bit[7:0]: Sub-Class Code
Bit[15:8]: Base Class Code
Class Code for Func 2
Bit[7:0]: Sub-Class Code
Bit[15:8]: Base Class Code
USB Physical Layer Control Register (USB Port 2), Bit[15:0]
Bit[15:0]: USB Physical Layer Control Register (USB
Port 2), Bit[15:0]
Page 36 of 102
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January 2018
© Diodes Incorporated
PI7C9X440SL
ADDRESS
60h
62h
64h
68h
6Ah
6Ch
6Eh
70h
PCI CFG OFFSET
214h (Port 0)
214h– Bit[7:0]
214h– Bit[9:8]
214h– Bit[12:10]
218h– Bit[0]
214h (Port 1)
214h– Bit[7:0]
214h– Bit[9:8]
214h– Bit[12:10]
218h– Bit[0]
214h (Port 2)
214h– Bit[7:0]
214h– Bit[9:8]
214h– Bit[12:10]
218h– Bit[0]
2Ch ~ 2Dh (Func 0)
2Ch ~ 2Dh (Func 1)
2Ch ~ 2Dh (Func 2)
E8h (Func 1)
E8h – Bit[0]
E8h – Bit[1]
E8h – Bit[2]
E8h – Bit[3]
E8h – Bit[7 :5]
E8h – Bit[10]
BCh (Port 0)
BCh – Bit[16]
BCh – Bit[17]
BCh – Bit[18]
BCh – Bit[19]
72h
BCh – Bit[21:20]
BCh – Bit[25:22]
BCh – Bit[29:26]
BCh – Bit[30]
BCh (Port 1)
BCh – Bit[16]
BCh – Bit[17]
BCh – Bit[18]
BCh – Bit[19]
74h
BCh – Bit[21:20]
BCh – Bit[25:22]
BCh – Bit[29:26]
BCh – Bit[30]
BCh (Port 2)
BCh – Bit[16]
BCh – Bit[17]
BCh – Bit[18]
BCh – Bit[19]
78h
7Ah
7Ch
80h
BCh – Bit[21:20]
BCh – Bit[25:22]
BCh – Bit[29:26]
BCh – Bit[30]
2Eh ~ 2Fh (Func 0)
2Eh ~ 2Fh (Func 1)
2Eh ~ 2Fh (Func 2)
BCh (Port 0)
BCh – Bit[8]
BCh – Bit[10 :9]
BCh – Bit[12 :11]
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
Power Budget Register for Port 0
Bit[7:0]: Base Power
Bit[9:8]: Data Scale
Bit[12:10]: PM State
Bit[15]: System Allocated
Power Budget Register for Port 1
Bit[7:0]: Base Power
Bit[9:8]: Data Scale
Bit[12:10]: PM State
Bit[15]: System Allocated
Power Budget Register for Port 2
Bit[7:0]: Base Power
Bit[9:8]: Data Scale
Bit[12:10]: PM State
Bit[15]: System Allocated
Subsystem Vendor ID for Func 0
Subsystem Vendor ID for Func 1
Subsystem Vendor ID for Func 2
PCI Express Capability for Func 1
Bi[0]: Correctable Error Reporting Enable
Bit[1]: Non-Fatal Error Reporting Enable
Bit[2]: Fatal Error Reporting Enable
Bit[3]: Unsupported Request Reporting Enable
Bit[7:5]: Max_Payload_Size
Bit[10]: Auxiliary (AUX) Power PM Enable
Physical Layer Control 2, Bit[30:16] for Port 0
Bit[0]: Per-Lane Main Drive Offset Enable (Margining)
Bit[1]: Per-Lane Main Drive Offset Enable (Nominal)
Bit[2]: Per-Lane De-Emphasis Drive Offset Enable
(Margining)
Bit[3]: Per-Lane De-Emphasis Drive Offset Enable
(Nominal)
Bit[5:4]: Receiver Signal Detection
Bit[9:6]: Receiver Equalization
Bit[13:10]: Reserved
Bit[14] : Transmitter Swing
Physical Layer Control 2, Bit[30:16] for Port 1
Bit[0]: Per-Lane Main Drive Offset Enable (Margining)
Bit[1]: Per-Lane Main Drive Offset Enable (Nominal)
Bit[2]: Per-Lane De-Emphasis Drive Offset Enable
(Margining)
Bit[3]: Per-Lane De-Emphasis Drive Offset Enable
(Nominal)
Bit[5:4]: Receiver Signal Detection
Bit[9:6]: Receiver Equalization
Bit[13:10]: Reserved
Bit[14] : Transmitter Swing
Physical Layer Control 2, Bit[30:16] for Port 2
Bit[0]: Per-Lane Main Drive Offset Enable (Margining)
Bit[1]: Per-Lane Main Drive Offset Enable (Nominal)
Bit[2]: Per-Lane De-Emphasis Drive Offset Enable
(Margining)
Bit[3]: Per-Lane De-Emphasis Drive Offset Enable
(Nominal)
Bit[5:4]: Receiver Signal Detection
Bit[9:6]: Receiver Equalization
Bit[13:10]: Reserved
Bit[14] : Transmitter Swing
Subsystem ID for Func 0
Subsystem ID for Func 1
Subsystem ID for Func 2
Physical Layer Control 2, Bit[12:8] for Port 0
Bit [0]: CDR Loop Bandwidth Enable
Bit [2:1]: CDR Threshold
Bit [4:3]: CDR Loop Bandwidth Gain
Page 37 of 102
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January 2018
© Diodes Incorporated
PI7C9X440SL
ADDRESS
82h
84h
88h
8Ah
8Ch
8Eh
90h
92h
94h
98h
9Ah
9Ch
PCI CFG OFFSET
BCh (Port 1)
BCh – Bit[8]
BCh – Bit[10 :9]
BCh – Bit[12 :11]
BCh (Port 2)
BCh – Bit[8]
BCh – Bit[10 :9]
BCh – Bit[12 :11]
34h (Func 0)
34h – Bit[7:0]
34h (Func 1)
34h – Bit[7:0]
34h (Func 2)
34h – Bit[7:0]
A8h (Func 0~2)
A8h – Bit[15 :0]
B4h (Port 0)
B4h – Bit[9:8]
B4h – Bit[11:10]
B4h – Bit[13:12]
DESCRIPTION
Physical Layer Control 2, Bit[12:8] for Port 1
Bit [0]: CDR Loop Bandwidth Enable
Bit [2:1]: CDR Threshold
Bit [4:3]: CDR Loop Bandwidth Gain
Physical Layer Control 2, Bit[12:8] for Port 2
Bit [0]: CDR Loop Bandwidth Enable
Bit [2:1]: CDR Threshold
Bit [4:3]: CDR Loop Bandwidth Gain
Capabilities Pointer for Func 0
Bit[7:0]: Capabilities Pointer
Capabilities Pointer for Func 1
Bit[7:0]: Capabilities Pointer
Capabilities Pointer for Func 2
Bit[7:0]: Capabilities Pointer
USB Physical Layer Control Register (USB Port 3), Bit[15:0]
Bit[15:0]: USB Physical Layer Control Register (USB
Port 3), Bit[15:0]
PM Control Parameter for Port 0
Bit[1:0] : D3 enters L1
Bit[3:2] : L1 delay count select
Bit[5:4] : L0s enable
B4h (Port 0)
B4h – Bit[14]
Rx Polarity Inversion Disable for port 0
Bit[6] : RX Polarity Inversion Disable
B0h (Port 0)
B0h – Bit[31]
B4h (Port 1)
B4h – Bit[9:8]
B4h – Bit[11:10]
B4h – Bit[13:12]
Decode VGA for Port 0
Bit[7]
PM Control Parameter for Port 1
Bit[1:0] : D3 enters L1
Bit[3:2] : L1 delay count select
Bit[5:4] : L0s enable
B4h (Port 1)
B4h – Bit[14]
Rx Polarity Inversion Disable for port 1
Bit[6] : RX Polarity Inversion Disable
B0h (Port 1)
B0h – Bit[31]
B4h (Port 2)
B4h – Bit[9:8]
B4h – Bit[11:10]
B4h – Bit[13:12]
Decode VGA for Port 1
Bit[7]
PM Control Parameter for Port 2
Bit[1:0] : D3 enters L1
Bit[3:2] : L1 delay count select
Bit[5:4] : L0s enable
B4h (Port 2)
B4h – Bit[14]
Rx Polarity Inversion Disable for port 2
Bit[6] : RX Polarity Inversion Disable
B0h (Port 2)
B0h – Bit[31]
80h (Func 0)
80h – Bit[15:8]
80h – Bit[21]
80h – Bit[24:22]
80h – Bit[25]
80h – Bit[26]
80h (Func 1)
80h – Bit[15:8]
80h – Bit[21]
80h – Bit[24:22]
80h – Bit[25]
80h – Bit[26]
80h (Func 2)
80h – Bit[15:8]
80h – Bit[21]
80h – Bit[24:22]
80h – Bit[25]
80h – Bit[26]
Decode VGA for Port 2
Bit[7]
Power Management Capability for Func 0
Bit[7:0]: Next Item Pointer
Bit[8]: Device Specific Initialization
Bit[11:9]: AUX Current
Bit[12]: D1 Power State Support
Bit[13]: D2 Power State Support
Power Management Capability for Func 1
Bit[7:0]: Next Item Pointer
Bit[8]: Device Specific Initialization
Bit[11:9]: AUX Current
Bit[12]: D1 Power State Support
Bit[13]: D2 Power State Support
Power Management Capability for Func 2
Bit[7:0]: Next Item Pointer
Bit[8]: Device Specific Initialization
Bit[11:9]: AUX Current
Bit[12]: D1 Power State Support
Bit[13]: D2 Power State Support
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
ADDRESS
9Eh
A0h
A2h
A4h
A8h
AAh
ACh
AEh
B0h
B2h
B4h
B8h
BAh
BCh
C0h
C8h
CAh
CCh
PCI CFG OFFSET
ACh (Func 0~2)
ACh – Bit[15 :0]
B0h (Port 0)
B0h – Bit[12 :0]
B0h (Port 1)
B0h – Bit[12 :0]
B0h (Port 2)
B0h – Bit[12 :0]
80h (Func 0)
80h – Bit[31 :27]
DESCRIPTION
USB Physical Layer Control Register (USB Port 4), Bit[15:0]
Bit[15:0]: USB Physical Layer Control Register (USB
Port 4), Bit[15:0]
Replay Time-out Counter for Port 0
Bit[12:0]: Replay Time-out Counter
Replay Time-out Counter for Port 1
Bit[12:0]: Replay Time-out Counter
Replay Time-out Counter for Port 2
Bit[12:0]: Replay Time-out Counter
Power Management Capability for Func 0
Bit[4:0]: PME# Support
84h (Func 0)
84h – Bit[3]
Power Management Data for Func 0
Bit[5]: No_Soft_Reset
8Ch (Func 0)
8Ch – Bit[15 :8]
80h (Func 1)
80h – Bit[31 :27]
Next Item Pointer for Func 0
Bit[15:8]: Next Item Pointer
Power Management Capability for Func 1
Bit[4:0]: PME# Support
84h (Func 1)
84h – Bit[3]
Power Management Data for Func 1
Bit[5]: No_Soft_Reset
8Ch (Func 1)
8Ch – Bit[15 :8]
80h (Func 2)
80h – Bit[31 :27]
Next Item Pointer for Func 1
Bit[15:8]: Next Item Pointer
Power Management Capability for Func 2
Bit[4:0]: PME# Support
84h (Func 2)
84h – Bit[3]
Power Management Data for Func 2
Bit[5]: No_Soft_Reset
8Ch (Func 2)
8Ch – Bit[15 :8]
E8h (Func 2)
E8h – Bit[0]
E8h – Bit[1]
E8h – Bit[2]
E8h – Bit[3]
E8h – Bit[7 :5]
E8h – Bit[10]
B0h (Port 0)
B0h – Bit[30 :16]
B0h (Port 1)
B0h – Bit[30 :16]
B0h (Port 2)
B0h – Bit[30 :16]
E0h (Func 0)
E0h – Bit[7 :0]
E0h – Bit[15 :8]
E0h (Func 1)
E0h – Bit[7 :0]
E0h – Bit[15 :8]
E0h (Func 2)
E0h – Bit[7 :0]
E0h – Bit[15 :8]
C0h – Bit[6 :0]
Next Item Pointer for Func 2
Bit[15:8]: Next Item Pointer
PCI Express Capability for Func 2
Bit[0]: Correctable Error Reporting Enable
Bit[1]: Non-Fatal Error Reporting Enable
Bit[2]: Fatal Error Reporting Enable
Bit[3]: Unsupported Request Reporting Enable
Bit[7:5]: Max_Payload_Size
Bit[10]: Auxiliary (AUX) Power PM Enable
Acknowledge Latency Timer for Port 0
Bit[14:0]: Acknowledge Latency Timer
Acknowledge Latency Timer for Port 1
Bit[14:0]: Acknowledge Latency Timer
Acknowledge Latency Timer for Port 2
Bit[14:0]: Acknowledge Latency Timer
PCI Express Capability for Func 0
Bit[7:0]: Enhanced Capabilities ID
Bit[15:8]: Next Item Pointer
PCI Express Capability for Func 1
Bit[7:0]: Enhanced Capabilities ID
Bit[15:8]: Next Item Pointer
PCI Express Capability for Func 2
Bit[7:0]: Enhanced Capabilities ID
Bit[15:8]: Next Item Pointer
Physical Layer Control 3 for Port 0
Bit [6:0]: Lane Mode
PCI Express Capability for Func 0
Bit[3:0]: Capability Version
Bit[7:4]: Device/Port Type
PCI Express Capability for Func 1
Bit[3:0]: Capability Version
Bit[7:4]: Device/Port Type
PCI Express Capability for Func 2
Bit[3:0]: Capability Version
Bit[7:4]: Device/Port Type
E0h (Func 0)
E0h – Bit[19 :16]
E0h – Bit[23 :20]
E0h (Func 1)
E0h – Bit[19 :16]
E0h – Bit[23 :20]
E0h (Func 2)
E0h – Bit[19 :16]
E0h – Bit[23 :20]
PI7C9X440SL
Document Number DS40394 Rev 3-2
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© Diodes Incorporated
PI7C9X440SL
ADDRESS
CEh
PCI CFG OFFSET
A0h (Func 0~2)
A0h – Bit[23 :16]
A4h (Func 0~2)
A4h – Bit[23 :16]
D8h
DAh
DCh
DEh
E4h (Func 0)
E4h – Bit[2 :0]
E4h – Bit[8 :6]
E4h – Bit[11 :9]
E4h – Bit[15]
E4h (Func 1)
E4h – Bit[2 :0]
E4h – Bit[8 :6]
E4h – Bit[11 :9]
E4h – Bit[15]
E4h (Func 2)
E4h – Bit[2 :0]
E4h – Bit[8 :6]
E4h – Bit[11 :9]
E4h – Bit[15]
A8h (Func 0~2)
A8h – Bit[23 :16]
ACh (Func 0~2)
ACh – Bit[23 :16]
E8h
EAh
ECh
6.2
E4h (Func 0)
E4h – Bit[25 :18]
E4h – Bit[27 :26]
E4h (Func 1)
E4h – Bit[25 :18]
E4h – Bit[27 :26]
E4h (Func 2)
E4h – Bit[25 :18]
E4h – Bit[27 :26]
DESCRIPTION
USB Physical Control Register (USB Port 1), Bit[23:16]
Bit[7:0]: USB Physical Control Register (USB Port 1),
Bit[23:16]
USB Physical Control Register (USB Port 2), Bit[23:16]
Bit[15:8]: USB Physical Control Register (USB Port 1),
Bit[23:16]
Device Capability 0 for Func 0
Bit[2:0]: Max_Payload_Size Supported
Bit[8:6]: Endpoint Los Acceptable Latency
Bit[11:9]: Endpoint L1 Acceptable Latency
Bit[15]: Role_Base Error Reporting
Device Capability 0 for Func 1
Bit[2:0]: Max_Payload_Size Supported
Bit[8:6]: Endpoint Los Acceptable Latency
Bit[11:9]: Endpoint L1 Acceptable Latency
Bit[15]: Role_Base Error Reporting
Device Capability 0 for Func 2
Bit[2:0]: Max_Payload_Size Supported
Bit[8:6]: Endpoint Los Acceptable Latency
Bit[11:9]: Endpoint L1 Acceptable Latency
Bit[15]: Role_Base Error Reporting
USB Physical Control Register (USB Port 3), Bit[23:16]
Bit[7:0]: USB Physical Control Register (USB Port 1),
Bit[23:16]
USB Physical Control Register (USB Port 4), Bit[23:16]
Bit[15:8]: USB Physical Control Register (USB Port 1),
Bit[23:16]
PCI Express Capability 1 for Func 0
Bit[9:2]: Captured Slot Power Limit Value
Bit[11:10]: Captured Slot Power Limit Scale
PCI Express Capability 1 for Func 1
Bit[9:2]: Captured Slot Power Limit Value
Bit[11:10]: Captured Slot Power Limit Scale
PCI Express Capability 1 for Func 2
Bit[9:2]: Captured Slot Power Limit Value
Bit[11:10]: Captured Slot Power Limit Scale
SMBus INTERFACE
The Swidge provides the System Management Bus (SMBus), a two-wire interface through which a simple device
can communicate with the rest of the system. The SMBus interface on the Swidge is a bi-directional slave interface.
It can receive data from the SMBus master or send data to the master. The interface allows full access to the
configuration registers. A SMBus master, such as the processor or other SMBus devices, can read or write to every
RW configuration register (read/write register). In addition, the RO and HwInt registers (read-only and hardware
initialized registers) that can be auto-loaded by the EEPROM interface can also be read and written by the SMBus
interface. This feature allows increases in the system expandability and flexibility in system implementation.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
Pericom PCIe
Swidge
Processor
(SMBus Master)
Other SMBus
Devices
SMBCLK
SMBDATA
Figure 6-1 SMBus Architecture Implementation on PI7C9X440SL
The SMBus interface on the Swidge consists of one SMBus clock pin (SMBCLK), a SMBus data pin (SMBDATA),
and 3 SMBus address pins (GPIO[5:7]). The SMBus clock pin provides or receives the clock signal. The SMBus
data pin facilitates the data transmission and reception. Both of the clock and data pins are bi-directional. The
SMBus address pins determine the address to which the Swidge responds to. The SMBus address pins generate
addresses according to the following table:
Table 6-1 SMBus Address Pin Configuration
BIT
0
1
2
3
4
5
6
SMBus Address
GPIO[5]
GPIO[6]
GPIO[7]
1
0
1
1
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
7 REGISTER DESCRIPTION
7.1
REGISTER TYPES
REGISTER TYPE
HwInt
RO
RW
RWC
RWCS
RWS
ROS
7.2
DEFINITION
Hardware Initialization
Read Only
Read / Write
Read / Write 1 to Clear
Sticky - Read Only / Write 1 to Clear
Sticky - Read / Write
Sticky – Read Only
PCI EXPRESS CONFIGURATION REGISTERS
When the PCI Express port of the Swidge is set to operate at the transparent mode, it is represented by
a logical PCI-to-PCI bridge that implements type 1 configuration space header. The following table
details the allocation of the register fields of the PCI 2.3 compatible type 1 configuration space header.
31 –24
23 – 16
7 –0
15 - 8
Device ID
Primary Status
Vendor ID
Command
Revision ID
Primary Latency Timer
Cache Line Size
Reserved
Secondary Latency
Subordinate Bus
Secondary Bus Number
Primary Bus Number
Timer
Number
Secondary Status
I/O Limit Address
I/O Base Address
Memory Limit Address
Memory Base Address
Prefetchable Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Base Address Upper 32-bit
Prefetchable Memory Limit Address Upper 32-bit
I/O Limit Address Upper 16-bit
I/O Base Address Upper 16-bit
Reserved
Capability Pointer to
80h
Reserved
Bridge Control
Interrupt Pin
Interrupt Line
Reserved
Power Management Capabilities
Next Item Pointer=8C
Capability ID=01
PM Data
PPB Support
Power Management Data
Extensions
Message Control
Next Item Pointer=9C
Capability ID=05
Message Address
Message Upper Address
Reserved
Message Data
VPD Register
Next Item Pointer=A4
Capability ID=03
VPD Data Register
Length in Bytes (14h)
Next Item Pointer=C0
Capability ID=09
XPIP_CSR0
XPIP_CSR1
ACK Latency Timer
Replay Time-out Counter
Physical Layer Control 0
Switch Operation Mode
Physical Layer Control 1
XPIP CSR2 / TL CSR
Physical Layer Control 2
Reserved
Lane Mode
Reserved
Next Item
SSID/SSVID
Pointer=E0
Capability ID=0D
SSID
SSVID
Reserved
Reserved
PI7C9X440SL
Document Number DS40394 Rev 3-2
Class Code
Header Type
Page 42 of 102
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BYTE OFFSET
00h
04h
08h
0Ch
10h – 17h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h – 7Fh
80h
84h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
C8h – D7h
January 2018
© Diodes Incorporated
PI7C9X440SL
31 –24
23 – 16
15 - 8
7 –0
GPIO Data and Control
EEPROM Data
EEPROM Address
EEPROM Control
PCI Express Capabilities Register
Next Item Pointer=00
Capability ID=10
Device Capabilities
Device Status
Device Control
Link Capabilities
Link Status
Link Control
Slot Capabilities
Slot Status
Slot Control
Reserved
BYTE OFFSET
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
Other than the PCI 2.3 compatible configuration space header, the Swidge also implements PCI
express extended configuration space header, which includes advanced error reporting, virtual channel,
and power budgeting capability registers. The following table details the allocation of the register
fields of PCI express extended capability space header. The first extended capability always begins at
offset 100h with a PCI Express Enhanced Capability header and the rest of capabilities are located at
an offset greater than 0FFh relative to the beginning of PCI compatible configuration space.
31 –24
23 – 16
15 - 8
Next Capability Offset
7 –0
Cap.
PCI Express Extended Capability ID=0001h
Version
Uncorrectable Error Status Register
Uncorrectable Error Mask Register
Uncorrectable Error Severity Register
Correctable Error Status Register
Correctable Error Mask Register
Advanced Error Capabilities and Control Register
Header Log Register
Reserved
Next Capability Offset=20Ch
Cap.
PCI Express Extended Capability ID=0002h
Version
Port VC Capability Register 1
VC Arbitration Table
Port VC Capability Register 2
Offset=3
Port VC Status Register
Port VC Control Register
Port Arbitration Table
VC Resource Capability Register (0)
Offset=4
VC Resource Control Register (0)
VC Resource Status Register (0)
Reserved
Reserved
Port Arbitration Table with 128 Phases for VC0
Reserved
Reserved
Next Capability Offset=000h
Cap.
PCI Express Extended Capability ID=0004h
Version
Reserved
Data Select Register
Data Register
Reserved
Power Budget
Capability Register
7.2.1
BYTE OFFSET
100h
104h
108h
10Ch
110h
114h
118h
11Ch – 128h
12Ch – 13Fh
140h
144h
148h
14Ch
150h
154h
158h
15Ch-17Ch
180h – 1BCh
1C0h – 1FCh
200h – 20Bh
20Ch
210h
214h
218h
VENDOR ID REGISTER – OFFSET 00h
BIT
15:0
FUNCTION
Vendor ID
TYPE
RO
DESCRIPTION
Identifies Pericom as the vendor of this device. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 12D8h.
PI7C9X440SL
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PI7C9X440SL
7.2.2
DEVICE ID REGISTER – OFFSET 00h
BIT
31:16
FUNCTION
Device ID
TYPE
RO
DESCRIPTION
Identifies this device as the PI7C9X440. The default value may be changed
by SMBus or auto-loading from EEPROM.
Resets to 400Ch.
7.2.3
COMMAND REGISTER – OFFSET 04h
BIT
FUNCTION
0
I/O Space Enable
1
RW
Bus Master Enable
RW
3
Special Cycle Enable
Memory Write And
Invalidate Enable
VGA Palette Snoop
Enable
RO
5
Reset to 0b.
0b: Does not initiate memory or I/O transactions on the upstream port and
handles as an Unsupported Request (UR) to memory and I/O transactions
on the downstream port. For Non-Posted Requests, a completion with UR
completion status must be returned
1b: Enables the Swidge Port to forward memory and I/O Read/Write
transactions in the upstream direction
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
RO
Does not apply to PCI Express. Must be hardwired to 0b.
RO
6
Parity Error
Response Enable
RW
7
Wait Cycle Control
RO
8
SERR# enable
RW
9
Fast Back-to-Back
Enable
DESCRIPTION
0b: Ignores I/O transactions on the primary interface
1b: Enables responses to I/O transactions on the primary interface
Resets to 0b.
0b: Ignores memory transactions on the primary interface
1b: Enables responses to memory transactions on the primary interface
RW
2
4
7.2.4
Memory Space
Enable
TYPE
0b: Swidge may ignore any parity errors that it detects and continue normal
operation
1b: Swidge must take its normal action when a parity error is detected
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0.
0b: Disables the reporting of Non-fatal and Fatal errors detected by the
Swidge to the Root Complex
b1: Enables the Non-fatal and Fatal error reporting to Root Complex
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
RO
10
Interrupt Disable
RW
Controls the ability of a PCI Express device to generate INTx Interrupt
Messages. In the Swidge, this bit does not affect the forwarding of INTx
messages from the downstream ports.
15:11
Reserved
RO
Reset to 0b.
Reset to 0b.
PRIMARY STATUS REGISTER – OFFSET 04h
BIT
18:16
FUNCTION
Reserved
19
Interrupt Status
RO
20
Capabilities List
RO
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
DESCRIPTION
Reset to 000b.
Indicates that an INTx Interrupt Message is pending internally to the device.
In the Swidge, the forwarding of INTx messages from the downstream device
of the Swidge port is not reflected in this bit. Must be hardwired to 0b.
Set to 1 to enable support for the capability list (offset 34h is the pointer to
the data structure).
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PI7C9X440SL
BIT
FUNCTION
21
22
66MHz Capable
Reserved
Fast Back-to-Back
Capable
23
TYPE
DESCRIPTION
Reset to 1b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
RO
RO
RO
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the primary side of the port in a Swidge.
24
Master Data Parity
Error
RWC
26:25
DEVSEL# timing
RO
27
Signaled Target
Abort
RO
28
29
30
31
Received Target
Abort
Received Master
Abort
Signaled System
Error
Detected Parity Error
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a completer) whenever completing a request on the primary side
using the Completer Abort Completion Status.
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status on the primary side.
RO
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status on primary side.
RO
RWC
RWC
Reset to 0b.
Set to 1 when the Swidge sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Command register is 1.
Reset to 0b.
Set to 1 whenever the primary side of the port in a Swidge receives a
Poisoned TLP.
Reset to 0b.
7.2.5
REVISION ID REGISTER – OFFSET 08h
BIT
7:0
7.2.6
TYPE
RO
DESCRIPTION
Indicates revision number of device. Hardwired to 00h.
CLASS CODE REGISTER – OFFSET 08h
BIT
15:8
23:16
31:24
7.2.7
FUNCTION
Revision
FUNCTION
Programming
Interface
Sub-Class Code
Base Class Code
TYPE
RO
RO
RO
DESCRIPTION
Read as 00h to indicate no programming interfaces have been defined for
PCI-to-PCI Bridges.
Read as 04h to indicate device is a PCI-to-PCI Bridge.
Read as 06h to indicate device is a Bridge device.
CACHE LINE REGISTER – OFFSET 0Ch
BIT
FUNCTION
7:0
Cache Line Size
TYPE
RW
DESCRIPTION
The cache line size register is set by the system firmware and the operating
system cache line size. This field is implemented by PCI Express devices as a
RW field for legacy compatibility, but it has no impact on any PCI Express
device functionality.
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
7.2.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
BIT
15:8
7.2.9
7.2.10
FUNCTION
Primary Latency
timer
TYPE
RO
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 00h.
HEADER TYPE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
23:16
Header Type
RO
DESCRIPTION
Read as 01h to indicate that the register layout conforms to the standard PCIto-PCI Bridge layout.
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
7:0
Primary Bus Number
TYPE
RW
DESCRIPTION
Indicates the number of the PCI bus to which the primary interface is
connected. The value is set in software during configuration.
Reset to 00h.
7.2.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
15:8
Secondary Bus
Number
TYPE
RW
DESCRIPTION
Indicates the number of the PCI bus to which the secondary interface is
connected. The value is set in software during configuration.
Reset to 00h.
7.2.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
23:16
Subordinate Bus
Number
TYPE
DESCRIPTION
Indicates the number of the PCI bus with the highest number that is subordinate
to the Bridge. The value is set in software during configuration.
RW
Reset to 00h.
7.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
BIT
31:24
7.2.14
FUNCTION
Secondary Latency
Timer
TYPE
RO
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 00h.
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
BIT
3:0
FUNCTION
32-bit Indicator
7:4
I/O Base Address
[15:12]
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
RW
DESCRIPTION
Read as 01h to indicate 32-bit I/O addressing.
Defines the bottom address of the I/O address range for the Bridge to
determine when to forward I/O transactions from one interface to the other.
The upper 4 bits correspond to address bits [15:12] and are writable. The
lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The
upper 16 bits corresponding to address bits [31:16] are defined in the I/O base
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PI7C9X440SL
BIT
FUNCTION
TYPE
DESCRIPTION
address upper 16 bits address register.
Reset to 0h.
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch
BIT
11:8
FUNCTION
32-bit Indicator
15:12
I/O Limit Address
[15:12]
TYPE
RO
RW
DESCRIPTION
Read as 01h to indicate 32-bit I/O addressing.
Defines the top address of the I/O address range for the Bridge to determine
when to forward I/O transactions from one interface to the other. The upper 4
bits correspond to address bits [15:12] and are writable. The lower 12 bits
corresponding to address bits [11:0] are assumed to be FFFh. The upper 16
bits corresponding to address bits [31:16] are defined in the I/O limit address
upper 16 bits address register.
Reset to 0h.
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
BIT
20:16
21
22
23
FUNCTION
Reserved
66MHz Capable
Reserved
Fast Back-to-Back
Capable
TYPE
RO
RO
RO
RO
DESCRIPTION
Reset to 00000b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the secondary side of the port in a Swidge.
24
Master Data Parity
Error
RWC
26:25
DEVSEL_L timing
RO
27
Signaled Target
Abort
RO
28
29
30
31
Received Target
Abort
Received Master
Abort
Received System
Error
Detected Parity Error
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a completer) whenever completing a request in the secondary side
using Completer Abort Completion Status.
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status in the secondary side.
RO
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status in secondary side.
RO
RWC
RWC
Reset to 0b.
Set to 1 when the Swidge sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Bridge Control register is 1.
Reset to 0b.
Set to 1 whenever the secondary side of the port in a Swidge receives a
Poisoned TLP.
Reset to 0b.
7.2.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h
BIT
3:0
15:4
FUNCTION
Reserved
Memory Base
Address [15:4]
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
RW
DESCRIPTION
Reset to 0h.
Defines the bottom address of an address range for the Bridge to determine
when to forward memory transactions from one interface to the other. The
Page 47 of 102
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PI7C9X440SL
BIT
FUNCTION
TYPE
DESCRIPTION
upper 12 bits correspond to address bits [31:20] and are able to be written to.
The lower 20 bits corresponding to address bits [19:0] are assumed to be 0.
Reset to 000h.
7.2.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h
BIT
19:16
FUNCTION
Reserved
31:20
Memory Limit
Address [31:20]
TYPE
RO
RW
DESCRIPTION
Reset to 0h.
Defines the top address of an address range for the Bridge to determine when
to forward memory transactions from one interface to the other. The upper
12 bits correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be FFFFFh.
Reset to 000h.
7.2.19
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
BIT
3:0
FUNCTION
64-bit addressing
15:4
Prefetchable Memory
Base Address [31:20]
TYPE
RO
RW
DESCRIPTION
Read as 0001b to indicate 64-bit addressing.
Defines the bottom address of an address range for the Bridge to determine
when to forward memory read and write transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits are assumed to be 0. The memory base register upper 32
bits contain the upper half of the base address.
Reset to 000h.
7.2.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h
BIT
19:16
FUNCTION
64-bit addressing
31:20
Prefetchable Memory
Limit Address
[31:20]
TYPE
RO
RW
DESCRIPTION
Read as 0001b to indicate 64-bit addressing.
Defines the top address of an address range for the Bridge to determine when
to forward memory read and write transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits are assumed to be FFFFFh. The memory limit upper 32 bits
register contains the upper half of the limit address.
Reset to 000h.
7.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
BIT
FUNCTION
31:0
Prefetchable Memory
Base Address, Upper
32-bits [63:32]
TYPE
RW
DESCRIPTION
Defines the upper 32-bits of a 64-bit bottom address of an address range for
the Bridge to determine when to forward memory read and write transactions
from one interface to the other.
Reset to 00000000h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 48 of 102
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PI7C9X440SL
7.2.22
7.2.23
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
BIT
FUNCTION
31:0
Prefetchable Memory
Limit Address,
Upper 32-bits
[63:32]
TYPE
RW
DESCRIPTION
Defines the upper 32-bits of a 64-bit top address of an address range for the
Bridge to determine when to forward memory read and write transactions
from one interface to the other.
Reset to 00000000h.
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
BIT
FUNCTION
15:0
I/O Base Address,
Upper 16-bits
[31:16]
TYPE
RW
DESCRIPTION
Defines the upper 16-bits of a 32-bit bottom address of an address range for
the Bridge to determine when to forward I/O transactions from one interface
to the other.
Reset to 0000h.
7.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
BIT
FUNCTION
31:16
I/O Limit Address,
Upper 16-bits
[31:16]
TYPE
RW
DESCRIPTION
Defines the upper 16-bits of a 32-bit top address of an address range for the
Bridge to determine when to forward I/O transactions from one interface to
the other.
Reset to 0000h.
7.2.25
CAPABILITY POINTER REGISTER – OFFSET 34h
BIT
FUNCTION
7:0
Capability Pointer
TYPE
DESCRIPTION
Pointer points to the PCI power management registers (80h).
RO
Reset to 80h.
7.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch
BIT
7:0
7.2.27
FUNCTION
Interrupt Line
TYPE
RW
DESCRIPTION
Reset to 00h.
INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
15:8
Interrupt Pin
RO
DESCRIPTION
The Swidge implements INTA virtual wire interrupt signals to represent hotplug events at downstream ports. The default value on the downstream ports
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 49 of 102
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PI7C9X440SL
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
FUNCTION
16
Parity Error
Response
17
18
S_SERR# enable
ISA Enable
TYPE
RW
DESCRIPTION
0b: Ignore Poisoned TLPs on the secondary interface
1b: Enable the Poisoned TLPs reporting and detection on the secondary
interface
Reset to 0b.
0b: Disables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
1b: Enables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
RW
Reset to 0b.
0b: Forwards downstream all I/O addresses in the address range defined by
the I/O Base, I/O Base, and Limit registers
1b: Forwards upstream all I/O addresses in the address range defined by the
I/O Base and Limit registers that are in the first 64KB of PCI I/O address
space (top 768 bytes of each 1KB block)
RW
Reset to 0b.
0: Ignores access to the VGA memory or IO address range
1: Forwards transactions targeted at the VGA memory or IO address range
19
VGA 16-bit decode
RW
21
Master Abort Mode
RO
22
Secondary Bus Reset
RW
24
25
26
27
31:28
Fast Back-to-Back
Enable
Primary Master
Timeout
Secondary Master
Timeout
Master Timeout
Status
Discard Timer
SERR# enable
Reserved
VGA memory range starts from 000A 0000h to 000B FFFFh
VGA IO addresses are in the first 64KB of IO address space.
AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh.
RW
20
23
7.2.29
VGA Enable
Reset to 0b. Please note that this bit is reserved in Port 2.
0b: Executes 10-bit address decoding on VGA I/O accesses
1b: Executes 16-bit address decoding on VGA I/O accesses
Reset to 0b. Please note that this bit is reserved in Port 2.
Does not apply to PCI Express. Must be hardwired to 0b.
0b: Does not trigger a hot reset on the corresponding PCI Express Port
1b: Triggers a hot reset on the corresponding PCI Express Port
At the downstream port, it asserts PORT_RST# to the attached downstream
device.
At the upstream port, it asserts the PORT_RST# at all the downstream
ports.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
RO
Does not apply to PCI Express. Must be hardwired to 0b.
RO
Does not apply to PCI Express. Must be hardwired to 0b.
RO
Does not apply to PCI Express. Must be hardwired to 0b.
RO
Does not apply to PCI Express. Must be hardwired to 0b.
RO
RO
Reset to 0h.
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
BIT
7:0
FUNCTION
Enhanced
Capabilities ID
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
DESCRIPTION
Read as 01h to indicate that these are power management enhanced capability
registers.
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PI7C9X440SL
7.2.30
NEXT ITEM POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
RO
DESCRIPTION
At upstream ports, the pointer points to the Vital Protocol Data (VPD)
capability register (9Ch).
At downstream ports, the pointer points to the Message capability register
(8Ch).
Reset to 9Ch (Upstream port).
Reset to 8Ch (Downstream port).
7.2.31
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
BIT
18:16
19
20
TYPE
RO
RO
Device Specific
Initialization
RO
24:22
AUX Current
RO
26
31:27
D1 Power State
Support
D2 Power State
Support
PME# Support
DESCRIPTION
Read as 011b to indicate the device is compliant to Revision 1.2 of PCI Power
Management Interface Specifications.
RO
21
25
7.2.32
FUNCTION
Power
Management
Revision
PME# Clock
Reserved
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Read as 0b to indicate Swidge does not have device specific initialization
requirements. The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset as 111b to indicate the Swidge needs 375 mA in D3 state. The default
value may be changed by SMBus or auto-loading from EEPROM.
Read as 1b to indicate Swidge supports the D1 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
Read as 1b to indicate Swidge supports the D2 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
Read as 11111b to indicate Swidge supports the forwarding of PME# message in
all power states. The default value may be changed by SMBus or auto-loading
from EEPROM.
RO
RO
RO
POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
1:0
Power State
RW
2
Reserved
RO
3
No_Soft_Reset
RO
7:4
8
Reserved
PME# Enable
RO
RWS
12:9
Data Select
RW
14:13
15
Data Scale
PME status
RO
ROS
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
Indicates the current power state of the Swidge. Writing a value of D0 when
the previous state was D3 cause a hot reset without asserting DWNRST_L.
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
Reset to 0b.
When set, this bit indicates that device transitioning from D3hot to D0 does
not perform an internal reset. When clear, an internal reset is performed when
power state transits from D3hot to D0. This bit can be rewritten with
EEPROM programming. The default value may be changed by SMBus or
auto-loading from EEPROM.
Reset to 1b.
Reset to 0b.
When asserted, the Swidge will generate the PME# message. Reset to 0b.
Select data registers.
Reset to 0h.
Reset to 00b.
Read as 0b as the PME# message is not implemented.
Page 51 of 102
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PI7C9X440SL
7.2.33
PPB SUPPORT EXTENSIONS – OFFSET 84h
BIT
21:16
22
23
7.2.34
FUNCTION
Reserved
B2_B3 Support for
D3HOT
Bus Power / Clock
Control Enable
TYPE
RO
RO
DESCRIPTION
Reset to 000000b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
RO
DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
31:24
Data Register
RO
DESCRIPTION
Data Register. The default value may be changed by SMBus or auto-loading
from EEPROM.
Reset to 0b.
7.2.35
MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
7:0
7.2.36
FUNCTION
Enhanced
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 05h to indicate that this is message signal interrupt capability
register.
NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to Vendor specific capability register (A4h).
RO
Reset to A4h.
7.2.37
MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
FUNCTION
TYPE
16
MSI Enable
RW
19:17
22:20
7.2.38
Multiple Message
Capable
Multiple Message
Enable
Reset to 0b.
Read as 000b.
RO
Reset to 000b.
RW
23
64-bit address
capable
RO
31:24
Reserved
RO
DESCRIPTION
0b: The function is prohibited from using MSI to request service
1b: The function is permitted to use MSI to request service and is prohibited
from using its INTx # pin
0b: The function is not capable of generating a 64-bit message address
1b: The function is capable of generating a 64-bit message address
Reset to 1b.
Reset to 00h.
MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only)
BIT
1:0
FUNCTION
Reserved
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
DESCRIPTION
Reset to 00b.
Page 52 of 102
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PI7C9X440SL
BIT
FUNCTION
TYPE
31:2
Message Address
RW
DESCRIPTION
If the message enable bit is set, the contents of this register specify the
DWORD aligned address for MSI memory write transaction.
Reset to 0.
7.2.39
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream
Port Only)
BIT
FUNCTION
31:0
Message Upper
Address
TYPE
RW
DESCRIPTION
This register is only effective if the device supports a 64-bit message address
is set.
Reset to 00000000h.
7.2.40
MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only)
BIT
15:0
7.2.41
7.2.42
FUNCTION
Message Data
TYPE
RW
DESCRIPTION
Reset to 0000h.
VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only)
BIT
FUNCTION
7:0
Enhanced
Capabilities ID
TYPE
DESCRIPTION
Read as 03h to indicate that these are VPD enhanced capability registers.
RO
Reset to 03h.
NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only)
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to the Vendor specific capability register (A4h).
RO
Reset to A4h.
7.2.43
VPD REGISTER – OFFSET 9Ch (Upstream Port Only)
BIT
17:16
FUNCTION
Reserved
TYPE
RO
23:18
VPD Address
RW
30:24
Reserved
RO
31
VPD operation
RW
DESCRIPTION
Reset to 00b.
Contains DWORD address that is used to generate read or write cycle to the
VPD table stored in EEPROM.
Reset to 000000b.
Reset to 0000000b.
0b: Performs VPD read command to VPD table at the location as specified
in VPD address. This bit is kept ‘0’ and then set to ‘1’ automatically
after EEPROM cycle is finished
1b: Performs VPD write command to VPD table at the location as specified
in VPD address. This bit is kept ‘1’ and then set to ‘0’ automatically
after EEPROM cycle is finished.
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
7.2.44
VPD DATA REGISTER – OFFSET A0h (Upstream Port Only)
BIT
FUNCTION
31:0
VPD Data
TYPE
DESCRIPTION
When read, it returns the last data read from VPD table at the location as
specified in VPD Address.
RW
When written, it places the current data into VPD table at the location as
specified in VPD Address.
7.2.45
7.2.46
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h
BIT
FUNCTION
7:0
Enhanced
Capabilities ID
TYPE
DESCRIPTION
Read as 09h to indicate that these are vendor specific capability registers.
RO
Reset to 09h.
NEXT ITEM POINTER REGISTER – OFFSET A4h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to the SSID/SSVID capability register (C0h).
RO
Reset to C4h.
7.2.47
LENGTH REGISTER – OFFSET A4h
BIT
FUNCTION
31:16
Length Information
TYPE
RO
DESCRIPTION
The length field provides the information for number of bytes in the
capability structure (including the ID and Next pointer bytes).
Reset to 000Ch.
7.2.48
XPIP CSR0 – OFFSET A8h (Test Purpose Only)
BIT
31:0
7.2.49
TYPE
RW
DESCRIPTION
Reset to 04001060h.
XPIP CSR1 – OFFSET ACh (Test Purpose Only)
BIT
31:0
7.2.50
FUNCTION
Reserved
FUNCTION
Reserved
TYPE
RW
DESCRIPTION
Reset to 04000800h.
REPLAY TIME-OUT COUNTER – OFFSET B0h (Upstream Port)
BIT
FUNCTION
11:0
User Replay Timer
TYPE
RW
DESCRIPTION
A 12-bit register contains a user-defined value. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 000h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 54 of 102
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PI7C9X440SL
BIT
FUNCTION
12
Enable User Replay
Timer
13
14
15
Power Management
Capability Disable
MSI Capability
Disable
AER Capability
Disable
TYPE
RW
DESCRIPTION
When asserted, the user-defined replay time-out value is be employed. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
RO
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
RO
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
RO
Reset to 0b.
7.2.51
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h
BIT
FUNCTION
29:16
User ACK Latency
Timer
30
31
Enable User ACK
Latency
VGA Capability
Enable
TYPE
RW
RW
RO
DESCRIPTION
A 14-bit register contains a user-defined value. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 0.
When asserted, the user-defined ACK latency value is be employed. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to 0b.
When asserted, the VGA Capability is enabled. The value may be changed by
auto-loading from EEPROM.
Reset to 1b.
7.2.52
SWITCH OPERATION MODE – OFFSET B4h (Upstream Port)
BIT
FUNCTION
TYPE
0
Store-Forward
RW
DESCRIPTION
When set, a store-forward mode is used. Otherwise, the chip is working
under cut-through mode. The default value may be changed by SMBus
or auto-loading from EEPROM.
Reset to 0b.
Cut-through Threshold. When forwarding a packet from low-speed port
to high-speed mode, the chip provides the capability to adjust the
forwarding threshold. The default value may be changed by SMBus or
auto-loading from EEPROM.
2:1
3
Cut-through Threshold
Port Arbitration Mode
RW
RW
00b: the threshold is set at the middle of forwarding packet
01b: the threshold is set ahead 1-cycle of middle point
10b: the threshold is set ahead 2-cycle of middle point.
11b: the threshold is set ahead 3-cycle of middle point.
Reset to 01b.
When set, the round-robin arbitration will stay in the arbitrated port even
if the credit is not enough but request is pending.
When clear, the round-robin arbitration will always go to the requesting
port, which the outgoing credit is enough for the packet queued in the
port.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
BIT
FUNCTION
4
Credit Update Mode
5
TYPE
RW
Ordering on Different
Egress Port Mode
RW
Reset to 0b.
When set, there has ordering rule on packets for different egress port.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
When set, there has ordering rule between completion packet with
different tag. The default value may be changed by SMBus or autoloading from EEPROM.
6
Ordering on Different Tag of
Completion Mode
RW
7
Reserved
RO
13:8
Power management Control
Parameter
RW
14
15
RX Polarity Inversion
Disable
RO
Compliance Pattern Parity
Control Disable
DESCRIPTION
When set, the frequency of releasing new credit to the link partner will
be one credit per update.
When clear, the frequency of releasing new credit to the link partner will
be two credits per update.
The default value may be changed by SMBus or auto-loading from
EEPROM.
RO
Reset to 0b.
Reset to 0.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 000001b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
7.2.53
PHYSICAL LAYER CONTROL 0 – OFFSET B4h (Upstream Port)
BIT
FUNCTION
TYPE
20:16
Drive Amplitude Level (3P5
Nom)
RO
25:21
Reserved
RO
30:26
Reserved
RO
DESCRIPTION
Low Driver Current (LODRV). The default value may be changed by
SMBus.
Reset to10111b.
7.2.54
Reset to 01101b.
Reset to 01000b.
SWITCH OPERATION MODE – OFFSET B4h (Downstream Port)
BIT
7:0
FUNCTION
Reserved
TYPE
RO
13:8
Power Management
Control Parameter
RW
14
15
RX Polarity Inversion
Disable
Compliance Pattern
Parity Control Disable
RW
RW
DESCRIPTION
Reset to 0.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 000001b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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© Diodes Incorporated
PI7C9X440SL
7.2.55
PHYSICAL LAYER CONTROL 0 – OFFSET B4h (Downstream Port)
BIT
FUNCTION
TYPE
20:16
Drive Amplitude Level
(3P5 Nom)
RO
DESCRIPTION
It indicates the status of the strapping pin LODRV. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to10111b.
7.2.56
25:21
Reserved
RO
30:26
Reserved
RO
FUNCTION
FTS Number
Scramble control
Both L0s
Reserved
TL CSR
TYPE
RO
RO
RO
RO
RO
DESCRIPTION
Reset to 30h.
Reset to 00b.
Reset to 0b.
Reset to 0b.
Reset to 0100b.
PHYSICAL LAYER CONTROL 1 – OFFSET B8h (Test Purpose Only)
BIT
20:16
25:21
30:26
7.2.58
Reset to 01000b.
XPIP CSR2 / TL CSR – OFFSET B8h (Test Purpose Only)
BIT
7:0
9:8
10
11
15:12
7.2.57
Reset to 01101b.
FUNCTION
Drive De-Emphasis Level
Reserved
Reserved
TYPE
RO
RO
RO
DESCRIPTION
Reset to10010b.
Reset to 01110b.
Reset to 10101b.
PHYSCIAL LAYER CONTROL 2 – OFFSET BCh
BIT
3:0
6:4
7
8
10:9
12:11
15:13
16
17
18
19
21:20
FUNCTION
Transmitter PHY
Latency
Receiver Detection
Threshold
Reserved
CDR Loop
Bandwidth Enable
CDR Threshold
CDR Loop
Bandwidth Gain
Reserved
Per-Lane Main Drive
Offset Enable
(Margining)
Per-Lane Main Drive
Offset Enable
(Nominal)
Per-Lane DeEmphasis Drive
Offset Enable
(Margining)
Per-Lane DeEmphasis Drive
Offset Enable
(Nominal)
Receiver Signal
Detection
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
RO
RO
RO
RO
RO
RO
DESCRIPTION
Reset to 0111b.
Reset to 010b.
Reset to 0b.
Reset to 0b.
Reset to 11b.
Reset to 11b.
Reset to 0b.
Reset to 0b.
RO
Reset to 0b.
RO
Reset to 0b.
RO
Reset to 0b.
RO
RO
Reset to 01b.
Page 57 of 102
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PI7C9X440SL
BIT
25:22
29:26
30
31
7.2.59
RO
RO
RO
RO
DESCRIPTION
Reset to 0011b.
Reset to 0110b.
Reset to 0b.
Reset to 0b.
FUNCTION
Lane Mode
Reserved
TYPE
RW
RO
DESCRIPTION
Reset to 0
Reset to 0
SSID/SSVID CAPABILITY ID REGISTER – OFFSET C4h
BIT
7:0
7.2.61
TYPE
PHYSICAL LAYER CONTROL 3 REGISTER – OFFSET C0h
BIT
6:0
31:7
7.2.60
FUNCTION
Receiver
Equalization
Reserved
Transmitter Swing
Reserved
FUNCTION
SSID/SSVID
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 0Dh to indicate that these are SSID/SSVID capability registers.
NEXT ITEM POINTER REGISTER – OFFSET C4h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to the PCI Express capability register (E0h).
RO
Reset to E0h.
7.2.62
SUBSYSTEM VENDOR ID REGISTER – OFFSET C8h
BIT
15:0
FUNCTION
SSVID
TYPE
RO
DESCRIPTION
It indicates the sub-system vendor id. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 0000h.
7.2.63
SUBSYSTEM ID REGISTER – OFFSET C8h
BIT
31:16
FUNCTION
SSID
TYPE
RO
DESCRIPTION
It indicates the sub-system device id. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 0000h.
7.2.64
GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)
BIT
0
FUNCTION
GPIO [0] Input
1
GPIO [0] Output
Enable
TYPE
RO
RW
DESCRIPTION
State of GPIO [0] pin
0b: GPIO [0] is an input pin
1b: GPIO [0] is an output pin
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 58 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
TYPE
2
GPIO [0] Output
Register
RW
3
4
Reserved
GPIO [1] Input
RO
RO
5
GPIO [1] Output
Enable
RW
6
GPIO [1] Output
Register
RW
7
8
Reserved
GPIO [2] Input
RO
RO
9
GPIO [2] Output
Enable
RW
10
GPIO [2] Output
Register
RW
11
12
Reserved
GPIO [3] Input
RO
RO
13
GPIO [3] Output
Enable
RW
14
GPIO [3] Output
Register
RW
15
16
Reserved
GPIO [4] Input
RO
RO
17
GPIO [4] Output
Enable
RW
18
GPIO [4] Output
Register
RW
19
20
Reserved
GPIO [5] Input
RO
RO
21
GPIO [5] Output
Enable
RW
22
GPIO [5] Output
Register
RW
23
24
Reserved
GPIO [6] Input
RO
RO
25
GPIO [6] Output
Enable
RW
26
GPIO [6] Output
Register
RW
27
28
Reserved
GPIO [7] Input
RO
RO
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
Value of this bit will be output to GPIO [0] pin if GPIO [0] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [1] pin.
0b: GPIO [1] is an input pin
1b: GPIO [1] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [1] pin if GPIO [1] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [2] pin
0b: GPIO [2] is an input pin
1b: GPIO [2] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [2] pin if GPIO [2] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [3] pin.
0b: GPIO [3] is an input pin
1b: GPIO [3] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [3] pin if GPIO [3] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [4] pin.
0b: GPIO [4] is an input pin
1b: GPIO [4] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [4] pin if GPIO [4] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [5] pin.
0b: GPIO [5] is an input pin
1b: GPIO [5] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [5] pin if GPIO [5] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [6] pin.
0b: GPIO [6] is an input pin
1b: GPIO [6] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [6] pin if GPIO [6] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [7] pin.
Page 59 of 102
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© Diodes Incorporated
PI7C9X440SL
7.2.65
BIT
FUNCTION
29
GPIO [7] Output
Enable
TYPE
RW
30
GPIO [7] Output
Register
RW
31
Reserved
RO
DESCRIPTION
0b: GPIO [7] is an input pin
1b: GPIO [7] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [7] pin if GPIO [7] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only)
BIT
FUNCTION
0
EEPROM Start
TYPE
DESCRIPTION
Starts the EEPROM read or write cycle.
RW
Reset to 0b.
Sends the command to the EEPROM.
1
2
3
4
5
EEPROM Command
0b: EEPROM read
1b: EEPROM write
RW
Reset to 0b.
1b: EEPROM acknowledge was not received during the EEPROM cycle.
EEPROM Error
Status
RO
EEPROM Autoload
Success
RO
Reset to 0b.
0b: EEPROM autoload was unsuccessful or is disabled
1b: EEPROM autolad occurred successfully after RESET. Configuration
registers were loaded with values in the EEPROM
RO
It will be cleared when read at this bit.
0b: EEPROM autoload was unsuccessful or is disabled
1b: EEPROM autoload occurred successfully after PREST. Configuration
registers were loaded with values stored in the EEPROM
EEPROM Autoload
Status
EEPROM Autoload
Disable
Reset to 0b.
0b: EEPROM autoload enabled
1b: EEPROM autoload disabled
RW
Reset to 1b.
Determines the frequency of the EEPROM clock, which is derived from the
primary clock.
7:6
EEPROM Clock
Rate
00b: Reserved
01b: PEXCLK / 1024 (PEXCLK is 125MHz)
10b: Reserved
11b: Test Mode
RW
Reset to 01b.
7.2.66
EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only)
BIT
8
FUNCTION
Reserved
15:9
EEPROM Address
TYPE
RO
DESCRIPTION
Reset to 0b.
Contains the EEPROM address.
RW
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 60 of 102
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© Diodes Incorporated
PI7C9X440SL
7.2.67
EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only)
BIT
FUNCTION
31:16
EEPROM Data
TYPE
RW
DESCRIPTION
Contains the data to be written to the EEPROM. After completion of a read
cycle, this register will contain the data from the EEPROM.
Reset to 0000h.
7.2.68
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h
BIT
7:0
7.2.69
RO
DESCRIPTION
Read as 10h to indicate that these are PCI express enhanced capability
registers.
FUNCTION
Next Item Pointer
TYPE
RO
DESCRIPTION
Read as 00h. No other ECP registers.
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h
BIT
FUNCTION
19:16
Capability Version
RO
23:20
Device/Port Type
RO
24
Slot Implemented
HwInt
29:25
31:30
7.2.71
TYPE
NEXT ITEM POINTER REGISTER – OFFSET E0h
BIT
15:8
7.2.70
FUNCTION
Enhanced
Capabilities ID
Interrupt Message
Number
Reserved
TYPE
RO
RO
DESCRIPTION
Read as 0001b to indicate the device is compliant to the PCI Express Base
Specifications.
Indicates the type of PCI Express logical device.
Reset to 0101b (Upstream port).
Reset to 0110b (Downstream port).
When set, indicates that the PCIe Link associated with this Port is connected
to a slot. This field is valid for downstream port of the Swidge. The default
value may be changed by the status of strapped pin, SMBUs, or auto-loading
from EEPROM.
Read as 0b. No MSI messages are generated in the transparent mode.
Reset to 00b.
DEVICE CAPABILITIES REGISTER – OFFSET E4h
BIT
FUNCTION
2:0
Max_Payload_Size
Supported
4:3
5
Phantom Functions
Supported
Extended Tag Field
Supported
TYPE
RO
RO
RO
DESCRIPTION
Indicates the maximum payload size that the device can support for TLPs.
Each port of the Swidge supports 256 bytes max payload size. The default
value may be changed by SMBus or auto-loading from EEPROM.
Reset to 001b.
Indicates the support for use of unclaimed function numbers as Phantom
functions. Read as 00b, since the Swidge does not act as a requester.
Reset to 00b.
Indicates the maximum supported size of Tag field as a Requester. Read as 0,
since the Swidge does not act as a requester.
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 61 of 102
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PI7C9X440SL
BIT
FUNCTION
8:6
Endpoint L0s
Acceptable Latency
TYPE
RO
DESCRIPTION
Acceptable total latency that an Endpoint can withstand due to the transition
from L0s state to the L0 state. For Swidge, the ASPM software would not
check this value.
Reset to 000b.
Acceptable total latency that an Endpoint can withstand due to the transition
from L1 state to the L0 state. For Swidge, the ASPM software would not
check this value.
11:9
Endpoint L1
Acceptable Latency
RO
14:12
Reserved
RO
15
Role_Based Error
Reporting
RO
17:16
Reserved
RO
25:18
Captured Slot Power
Limit Value
RO
Reset to 000b.
Reset to 000b.
When set, indicates that the device implements the functionality originally
defined in the Error Reporting ECN. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 1b.
Reset to 00b.
It applies to Upstream Port only. In combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by slot.
This value is set by the Set_Slot_Power_Limit message or hardwired to 00h.
Reset to 00h.
It applies to Upstream Port only. Specifies the scale used for the Slot Power
Limit Value.
7.2.72
27:26
Captured Slot Power
Limit Scale
RO
31:28
Reserved
RO
This value is set by the Set_Slot_Power_Limit message or hardwired to 00b.
Reset to 00b.
Reset to 0h.
DEVICE CONTROL REGISTER – OFFSET E8h
BIT
FUNCTION
0
Correctable Error
Reporting Enable
1
2
3
4
7:5
Non-Fatal Error
Reporting Enable
Fatal Error Reporting
Enable
Unsupported Request
Reporting Enable
Enable Relaxed
Ordering
Max_Payload_Size
TYPE
RW
RW
RW
RW
RO
RW
DESCRIPTION
0b: Disable Correctable Error Reporting
1b: Enable Correctable Error Reporting
Reset to 0b.
0b: Disable Non-Fatal Error Reporting
1b: Enable Non-Fatal Error Reporting
Reset to 0b.
0b: Disable Fatal Error Reporting
1b: Enable Fatal Error Reporting
Reset to 0b.
0b: Disable Unsupported Request Reporting
1b: Enable Unsupported Request Reporting
Reset to 0b.
When set, it permits the device to set the Relaxed Ordering bit in the attribute
field of transaction. Since the Swidge can not either act as a requester or alter
the content of packet it forwards, this bit always returns ‘0’ when read.
Reset to 0b.
This field sets maximum TLP payload size for the device. Permissible values
that can be programmed are indicated by the Max_Payload_Size Supported in
the Device Capabilities register. Any value exceeding the Max_Payload_Size
Supported written to this register results into clamping to the
Max_Payload_Size Supported value.
Reset to 000b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 62 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
8
Extended Tag Field
Enable
RW
Phantom Function
Enable
RW
Auxiliary (AUX)
Power PM Enable
RWS
9
10
11
7.2.73
DESCRIPTION
Does not apply to PCI Express Swidge. Returns ‘0’ when read.
Reset to 0b.
Does not apply to PCI Express Swidge. Returns ‘0’ when read.
Reset to 0b.
When set, indicates that a device is enabled to draw AUX power independent
of PME AUX power.
RO
Reset to 0b.
When set, it permits to set the No Snoop bit in the attribute field of
transaction. Since the Swidge can not either act as a requester or alter the
content of packet it forwards, this bit always returns ‘0’ when read.
14:12
Max_Read_
Request_Size
RO
Reset to 0b.
This field sets the maximum Read Request size for the device as a Requester.
Since the Swidge does not generate read request by itself, these bits are
hardwired to 000b.
15
Reserved
RO
Reset to 000b.
Reset to 0b.
DEVICE STATUS REGISTER – OFFSET E8h
BIT
FUNCTION
TYPE
16
Correctable Error
Detected
RW1C
DESCRIPTION
Asserted when correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when non-fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when unsupported request is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device
Control register.
17
18
7.2.74
Enable No Snoop
TYPE
Non-Fatal Error
Detected
Fatal Error Detected
19
Unsupported Request
Detected
20
AUX Power
Detected
RO
21
Transactions Pending
RO
31:22
Reserved
RO
Reset to 0b.
Asserted when the AUX power is detected by the Swidge
Reset to 1b.
Each port of Swidge does not issue Non-posted Requests on its own behalf,
so this bit is hardwired to 0b.
Reset to 0b.
Reset to 0.
LINK CAPABILITIES REGISTER – OFFSET ECh
BIT
3:0
FUNCTION
Maximum Link
Speed
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
DESCRIPTION
Read as 0001b to indicate the maximum speed of the Express link is 2.5 Gb/s.
Page 63 of 102
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PI7C9X440SL
BIT
FUNCTION
9:4
Maximum Link
Width
RO
11:10
Active State Power
Management
(ASPM) Support
RO
14:12
L1 Exit
Latency
RO
18
Reserved
RO
19
Surprise Down Error
Reporting Capable
RO
Data Link Layer
Active Reporting
Capable
DESCRIPTION
Indicates the maximum width of the given PCIe Link. The width of each port
is determined by strapped pin or EEPROM pre-loaded value.
Reset to 000001b (x1) for Port 0.
Reset to 000001b (x1) for Port 1.
Reset to 000001b (x1) for Port 2.
Indicates the level of ASPM supported on the given PCIe Link. Each port of
Swidge supports L0s and L1 entry. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 01b.
Indicates the L0s exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L0s to L0 is
in the range of 256ns to less than 512ns. The default value may be changed
by SMBus or auto-loading from EEPROM.
RO
17:15
20
7.2.75
L0s Exit Latency
TYPE
Reset to 011b.
Indicates the L1 exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L1 to L0 is in
the range of 16us to less than 32us. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 000b.
Reset to 0b.
For a Downstream port, this bit must be set to 1b if the component supports
the optional capability of detecting and reporting a Surprise Down error
condition.
For Upstream Ports, which does not support this optional capability, this bit
must be hardwired to 0b.
Rest to 0b.
For a Downstream Port, this bit must be set to 1b if the component supports
the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine. For a hot-plug capable Downstream
Port, this bit must be set to 1b.
RO
For Upstream Port, this bit must be hardwired to 0b.
23:21
Reserved
R0
31:24
Port Number
RO
Reset to 0b for upstream port.
Reset to 1b for downstream ports with hot-plug capable
Reset to 000b
Indicates the PCIe Port Number for the given PCIe Link. The default value
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h for Port 0.
Reset to 01h for Port 1.
Reset to 02h for Port 2.
LINK CONTROL REGISTER – OFFSET F0h
BIT
FUNCTION
1:0
Active State Power
Management
(ASPM) Control
RW
Reserved
RO
2
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
DESCRIPTION
00b: ASPM is Disabled
01b: L0s Entry Enabled
10b: L1 Entry Enabled
11b: L0s and L1 Entry Enabled
Note that the receiver must be capable of entering L0s even when the field is
disabled.
Reset to 00b.
Reset to 0b.
Page 64 of 102
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PI7C9X440SL
BIT
FUNCTION
3
Read Completion
Boundary (RCB)
RO
Link Disable
RW
4
5
6
7.2.76
Retrain Link
Common Clock
Configuration
TYPE
Reset to 0b.
At upstream port, it is not allowed to disable the link, so this bit is hardwired
to ‘0’. For downstream ports, it disables the link when this bit is set.
Reset to 0b.
At upstream port, it is not allowed to retrain the link, so this bit is hardwired
to 0b. For downstream ports, it initiates Link Retraining when this bit is set.
RW
This bit always returns 0b when read.
0b: The components at both ends of a link are operating with asynchronous
reference clock
1b: The components at both ends of a link are operating with a distributed
common reference clock
RW
7
Extended Synch
RW
15:8
Reserved
RO
DESCRIPTION
Does not apply to PCI Express Swidge. Returns ‘0’ when read.
Reset to 0b.
When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0
state and transmits 1024 TS1 ordered sets in the L1 state for entering L0 state.
Reset to 0b.
Reset to 00h.
LINK STATUS REGISTER – OFFSET F0h
BIT
FUNCTION
19:16
Link Speed
RO
25:20
Negotiated Link
Width
RO
Training Error
RO
26
27
28
Link Training
Slot Clock
Configuration
TYPE
Reset to 0b.
When set, indicates the link training is in progress. Hardware clears this bit
once link training is complete.
Reset to 0b.
0b: the Swidge uses an independent clock irrespective of the presence of a
reference on the connector
1b: the Swidge uses the same reference clock that the platform provides on
the connector
HwInt
The default value may be changed by the status of strapped pin, SMBus, or
auto-loading from EEPROM.
Data Link Layer
Link Active
RO
31:30
Reserved
RO
Document Number DS40394 Rev 3-2
Reset to 000001b (x1).
When set, indicates a Link training error occurred.
This bit is cleared by hardware upon successful training of the link to the L0
link state.
RO
29
PI7C9X440SL
DESCRIPTION
Read as 0001b to indicate the negotiated speed of the Express link is 2.5
Gb/s.
Indicates the negotiated width of the given PCIe link.
Reset to 0b.
Indicates the status of the Data Link Control and Management State Machine.
It returns a 1b to indicate the DL_Active state, 0b otherwise.
Reset to 0b.
Reset to 00b.
Page 65 of 102
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© Diodes Incorporated
PI7C9X440SL
7.2.77
SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h
BIT
FUNCTION
0
Attention Button
Present
TYPE
RO
DESCRIPTION
When set, it indicates that an Attention Button is implemented on the chassis
for this slot. The default value may be changed by SMBus or auto-loading
from EEPROM.
Reset to 0b.
When set, it indicates that a Power Controller is implemented for this slot.
The default value may be changed by SMBus or auto-loading from
EEPROM.
1
Power Controller
Present
RO
2
Reserved
RO
3
Attention Indicator
Present
RO
Reset to 0b.
Reset to 0b.
When set, it indicates that an Attention Indicator is implemented on the
chassis for this slot. The default value may be changed by SMBus or autoloading from EEPROM.
RO
Reset to 0b.
When set, it indicates that a Power Indicator is implemented on the chassis
for this slot. The default value may be changed by SMBus or auto-loading
from EEPROM.
RO
Reset to 0b.
When set, it indicates that a device present in this slot might be removed from
the system without any prior notification. The default value may be changed
by SMBus or auto-loading from EEPROM.
4
5
Power Indicator
Present
Hot-Plug Surprise
6
Hot-Capable
14:7
Slot Power Limit
Value
HwInt
RW
16:15
Slot Power Limit
Scale
RW
18:17
Reserved
RO
31:19
Physical Slot
Number
RO
Reset to 0b.
When set, it indicates that this slot is capable of supporting Hot-Plug
operation. The default value may be changed by the status of strapped pin or
auto-loading from EEPROM.
It applies to Downstream Port only. In combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by slot. Writes to this
register also cause the Port to send the Set_Slot_Power_Limit message. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
It applies to Downstream Port only. Specifies the scale used for the Slot
Power Limit Value. Writes to this register also cause the Port to send the
Set_Slot_Power_Limit message. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 00b.
Reset to 00b.
It indicates the physical slot number attached to this Port. The default value
may be changed by SMBus or auto-loading from EEPROM.
Reset to 0.
7.2.78
SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h
BIT
FUNCTION
0
Attention Button
Pressed Enable
TYPE
RW
1
Power Fault Detected
Enable
RW
2
Reserved
RO
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
When set, it enables the generation of Hot-Plug interrupt or wakeup event on
an attention button pressed event.
Reset to 0b.
When set, it enables the generation of Hot-Plug interrupt or wakeup event on
a power fault event.
Reset to 0b.
Reset to 0b.
Page 66 of 102
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PI7C9X440SL
BIT
FUNCTION
3
Presence Detect
Changed Enable
4
5
TYPE
RW
Command
Completed Interrupt
Enable
RW
Hot-Plug Interrupt
Enable
RW
DESCRIPTION
When set, it enables the generation of Hot-Plug interrupt or wakeup event on
a presence detect changed event.
Reset to 0b.
When set, it enables the generation of Hot-Plug interrupt when the Hot-Plug
Controller completes a command.
Reset to 0b.
When set, it enables generation of Hot-Plug interrupt on enabled Hot-Plug
events.
Reset to 0b.
Controls the display of Attention Indicator.
7:6
Attention Indicator
Control
00b: Reserved
01b: On
10b: Blink
11b: Off
RW
Writes to this register also cause the Port to send the
ATTENTION_INDICATOR_* Messages.
Reset to 11b.
Controls the display of Power Indicator.
9:8
Power Indicator
Control
00b: Reserved
01b: On
10b: Blink
11b: Off
RW
Writes to this register also cause the Port to send the
POWER_INDICATOR_* Messages.
7.2.79
Reset to 11b.
0b: reset the power state of the slot (Power On)
1b: set the power state of the slot (Power Off)
10
Power Controller
Control
RW
11
Reserved
RO
12
Data Link Layer
State Changed
Enable
RW
Reset to 0b.
Reset to 0b.
If the Data Link Layer Link Active capability is implemented, when set to 1b,
this field enables software notification when Data Link Layer Link Active
field is changed.
15:13
Reserved
RO
Reset to 0b.
Reset to 000b
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h
BIT
FUNCTION
TYPE
16
Attention Button
Pressed
RW1C
Power Fault Detected
RW1C
17
18
19
20
MRL Sensor
Changed
Reset to 0b.
When set, it indicates a Power Fault is detected.
Reset to 0b.
When set, it indicates a MRL Sensor Changed is detected.
RO
Reset to 0b.
When set, it indicates a Presence Detect Changed is detected.
Presence Detect
Changed
RW1C
Command
Completed
RW1C
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
When set, it indicates the Attention Button is pressed.
Reset to 0b.
When set, it indicates the Hot-Plug Controller completes an issued command.
Reset to 0b.
Page 67 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
21
MRL Sensor State
TYPE
DESCRIPTION
Reflects the status of MRL Sensor.
0b: MRL Closed
1b: MRL Opened
RO
Reset to 0b.
Indicates the presence of a card in the slot.
0b: Slot Empty
1b: Card Present in slot
22
Presence Detect State
RO
23
Reserved
Data Link Layer
State Changed
Reserved
RO
24
31:25
7.2.80
Reset to 1b.
Reset to 0.
This bit is set when the value reported in the Data Link Layer Link Active
field of the Link Status register is changed.
Reset to 0
RW1C
RO
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID
REGISTER – OFFSET 100h
BIT
15:0
7.2.81
This register is implemented on all Downstream Ports that implement slots.
For Downstream Ports not connected to slots (where the Slot Implemented bit
of the PCI Express Capabilities register is 0b), this bit returns 1b.
FUNCTION
Extended
Capabilities ID
TYPE
DESCRIPTION
Read as 0001h to indicate that these are PCI express extended capability
registers for advance error reporting.
RO
CAPABILITY VERSION – OFFSET 100h
BIT
FUNCTION
19:16
Capability Version
TYPE
DESCRIPTION
Read as 1h. Indicates PCI-SIG defined PCI Express capability structure
version number.
RO
Reset to 1h.
7.2.82
7.2.83
NEXT ITEM POINTER REGISTER – OFFSET 100h
BIT
FUNCTION
31:20
Next Capability
Offset
TYPE
DESCRIPTION
Pointer points to the PCI Express Extended VC capability register (140h).
RO
Reset to 140h (upstream port).
Reset to 20Ch (downstream port).
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h
BIT
FUNCTION
0
Training Error Status
3:1
Reserved
4
Data Link Protocol
Error Status
11:5
Reserved
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
DESCRIPTION
When set, indicates that the Training Error event has occurred.
RW1CS
Reset to 0b.
Reset to 000b.
When set, indicates that the Data Link Protocol Error event has occurred.
RO
RW1CS
RO
Reset to 0b.
Reset to 0.
Page 68 of 102
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January 2018
© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
12
Poisoned TLP Status
13
14
15
16
17
18
19
7.2.84
TYPE
RW1CS
Reset to 0b.
When set, indicates that the Flow Control Protocol Error event has occurred.
Flow Control
Protocol Error Status
RW1CS
Completion Timeout
Status
RW1CS
Completer Abort
Status
RW1CS
Unexpected
Completion Status
RW1CS
Receiver Overflow
Status
RW1CS
Malformed TLP
Status
RW1CS
ECRC Error Status
RW1CS
20
Unsupported Request
Error Status
31:21
Reserved
DESCRIPTION
When set, indicates that a Poisoned TLP has been received or generated.
Reset to 0b.
When set, indicates that the Completion Timeout event has occurred.
Reset to 0b.
When set, indicates that the Completer Abort event has occurred.
Reset to 0b.
When set, indicates that the Unexpected Completion event has occurred.
Reset to 0b.
When set, indicates that the Receiver Overflow event has occurred.
Reset to 0b.
When set, indicates that a Malformed TLP has been received.
Reset to 0b.
When set, indicates that an ECRC Error has been detected.
Reset to 0b.
When set, indicates that an Unsupported Request event has occurred.
RW1CS
Reset to 0b.
Reset to 0.
RO
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h
BIT
FUNCTION
TYPE
0
Training Error Mask
RWS
3:1
Reserved
4
Data Link Protocol
Error Mask
11:5
Reserved
12
Poisoned TLP Mask
13
14
15
16
Flow Control
Protocol Error Mask
Completion Timeout
Mask
Completer Abort
Mask
Unexpected
Completion Mask
RO
RWS
RO
RWS
RWS
RWS
RWS
RWS
DESCRIPTION
When set, the Training Error event is not logged in the Header Log register
and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 000b.
When set, the Data Link Protocol Error event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 0.
When set, an event of Poisoned TLP has been received or generated is not
logged in the Header Log register and not issued as an Error Message to RC
either.
Reset to 0b.
When set, the Flow Control Protocol Error event is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Completion Timeout event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Completer Abort event is not logged in the Header Log register
and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Unexpected Completion event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 69 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
TYPE
17
Receiver Overflow
Mask
RWS
18
19
7.2.85
Malformed TLP
Mask
ECRC Error Mask
20
Unsupported Request
Error Mask
31:21
Reserved
RWS
RWS
RWS
DESCRIPTION
When set, the Receiver Overflow event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
When set, an event of Malformed TLP has been received is not logged in the
Header Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, an event of ECRC Error has been detected is not logged in the
Header Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Unsupported Request event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 0.
RO
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch
BIT
FUNCTION
TYPE
0
Training Error
Severity
RWS
3:1
Reserved
4
Data Link Protocol
Error Severity
11:5
Reserved
12
Poisoned TLP
Severity
13
Flow Control
Protocol Error
Severity
RWS
Completion Timeout
Error Severity
RWS
14
15
16
17
18
19
Completer Abort
Severity
Unexpected
Completion Severity
Receiver Overflow
Severity
Malformed TLP
Severity
ECRC Error Severity
RO
RWS
RO
RWS
RWS
RWS
RWS
RWS
RWS
DESCRIPTION
0b: Non-Fatal
1b: Fatal
Reset to 1b.
Reset to 000b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
Reset to 0.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
0b: Non-Fatal
1b: Fatal
Reset to 0.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 70 of 102
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© Diodes Incorporated
PI7C9X440SL
7.2.86
BIT
FUNCTION
TYPE
20
Unsupported Request
Error Severity
RWS
31:21
Reserved
DESCRIPTION
0b: Non-Fatal
1b: Fatal
Reset to 0b.
Reset to 0.
RO
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h
BIT
FUNCTION
0
Receiver Error Status
5:1
Reserved
6
Bad TLP Status
TYPE
DESCRIPTION
When set, the Receiver Error event is detected.
RW1CS
Reset to 0b.
Reset to 00000b.
When set, the event of Bad TLP has been received is detected.
RO
RW1CS
Reset to 0b.
When set, the event of Bad DLLP has been received is detected.
7.2.87
7
Bad DLLP Status
RW1CS
8
REPLAY_NUM
Rollover status
11:9
Reserved
12
Replay Timer
Timeout status
RW1CS
13
Advisory Non-Fatal
Error status
RW1CS
31:14
Reserved
Reset to 0b.
When set, the REPLAY_NUM Rollover event is detected.
RW1CS
Reset to 0b.
Reset to 000b.
When set, the Replay Timer Timeout event is detected.
RO
Reset to 0b.
When set, the Advisory Non-Fatal Error event is detected.
Reset to 0b.
Reset to 0b.
RO
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h
BIT
FUNCTION
TYPE
0
Receiver Error Mask
RWS
5:1
Reserved
6
Bad TLP Mask
7
Bad DLLP Mask
8
REPLAY_NUM
Rollover Mask
11:9
Reserved
12
Replay Timer
Timeout Mask
13
Advisory Non-Fatal
Error Mask
31:14
Reserved
PI7C9X440SL
Document Number DS40394 Rev 3-2
RO
RWS
RWS
RWS
RO
RWS
RWS
RO
DESCRIPTION
When set, the Receiver Error event is not logged in the Header Log register
and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 00000b.
When set, the event of Bad TLP has been received is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the event of Bad DLLP has been received is not logged in the
Header Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the REPLAY_NUM Rollover event is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 000b.
When set, the Replay Timer Timeout event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Advisory Non-Fatal Error event is not logged in the Header
Long register and not issued as an Error Message to RC either.
Reset to 1b.
Reset to 0.
Page 71 of 102
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© Diodes Incorporated
PI7C9X440SL
7.2.88
7.2.89
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET
118h
BIT
FUNCTION
4:0
First Error Pointer
5
ECRC Generation
Capable
RO
6
ECRC Generation
Enable
RWS
7
ECRC Check
Capable
8
ECRC Check Enable
31:9
Reserved
Reset to 00000b.
When set, it indicates the Swidge has the capability to generate ECRC.
Reset to 1b.
When set, it enables the generation of ECRC when needed.
Reset to 0b.
When set, it indicates the Swidge has the capability to check ECRC.
RO
Reset to 1b.
When set, the function of checking ECRC is enabled.
RWS
Reset to 0b.
Reset to 0.
RO
FUNCTION
1st DWORD
2nd DWORD
3rd DWORD
4th DWORD
TYPE
ROS
ROS
ROS
ROS
DESCRIPTION
Hold the 1st DWORD of TLP Header. The Head byte is in big endian.
Hold the 2nd DWORD of TLP Header. The Head byte is in big endian.
Hold the 3rd DWORD of TLP Header. The Head byte is in big endian.
Hold the 4th DWORD of TLP Header. The Head byte is in big endian.
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET
140h (Upstream Only)
BIT
15:0
7.2.91
ROS
DESCRIPTION
It indicates the bit position of the first error reported in the Uncorrectable
Error Status register.
HEADER LOG REGISTER – OFFSET From 11Ch to 128h
BIT
31:0
63:32
95:64
127:96
7.2.90
TYPE
FUNCTION
Extended
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 0002h to indicate that these are PCI express extended capability
registers for virtual channel.
CAPABILITY VERSION – OFFSET 140h (Upstream Only)
BIT
FUNCTION
19:16
Capability Version
TYPE
DESCRIPTION
Read as 1h. Indicates PCIe Base Specification compliance.
RO
Reset to 1h.
7.2.92
NEXT ITEM POINTER REGISTER – OFFSET 140h (Upstream Only)
BIT
FUNCTION
31:20
Next Capability
Offset
TYPE
RO
DESCRIPTION
Pointer points to the PCI Express Power Budgeting Capability register
(20Ch).
Reset to 20Ch.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 72 of 102
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© Diodes Incorporated
PI7C9X440SL
7.2.93
7.2.94
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h (Upstream Only)
BIT
FUNCTION
TYPE
2:0
Extended VC Count
RO
3
Reserved
RO
6:4
Low Priority
Extended VC Count
RO
7
Reserved
RO
9:8
Reference Clock
RO
11:10
Port Arbitration
Table Entry Size
RO
31:12
Reserved
RO
DESCRIPTION
It indicates the number of extended Virtual Channels in addition to the default
VC supported by the Swidge.
Reset to 000b.
Reset to 0b.
It indicates the number of extended Virtual Channels in addition to the default
VC belonging to the low-priority VC (LPVC) group. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 000b.
Reset to 0b.
It indicates the reference clock for Virtual Channels that support time-based
WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock.
Reset to 00b.
Read as 10b to indicate the size of Port Arbitration table entry in the device is
4 bits.
Reset to 10b.
Reset to 0.
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h (Upstream Only)
BIT
FUNCTION
TYPE
7:0
VC Arbitration
Capability
RO
23:8
Reserved
RO
31:24
VC Arbitration Table
Offset
RO
DESCRIPTION
It indicates the types of VC Arbitration supported by the device for the LPVC
group. This field is valid when LPVC is greater than 0. The Swidge supports
Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round
Robin arbitration with 32 phases in LPVC.
Reset to 00000000b.
Reset to 0.
It indicates the location of the VC Arbitration Table as an offset from the base
address of the Virtual Channel Capability register in the unit of DQWD (16
bytes).
Reset to 00h.
7.2.95
PORT VC CONTROL REGISTER – OFFSET 14Ch (Upstream Only)
BIT
FUNCTION
0
Load VC Arbitration
Table
TYPE
RW
3:1
VC Arbitration
Select
RW
15:4
Reserved
RO
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
When set, the programmed VC Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
This field is used to configure the VC Arbitration by selecting one of the
supported VC Arbitration schemes. The valid values for the schemes
supported by Swidge are 0b and 1b. Other value than these written into this
register will be treated as default.
Reset to 0b.
Reset to 0.
Page 73 of 102
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© Diodes Incorporated
PI7C9X440SL
7.2.96
7.2.97
PORT VC STATUS REGISTER – OFFSET 14Ch (Upstream Only)
BIT
FUNCTION
TYPE
16
VC Arbitration Table
Status
RO
DESCRIPTION
When set, it indicates that any entry of the VC Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set.
31:17
Reserved
RO
Reset to 0b.
Reset to 0.
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h (Upstream
Only)
BIT
FUNCTION
TYPE
7:0
Port Arbitration
Capability
RO
13:8
Reserved
RO
14
Advanced Packet
Switching
RO
15
Reject Snoop
Transactions
RO
22:16
Maximum Time
Slots
RO
23
Reserved
RO
31:24
Port Arbitration
Table Offset
RO
DESCRIPTION
It indicates the types of Port Arbitration supported by the VC resource. The
Swidge supports Hardware fixed arbitration scheme, e.g., Round Robin,
Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports)
and Time-based WRR with 128 phases (3~4 enabled ports).
Reset to 00001001b.
Reset to 000000b.
When set, it indicates the VC resource only supports transaction optimized
for Advanced Packet Switching (AS).
Reset to 0b.
This bit is not applied to PCIe Switch.
Reset to 0b.
It indicates the maximum numbers of time slots (minus one) are allocated for
Isochronous traffic. The default value may be changed by SMBus or autoloading from EEPROM.
Reset to 7Fh.
Reset to 0b.
It indicates the location of the Port Arbitration Table (n) as an offset from the
base address of the Virtual Channel Capability register in the unit of DQWD
(16 bytes).
Reset to 04h for Port Arbitration Table (0).
7.2.98
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h (Upstream
Only)
BIT
FUNCTION
TYPE
7:0
TC/VC Map
RW
15:8
Reserved
RO
16
Load Port Arbitration
Table
RW
19:17
Port Arbitration
Select
RW
DESCRIPTION
This field indicates the TCs that are mapped to the VC resource. Bit locations
within this field correspond to TC values. When the bits in this field are set, it
means that the corresponding TCs are mapped to the VC resource. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to FFh.
Reset to 00h.
When set, the programmed Port Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
This field is used to configure the Port Arbitration by selecting one of the
supported Port Arbitration schemes. The permissible values for the schemes
supported by Swidge are 000b and 011b at VC0, other value than these
written into this register will be treated as default.
Reset to 000b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 74 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
23:20
FUNCTION
Reserved
TYPE
RO
26:24
VC ID
RO
30:27
Reserved
RO
31
VC Enable
RW
DESCRIPTION
Reset to 0h.
This field assigns a VC ID to the VC resource.
Reset to 000b.
Reset to 0h.
0b: it disables this Virtual Channel
1b: it enables this Virtual Channel
Reset to 1b.
7.2.99
7.2.100
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h (Upstream Only)
BIT
15:0
FUNCTION
Reserved
16
Port Arbitration
Table Status
TYPE
RO
RO
17
VC Negotiation
Pending
RO
31:18
Reserved
RO
DESCRIPTION
Reset to 0000h.
When set, it indicates that any entry of the Port Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the Port Arbitration Table after the bit of “Load Port Arbitration Table” is set.
Reset to 0b.
When set, it indicates that the VC resource is still in the process of
negotiation. This bit is cleared after the VC negotiation is complete.
Reset to 0b.
Reset to 0.
PORT ARBITRATION TABLE REGISTER (0) – OFFSET 180h-1BCh
(Upstream Only)
The Port arbitration table is a read-write register array that contains a table for Port arbitration. Each
table entry allocates two bits to represent Port Number. The table entry size is dependent on the
number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arbitration table
contains 128 entries if three or four ports are to be enabled. The following table shows the register
array layout for the size of entry equal to two.
Table 7-1 Table Entry Size in 4 Bits
63 - 56
Phase
[15:14]
Phase
[31:30]
Phase
[47:46]
Phase
[63:62]
Phase
[79:78]
Phase
[95:94]
Phase
[111:110]
Phase
[127:126]
55 - 48
Phase
[13:12]
Phase
[29:28]
Phase
[45:44]
Phase
[61:60]
Phase
[77:76]
Phase
[93:92]
Phase
[109:108]
Phase
[125:124]
PI7C9X440SL
Document Number DS40394 Rev 3-2
47 - 40
Phase
[11:10]
Phase
[27:26]
Phase
[43:42]
Phase
[59:58]
Phase
[75:74]
Phase
[91:90]
Phase
[107:106]
Phase
[123:122]
39 - 32
Phase
[9:8]
Phase
[25:24]
Phase
[41:40]
Phase
[57:56]
Phase
[73:72]
Phase
[89:88]
Phase
[105:104]
Phase
[121:120]
31 - 24
Phase
[7:6]
Phase
[23:22]
Phase
[39:38]
Phase
[55:54]
Phase
[71:70]
Phase
[87:86]
Phase
[103:102]
Phase
[119:118]
Page 75 of 102
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23 - 16
Phase
[5:4]
Phase
[21:20]
Phase
[37:36]
Phase
[53:52]
Phase
[69:68]
Phase
[85:84]
Phase
[101:100]
Phase
[117:116]
15 - 8
Phase
[3:2]
Phase
[19:18]
Phase
[35:34]
Phase
[51:50]
Phase
[67:66]
Phase
[83:82]
Phase
[99:98]
Phase
[115:114]
7-0
Phase
[1:0]
Phase
[17:16]
Phase
[33:32]
Phase
[49:48]
Phase
[65:64]
Phase
[81:80]
Phase
[97:96]
Phase
[113:112]
Byte Location
00h
08h
10h
18h
20h
28h
30h
38h
January 2018
© Diodes Incorporated
PI7C9X440SL
7.2.101
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER –
OFFSET 20Ch
BIT
15:0
7.2.102
FUNCTION
Extended
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 0004h to indicate that these are PCI express extended capability
registers for power budgeting.
CAPABILITY VERSION – OFFSET 20Ch
BIT
FUNCTION
19:16
Capability Version
TYPE
DESCRIPTION
Read as 1h. Indicates PCIe Base Specification compliance.
RO
Reset to 1h.
7.2.103
7.2.104
7.2.105
NEXT ITEM POINTER REGISTER – OFFSET 20Ch
BIT
FUNCTION
31:20
Next Capability
Offset
TYPE
DESCRIPTION
Read as 000h. No other ECP registers.
RO
Reset to 000h.
DATA SELECT REGISTER – OFFSET 210h
BIT
FUNCTION
TYPE
7:0
Data Selection
RW
31:8
Reserved
RO
DESCRIPTION
It indexes the power budgeting data reported through the data register.
When 00h, it selects D0 Max power budget
When 01h, it selects D0 Sustained power budget
Other values would return zero power budgets, which means not supported
Reset to 00h.
Reset to 000000h.
POWER BUDGETING DATA REGISTER – OFFSET 214h
BIT
FUNCTION
7:0
Base Power
9:8
12:10
14:13
Data Scale
PM Sub State
PM State
TYPE
RO
RO
RO
RO
DESCRIPTION
It specifies the base power value in watts. This value represents the required
power budget in the given operation condition. The default value may be
changed by auto-loading from EEPROM.
Reset to 04h.
It specifies the scale to apply to the base power value. The default value may
be changed by auto-loading from EEPROM.
Reset to 00b.
It specifies the power management sub state of the given operation condition.
It is initialized to the default sub state.
Reset to 000b.
It specifies the power management state of the given operation condition.
It defaults to the D0 power state. The default value may be changed by autoloading from EEPROM.
Reset to 00b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 76 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
17:15
Type
TYPE
RO
DESCRIPTION
It specifies the type of the given operation condition.
It defaults to the Maximum power state. The default value may be changed by
auto-loading from EEPROM.
Reset to 111b.
It specifies the power rail of the given operation condition.
7.2.106
20:18
Power Rail
RO
31:21
Reserved
RO
Reset to 010b.
Reset to 0.
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h
BIT
FUNCTION
0
System Allocated
RO
DESCRIPTION
When set, it indicates that the power budget for the device is included within
the system power budget. The default value may be changed by auto-loading
from EEPROM.
31:1
Reserved
RO
Reset to 0b.
Reset to 0.
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
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PI7C9X440SL
7.3
USB DEVICE CONFIGURATION REGISTERS (FUNC0/FUNC1/FUNC2)
The swidge contains two Open HCI (OHCI) host controllers (function number 0 and 1) and one
Enhanced HCI (EHCI) controller (function number 2). OHCI host controllers handle full-speed and
low-speed device while EHCI host controller handles high speed device. The OHCI and EHCI host
controllers are connected to an internal PCI express port (device number 3).
The following table details the allocation of the register fields of the PCI 2.3 compatible type 0
configuration space header.
31 – 24
23 – 16
15 – 8
7–0
Vendor ID
Command
Class Code
Revision ID
Reserved
Header Type
Master Latency
Cache Line Size
Timer
Base Address Register 0
Reserved
Subsystem ID
Subsystem Vendor ID
Reserved
Capability Pointer
Reserved
Reserved
Interrupt Pin
Interrupt Line
Reserved
Port Wake Capability Register
FLADJ
SBRN
Reserved
Miscellaneous Register
Reserved
Power Management Capabilities
Next ID = 8C
Capability ID = 01
PM Data
PPB Support
Power Management Data
Message Control Register
Next ID =E0
Capability ID = 05
Low 32-bit Message Address
Message Data Register
Reserved
USB Physical Layer Control Register (USB Port 1)
USB Physical Layer Control Register (USB Port 2)
USB Physical Layer Control Register (USB Port 3)
USB Physical Layer Control Register (USB Port 4)
Reserved
PCI Express Capability Register
Next ID = 00h
Capability ID = 10
Device Capability
Device Status
Device Control
Link Capability
Link Status
Link Control
Reserved
Device ID
Status
7.3.1
BYTE OFFSET
00h
04h
08h
0Ch
10h
14h – 28h
2Ch
30h
34h
38h
3Ch
40h – 5Fh
60h
64h
68h
6Ch – 7Fh
80h
84h
8Ch
90h
94h
98h - 9Ch
A0h
A4h
A8h
ACh
B0h – DCh
E0h
E4h
E8h
ECh
F0h
F4h - FCh
VENDOR ID REGISTER – OFFSET 00h
BIT
15:0
FUNCTION
Vendor ID
TYPE
RO
DESCRIPTION
Identifies Pericom as the vendor of this device. The default value may be changed
by auto-loading from EEPROM.
Reset to 12D8h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
7.3.2
DEVICE ID REGISTER – OFFSET 00h
BIT
31:16
FUNCTION
Device ID
TYPE
RO
DESCRIPTION
Identifies this device as the PCIe to OHCI/EHCI I/O bridge. The default
value may be changed by SMBUS or auto-loading from EEPROM.
Reset to 400Eh for OHCI (Func 0 /Func 1).
Reset to 400Fh for EHCI (Func 2)
7.3.3
COMMAND REGISTER – OFFSET 04h
BIT
FUNCTION
0
I/O Space Enable
1
Memory Space
Enable
TYPE
RW
DESCRIPTION
Controls a device’s response to I/O Space accesses. A value of 0 disables the
device response. A value of 1 allows the device to respond to I/O Space
accesses.
RW
Reset to 0b.
Controls a device’s response to Memory Space accesses. A value of 0
disables the device response. A value of 1 allows the device to response to
memory Space accesses.
Reset to 0b.
Controls a device’s ability to act as a master on the PCI bus. A value of 0
disables the device from generating PCI accesses. A value of 1 allows the
device to behave as a bus master.
2
Bus Master Enable
RO
3
Special Cycle Enable
Memory Write And
Invalidate Enable
VGA Palette Snoop
Enable
RO
4
5
RO
RO
6
Parity Error
Response Enable
RW
7
Wait Cycle Control
RO
8
SERR# enable
RW
9
Fast Back-to-Back
Enable
RO
10
Interrupt Disable
RW
15:11
Reserved
RO
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Controls the device’s response to parity errors. When the bit is set, the device
must take its normal action when a parity error is detected. When the bit is 0,
the device sets its Detected Parity Error Status bit when an error is detected.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
This bit, when set, enables reporting of Non-fatal and Fatal errors detected by
the device to the Root Complex.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Controls the ability of the I/O bridge to generate INTx interrupt Messages.
7.3.4
Reset to 0b.
Reset to 00000b.
STATUS REGISTER – OFFSET 04h
BIT
18:16
FUNCTION
Reserved
19
Interrupt Status
TYPE
RO
RO
20
Capabilities List
RO
21
66MHz Capable
RO
PI7C9X440SL
Document Number DS40394 Rev 3-2
DESCRIPTION
Reset to 000b.
Indicates that an INTx interrupt Message is pending internally to the device.
Reset to 0b.
Set to 1 to enable support for the capability list (offset 34h is the pointer to the
data structure)
Reset to 1b.
Does not apply to PCI Express. Must be hardwired to 0b.
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PI7C9X440SL
BIT
22
23
24
26:25
27
28
29
7.3.5
FUNCTION
Reserved
Fast Back-to-Back
Capable
Master Data Parity
Error
DEVSEL# Timing
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
30
Signaled System
Error
31
Detected Parity
Error
TYPE
RO
DESCRIPTION
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
RO
It is not implemented. Hardwired to 0b.
RWC
RO
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a completer) whenever completing a request in the I/O bridge side
using Completer Abort Completion Status.
RWC
Reset to 0b.
It is not implemented. Hardwired to 0b.
RWC
It is not implemented. Hardwired to 0b.
RWC
Set to 1 when the I/O bridge sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Command register is 1.
RWC
Reset to 0b.
Set to 1 whenever the I/O bridge receives a Poisoned TLP.
RWC
Reset to 0b.
REVISION ID REGISTER – OFFSET 08h
BIT
7:0
FUNCTION
Revision
TYPE
RO
DESCRIPTION
Indicates revision number of the I/O bridge. The default value may be
changed by SMBUS or auto-loading from EEPROM.
Reset to 00h.
7.3.6
7.3.7
CLASS CODE REGISTER – OFFSET 08h
BIT
15:8
FUNCTION
Programming
Interface
TYPE
RO
23:16
Sub-Class Code
RO
31:24
Base Class Code
RO
DESCRIPTION
Read as 10h to indicate no programming interfaces have been defined for
OHCI controllers.
Read as 20h to indicate no programming interfaces have been defined for
EHCI controllers.
The default value may be changed by SMBUS or auto-loading from
EEPROM.
Read as 03h to indicate device is USB bus controller. The default value may
be changed by SMBUS or auto-loading from EEPROM.
Read as 0Ch to indicate device is a serial bus controller. The default value
may be changed by SMBUS or auto-loading from EEPROM.
CACHE LINE REGISTER – OFFSET 0Ch
BIT
FUNCTION
7:0
Cache Line Size
TYPE
RW
DESCRIPTION
The cache line size register is set by the system firmware and the operating
system to system cache line size. This field is implemented by PCI Express
devices as a RW field for legacy compatibility purposes but has no impact on
any PCI Express device functionality.
Reset to 00h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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PI7C9X440SL
7.3.8
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch
BIT
15:8
7.3.9
TYPE
RO
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 00h.
HEADER TYPE REGISTER – OFFSET 0Ch
BIT
23:16
7.3.10
FUNCTION
Latency timer
FUNCTION
Header Type
TYPE
RO
DESCRIPTION
Read as 80h to indicate it is a multi-function device.
BASE ADDRESS REGISTER 0 – OFFSET 10h (Func 0 and Func 1)
BIT
11:0
FUNCTION
Base Address 0
TYPE
RO
31:12
Base Address 0
RW
DESCRIPTION
Reset to 000h.
Use this I/O base address to map the OHCI registers.
Reset to 00000h.
7.3.11
BASE ADDRESS REGISTER 0 – OFFSET 10h (Func 2 Only)
BIT
7:0
FUNCTION
Base Address 0
TYPE
RO
31:8
Base Address 0
RW
DESCRIPTION
Reset to 00h.
Use this I/O base address to map the EHCI registers.
Reset to 000000h.
7.3.12
SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch
BIT
FUNCTION
15:0
Sub Vendor ID
TYPE
RO
DESCRIPTION
Indicates the sub-system vendor id. The default value may be changed by
SMBUS or auto-loading from EEPROM.
Reset to 12D8h.
7.3.13
SUBSYSTEM ID REGISTER – OFFSET 2Ch
BIT
FUNCTION
31:16
Sub System ID
TYPE
DESCRIPTION
Indicates the sub-system device id. The default value may be changed by
SMBUS or auto-loading from EEPROM.
RO
Reset to 400Eh for OHCI (Func 0 /Func 1)
Reset to 400Fh for EHCI (Func 2)
7.3.14
CAPABILITIES POINTER REGISTER – OFFSET 34h
BIT
FUNCTION
7:0
Capabilities Pointer
TYPE
RO
DESCRIPTION
This optional register points to a linked list of new capabilities implemented
by the device. This default value may be changed by SMBUS or auto-loading
from EEPROM.
The default value is 80h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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© Diodes Incorporated
PI7C9X440SL
7.3.15
INTERRUPT LINE REGISTER – OFFSET 3Ch
BIT
7:0
FUNCTION
Interrupt Line
TYPE
RW
DESCRIPTION
Used to communicate interrupt line routing information. POST software will
write the routing information into this register as it initializes and configures
the system.
Reset to 00h.
7.3.16
7.3.17
7.3.18
INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
15:8
Interrupt Pin
RO
Reset to 01h for Func 0.
Reset to 02h for Func 1
Reset to 03h for Func 2
SERIAL BUS RELEASE NUMBER REGISTER – OFFSET 60h (Func 2 Only)
BIT
FUNCTION
7:0
Serial Bus Release
Number
TYPE
DESCRIPTION
Release Number. All other combinations are reserved.
RO
Reset to 20h
FRAME LENGTH ADJUSTMENT REGISTER – OFFSET 60h (Func 2 Only)
BIT
FUNCTION
13:8
Frame Length
Adjustment
15:14
7.3.19
DESCRIPTION
Identifies the legacy interrupt Message(s) the device uses.
Reserved
TYPE
RW
RO
DESCRIPTION
Frame Length Timing Value. Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF
counter clock periods to generate a SOF micro-frame length) is equal to 59488 +
value in this field. The default value is 32 (20h), which gives a SOF cycle time of
6000.
Frame Length
(# High Speed bit times)
(decimal)
59488
59504
59520
…
59984
60000
…
60480
60496
FLADJ Value
(Decimal)
0 (00h)
1 (01h)
2 (02h)
31 (1Fh)
32 (20h)
62 (3Eh)
63 (3Fh)
Reset to 20h
Reset to 0
PORT WAKE CAPABILITY REGISTER – OFFSET 60h (Func 2 Only)
BIT
FUNCTION
20:16
Port Wake
Capability Mask
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RW
DESCRIPTION
Bit position zero of this register indicates whether the register is implemented. A
one in bit position zero indicates that the register is implemented. Bit positions 1
through 4 correspond to a physical port implemented on this host controller. For
example, bit position 1 corresponds to port 1, position 2 to port 2, etc.
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PI7C9X440SL
7.3.20
BIT
FUNCTION
31:21
Reserved
TYPE
DESCRIPTION
Reset to Fh
Reset to 0
RO
MISCELLANEOUS REGISTER – OFFSET 68h (Func 2 Only)
BIT
FUNCTION
0
Enable Basic Mode
1
Enable Boundary 64-byte
TYPE
RW
RW
2
Enable EHCI Prefetch
RW
3
Reserved
RW
4
Enable User
Max_Read_Request_Size
RW
DESCRIPTION
When set, only one USB controller will active at the same time. Otherwise,
all USB controllers allow active at the same time. The default value may be
changed by SMBUS or auto-loading from EEPROM.
Reset to 0b.
When set, the max_read_request_size is set to 64 byte. The default value
may be changed by SMBUS or auto-loading from EEPROM.
Reset to 0b.
When set, EHCI will enable the prefetect function. The default value may
be changed by SMBUS or auto-loading from EEPROM.
Reset to 0b.
Reset to 0b.
When set, the user-defined max_read_request_size value is employed. The
default value may be changed by SMBUS or auto-loading from EEPROM.
Reset to 0b.
A 2-bit register contains a user-defined value. The default value may be
changed by SMBUS or auto-loading from EEPROM.
7.3.21
User
Max_Read_Request_Size
RW
7
Reserved
RO
14:8
Prefetch DW Size
RW
Reset to 00b.
Reset to 0
A 7-bit register contains a user-defined value for the prefetch size and the
unit is dword. The default value may be changed by SMBUS or autoloading from EEPROM.
15
31:16
Reserved
Reserved
RW
RO
Reset to 10h.
Reset to 1b.
Reset to 0000h.
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
BIT
7:0
7.3.22
00b: 128 byte
01b: Reserved
10b: Reserved
11b: Reserved
6:5
FUNCTION
Enhanced
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 01h to indicate that these are power management enhanced capability
registers.
NEXT ITEM POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
RO
DESCRIPTION
The pointer points to the Message capability register (8Ch). The default value
may be changed by SMBUS or auto-loading from EEPROM.
Reset to 8Ch.
PI7C9X440SL
Document Number DS40394 Rev 3-2
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© Diodes Incorporated
PI7C9X440SL
7.3.23
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
BIT
18:16
19
20
7.3.24
FUNCTION
Power Management
Revision
PME# Clock
Reserved
TYPE
DESCRIPTION
Read as 011b to indicate the I/O bridge is compliant to Revision 1.1 of PCI
Power Management Interface Specifications.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Read as 0b to indicate the I/O bridge does not have device specific
initialization requirements. The default value may be changed by SMBUS or
auto-loading from EEPROM.
Reset as 111b to indicate the I/O bridge need 375 mA in D3 state. The default
value may be changed by SMBUS or auto-loading from EEPROM.
Read as 1b to indicate the I/O bridge supports the D1 power management
state. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Read as 1b to indicate the I/O bridge supports the D2 power management
state. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Read as 11111b to indicate the I/O bridge supports the forwarding of PME#
message in all power states. The default value may be changed by SMBUS or
auto-loading from EEPROM.
RO
RO
RO
21
Device Specific
Initialization
RO
24:22
AUX Current
RO
25
D1 Power State
Support
RO
26
D2 Power State
Support
RO
31:27
PME# Support
RO
POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
1:0
Power State
RW
2
Reserved
RO
3
No_Soft_Reset
RO
7:4
Reserved
RO
8
PME# Enable
RW
DESCRIPTION
Indicates the current power state of the I/O bridge. Writing a value of D0
causes a hot reset without asserting PEREST_L when the previous state was
D3.
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
Read as 0b.
When set, this bit indicates that I/O bridge transitioning from D3hot to D0
does not perform an internal reset.
When clear, an internal reset is performed when power state transits from
D3hot to D0. The default value may be changed by SMBUS or auto-loading
from EEPROM.
Reset to 1b.
Read as 0h.
When asserted, the I/O bridge will generate the PME# message.
Reset to 0b.
Select data registers.
12:9
Data Select
RW
14:13
Data Scale
RO
15
PME status
RWC /
RO
Reset to 0h.
Read as 00b.
Indicates that the PME# message is pending internally to the I/O bridge for
Func 0 and Func 1.
This bit is reserved for Func 2 and always read as 0.
Reset to 0b (RWC) for OHCI (Func 0 /Func 1).
Read as 0b (RO) for EHCI (Func 2)
PI7C9X440SL
Document Number DS40394 Rev 3-2
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© Diodes Incorporated
PI7C9X440SL
7.3.25
PPB SUPPORT EXTENSIONS – OFFSET 84h
BIT
21:16
22
23
7.3.26
FUNCTION
Reserved
B2_B3 Support for
D3HOT
Bus Power / Clock
Control Enable
TYPE
RO
RO
DESCRIPTION
Reset to 000000b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
RO
PM DATA REGISTER – OFFSET 84h
BIT
FUNCTION
31:24
PM Data Register
TYPE
DESCRIPTION
PM Data Register.
RO
Reset to 00h
7.3.27
MESSAGE SIGNALED INTERRUPT (MSI) Capability ID Register 8Ch
BIT
FUNCTION
TYPE
7:0
Enhanced
Capability ID
RO
DESCRIPTION
Read as 05h to indicate that this is Message Signaled Interrupt capability
register.
The MSI Function is not implemented on this device.
7.3.28
MESSAGE SIGNALED INTERRUPT (MSI) NEXT ITEM POINTER 8Ch
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
RO
DESCRIPTION
The pointer points to the PCI Express capability register (E0h). The default
value may be changed by SMBUS or auto-loading from EEPROM.
Reset to E0h.
7.3.29
MESSAGE CONTROL REGISTER – OFFSET 8Ch
BIT
FUNCTION
TYPE
16
MSI Enable
RW
RO
Multiple Message
Enable
RW
23
64-bit address
capable
RO
31:24
Reserved
RO
22:20
7.3.30
Reset to 0b.
The MSI Function is not implemented on this device.
Multiple Message
Capable
19:17
DESCRIPTION
The MSI Function is not implemented on this device.
Read as 000b.
The MSI Function is not implemented on this device.
Reset to 000b.
The MSI Function is not implemented on this device.
Reset to 0b.
Reset to 00h.
MESSAGE ADDRESS REGISTER – OFFSET 90h
BIT
1:0
FUNCTION
Reserved
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
DESCRIPTION
Reset to 00b.
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PI7C9X440SL
BIT
FUNCTION
TYPE
31:2
Message Address
RW
DESCRIPTION
The MSI Function is not implemented on this device.
Reset to 0.
7.3.31
MESSAGE DATA REGISTER – OFFSET 94h
BIT
FUNCTION
TYPE
15:0
Message Data
RW
DESCRIPTION
The MSI Function is not implemented on this device.
Reset to 0000h.
7.3.32
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 1) – OFFSET
A0h
BIT
0
2:1
4:3
8:5
10:9
12:11
15:13
17:16
19:18
21:20
23:22
7.3.33
FUNCTION
PMOS Strength for
HS Driver Timing
Control
NMOS Strength for
HS Driver Timing
Control
HS Driver
Amplitude
HS Driver Slope
Control
Reference Voltage
for Disconnect
Circuit
Reference Voltage
for Squelch Circuit
Reference Voltage
for Calibration
Circuit
Charge Pump
Current for PLL
FS Rise/Fall Time
Control
LS Rise/Fall Time
Control
HS Driver PreEmphasis
TYPE
RO
DESCRIPTION
Reset to 0b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 0000b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
RO
RO
RO
RO
RO
RO
RO
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 100b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 2) – OFFSET
A4h
BIT
0
2:1
4:3
8:5
10:9
FUNCTION
PMOS Strength for
HS Driver Timing
Control
NMOS Strength for
HS Driver Timing
Control
HS Driver
Amplitude
HS Driver Slope
Control
Reference Voltage
for Disconnect
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
DESCRIPTION
Reset to 0b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 0000b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
RO
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PI7C9X440SL
BIT
12:11
15:13
17:16
19:18
21:20
23:22
7.3.34
TYPE
RO
RO
RO
RO
RO
RO
DESCRIPTION
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 100b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 3) – OFFSET
A8h
BIT
0
2:1
4:3
8:5
10:9
12:11
15:13
17:16
19:18
21:20
23:22
7.3.35
FUNCTION
Circuit
Reference Voltage
for Squelch Circuit
Reference Voltage
for Calibration
Circuit
Charge Pump
Current for PLL
FS Rise/Fall Time
Control
LS Rise/Fall Time
Control
HS Driver PreEmphasis
FUNCTION
PMOS Strength for
HS Driver Timing
Control
NMOS Strength for
HS Driver Timing
Control
HS Driver
Amplitude
HS Driver Slope
Control
Reference Voltage
for Disconnect
Circuit
Reference Voltage
for Squelch Circuit
Reference Voltage
for Calibration
Circuit
Charge Pump
Current for PLL
FS Rise/Fall Time
Control
LS Rise/Fall Time
Control
HS Driver PreEmphasis
TYPE
RO
DESCRIPTION
Reset to 0b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 0000b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
RO
RO
RO
RO
RO
RO
RO
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 100b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
USB PHYSICAL LAYER CONTROL REGISTER (USB PORT 4) – OFFSET
ACh
BIT
0
2:1
4:3
8:5
FUNCTION
PMOS Strength for
HS Driver Timing
Control
NMOS Strength for
HS Driver Timing
Control
HS Driver
Amplitude
HS Driver Slope
Control
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
DESCRIPTION
Reset to 0b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 0000b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
RO
Page 87 of 102
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PI7C9X440SL
BIT
10:9
12:11
15:13
17:16
19:18
21:20
23:22
7.3.36
7.3.37
FUNCTION
Reference Voltage
for Disconnect
Circuit
Reference Voltage
for Squelch Circuit
Reference Voltage
for Calibration
Circuit
Charge Pump
Current for PLL
FS Rise/Fall Time
Control
LS Rise/Fall Time
Control
HS Driver PreEmphasis
TYPE
RO
DESCRIPTION
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
Reset to 10b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 100b. The default value may be changed by SMBUS or auto-loading
from EEPROM.
RO
RO
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 01b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
Reset to 00b. The default value may be changed by SMBUS or auto-loading from
EEPROM.
RO
RO
RO
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h
BIT
FUNCTION
7:0
Enhanced
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 10h to indicate that these are PCI express enhanced capability
registers. The default value may be changed by SMBUS or auto-loading from
EEPROM.
NEXT ITEM POINTER REGISTER – OFFSET E0h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
RO
DESCRIPTION
Read as 00h. No other ECP registers. The default value may be changed by
SMBUS or auto-loading from EEPROM.
Reset to 00h.
7.3.38
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h
BIT
FUNCTION
19:16
Capability Version
RO
23:20
Device/Port Type
RO
24
Slot Implemented
Interrupt Message
Number
Reserved
RO
29:25
31:30
7.3.39
TYPE
RO
RO
DESCRIPTION
Read as 0001b to indicate the I/O bridge is compliant to Revision 1.0a of PCI
Express Base Specifications. The default value may be changed by SMBUS
or auto-loading from EEPROM.
Indicates the type of Legacy PCI Express Endpoint device. The default value
may be changed by SMBUS or auto-loading from EEPROM.
Reset to 1h.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 00000b.
Reset to 00b.
DEVICE CAPABILITIES REGISTER – OFFSET E4h
BIT
FUNCTION
2:0
Max_Payload_Size
Supported
TYPE
RO
DESCRIPTION
Indicates the maximum payload size that the I/O bridge can support for TLPs.
The I/O bridge supports 256 bytes max payload size. The default value may be
changed by SMBUS or auto-loading from EEPROM.
Reset to 001b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 88 of 102
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PI7C9X440SL
BIT
4:3
5
8:6
11:9
12
13
14
FUNCTION
Phantom Functions
Supported
Extended Tag Field
Supported
Endpoint L0s
Acceptable Latency
Endpoint L1
Acceptable Latency
Attention Button
Present
Attention Indicator
Present
Power Indicator
Present
TYPE
RO
RO
DESCRIPTION
It is not implemented. Hardwired to 00b.
It is not implemented. Hardwired to 0b.
RO
Acceptable total latency that an Endpoint can withstand due to the transition
from L0s state to the L0 state. The default value may be changed by SMBUS or
auto-loading from EEPROM.
RO
Reset to 000b.
Acceptable total latency that an Endpoint can withstand due to the transition
from L1 state to the L0 state. The default value may be changed by SMBUS or
auto-loading from EEPROM.
RO
RO
RO
15
Role_Base Error
Reporting
RO
17:16
Reserved
RO
25:18
Captured Slot Power
Limit Value
RO
Reset to 000b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
When set, indicated that the device implements the functionality originally
defined in the Error Reporting ECN. The default value may be changed by
SMBUS or auto-loading from EEPROM.
Reset to 1b.
Reset to 00b.
In combination with the Slot Power Limit Scale value, specifies the upper limit
on power supplied by slot.
This value is set by the Set_Slot_Power_Limit message or hardwired to “00h”.
The default value may be changed by SMBUS or auto-loading from EEPROM.
Reset to 00b.
Specifies the scale used for the Slot Power Limit Value.
7.3.40
27:26
Captured Slot Power
Limit Scale
RO
31:28
Reserved
RO
This value is set by the Set_Slot_Power_Limit message or hardwired to “00b”.
The default value may be changed by SMBUS or auto-loading from EEPROM.
Reset to 00b.
Reset to 0h.
DEVICE CONTROL REGISTER – OFFSET E8h
BIT
FUNCTION
0
Correctable Error
Reporting Enable
1
2
3
Non-Fatal Error
Reporting Enable
Fatal Error
Reporting Enable
Unsupported
Request Reporting
Enable
TYPE
RW
DESCRIPTION
0b: Disable Correctable Error Reporting.
1b: Enable Correctable Error Reporting.
The default value may be changed by SMBUS or auto-loading from EEPROM.
RW
Reset to 0b.
0b: Disable Non-Fatal Error Reporting.
1b: Enable Non-Fatal Error Reporting.
The default value may be changed by SMBUS or auto-loading from EEPROM.
RW
Reset to 0b.
0b: Disable Fatal Error Reporting.
1b: Enable Fatal Error Reporting.
The default value may be changed by SMBUS or auto-loading from EEPROM.
RW
Reset to 0b.
0b: Disable Unsupported Request Reporting.
1b: Enable Unsupported Request Reporting.
The default value may be changed by SMBUS or auto-loading from EEPROM.
Reset to 0b.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 89 of 102
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PI7C9X440SL
BIT
4
7:5
8
9
10
11
14:12
15
7.3.41
Max_Payload_Size
Extended Tag Field
Enable
Phantom Function
Enable
Auxiliary (AUX)
Power PM Enable
Enable No Snoop
Max_Read_
Request_Size
Reserved
TYPE
DESCRIPTION
RW
Reset to 1b.
This field sets maximum TLP payload size for the device. Permissible values
that can be programmed are indicated by the Max_Payload_Size Supported in
the Device Capabilities register. Any value exceeding the Max_Payload_Size
Supported written to this register results into clamping to the Max_Payload_Size
Supported value. The default value may be SMBUS or changed by auto-loading
from EEPROM.
RW
Reset to 000b.
It is not implemented. Hardwired to 0b.
RO
It is not implemented. Hardwired to 0b.
RO
RO
When set, indicates that the I/O bridge is enabled to draw AUX power
independent of PME AUX power. The default value may be changed by
SMBUS or auto-loading from EEPROM.
RO
Reset to 0b.
It is not implemented. Hardwired to 0b.
RO
Reset to 000b.
Reset to 0b.
RO
DEVICE STATUS REGISTER – OFFSET E8h
BIT
FUNCTION
TYPE
16
Correctable Error
Detected
RW1C
DESCRIPTION
Asserted when correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when non-fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when unsupported request is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device
Control register.
17
18
7.3.42
FUNCTION
Enable Relaxed
Ordering
Non-Fatal Error
Detected
Fatal Error Detected
19
Unsupported Request
Detected
20
AUX Power
Detected
RO
21
31:22
Transactions Pending
Reserved
RO
RO
Reset to 0b.
Asserted when the AUX power is detected by the I/O bridge
Reset to 1b.
It is not implemented. Hardwired to 0b.
Reset to 000h.
LINK CAPABILITIES REGISTER – OFFSET ECh
BIT
FUNCTION
3:0
Maximum Link
Speed
TYPE
DESCRIPTION
Indicates the Maximum Link Speed of the given PCIe Link.
RO
Defined encodings are: 0001b, which indicates 2.5 Gb/s Link
Reset to 1h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 90 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
9:4
Maximum Link
Width
RO
Active State Power
Management
(ASPM) Support
RO
11:10
14:12
7.3.43
L1 Exit
Latency
RO
23:18
31:24
Reserved
Port Number
RO
RO
DESCRIPTION
Indicates the maximum width of the given PCIe Link.
Reset to 000001b (x1).
Indicates the level of ASPM supported on the given PCIe Link. The I/O
bridge supports L0s and L1 entry. The default value may be changed by
SMBUS or auto-loading from EEPROM.
Reset to 01b.
Indicates the L0s exit latency for the given PCIe Link. The length of time this
I/O bridge requires to complete transition from L0s to L0 is in the range of
256ns to less than 512ns. The default value may be changed by SMBUS or
auto-loading from EEPROM.
RO
17:15
Reset to 011b.
Indicates the L1 exit latency for the given PCIe Link. The length of time this
I/O bridge requires to complete transition from L1 to L0 is in the range of
16us to less than 32us. The default value may be changed by SMBUS or autoloading from EEPROM.
Reset to 000b.
Reset to 00000b.
It is not implemented. Hardwired to 00h.
LINK CONTROL REGISTER – OFFSET F0h
BIT
FUNCTION
1:0
Active State Power
Management
(ASPM) Control
2
3
4
5
6
7.3.44
L0s Exit Latency
TYPE
Reserved
Read Completion
Boundary (RCB)
Link Disable
Retrain Link
Common Clock
Configuration
TYPE
DESCRIPTION
00b: ASPM is Disabled.
01b: L0s Entry Enabled.
10b: L1 Entry Enabled.
11b: L0s and L1 Entry Enabled.
RW
Note that the receiver must be capable of entering L0s even when the field is
disabled.
Reset to 00b.
Reset to 0h.
It is not implemented. Hardwired to 0b.
RO
RO
RW
RW
Reset to 0b.
Reset to 0b.
0b: The components at both ends of a link are operating with asynchronous
reference clock.
1b: The components at both ends of a link are operating with a distributed
common reference clock.
RW
7
Extended Synch
RW
15:8
RsvdP
RO
Reset to 0b.
When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0
state and transmits 1024 TS1 ordered sets in the L1 state for entering L0 state
Reset to 0b.
Reset to 00h.
LINK STATUS REGISTER – OFFSET F0h
BIT
FUNCTION
19:16
Link Speed
TYPE
DESCRIPTION
Indicates the negotiated Link Speed of the given PCIe Link.
RO
Defined encodings are: 0001b, which indicates 2.5 Gb/s Link
Reset to 1h.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 91 of 102
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© Diodes Incorporated
PI7C9X440SL
BIT
FUNCTION
25:20
Negotiated Link
Width
RO
Training Error
RO
26
27
28
31:29
Link Training
Slot Clock
Configuration
Reserved
PI7C9X440SL
Document Number DS40394 Rev 3-2
TYPE
RO
RO
RO
DESCRIPTION
Indicates the negotiated width of the given PCIe Link,
Reset to 000001b.
When set, indicates a Link training error occurred.
This bit is cleared by hardware upon successful training of the link to the L0
link state.
Reset to 0b.
When set, indicates the link training is in progress. Hardware clears this bit
once link training is complete.
Reset to 0b.
It is not implemented. Hardwired to 0b.
Reset to 000b.
Page 92 of 102
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PI7C9X440SL
8 CLOCK SCHEME
8.1
PCI EXPRESS INTERFACE
The PCI Express interface of PI7C9X440SL requires 100MHz differential clock inputs through REFCLKP and
REFCLKN Pins as shown in the following table.
Table 8-1 Input Clock Requirements for PCI Express Interface
Parameter
Symbol
Min
Max.
Unit
Reference Frequency(1)
fj
83.3
312.5
MHz
Accuracy
Aj
-300
+300
ppm
Duty Cycle
DCj
45
55
%
> 1.5 MHz to Nyquist RMS jitter after
TREFCLK-HF-RMS
3.1
ps RMS
applying PCIe filter function
10 KHz – 1.5 MHz RMS jitter
TREFCLK-LF-RMS
3.0
ps RMS
Spread Spectrum Clock frequency
SSCfreq
30
33
KHz
(1) Does not include ±300ppm. Only certain clock frequencies will produce valid PCI Express data.
(2) Specified as per PCI Express Card Electromechanical specification, Rev 1.1.
8.2
USB INTERFACE
PI7C9X440SL requires an external 12 MHz crystal or oscillator of ±60ppm tolerance.
Table 8-2 Input Clock Requirements for USB Interface
Parameter
Clock deviation
Rise/fall time
Jitter (peak-to-peak)
Jitter (peak-to-peak)
Duty-cycle
PI7C9X440SL
Document Number DS40394 Rev 3-2
Condition
Min
-150
1.2MHz
0
0
40
Page 93 of 102
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Typ.
Max.
150
200
50
100
60
Unit
ppm
ps
ps
ps
%
January 2018
© Diodes Incorporated
PI7C9X440SL
9 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support
boundary scan in PI7C9X440SL for board-level continuity test and diagnostics. The TAP pins assigned are TCK,
TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins.
9.1
INSTRUCTION REGISTER
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers
including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the
Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to
ensure the machine is in TEST_LOGIC_RESET state at power-up.
PI7C9X440SL implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined
instruction codes are shown in the following table. Those bit combinations that are not listed are equivalent to the
BYPASS (11111) instruction:
Table 9-1 Instruction Register Codes
Instruction
EXTEST
SAMPLE
HIGHZ
CLAMP
9.2
Operation Code (binary)
00000
00001
00101
00100
Register Selected
Boundary Scan
Boundary Scan
Bypass
Bypass
IDCODE
01100
Device ID
BYPASS
INT_SCAN
MEM_BIST
11111
00010
01010
Bypass
Internal Scan
Memory BIST
Operation
Drives / receives off-chip test data
Samples inputs / pre-loads outputs
Tri-states output and I/O pins except TDO pin
Drives pins from boundary-scan register and selects Bypass
register for shifts
Accesses the Device ID register, to read manufacturer ID, part
number, and version number
Selected Bypass Register
Scan test
Memory BIST test
BYPASS REGISTER
The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a
bypass instruction is in effect. This allows rapid movement of test data to and from other components on the
board. This path can be selected when no test operation is being performed on the PI7C9X440SL.
9.3
DEVICE ID REGISTER
This register identifies Pericom as the manufacturer of the device and details the part number and revision
number for the device.
Table 9-2 JTAG Device ID Register
Bit
31-28
27-12
11-1
0
Type
RO
RO
RO
RO
PI7C9X440SL
Document Number DS40394 Rev 3-2
Value
0001
1001001000000100
01000111111
1
Description
Version number
Last 4 digits (hex) of the die part number
Pericom identifier assigned by JEDEC
Fixed bit equal to 1’b1
Page 94 of 102
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PI7C9X440SL
9.4
BOUNDARY SCAN REGISTER
The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by
connected the internal signal of the PI7C9X440SL package pins. The VDD, VSS, and JTAG pins are not in
the boundary scan chain. The input to the shift register is TDI and the output from the shift register is TDO.
There are 4 different types of boundary scan cells, based on the function of each signal pin.
The boundary scan register cells are dedicated logic and do not have any system function. Data may be
loaded into the boundary scan register master cells from the device input pins and output pin-drivers in
parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising
edge of TCK.
9.5
JTAG BOUNDARY SCAN REGISTER ORDER
Table 9-3 JTAG Boundary Scan Register Definition
Boundary Scan
Register Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PI7C9X440SL
Document Number DS40394 Rev 3-2
Pin Name
TEST5
IRQ1_I
IRQ12_I
IRQ1_O
Pin No
114
16
17
18
IRQ12_O
LEG_EMU_EN
SMBCLK
SMBDATA
TEST3
TEST6
GPIO[0]
19
20
21
64
65
66
69
GPIO[1]
70
GPIO[2]
71
GPIO[3]
72
GPIO[4]
73
GPIO[5]
74
GPIO[6]
75
GPIO[7]
76
TEST4
77
EECLK
EEPD
99
98
PERST_L
104
MAIN_DETECT
24
TEST1
1
Page 95 of 102
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Type
Input
Bidir
Bidir
Bidir
Control
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Internal
Internal
Internal
Output2
Bidir
Control
Input
Internal
Internal
Internal
Input
Internal
Internal
Bidir
Tri-state Control Cell
4
4
4
4
4
4
4
4
4
4
12
14
16
18
20
22
24
26
4
33
4
January 2018
© Diodes Incorporated
PI7C9X440SL
Boundary Scan
Register Number
42
43
44
45
46
47
48
49
50
51
52
53
PI7C9X440SL
Document Number DS40394 Rev 3-2
Pin Name
Pin No
IO_HIT_I
OCI[1]
OCI[2]
OCI[3]
OCI[4]
POE[1]
POE[2]
POE[3]
POE[4]
SMI_O
3
4
5
6
7
10
11
12
13
14
Page 96 of 102
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Type
Internal
Bidir
Input
Input
Input
Input
Bidir
Bidir
Bidir
Bidir
Bidir
Internal
Tri-state Control Cell
4
4
4
4
4
4
January 2018
© Diodes Incorporated
PI7C9X440SL
10 POWER MANAGEMENT
10.1 PCI EXPRESS POWER STATES
The PI7C9X440SL implements a full set of PCI Express power management capabilities including full support for
D0, D1, D2, D3-hot, and D3-cold Power States. The PCI Express Physical Link Layer of the PI7C9X440SL device
supports the PCI Express Link Power Management with L0, L0s, L1, L2/L3 ready and L3 Power States.
During the transition from D3-hot to D3-cold state, the main power supplies of VDDC and VDDR are turned off to
save power. PI7C9X440SL has been designed to have sticky registers that are powered by auxiliary power supplies.
PI7C9X440SL forwards power management messages to the upstream Switches or root complex.
PI7C9X440SL also supports ASPM (Active State Power Management) to facilitate the link power saving and PME
messaging.
10.2 USB POWER STATES
The EHCI Host Controller implements power management states compliant to PCI Bus Power Management
Interface Specification, Revision 1.1 including D0, D1, D2, and D3-hot.
The OHCI Host Controller implements the following power states via the operational registers: USB_Reset,
USB_Operational, USB_Suspend and USB_Resume. These states define the Host Controller’s responsibilities
relating to USB signaling and bus states. The OHCI Host Controller asserts the Power Management Event signal
(PME_L) whenever the power state is resumed to Operational State from Suspend State.
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 97 of 102
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PI7C9X440SL
11 ELECTRICAL AND TIMING SPECIFICATIONS
11.1 ABSOLUTE MAXIMUM RATINGS
Table 11-1 Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Item
Storage Temperature
Junction Temperature, Tj
Digital core and analog supply voltage to ground potential (VDDC and AVDD)
Digital I/O and analog high supply voltage to ground potential (VDDR, VDDA and AVDDH)
DC input voltage for Digital I/O signals
Absolute Max. Rating
-65oC to 150oC
125 oC
-0.3v to 1.2v
-0.3v to 3.8v
-0.3v to 3.8v
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
11.2 Operating Ambient Temperature
Table 11-2 Operating Ambient Temperature
(Above witch the useful life may be impaired.)
Item
Low
High
Unit
o
Ambient Temperature with power applied
-40
85
C
Note: Exposure to high temperature conditions for extended periods of time may affect reliability.
11.3 POWER CONSUMPTION
Table 11-3 PI7C9X440SL Power Dissipation
Mode
L0 Normal Mode
Typical Power Dissipation (mW)
432
11.4 DC SPECIFICATIONS
Table 11-4 DC Electrical Characteristics
Power Pins
VDDC
VDDR
VDDA
AVDD
AVDDH
Min.
0.9v
3.0v
3.0v
0.95v
3.0v
Typ.
1.0v
3.3v
3.3v
1.0v
3.3v
Max.
1.1v
3.6v
3.6v
1.1v
3.6v
VDDC: digital power supply for the core
VDDR: digital power supply for 3.3v I/O Interface
VDDA: analog power supply for 3.3v USB Interface
AVDD: analog power supply for 1.0v PCI Express Interface
AVDDH: analog power supply for 3.3v PCI Express Interface
PI7C9X440SL
Document Number DS40394 Rev 3-2
Page 98 of 102
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© Diodes Incorporated
PI7C9X440SL
Table 11-5 DC Electrical Characteristics for Digital I/O
Symbol
VIH
VIL
VT
VT+
VTIL
Ioz
PPU
PPD
VOL
VOH
IOL
IOH
Parameter
Input High Voltage
Input Low Voltage
Threshold Point
Schmitt trig. Low to High Threshold Point
Schmitt trig. High to Low Threshold Point
Input Leakage Current
Tri-State Output Leakage Current
Pull-up Resistor
Pull-down Resistor
Output Low Voltage @ IOL=2, 4mA
Output High Voltage @ IOH=2, 4mA
Low Level Output Current @VOL =0.4V 2mA
4mA
High Level Output Current @VOH =2.4V 2mA
4mA
Min.
2.0V
Typ.
Max.
1.29V
1.47V
0.99V
1.39V
1.61V
1.08V
61kohm
101kohm
75kohm
199kohm
2.4V
2.1mA
4.2mA
2.8mA
5.5mA
3.3mA
6.6mA
6.1mA
12.2mA
0.8V
1.49V
1.75V
1.18V
±1uA
±1uA
105kohm
332kohm
0.4V
4.1mA
8.2mA
9.9mA
19.8mA
11.5 AC SPECIFICATIONS
Table 11-6 PCI Express Interface - Differential Transmitter (TX) Output Characteristics
Parameter
Unit Interval
Differential p-p TX voltage swing
Symbol
UI
VTX-DIFF-P-P
Min
399.88
800
Typ
400.0
-
Max
400.12
-
Lower power differential p-p TX voltage
swing
TX de-emphasis level ratio
Minimum TX eye width
Maximum time between the jitter median
and max deviation from the median
Transmitter rise and fall time
Maximum TX PLL Bandwidth
Maximum TX PLL BW for 3dB peaking
Absolute Delta of DC Common Mode
Voltage During L0 and Electrical Idle
Absolute Delta of DC Common Mode
Voltage between D+ and D–
Electrical Idle Differential Peak Output
Voltage
The Amount of Voltage Change Allowed
During Receiver Detection
Transmitter DC Common Mode Voltage
Transmitter Short-Circuit Current Limit
DC Differential TX Impedance
Lane-to-Lane Output Skew
VTX-DIFF-P-P-LOW
400
-
-
VTX-DE-RATIO
TTX-EYE
TTX-EYE-MEDIAN-to-MAX-
-3.0
0.75
-
-
-4.0
0.125
Unit
ps
mV
ppd
mV
ppd
dB
UI
UI
0.125
1.5
0
-
22
100
UI
MHz
MHz
mV
VTX-CM-DC-LINE-DELTA
0
-
25
mV
VTX-IDLE-DIFF-AC-p
0
-
20
mV
VTX-RCV-DETECT
-
-
600
mV
VTX-DC-CM
ITX-SHORT
ZTX-DIFF-DC
LTX-SKEW
0
80
-
100
-
3.6
90
120
500 ps
+ 2 UI
V
mA
Ω
ps
JITTER
TTX-RISE-FALL
BWTX-PLL
BWTX-PLL-LO-3DB
VTX-CM-DC-ACTIVE-IDLEDELTA
Table 11-7 PCI Express Interface - Differential Receiver (RX) Input Characteristics
Parameter
Unit Interval
Differential RX Peak-to-Peak Voltage
Receiver eye time opening
Maximum time delta between median and
deviation from median
Receiver DC common mode impedance
DC differential impedance
RX AC Common Mode Voltage
DC input CM input impedance during reset
or power down
PI7C9X440SL
Document Number DS40394 Rev 3-2
Symbol
UI
VRX-DIFF-PP-CC
TRX-EYE
TRX-EYE-MEDIAN-to-MAX-
Min
399.88
175
0.4
-
Typ
400.0
-
Max
400.12
1200
0.3
Unit
ps
mV
UI
UI
40
80
200
-
60
120
150
-
Ω
Ω
mV
kΩ
JITTER
ZRX-DC
ZRX-DIFF-DC
VRX-CM-AC-P
ZRX-HIGH-IMP-DC
Page 99 of 102
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January 2018
© Diodes Incorporated
PI7C9X440SL
Parameter
Electrical Idle Detect Threshold
Lane to Lane skew
Symbol
VRX-IDLE-DET-DIFFp-p
LRX-SKEW
Min
65
-
Typ
-
Max
175
20
Unit
mV
ns
Table 11-8 USB Interface Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
75
4
0.5
75
4
0.5
-
-
300
20
ns
-
300
20
ns
-
10
1
0.2
ns
-0.05
0.8
1.3
1.3
-10
-50
-50
-
V
0
0
0
0.5
2.5
2
2
10
50
50
-
2.0
4.0
0.8
4.75
V
V
V
V
3.0
3.0
0.0
400
400
0.0
0.0
0.0
3.6
3.6
10.0
440
440
10.0
10.0
10.0
V
V
mV
mV
mV
mV
mV
mV
-
1100
-500
mV
mV
Timing Characteristics
trise
tfall
Jitter
1.5 Mbps
12 Mbps
480 Mbps
1.5 Mbps
12 Mbps
480 Mbps
1.5 Mbps
12 Mbps
480 Mbps
Electrical Characteristics
Vcm DC
(DC level measured at receiver connector)
Crossover Voltages
Power supply ripple noise
(Analog 3.3V)
Power supply ripple noise
CORE
(Digital Supply)
A-Device Session Valid
B-Device Session Valid
B-Device Session End
VBUS Valid
LS Idle Voltage
FS Idle Voltage
HS Test K
HS Test J
HS Test SE0
CHIRP ‘J’
CHIRP ‘K’
HS Mode
LS/FS Mode
LS Mode
FS Mode
< 1.2MHz
> 1.2MHz
All conditions
VBUS Comparators Voltage Thresholds
0.8
0.8
0.2
4.4
DC Levels
2.7
2.7
D+
-10.0
D360
D+
360
D-10.0
D+
-10.0
D-10.0
CHIRP Levels
D+ - D700
D+ - D-900
-
-
V
mV
mV
PI7C9X440SL
Page 100 of 102
January 2018
Document Number DS40394 Rev 3-2
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© Diodes Incorporated
PI7C9X440SL
12 PACKAGE INFORMATION
The package of PI7C9X440SL is a 14mm x 14mm LQFP (128 Pin) package. The following are the package
information and mechanical dimension:
Figure 12-1 Package Outline Drawing
Figure 12-2 Part Marking
PI7C9X440SL
Page 101 of 102
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Document Number DS40394 Rev 3-2
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© Diodes Incorporated
PI7C9X440SL
13 ORDERING INFORMATION
Part Number
PI7C9X440SL□FDEX
Temperature Range
-40o to 85oC
(Industrial Temperature Range)
Package
128-pin LQFP
14mm x 14mm
Pb-Free & Green
Yes
Notes:
1.
EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. All applicable RoHS exemptions applied.
2.
See http://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,
“Green” and Lead-free.
3.
Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/
4.
E = Pb-free and Green
5.
X suffix = Tape/Reel
PI 7C 9X440SL
FD E X
Tape & Reel
Pb-Free and Green
Package Code
Blank=Standard
=Revision
Device Type
Device Number
Family
Pericom
PI7C9X440SL
Page 102 of 102
January 2018
Document Number DS40394 Rev 3-2
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© Diodes Incorporated
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