74ALVCH16344DLRG4

SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES054H – SEPTEMBER 1995 – REVISED SEPTEMBER 2004 FEATURES • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) OE1 1B1 1B2 GND 1B3 1B4 VCC 1A 2B1 2B2 GND 2B3 2B4 2A 3A 3B1 3B2 GND 3B3 3B4 4A VCC 4B1 4B2 GND 4B3 4B4 OE2 DESCRIPTION/ORDERING INFORMATION This 1-bit to 4-bit address driver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16344 is used in applications in which four separate memory locations must be addressed by a single address. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE4 8B1 8B2 GND 8B3 8B4 VCC 8A 7B1 7B2 GND 7B3 7B4 7A 6A 6B1 6B2 GND 6B3 6B4 5A VCC 5B1 5B2 GND 5B3 5B4 OE3 ORDERING INFORMATION PACKAGE (1) TA -40°C to 85°C SSOP - DL TSSOP - DGG (1) ORDERABLE PART NUMBER Tube SN74ALVCH16344DL Tape and reel SN74ALVCH16344DLR Tape and reel SN74ALVCH16344DGGR TOP-SIDE MARKING ALVCH16344 ALVCH16344 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE A OUTPUT Bn L H H L L L H H Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2004, Texas Instruments Incorporated SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES054H – SEPTEMBER 1995 – REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) OE4 56 29 OE3 OE2 OE1 28 1 2 3 1A 34 1B1 5B1 33 1B2 8 5A 5 6 9 31 1B3 5B3 30 1B4 41 2B1 10 2A 6A 12 13 16 17 6B1 6B2 42 38 2B3 37 2B4 48 3B1 47 3B2 15 6B3 6B4 7B1 7B2 43 3A 7A 19 20 23 45 3B3 44 3B4 55 4B1 24 7B3 7B4 8B1 54 4B2 21 4A 8B2 49 8A 26 27 2 5B4 40 2B2 14 5B2 36 4B3 4B4 52 51 8B3 8B4 SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES054H – SEPTEMBER 1995 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.5 IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) mA -50 mA ±50 mA ±100 mA DGG package 64 DL package 56 -65 V -50 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 Low-level input voltage V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL UNIT VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) VCC = 1.65 V -4 VCC = 2.3 V -12 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 -40 mA mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES054H – SEPTEMBER 1995 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 µA 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IOH = -12 mA V 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 ±5 VI = VCC or GND 3.6 V VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V -25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V -45 VI = 0.8 V 3V 75 3V -75 VI = 2 V UNIT 1.2 1.65 V to 3.6 V IOL = 24 mA II(hold) MAX IOL = 4 mA IOL = 12 mA II TYP (1) VCC - 0.2 IOH = -4 mA VOH VOL MIN V µA µA 3.6 V ±500 IOZ VO = VCC or GND 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA ∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA VI = 0 to 3.6 Ci Co (1) (2) Control inputs Data inputs Outputs V (2) VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V 2.5 pF 3.5 4 pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER VCC = 1.8 V A B TYP VCC = 2.5 V ± 0.2 V MIN MAX (1) 1 VCC = 2.7 V UNIT MAX 4.6 4.6 1.4 4 ns 1 6.2 6.2 1.2 5.1 ns 1 5.1 4.4 1.2 4 ns tsk(o) (2) 0.35 ns (3) 0.5 ns ten OE B (1) tdis OE B (1) This information was not available at the time of publication. Skew between outputs of same bank and same package (same transition) Skew between outputs of all banks and same package (A1 through A8 tied together) MIN VCC = 3.3 V ± 0.3 V MIN tsk(o) 4 TO (OUTPUT) MAX tpd (1) (2) (3) FROM (INPUT) SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES054H – SEPTEMBER 1995 – REVISED SEPTEMBER 2004 OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd (1) Power dissipation capacitance per bit (four outputs switching) TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 68 84 (1) 11 14 UNIT pF This information was not available at the time of publication. 5 SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES054H – SEPTEMBER 1995 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) tPLZ VLOAD/2 VM tPZH VOH VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPHL VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 74ALVCH16344DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office 74ALVCH16344DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office 74ALVCH16344DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples 74ALVCH16344DLRG4 ACTIVE SSOP DL 56 Call TI Purchase Samples SN74ALVCH16344DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) TBD CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74ALVCH16344DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74ALVCH16344DLR ACTIVE SSOP DL 56 TBD Call TI Call TI Call TI Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2010 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74ALVCH16344DGGR TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH16344DGGR TSSOP DGG 56 2000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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