ADS125H02IRHBT

ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com 16-BIT, 500-KSPS, SERIAL INTERFACE MICROPOWER, MINIATURE, SAR ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS8318 FEATURES DESCRIPTION • • • • • The ADS8318 is a 16-bit, 500-KSPS analog-to-digital converter. It operates with a 2.048-V to 5.5-V external reference. The device includes a capacitor based, SAR A/D converter with inherent sample and hold. 1 • • • • • 500-kHz Sample Rate 16-Bit Resolution Zero Latency at Full Speed Unipolar, Differential Input, Range: –Vref to Vref SPI Compatible Serial Interface with Daisy Chain Option Excellent Performance: – 95.2dB SNR Typ at 10-kHz I/P – –108dB THD Typ at 10-kHz I/P – ±1.0 LSB Max INL – ±0.75 LSB Max DNL Low Power Dissipation: 18 mW Typ at 500 KSPS Power Scales Linearly with Speed: 3.6 mW/100 KSPS Power Dissipation During Power-Down State: 0.25 μW Typ 10-Pin MSOP and SON Packages The devices includes a 50-MHz SPI compatible serial interface. The interface is designed to support daisy chaining or cascading of multiple devices. Also a Busy Indicator makes it easy to synchronize with the digital host. The ADS8318 unipolar differential input range supports a differential input swing of –Vref to +Vref with a common-mode of +Vref/2. Device operation is optimized for very low power operation, and the power consumption directly scales with speed. This feature makes it attractive for lower speed applications. It is available in 10-pin MSOP and SON packages. +VA APPLICATIONS • • • • • Battery Powered Equipments Data Acquisition Systems Instrumentation and Process Control Medical Electronics Optical Networking SAR O/P Drive COMP I/P Shift Reg IN+ CDAC +VBD IN- REFIN Conversion and I/O Control Logic ADS8318 GND SDO SDI SCLK CONVST 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2011, Texas Instruments Incorporated ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) DEVICE ADS8318I MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±1.5 NO MISSING CODES AT RESOLUTION (BIT) ±1 PACKAGE TYPE PACKAGE DESIGNATOR 10 Pin MSOP DGS 10 Pin MSOP ±1.0 ±0.75 ORDERING INFORMATION TRANSPORT MEDIA QUANTITY ADS8318IDGST 250 ADS8318IDGSR 2500 CBC DRC ADS8318IDRCT 250 ADS8318IDRCR 2500 CBE DGS ADS8318IBDGST 250 ADS8318IBDGSR 2500 CBC –40°C to 85°C 16 10 Pin SON (1) PACKAGE MARKING –40°C to 85°C 16 10 Pin SON ADS8318IB TEMPERATURE RANGE DRC ADS8318IBDRCT 250 ADS8318IBDRCR 2500 CBE For the most current specifications and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) +IN VALUE UNIT –0.3 to +VA + 0.3 V ±130 mA –0.3 to +VA + 0.3 V ±130 mA +VA to AGND –0.3 to 7 V +VBD to BDGND –0.3 to 7 V Digital input voltage to GND –0.3 to +VBD + 0.3 V Digital output to GND –0.3 to +VBD + 0.3 V –IN TA Operating free-air temperature range –40 to 85 °C Tstg Storage temperature range –65 to 150 °C 150 °C Junction temperature (TJ max) MSOP package Maximum MSOP reflow temperature SON package Maximum SON reflow temperature (1) 2 Power dissipation θJA thermal impedance (TJMax – TA)/θJA °C 180 °C/W ADS8318 is rated to MSL2 260°C per the JSTD-020 specification (TJMax – TA)/θJA Power dissipation θJA thermal impedance 70 °C/W ADS8318 is rated to MSL2 260°C per the JSTD-020 specification Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Operating input range +IN – (–IN) –Vref Vref +IN – 0.1 Vref + 0.1 –IN – 0.1 Input common-mode range 0 Input capacitance +IN and -IN terminal to GND Input leakage current During acquisition V Vref + 0.1 Vref/2 Vref/2+0.1 V 59 pF 1000 pA 16 Bits SYSTEM PERFORMANCE Resolution No missing codes 16 ADS8318I INL Integral linearity (2) DNL Differential linearity EO Offset error (4) EG Gain error CMRR Common-mode rejection ratio With common mode input signal = 200 mVp-p at 500 kHz PSRR Power supply rejection ratio At FFF0h output code ADS8318IB ADS8318I ADS8318IB At 16-bit level Bits –1.5 ±0.65 1.5 –1 ±0.65 1 –1 ±0.4 1 –0.75 ±0.4 0.75 LSB (3) LSB (3) –1.5 ±0.3 1.5 mV –0.03 ±0.003 0.03 %FSR 78 dB 80 Transition noise dB 0.25 LSB SAMPLING DYNAMICS tCONV Conversion time Acquisition time +VBD = 5 V 1400 +VBD = 3 V 1400 +VBD = 5 V 600 +VBD = 3 V 600 ns Maximum throughput rate with or without latency 0.5 Aperture delay Aperture jitter, RMS Step response Overvoltage recovery (1) (2) (3) (4) Settling to 16-bit accuracy ns MHz 2.5 ns 6 ps 600 ns 600 ns Ideal input span, does not include gain or offset error. This is endpoint INL, not best fit. LSB means least significant bit Measured relative to actual measured reference. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 3 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS –114 VIN 0.4 dB below FS at 1 kHz, Vref = 5 V THD Total harmonic distortion (5) VIN 0.4 dB below FS at 10 kHz, Vref = 5 V –108 VIN 0.4 dB below FS at 100 kHz, Vref = 5 V –91.5 VIN 0.4 dB below FS at 1 kHz, Vref = 5 V SNR Signal-to-noise ratio ADS8318IB SINAD SFDR Signal-to-noise + distortion Spurious free dynamic range 96 VIN 0.4 dB below FS at 10 kHz, Vref = 5 V 95.2 VIN 0.4 dB below FS at 100 kHz, Vref = 5 V 92.5 VIN 0.4 dB below FS at 1 kHz, Vref = 5 V dB dB 95.5 VIN 0.4 dB below FS at 1 kHz, Vref = 5 V 96 VIN 0.4 dB below FS at 10 kHz, Vref = 5 V 95 VIN 0.4 dB below FS at 100 kHz, Vref = 5 V 89.5 VIN 0.4 dB below FS at 1 kHz, Vref = 5 V 116 VIN 0.4 dB below FS at 10 kHz, Vref = 5 V 109 VIN 0.4 dB below FS at 100 kHz, Vref = 5 V 92 –3dB Small signal bandwidth dB dB 15 MHz EXTERNAL REFERENCE INPUT Vref Input range 2.048 Reference input current (6) During conversion 4.096 VDD+0.1 V μA 250 POWER SUPPLY REQUIREMENTS Power supply voltage +VBD Supply current +VA 2.375 3.3 5.5 4.5 5 5.5 V 500-kHz Sample rate 3.6 4.5 mA +VA V PVA Power dissipation +VA = 5 V, 500-kHz Sample rate 18 22.5 mW IVApd Device power-down current (7) +VA = 5 V 50 300 nA LOGIC FAMILY CMOS VIH IIH = 5 μA +(0.7×VBD) +VBD+0.3 V VIL IIL = 5 μA –0.3 +(0.3×VBD) V IOH = 2 TTL loads +VBD–0.3 +VBD V IOL = 2 TTL loads 0 0.4 V –40 85 °C VOH Logic level VOL TEMPERATURE RANGE TA (5) (6) (7) 4 Operating free-air temperature Calculated on the first nine harmonics of the input frequency Can vary ±20% Device automatically enters power-down state at the end of every conversion, and continues to be in power-down state as long as it is in acquistion phase. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD ≥ 3.1 V PARAMETER REF FIGURE MIN TYP MAX UNIT SAMPLING AND CONVERSION RELATED tacq Acquisition time tcnv Conversion time tcyc Time between conversions t1 Pulse duration, CONVST high t6 Pulse duration, CONVST low 600 Figure 46, Figure 48, Figure 50, Figure 52 ns 1400 ns 2000 ns Figure 46, Figure 48 10 ns Figure 50, Figure 52, Figure 54 20 ns 20 ns 8 ns 8 ns I/O RELATED tclk SCLK Period tclkl SCLK Low time tclkh SCLK High time t2 SCLK Falling edge to data remains valid t3 SCLK Falling edge to next data valid delay ten Enable time, CONVST or SDI Low to MSB valid tdis Disable time, CONVST or SDI high or last SCLK falling edge to SDO 3-state (CS mode) t4 Setup time, SDI valid to CONVST rising edge t5 Hold time, SDI valid from CONVST rising edge t7 Setup time, SCLK valid to CONVST rising edge t8 Hold time, SCLK valid from CONVST rising edge Figure 46, Figure 48, Figure 50, Figure 52, Figure 54, Figure 56 5 ns 16 ns Figure 46, Figure 50 15 ns Figure 46, Figure 48, Figure 50, Figure 52 12 ns Figure 50, Figure 52 Figure 54 5 ns 5 ns 5 ns 5 ns Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 5 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS All specifications typical at –40°C to 85°C, +VA = 5 V, +3.1 V > +VBD ≥ 2.375 V PARAMETER REF FIGURE MIN TYP MAX UNIT SAMPLING AND CONVERSION RELATED tacq Acquisition time tcnv Conversion time tcyc Time between conversions t1 Pulse width CONVST high t6 Pulse width CONVST low 600 Figure 46, Figure 48, Figure 50, Figure 52 ns 1400 ns 2000 ns Figure 46, Figure 48 10 ns Figure 50, Figure 52, Figure 54 20 ns I/O RELATED tclk SCLK period 30 ns tclkl SCLK low time 13 ns tclkh SCLK high time 13 ns t2 SCLK falling edge to data remains valid t3 SCLK falling edge to next data valid delay ten CONVST or SDI low to MSB valid tdis CONVST or SDI high or last SCLK falling edge to SDO 3-state (CS mode) t4 SDI valid setup time to CONVST rising edge t5 SDI valid hold time from CONVST rising edge t7 SCLK valid setup time to CONVST rising edge t8 SCLK valid hold time from CONVST rising edge Figure 46, Figure 48, Figure 50, Figure 52, Figure 54, Figure 56 5 ns Figure 46, Figure 50 22 ns Figure 46, Figure 48, Figure 50, Figure 52 15 ns Figure 50, Figure 52 Figure 54 500µA ns 24 5 ns 5 ns 5 ns 5 ns I ol From SDO 1.4V 20pF 500µA I oh Figure 1. Load Circuit for Digital Interface Timing 0.7 VBD 0.3 VBD t DELAY tDELAY 2V 2V 0.8V 0.8V Figure 2. Voltage Levels for Timing 6 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com PIN ASSIGNMENTS MSOP PACKAGE (TOP VIEW) REFIN +VA IN+ INGND 1 10 2 9 3 8 4 7 5 6 SON PACKAGE (TOP VIEW) +VBD SDI SCLK SDO CONVST REFIN +VA IN+ INGND 1 10 2 9 3 8 4 7 5 6 +VBD SDI SCLK SDO CONVST Terminal Functions TERMINAL NO. I/O NAME DESCRIPTION ANALOG PINS 1 REFIN I Reference (positive) input. Decouple with GND pin using 0.1-μF bypass capacitor and 10-μF storage capacitor. 3 +IN I Noninverting analog signal input 4 –IN I Inverting analog signal input 6 CONVST I Convert input. It also functions as the CS input in 3-wire interface mode. Refer to Description and Timing Diagrams sections for more details. 7 SDO O Serial data output. 8 SCLK I Serial I/O clock input. Data (on SDO o/p) is synchronized with this clock. 9 SDI I Serial data input. The SDI level at the start of a conversion selects the mode of operation such as CS or daisy chain mode. It also serves as the CS input in 4-wire interface mode. Refer to Description and Timing Diagrmas sections for more details. I/O PINS POWER SUPPLY PINS 2 +VA – Analog power supply. Decoupled with GND pin. 5 GND – Device ground. Note this is a common ground pin for both analog power supply (+VA) and digital I/O supply (+VBD). 10 +VBD – Digital I/O power supply. Decouple with GND pin. TYPICAL CHARACTERISTICS OFFSET ERROR vs SUPPLY VOLTAGE GAIN ERROR vs SUPPLY VOLTAGE -0.001 0.4 0.32 0.3 0.28 0.26 -0.004 -0.005 -0.006 -0.007 0.24 -0.008 0.22 -0.009 4.75 5 5.25 +VA - Supply Voltage - V 0.3 -0.003 0.34 0.2 4.5 0.35 -0.002 5.5 Figure 3. Offset Error - mV Offset Error - mV 0.36 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C Gain Error - %FSR 0.38 OFFSET ERROR vs REFERENCE VOLTAGE -0.01 4.5 0.25 0.2 0.15 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, TA = 30°C 0.1 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C 0.05 0 4.75 5 5.25 +VA - Supply Voltage - V Figure 4. 5.5 2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V Figure 5. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 5 7 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) GAIN ERROR vs REFERENCE VOLTAGE OFFSET ERROR vs FREE-AIR TEMPERATURE -0.001 1 -0.002 0.9 -0.006 -0.007 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, TA = 30°C -0.008 -0.009 -0.01 2 0 0.7 Gain Error - %FSR Offset Error - mV -0.005 0.6 0.5 0.4 0.3 0.2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V -0.006 -0.008 0 -40 5 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -0.01 -40 -25 80 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 8. GAIN ERROR DRIFT HISTOGRAM OFFSET ERROR DRIFT HISTOGRAM DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 16 10 9 8 8 8 6 1 19 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 18 DNL - Differential Nonlinearity - LSBs 12 20 15 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 17 14 12 10 8 6 4 4 2 0 0 0 0 0 0 2 2 1 0 0 0 1 0 1 0 0 0 1 0.8 0.6 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C DNLMAX 0.4 0.2 0 -0.2 DNLMIN -0.4 -0.6 -0.8 -1 4.5 -0.5-0.4-0.3-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 ppm/°C -0.5 -0.4 -0.3-0.2-0.1 0 0.1 0.2 0.3 0.4 0.5 ppm/°C Figure 9. Figure 10. Figure 11. INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 1 0.8 0.6 INLMAX 0.4 0.2 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C 0 -0.2 -0.4 INLMIN -0.6 -0.8 -1 0.6 DNLMAX 0.4 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, TA = 30°C 0.2 0 -0.2 -0.4 DNLMIN -0.6 -0.8 -1 4.5 4.75 5 5.25 +VA - Supply Voltage - V Figure 12. 5.5 4.75 5 5.25 +VA - Supply Voltage - V 5.5 1 INL - Integral Nonlinearity - LSBs 1 0.8 DNL - Differential Nonlinearity - LSBs INL - Integral Nonlinearity - LSBs -0.004 Figure 7. 14 8 -0.002 Figure 6. 16 0 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.1 Number of Devices Gain Error - %FSR -0.004 Number of Devices 0.002 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.8 -0.003 GAIN ERROR vs FREE-AIR TEMPERATURE 2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V Figure 13. Submit Documentation Feedback 5 0.8 INLMAX 0.6 0.4 0.2 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, TA = 30°C 0 -0.2 -0.4 INLMIN -0.6 -0.8 2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 5 Figure 14. Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.8 DNLMAX 0.4 0.2 0 -0.2 ENOB - Effective Number Of Bits - LSBs 0.6 DNLMIN -0.4 -0.6 -0.8 INLMAX 0.6 0.4 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.2 0 -0.2 -0.4 INLMIN -0.6 -0.8 -1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -1 -40 80 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz TA = 30°C 15.9 15.8 15.7 15.6 15.5 15.4 15.3 15.2 15.1 15 4.5 80 4.75 5 5.25 +VA - Supply Voltage - V 5.5 Figure 15. Figure 16. Figure 17. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs SUPPLY VOLTAGE 15.8 15.7 ENOB - Effective Number Of Bits - LSBs +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 15.9 15.6 15.5 15.4 15.3 15.2 15.1 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 15.8 15.7 5 122 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 15.6 15.5 15.4 15.3 15.2 15.1 15 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 15 2 15.9 Spurious Free Dynamic Range - dB 16 16 ENOB - Effective Number Of Bits - LSBs 16 1 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.8 INL - Integral Nonlinearity - LSBs DNL - Differential Nonlinearity - LSBs 1 EFFECTIVE NUMBER OF BITS vs SUPPLY VOLTAGE 121 120 119 118 117 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz TA = 30°C 116 115 114 4.5 80 4.75 5 5.25 +VA - Supply Voltage - V 5.5 Figure 18. Figure 19. Figure 20. SIGNAL-TO-NOISE + DISTORTION vs SUPPLY VOLTAGE SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE TOTAL HARMONIC DISTORTION vs SUPPLY VOLTAGE 96.4 96.2 96.2 96 95.8 95.6 +VBD = 2.7 V, 95.4 Vref = 4.096 V, fs = 500 KSPS, 95.2 fi = 1.9 kHz TA = 30°C 95 4.5 4.75 5 5.25 +VA - Supply Voltage - V 5.5 Figure 21. Total Harmonic Distortion - dB 121 Signal-to-Noise Ratio - dB Signal-to-Noise + Distortion - dB 122 96.4 96 95.8 95.6 +VBD = 2.7 V, 95.4 Vref = 4.096 V, fs = 500 KSPS, 95.2 fi = 1.9 kHz TA = 30°C 95 4.5 4.75 5 5.25 +VA - Supply Voltage - V Figure 22. 5.5 120 119 118 117 116 115 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz TA = 30°C 114 4.5 4.75 5 5.25 +VA - Supply Voltage - V Figure 23. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 5.5 9 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SPURIOUS FREE DYNAMIC RANGE vs REFERENCE VOLTAGE SIGNAL-TO-NOISE + DISTORTION vs REFERENCE VOLTAGE 121 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 120 119 118 117 116 96 95.5 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 95 94.5 94 95.5 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 95 94.5 94 93.5 93.5 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 5 2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 2 5 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 5 Figure 24. Figure 25. Figure 26. TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE 123 122 121 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 120 119 118 117 116 115 96.4 117 116.5 116 115.5 115 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 114.5 114 5 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 96.3 96.2 96.1 96 95.9 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 95.8 95.7 95.6 95.5 -40 -25 80 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 27. Figure 28. Figure 29. SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 120 118 SNR 96.4 96.3 96.2 96.1 96 95.9 95.8 95.7 95.6 95.5 -40 -25 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 30. Total Harmonic Distortion - dB 117.5 117 116.5 116 115.5 115 114.5 114 113.5 -40 -25 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz THD - Total Harmonic Distortion - dB 96.5 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 96.5 113.5 -40 -25 114 2 118 117.5 Signal-to-Noise + Distortion - dB Spurious Free Dynamic Range - dB 124 Total Harmonic Distortion - dB 96 115 2 Signal-to-Noise Ratio - dB 96.5 Signal-to-Noise Ratio - dB 122 114 10 96.5 123 Signal-to-Noise + Distortion - dB Spurious Free Dynamic Range - dB 124 SIGNAL-TO-NOISE RATIO vs REFERENCE VOLTAGE 115 110 105 100 THD @ -0.5 dB 95 Figure 31. Submit Documentation Feedback 80 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 90 85 80 -10 5 20 35 50 65 TA - Free-Air Temperature - °C THD @ -10 dB 1 10 fi - Input frequency - kHz 100 Figure 32. Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SINAD @ -10 dB 97 200000 95 SINAD @ -0.5 dB +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 150000 93 91 100000 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 89 87 46104 50000 0 85 THD - Total Harmonic Distortion - dB 216040 0 10 fi - Input frequency - kHz 100 32757 111 0 32760 100 200 300 400 Source Resistance - W 500 SUPPLY CURRENT vs SAMPLING FREQUENCY 4 4.2 4 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 3.8 3.6 3.4 3.2 3 -40 -25 5.5 3 2.5 2 1.5 1 0.5 3.35 4.75 5 5.25 +VA - Supply Voltage - V +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, TA = 30°C 3.5 Iavdd - Supply Current - mA +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C 3.4 0 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 0 80 50 100 150 200 250 300 350 400 450 500 fs - Sampling Frequency - KSPS Figure 36. Figure 37. Figure 38. POWER DISSIPATION vs SAMPLING FREQUENCY POWERDOWN CURRENT vs SUPPLY VOLTAGE POWERDOWN CURRENT vs FREE-AIR TEMPERATURE 500 Iavdd-pd - Powerdown Current - nA +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, TA = 30°C 12 10 8 6 4 450 400 350 500 +VBD = 2.7 V, Vref = 4.096 V, fs = 0.0 KSPS, TA = 30°C Iavdd-pd - Powerdown Current - nA 20 300 250 200 150 100 50 2 0 0 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C SUPPLY CURRENT vs FREE-AIR TEMPERATURE 3.5 14 680 pF 112 SUPPLY CURRENT vs SUPPLY VOLTAGE 3.45 16 113 Figure 35. 3.6 18 114 Figure 34. 3.55 3.3 4.5 115 Figure 33. Iavdd - Supply Current - mA 3.7 3.65 32758 32759 Codes 0 pF 100 pF 116 110 0 1 3.8 Iavdd - Supply Current - mA 117 250000 99 3.75 Iavdd*VA - Power Dissipation - mW TOTAL HARMONIC DISTORTION vs SOURCE RESISTANCE DC HISTORAM OF ADC CLOSE TO CENTER CODE Hits SINAD - Signal-to-Noise + Noise Distortion - dB SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 50 100 150 200 250 300 350 400 450 500 fs - Sampling Frequency - KSPS Figure 39. 0 4.5 450 400 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 0.0 KSPS 350 300 250 200 150 100 50 4.75 5 5.25 +VA - Supply Voltage - V Figure 40. 5.5 0 -40 -25 -10 5 20 35 50 65 Figure 41. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 80 TA - Free-Air Temperature - °C 11 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DNL DNL - LSBs 1 0.8 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 10000 20000 30000 Codes 40000 50000 60000 Figure 42. INL 1 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 0.8 INL - LSBs 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 10000 20000 30000 40000 Codes 50000 60000 Figure 43. Amplitude - dB FFT 0 -20 -40 -60 -80 -100 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30C -120 -140 -160 -180 -200 0 50 100 150 f - Frequency - kHz 200 250 Figure 44. 12 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com DETAILED DESCRIPTIONS AND TIMING DIAGRAMS The ADS8318 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The ADS8318 is a single channel device. The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and -IN inputs are disconnected from any internal function. The ADS8318 has an internal clock that is used to run the conversion, and hence the conversion requires a fixed amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and –IN pins, and the device is in the acquisition phase. During this phase the device is powered down and conversion data can be read. The device digital output is available in SPI compatible format. It easily interfaces with microprocessors, DSPs, or FPGAs. This is a low pin count device; however, it offers six different options for the interface. They can be grossly classified as CS mode (3- or 4-wire interface) and daisy chain mode. In both modes it can either be with or without a busy indicator, where the busy indicator is a bit preceeding the 16-bit serial data. The 3-wire interface CS mode is useful for applications which need galvanic isolation on-board, where as 4-wire interface CS mode makes it easy to control an individual device while having multiple devices on-board. The daisy chain mode is provided to hook multiple devices in a chain like a shift register and is useful to reduce component count and the number signal traces on the board. CS MODE CS Mode is selected if SDI is high at the rising edge of CONVST. As indicated before there are four different interface options available in this mode, namely 3-wire CS mode without busy indicator, 3-wire CS mode with busy indicator, 4-wire CS mode without busy indicator, 4-wire CS mode with busy indicator. The following section discusses these interface options in detail. 3-Wire CS Mode Without Busy Indicator Digital Host ADS8318 +VBD SDI CONVST CNV SCLK CLK SDO SDI Figure 45. Connection Diagram, 3-Wire CS Mode without Busy Indicator (SDI = 1) The three wire interface option in CS mode is selected if SDI is tied to +VBD (see Figure 45). In the three wire interface option, CONVST acts like CS. As shown in Figure 46, the device samples the input signal and enters the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3-state. Conversion is done with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to bring CONVST (acting as CS) low after the start of the conversion to select other devices on the board. But it is absolutely necessary that CONVST is high again before the minimum conversion time (tcnv in timing requirements table) is elapsed. A high level on CONVST at the end of the conversion ensures the device does not generate a busy indicator. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 13 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com When the conversion is over, the device enters the acquisition phase and powers down. On the falling edge of CONVST, SDO comes out of three state, and the device outputs the MSB of the data. After this, the device outputs the next lower data bits on every falling edge of SCLK. SDO goes to 3-state after the 16th falling edge of SCLK or CONVST high, whichever occurs first. It is necessary that the device sees a minimum of 15 falling edges of SCLK during the low period of CONVST. tcyc t1 CONVST tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkl t2 SCLK 1 2 ten t3 SDO D15 16 15 tclkh tdis tclk D14 D1 D0 Figure 46. Interface Timing Diagram, 3 Wire CS Mode Without Busy Indicator (SDI = 1) 3 Wire CS Mode With Busy Indicator Digital Host ADS8318 CNV CONVST SDI SCLK + VBD SDO CLK SDI IRQ Figure 47. Connection Diagram, 3 Wire CS Mode With Busy Indicator The three wire interface option in CS mode is selected if SDI is tied to +VBD (see Figure 47). In the three wire interface option, CONVST acts like CS. As shown in Figure 48, the device samples the input signal and enters the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3 state. Conversion is done with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to toggle CONVST (acting as CS) after the start of the conversion to select other devices on the board. But it is absolutely necessary that CONVST is low again before the minimum conversion time (tcnv in timing requirements table) is elapsed and continues to stay low until the end of maximum conversion time. A low level on the CONVST input at the end of a conversion ensures the device generates a busy indicator. When the conversion is over, the device enters the acquisition phase and powers down, and the device forces SDO out of three state and outputs a busy indicator bit (low level). The device outputs the MSB of data on the first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every subsequent falling edge of SCLK. SDO goes to three state after the 17th falling edge of SCLK or CONVST high, whichever occurs first. It is necessary that the device sees a minimum of 16 falling edges of SCLK during the low period of CONVST. 14 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com tcyc t1 CONVST tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkl t2 1 SCLK 2 3 16 t3 SDO D15 tclk D14 D1 17 tclkh tdis D0 Figure 48. Interface Timing Diagram, 3 Wire CS Mode With Busy Indicator (SDI = 1) 4 Wire CS Mode Without Busy Indicator CS1 CS2 CNV CONVST SDI CONVST SDO SCLK SDI SDO SDI SCLK CLK ADS8318#1 ADS8318#2 Digital Host Figure 49. Connection Diagram, 4 Wire CS Mode Without Busy Indicator As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising edge. Unlike in three wire interface option, SDI is controlled by digital host and acts like CS. As shown in Figure 50, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of SDI. As a result it is possible to bring SDI (acting as CS) low to select other devices on the board. But it is absolutely necessary that SDI is high again before the minimum conversion time (tcnv in timing requirements table) is elapsed. When the conversion is over, the device enters the acquisition phase and powers down. SDI falling edge can occur after the maximum conversion time (tcnv in timing requirements table). Note that it is necessary that SDI is high at the end of the conversion, so that the device does not generate a busy indicator. The falling edge of SDI Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 15 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com brings SDO out of 3-state and the device outputs the MSB of the data. Subsequent to this the device outputs the next lower data bits on every falling edge of SCLK. SDO goes to three state after the 16th falling edge of SCLK or SDI (CS) high, whichever occurs first. As shown in Figure 49, it is possible to hook multiple devices on the same data bus. In this case the second device SDI (acting as CS) can go low after the first device data is read and device 1 SDO is in three state. Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle. CONVST t6 SDI (CS) #1 t4 t5 SDI (CS) #2 tcnv ACQUISITION tacq CONVERSION ten ACQUISITION tclkl t2 SCLK 1 2 ten t3 SDO D15#1 D14#1 17 16 15 tclkh tclk D1#1 18 31 D0#1 32 tdis tdis D15#2 D14#2 D1#2 D0#2 Figure 50. Interface Timing Diagram, 4 Wire CS Mode Without Busy Indicator 4 Wire CS Mode With Busy Indicator CS SDI CNV CONVST + VBD SDO ADS8318 CLK SDI IRQ Digital Host Figure 51. Connection Diagram, 4 Wire CS Mode With Busy Indicator As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising edge. Unlike in the three wire interface option, SDI is controlled by the digital host and acts like CS. As shown in Figure 52, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of SDI. As a result it is possible to toggle SDI (acting as CS) to select other devices on the board. But it is absolutely necessary that SDI is low before the minimum conversion time (tcnv in timing requirements table) is elapsed and continues to stay low until the end of the maximum conversion time. A low level on the SDI input at the end of a conversion ensures the device generates a busy indicator. When the conversion is over, the device enters the acquisition phase and powers down, forces SDO out of three state, and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every falling edge of SCLK. SDO goes to three state after the 17th falling edge of SCLK or SDI (CS) high, whichever occurs first. 16 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle. tcyc t6 CNVST t5 SDI (CS) t 4 tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkh t2 1 SCLK 2 3 t3 SDO D15 17 16 tclkl tdis tclk D14 D1 D0 Figure 52. Interface Timing Diagram, 4 Wire CS Mode With Busy Indicator Daisy Chain Mode Daisy chain mode is selected if SDI is low at the time of CONVST rising edge. This mode is useful to reduce wiring and hardware like digital isolators in the applications where multiple (ADC) devices are used. In this mode all of the devices are connected in a chain (SDO of one device connected to the SDI of the next device) and data transfer is analogous to a shift register. Like CS mode even this mode offers operation with or without a busy indicator. The following section discusses these interface options in detail. Daisy Chain Mode Without Busy Indicator CNV CONVST SDI CONVST SDO SCLK ADS8318#1 SDI SDO SDI SCLK ADS8318#2 CLK Digital Host Figure 53. Connection Diagram, Daisy Chain Mode Without Busy Indicator (SDI = 0) Refer to Figure 53 for the connection diagram. SDI for device 1 is tied to ground and SDO of device 1 goes to SDI of device 2 and so on. SDO of the last device in the chain goes to the digital host. CONVST for all of the devices in the chain are tied together. In this mode there is no CS signal. The device SDO is driven low when Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 17 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com SDI and CONVST are low together. The rising edge of CONVST while SDI is low selects daisy chain mode and the device samples the analog input and enters the conversion phase. It is necessary that SCLK is low at the rising edge of CONVST so that the device does not generate a busy indicator at the end of the conversion. In this mode CONVST continues to be high from the start of the conversion until all of the data bits are read. Once started, conversion continues irrespective of the state of SCLK. At the end of the conversion, every device in the chain initiates output of its conversion data starting with the MSB bit. Further the next lower data bit is output on every falling edge of SCLK. While every device outputs its data on the SDO pin, it also receives previous device data on the SDI pin (other than device #1) and stores it in the shift register. The device latches incoming data on every falling edge of SCLK. SDO of the first device in the chain goes low after the 16th falling edge of SCLK. All subsequent devices in the chain output the stored data from the previous device in MSB first format immediately following their own data word. It needs 16 × N clocks to read data for N devices in the chain. tcyc t6 CONVST tacq tcnv ACQUISITION ACQUISITION CONVERSION t7 tclkl t2 SCLK 1 2 16 15 t8 tclk #1-D15 SDO #1, SDI #2 #1-D14 17 18 31 32 #2-D1 #2-D0 tclkh #1-D1 #1-D0 #1-D1 #1-D0 #2-D15 t3 #1-D15 SDO #2 #1-D14 #2-D14 Figure 54. Interface Timing Diagram, Daisy Chain Mode Without Busy Indicator Daisy Chain Mode With Busy Indicator CNV CONVST SDI CONVST SDO SCLK ADS8318#1 SDI IRQ SDO SDI SCLK ADS8318#2 CLK Digital Host Figure 55. Connection Diagram, Daisy Chain Mode With Busy Indicator (SDI = 0) Refer to Figure 55 for the connection diagram. SDI for device 1 is wired to it's CONVST and CONVST for all the devices in the chain are wired together. SDO of device 1 goes to SDI of device 2 and so on. SDO of the last device in the chain goes to the digital host. In this mode there is no CS signal. On the rising edge of CONVST, all of the device in the chain sample the analog input and enter the conversion phase. For the first device, SDI 18 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com and CONVST are wired together, and the setup time of SDI to rising edge of CONVST is adjusted so that the device still enters chain mode even though SDI and CONVST rise together. It is necessary that SCLK is high at the rising edge of CONVST so that the device generates a busy indicator at the end of the conversion. In this mode, CONVST continues to be high from the start of the conversion until all of the data bits are read. Once started, conversion continues irrespective of the state of SCLK. At the end of the conversion, all the devices in the chain generate busy indicators. On the first falling edge of SCLK following the busy indicator bit, all of the devices in the chain output their conversion data starting with the MSB bit. After this the next lower data bit is output on every falling edge of SCLK. While every device outputs its data on the SDO pin, it also receives the previous device data on the SDI pin (except for device #1) and stores it in the shift register. Each device latches incoming data on every falling edge of SCLK. SDO of the first device in the chain goes high after the 17th falling edge of SCLK. All subsequent devices in the chain output the stored data from the pervious device in MSB first format immediately following their own data word. It needs 16 × N + 1 clock pulses to read data for N devices in the chain. tcyc t6 CONVST tacq tcnv ACQUISITION ACQUISITION CONVERSION t7 tclkl t2 1 SCLK 2 3 16 17 18 19 32 33 #2-D14 #2-D1 #2-D0 tclk t8 tclkh SDO #1, SDI #2 #1-D15 #1-D14 SDO #2 #1-D15 #1-D14 #1-D1 #1-D0 #1-D1 #1-D0 #2-D15 t3 Figure 56. Interface Timing Diagram, Daisy Chain Mode With Busy Indicator Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 19 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION ANALOG INPUT When the converter samples the input, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the +IN and –IN inputs individually is limited between GND –0.1 V and Vref + 0.1 V; where as the differential signal range [(+IN) – (–IN)] is 2Vref (–Vref to +Vref) with a common mode of (Vref/2). This allows the input to reject small signals which are common to both the +IN and –IN inputs. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS8318 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and -IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, and linearity error which change with temperature and input voltage. Device in Hold Mode 218 W +IN 55 pF 4 pF +VA AGND 4 pF 218 W -IN 55 pF Figure 57. Input Equivalent Circuit DRIVER AMPLIFIER CHOICE The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031, OPA211. An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 5Ω and a differential capacitor of 1nF is recommended. The input to the converter is a unipolar input voltage in the range 0 V to Vref. The minimum –3dB bandwidth of the driving operational amplifier can be calculated as: f3db = (ln(2) × (n+2))/(2π × tACQ) where n is equal to 16, the resolution of the ADC (in the case of the ADS8318). When tACQ = 600 ns (minimum acquisition time), the minimum bandwidth of the driving circuit is ~3 MHz (including RC following the driver OPA). The bandwidth can be relaxed if the acquisition time is increased by the application. Typically a low noise OPA with ten times or higher bandwidth is selected. The driving circuit bandwidth is adjusted (to the required value) with a RC following the OPA. The OPA211 or THS4031 from Texas Instruments is recommended for driving high-resolution high-speed ADCs. DRIVER AMPLIFIER CONFIGURATIONS Configuration for Unipolar Differential Input It is better to use a unity gain, noninverting buffer configuration for a unipolar, differential input having a ±Vref signal range with Vref/2 common-mode. As explained before a RC following the OPA limits the input circuit bandwidth just enough for 16-bit settling. Note higher bandwidth reduces the settling time (beyond what is needed) but increases the noise in the ADC sampled signal, and hence the ADC output. 20 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com Figure 58. Unipolar Differential Input Drive Configuration Configuration for Bipolar Single-Ended Input The following circuit shows a way to convert a single-ended bipolar input to the unipolar differential input needed for for converter. Note that the higher values of the resistors at the input of the top OPA may reduce power consumption of the circuit but increase noise in the driving circuit. One can choose these components based on application needs. Vref Bipolar Analog Input ± Vref _ R + R 100 E 5E +IN 1 nF _ 100 E Vref/2 -IN 5E ADS8318 + OPA Shown is THS4031 or OPA211 Figure 59. Bipolar Single-Ended Input Drive Configuration REFERENCE The ADS8318 can operate with an external reference with a range from 2.048 V to VDD + 0.1 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF5050 can be used to drive this pin as shown in Figure 60 and Figure 61. The capacitor should be placed as close as possible to the pins of the device. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 21 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com 50 W - REF5050 OUT TRIM + + - 47 mF, OPA365 1.5 W ESR (High ESR) + IN+ - 4.7 mF, Low ESR 10 mF REFIN ADS8318 IN- Figure 60. External Reference Driving Circuit REF5050 OUT + - 47 mF, 1.5 W ESR (High ESR) 22 mF REFIN TRIM + - 4.7 mF, Low ESR IN+ ADS8318 IN- Figure 61. Direct External Reference Driving Circuit POWER SAVING The ADS8318 has an auto power-down feature. The device powers down at the end of every conversion. The input signal is acquired on sampling capacitors while the device is in the power-down state, and at the same time the conversion results are available for reading. The device powers up by itself on the start of the conversion. As discussed before, the conversion runs on an internal clock and takes a fixed time. As a result, device power consumption is directly proportional to the speed of operation. DIGITAL OUTPUT As discussed before (in the DESCRIPTION and TIMING DIAGRAMS sections) the device digital output is SPI compatible. The following table lists the output codes corresponding to various analog input voltages. DESCRIPTION ANALOG VALUE (V) DIGITAL OUTPUT STRAIGHT BINARY Full-scale range 2*Vref Least significant bit (LSB) 2*Vref/65536 Positive full scale +Vref – 1 LSB 0111 1111 1111 1111 7FFF Midscale 0V 0000 0000 0000 0000 0000 Midscale – 1 LSB 0 – 1 LSB 1111 1111 1111 1111 FFFF Negative full scale –Vref 1000 0000 0000 0000 8000 BINARY CODE HEX CODE SCLK INPUT The device uses SCLK for serial data output. Data is read after the conversion is over and the device is in the acquisition phase. It is possible to use a free running SCLK for the device, but it is recommended to stop the clock during a conversion, as the clock edges can couple with the internal analog circuit and can affect conversion results. 22 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com REVISION HISTORY Changes from Original (May 2008) to Revision A Page • Changed Condition in first TIMING REQUIREMENTS from 4.5 V to 3.1 V ......................................................................... 5 • Changed SCLK Low time MIN value from 9ns to 8ns and SCLK High time MIN value from 9ns to 8ns ............................. 5 • Changed Condition in second TIMING REQUIREMENTS from +4.5 V to + 3.1 V .............................................................. 6 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8318 23 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS8318IBDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CBC ADS8318IBDGST ACTIVE VSSOP DGS 10 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CBC ADS8318IBDRCT ACTIVE VSON DRC 10 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 CBE ADS8318IDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CBC ADS8318IDGST ACTIVE VSSOP DGS 10 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CBC ADS8318IDRCT ACTIVE VSON DRC 10 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 CBE ADS8318IDRCTG4 ACTIVE VSON DRC 10 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 CBE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of