ADS62C15IRGCR

ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs Check for Samples: ADS62P15 FEATURES 1 • • • • • • • • • • • Maximum Sample Rate: 125 MSPS 11-Bit Resolution With No Missing Codes 84 dBc SFDR at Fin = 50 MHz 67.1 dBFS SNR at Fin = 50 MHz 92 dB Crosstalk Parallel CMOS and DDR LVDS Output Options 3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off Digital Processing Block With: – Offset Correction – Fine Gain Correction, in Steps of 0.05 dB – Decimation by 2/4/8 – Built-in and Custom Programmable 24-Tap Low/High /Band Pass Filters Supports Sine, LVPECL, LVDS & LVCMOS Clocks & Amplitude Down to 400 mVPP Clock Duty Cycle Stabilizer Internal Reference; Supports External • • Reference also 64-QFN Package (9mm × 9mm) Pin Compatible 14-bit and 12-bit Family (ADS62P4X/ADS62P2X) APPLICATIONS • • • • • • • Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Medical Imaging Radar Systems Test and Measurement Instrumentation Table 1. ADS62PXX Dual Channel Family 125 MSPS 105 MSPS 80 MSPS 65 MSPS ADS62P4X (14 bit) ADS62P45 ADS62P44 ADS62P43 ADS62P42 ADS62P2X (12 bit) ADS62P25 ADS62P24 ADS62P23 ADS62P22 (11 bit) ADS62P15 - - - DESCRIPTION ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. ADS62P15 includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled. Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2012, Texas Instruments Incorporated ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DRGND DRVDD AGND AVDD FUNCTIONAL BLOCK DIAGRAM Digital Processing Block Channel A INA_P SHA 11-Bit ADC INA_M Output Buffers Digital Encoder 11 Bit CLKP CLKM 11 Bit Output Clock Buffer CLOCKGEN 11 Bit INB_P SHA 11-Bit ADC INB_M Channel A 11 Bit Digital Encoder Output Buffers Channel B Digital Processing Block DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 CLKOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 Channel B 2 CMOS INTERFACE CTRL1 CTRL2 CTRL3 Reference RESET SCLK SEN SDATA VCM Control Interface Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com CLIPPER From ADC 11bits output 11bits 11bits 11bits 11 bits To LVDS or CMOS output buffers FINE GAIN (0 to 6 dB, 0.5 dB steps) 0 OFFSET ESTIMATION BLOCK 24TAP FILTER - LOW PASS - HIGH PASS - BAND PASS GAIN CORRECTION (0.05dB steps) DISABLE OFFSET CORRECTION DECIMATION BY2/4/8 FILTER SELECTION 11bits BYPASS FILTER BYPASS DECIMATION FREEZE OFFSET CORRECTION DIGITAL PROCESSING BLOCK Figure 1. Digital Processing Block Diagram PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE LEAD/BALL FINISH PACKAGE MARKING ADS62P15 QFN-64 RGC –40°C to 85°C Cu NiPdAu AZ62P15 (1) (2) ORDERING (2) NUMBER TRANSPORT MEDIA, QUANTITY ADS62P15RGCT 250 Tape/Reel ADS62P15RGCR 2000 Tape/Reel For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM airflow), θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT –0.3 V to 3.9 V –0.3 V to 3.9 V Voltage between AGND and DRGND –0.3 to 0.3 V Voltage between AVDD to DRVDD –0.3 to 3.3 V -0.3 to 2 V –0.3V to minimum ( 3.6, AVDD + 0.3 V ) V Supply voltage range, AVDD, DRVDD VSS Voltage applied to external pin, CM (in external reference mode) Voltage applied to analog input pins, INA_P, INA_M, INB_P, INB_M Voltage applied to clock input pins, CLKP, CLKM TA Operating free-air temperature range TJ Operating junction temperature range Tstg Storage temperature range (1) –0.3 V to AVDD + 0.3 V V –40 to 85 °C 125 °C –65 to 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 3 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES Analog supply voltage, AVDD VSS Digital supply voltage, DRVDD 3 3.3 3.6 CMOS interface 1.65 1.8 to 3.3 3.6 LVDS interface 3.0 3.3 3.6 V V ANALOG INPUTS Differential input voltage range 2 VPP Input common-mode voltage 1.5 ± 0.1 V Voltage applied on CM in external reference mode 1.5 ±0.05 V CLOCK INPUT Fs Input clock sample rate 1 Sine wave, ac-coupled Input clock amplitude differential (VCLKP–VCLKM) 0.4 125 3 LVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 LVCMOS, single-ended, ac-coupled 3.3 Input clock duty cycle 35% MSPS 50% VPP V 65% DIGITAL OUTPUTS Output buffer drive strength (1) For CLOAD ≤ 5 pF and DRVDD ≥ 2.2 V Default strength For CLOAD ≥ 5 pF and DRVDD ≥ 2.2 V Maximum strength For DRVDD < 2.2 V Maximum strength CMOS interface 5 LVDS interface, without internal termination 5 CLOAD Maximum external load capacitance from each output pin to DRGND RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) TA Operating free-air temperature (1) 4 LVDS interface, with 100 Ω internal termination pF 10 Ω 100 –40 85 °C See the Output buffer strength programmability in application section Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Typical values at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 11 bits ANALOG INPUTS Differential input voltage range 2 VPP Differential input resistance (at dc) See Figure 33 >1 MΩ Differential input capacitance See Figure 34 7 pF Analog input bandwidth 450 MHz Analog input common mode current (per input pin) 125 μA VCM common mode voltage output 1.5 VCM output current capability V 4 mA POWER SUPPLY Analog supply current (AVDD) ISS 216 Output buffer supply current (DRVDD) CMOS interface DRVDD=1.8V, 2.5 MHz input signal no load capacitance (1) mA 17 Total power – CMOS interface 0.74 Total power – CMOS interface DRVDD=3.3V, 50MHz input signal 10pF load capacitance Total power – LVDS interface DRVDD = 3.3V W 1.225 W 0.94 Global power down 30 W 60 mW DC ACCURACY No missing codes Specified DNL Differential Non-Linearity -0.8 ±0.4 0.8 LSB INL Integral Non-Linearity -3.5 ±1 3.5 LSB EO Offset Error -10 ±3 10 Offset error temperature coefficient 0.05 mV mV/°C There are two sources of gain error – internal reference inaccuracy and channel gain error EGREF EGCHAN Gain error due to internal reference inaccuracy alone Gain error of channel alone (2) -1 Channel gain error temperature coefficient (1) (2) -1 ±0.25 1 ±0.3 1 0.005 %FS %FS Δ%/°C In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins (see Figure 30). This is specified by design and characterization; it is not tested in production. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 5 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces (unless otherwise noted). PARAMETER TEST CONDITIONS MIN Fin= 10 MHz 65.5 Fin = 70 MHz Signal to noise ratio Fin= 170 MHz Fin = 230 MHz 67.1 66.8 3.5 dB gain 66.4 0 dB gain 66.6 3.5 dB gain 66.2 65 Fin = 70 MHz Fin= 170 MHz Fin = 230 MHz ENOB Effective number of bits 66.9 66.5 3.5 dB gain 66.2 0 dB gain 66.3 3.5 dB gain Fin = 50 MHz Fin = 230 MHz 85 82 3.5 dB gain 84 0 dB gain 78 3.5 dB gain 80 72 Fin = 70 MHz Fin= 170 MHz Fin = 230 MHz 0 dB gain 79 3.5 dB gain 81 0 dB gain 75 3.5 dB gain 77 75 Fin = 70 MHz Fin= 170 MHz Fin = 230 MHz 0 dB gain 85 3.5 dB gain 87 0 dB gain 82 3.5 dB gain 84 75 Fin = 70 MHz Fin= 170 MHz Fin = 230 MHz 6 dBc 89 Fin = 50 MHz Third harmonic distortion 93 93 Fin= 10 MHz HD3 dBc 95 Fin = 50 MHz Second harmonic distortion 77 83 Fin= 10 MHz HD2 dBc 87 Fin = 50 MHz Total harmonic distortion LSB 79 0 dB gain Fin= 10 MHz THD 10.8 89 75 Fin = 70 MHz Fin= 170 MHz dBFS 65.9 10.5 Fin = 50 MHz Spurious free dynamic range 66.9 0 dB gain Fin= 10 MHz SFDR dBFS 67.1 Fin = 50 MHz Signal to noise and distortion ratio UNIT 67.1 0 dB gain Fin= 10 MHz SINAD MAX 67.2 Fin = 50 MHz SNR TYP 79 85 0 dB gain 82 3.5 dB gain 84 0 dB gain 78 3.5 dB gain 80 Submit Documentation Feedback dBc Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces (unless otherwise noted). PARAMETER Worst Spur IMD MIN TYP MAX UNIT 94 Fin = 50 MHz 92 Fin = 70 MHz 94 Fin= 170 MHz 90 Fin = 230 MHz 88 2-Tone intermodulation distortion F1 = 185 MHz, F2 = 190 MHz each tone at –7 dBFS 88 dBFS Recovery to within 1% (of final value) for 6-dB overload with sine wave input 1 Input overload recovery clock cycles Cross-talk signal frequency upto 100 MHz 95 dB 45 dBc Other than second, third harmonics Cross-talk PSRR TEST CONDITIONS Fin= 10 MHz AC Power supply rejection ratio For 100 mV pp signal on AVDD supply, frequency upto 10 MHz dBc Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 7 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com DIGITAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD=3.3V, DRVDD=1.8V to 3.3V, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 μA Low-level input current –33 μA 4 Pf High-level output voltage DRVDD V Low-level output voltage 0 V Output capacitance (internal to device) 2 pF High-level output voltage 1375 mV Low-level output voltage 1025 Input capacitance DIGITAL OUTPUTS – CMOS MODE, DRVDD = 1.8 to 3.3V DIGITAL OUTPUTS – LVDS MODE (1) (2) , DRVDD = 3.3V |VOD| Output differential voltage VOS Output offset voltage Common-mode voltage of OUTP and OUTM Output Capacitance Output capacitance inside the device, from either output to ground (1) (2) 8 250 350 mV 500 mV 1200 mV 2 pF LVDS buffer current setting, IO = 3.5 mA. External differential load resistance between the LVDS output pairs, RLOAD = 100 Ω. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com TIMING REQUIREMENTS – LVDS AND CMOS MODES (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125MSPS, sine wave input clock, 3VPP clock amplitude, CLOAD = 5pF (2) , Io = 3.5mA, RLOAD = 100Ω (3), no internal termination, unless otherwise noted. PARAMETER ta TEST CONDITIONS MIN Aperture delay TYP MAX 0.8 1.8 | ta1 - ta2 | , Channel-to-channel within the same device Aperture delay matching tj 2.8 | ta1 - ta2 | , Channel-to-channel across two devices at same temperature ps 450 130 from global power down Latency from channel standby from output buffer disable ns 50 Aperture jitter Wake-up time to valid output data UNIT fs rms 15 50 μs 100 200 ns CMOS 100 200 ns LVDS 200 500 ns default, after reset 14 clock cycles in low latency mode 10 clock cycles with decimation filter enabled 15 clock cycles DDR LVDS MODE (4) DRVDD = 3.3V Data setup time (5) tsu 0.6 1.5 ns Zero-crossing of CLKOUTP to data becoming invalid(6) 1.0 2.3 ns Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 20 MSPS ≤ Sampling frequency ≤ 125 MSPS 3.5 5.5 7.5 LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP-CLKOUTM) 10 MSPS ≤ Sampling frequency ≤ 125 MSPS 46% 49% 52% tRISE Data rise time Rise time measured from –100 mV to +100 mV 1 MSPS ≤ Sampling frequency ≤ 125 MSPS 70 110 170 ps tFALL Data fall time Fall time measured from +100mV to –100 mV 1 MSPS ≤ Sampling frequency ≤ 125 MSPS 70 110 170 ps tCLKRISE Output clock rise time Rise time measured from –100mV to +100mV 1 MSPS ≤ Sampling frequency ≤ 125 MSPS 70 110 170 ps tCLKFALL Output clock fall time Fall time measured from +100mV to –100mV 1 MSPS ≤ Sampling frequency ≤ 125 MSPS 70 110 170 ps Data valid (7) to 50% of CLKOUT rising edge 2.0 3.5 ns 50% of CLKOUT rising edge to data becoming invalid (7) 2.0 3.5 ns 5.8 7.3 8.8 45% 53% 60% th tPDI Data valid (6) Data hold time (5) to zero-crossing of CLKOUTP ns PARALLEL CMOS MODE DRVDD = 2.5V to 3.3V tsu Data setup time (5) th Data hold time tPDI Clock propagation delay 50% of input clock rising edge to 50% of CLKOUT rising edge 20 MSPS ≤ Sampling frequency ≤ 125 MSPS Output clock duty cycle Duty cycle of output clock, CLKOUT 10 MSPS ≤ Sampling frequency ≤ 125 MSPS tRISE Data rise time Rise time measured from 20% to 80% of DRVDD 1 MSPS ≤ Sampling frequency ≤ 125 MSPS 0.7 1.5 2.5 ns tFALL Data fall time Fall time measured from 80% to 20% of DRVDD 1 MSPS ≤ Sampling frequency ≤ 125 MSPS 0.7 1.5 2.5 ns tCLKRISE Output clock rise time Rise time measured from 20% to 80% of DRVDD 1 MSPS ≤ Sampling frequency ≤ 125 MSPS 0.7 1.5 2.5 ns (1) (2) (3) (4) (5) (6) (7) (5) ns Timing parameters are ensured by design and characterization and not tested in production. CLOAD is the effective external single-ended load capacitance between each output pin and ground IO refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to LOGIC HIGH of +100.0 mV and LOGIC LOW of –100.0mV. Data valid refers to LOGIC HIGH of 2V (1.7V) and LOGIC LOW of 0.8V (0.7V) for DRVDD = 3.3V (2.5V) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 9 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com TIMING REQUIREMENTS – LVDS AND CMOS MODES(1) (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125MSPS, sine wave input clock, 3VPP clock amplitude, CLOAD = 5pF (2) , Io = 3.5mA, RLOAD = 100Ω (3), no internal termination, unless otherwise noted. PARAMETER tCLKFALL Output clock fall time TEST CONDITIONS MIN Fall time measured from 80% to 20% of DRVDD 1 MSPS ≤ Sampling frequency ≤ 125 MSPS TYP MAX 0.7 1.5 3.3 6.0 UNIT 2.5 ns 8.5 ns PARALLEL CMOS INTERFACE, DRVDD = 1.8V, maximum buffer drive strength (8) tSTART Start time Input clock rising edge to data getting valid, tDV (9) (10) Width of valid data window ns PARALLEL CMOS INTERFACE, DRVDD = 1.8V, MULTIPLEXED MODE, FS = 65 MSPS, maximum buffer drive strength tSTART_CHA Start time, channel A Input clock falling edge to channel A data getting valid, tDV_CHA Data valid, channel A Width of valid data window tSTART_CHB Start time, channel B Input clock rising edge to channel B data getting valid tDV_CHB Data valid, channel B Width of valid data window (9) (10) 0.8 5.4 2.3 6.4 ns 1.1 5 ns 2.4 6 ns ns PARALLEL CMOS INTERFACE, DRVDD = 1.8V, MULTIPLEXED MODE, FS = 40 MSPS, maximum buffer drive strength tSTART_CHA Start time, channel A Input clock falling edge to channel A data getting valid, tDV_CHA Data valid, channel A Width of valid data window tSTART_CHB Start time, channel B Input clock rising edge to channel B data getting valid tDV_CHB Data valid, channel B Width of valid data window (9) (10) –4.5 10.3 –4.1 9.7 –3 11.3 ns ns –2.5 10.7 ns ns For DRVDD < 2.2V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the desired setup & hold times at the receiving chip (9) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V for DRVDD = 1.8V. (10) Measured from zero-crossing of input clock having 50% duty cycle. (8) Table 2. Timing Characteristics at Lower Sampling Frequencies tsu DATA SETUP TIME, ns Sampling Frequency, MSPS MIN TYP th DATA HOLD TIME, ns MAX MIN TYP MAX CMOS INTERFACE, DRVDD = 2.5 TO 3.3V 105 2.8 4.3 2.7 4.2 80 4.3 5.8 4.2 5.7 65 5.7 7.2 5.6 7.1 40 10.5 12 10.3 11.8 20 23 24.5 23 24.5 105 1 2.3 80 2.4 3.8 65 3.8 5.2 1.0 2.3 40 8.5 10 20 21 22.5 DDR LVDS INTERFACE, DRVDD = 3.3V 10 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com N+4 N+3 N+2 N+16 N+15 N+1 Sample N N+14 Input Signal ta CLKP Input Clock CLKM CLKOUTM CLKOUTP tsu 14 Clock Cycles DDR LVDS Output Data DXP, DXM E E – Even Bits D0,D2,D4,D6,D8,D10 O – Odd Bits D1,D3,D5,D7,D9 O E N–14 O E N–13 E O N–12 O (1) E N–11 tPDI th O E N–10 E O E O N–1 E O N+1 N E O O N+2 tPDI CLKOUT tsu Parallel CMOS 14 Clock Cycles Output Data D0–D10 N–14 N–13 N–12 (1) N–11 th N–10 N–1 N N+1 N+2 T0105-05 (1) Latency is 10 clock cycles in low-latency mode Figure 2. Latency Diagram Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 11 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com CLKM Input Clock clock CLKP t PDI CLKOUTM Output Clock clock CLKOUTP t su su Output Output Data data Pair pair Dn_Dn+1_P, Dn_Dn+1_M t hh t su su Dn * t hh Dn +1* *Dn - Bits D1, D3, D5, D7, D9 *Dn+1 - Bits D0, D2, D4, D6, D8, D10 Figure 3. LVDS Mode Timing 12 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com CLKM Input Clock clock CLKP t PDI PDI Output Clock clock CLKOUTCLKOUT t su su Output Data data Dn * Dn DAn, DBn t hh CLKM Input Clock clock CLKP t START PDI t DV su Output Data data DAn, DBn Dn * Dn *Dn - Bits D0, D1, D2, . . . of Channels A & B Figure 4. CMOS Mode Timing CLKM CLKP Input Clock clock CLKM CLKP t START_CHA PDI t START_CHB PDI t DV_CHB su t DV_CHA su Output Data data Pin DBn Dn * * *Dn - Bits D0, D1, D2, . . . Figure 5. Multiplexed Mode Timing (CMOS only) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 13 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com DEVICE CONFIGURATION ADS62P15 can be configured independently using either parallel interface control or serial interface programming. USING PARALLEL INTERFACE CONTROL ONLY To control the device using the parallel interface, keep RESET tied to high (AVDD). Pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC. After power-up, the device will automatically get configured as per the parallel pin voltage settings (Table 4 to Table 6). In this mode, SEN and SCLK function as parallel analog control pins, which can be configured using a simple resistor divider (Figure 6, using resistors ≤ 10% tolerance). Table 3 has a brief description of the modes controlled by the parallel pins. SDATA has no parallel function and can be kept low. Table 3. Parallel Pin Definition PIN SCLK SEN CTRL1 CTRL2 CTRL3 TYPE OF PIN CONTROLS MODES Analog control pins (controlled by analog voltage levels, see ) Coarse Gain and Internal/External reference Digital control pins (controlled by digital logic levels) LVDS/CMOS interface and Output Data Format Together control various power down modes and MUX mode. USING SERIAL INTERFACE PROGRAMMING ONLY To program the device using the serial interface, keep RESET low. Pins SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by setting bit = 1. After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since the parallel pins (CTRL1, CTRL2, CTRL3) are not used in this mode, they must be tied to ground. USING BOTH SERIAL INTERFACE and PARALLEL CONTROLS For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3) can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device will automatically get configured as per the voltage settings on these pins (Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by setting bit = 1. After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since the power down modes can be controlled using both the parallel pins and serial registers, the priority between the two is determined by bit. When bit = 0, pins CTRL1 to CTRL3 control the power down modes. With = 1, register bits control these modes, over-riding the pin settings. 14 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com DETAILS OF PARALLEL CONFIGURATION ONLY The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is shown in Figure 6. Table 4. SCLK (Analog Control Pin) VOLTAGE APPLIED ON SCLK DESCRIPTION 0 +200mV/-0mV 0dB gain and Internal reference (3/8)AVDD +/- 200mV 0dB gain and External reference (5/8)2AVDD +/- 200mV 3.5dB Coarse gain and External reference AVDD +0mV/-200mV 3.5dB Coarse gain and Internal reference Table 5. SEN (Analog Control Pin) VOLTAGE APPLIED ON SEN 0 +200mV/-0mV DESCRIPTION 2s complement format and DDR LVDS output (3/8)AVDD +/- 200mV Straight binary and DDR LVDS output (5/8)AVDD +/- 200mV Straight binary and parallel CMOS output AVDD +0mV/-200mV 2s complement format and parallel CMOS output Table 6. CTRL1, CTRL2 and CTRL3 (Digital Control Pins) CTRL1 CTRL2 CTRL3 LOW LOW LOW Normal operation DESCRIPTION LOW LOW HIGH Channel A output buffer disabled LOW HIGH LOW Channel B output buffer disabled LOW HIGH HIGH Channel A and B output buffer disabled HIGH LOW LOW Power down global HIGH LOW HIGH Channel A standby HIGH HIGH LOW Channel B standby HIGH HIGH HIGH MUX mode of operation , channel A and B data is multiplexed and output on DB10 to DB0 pins. See Multiplexed output mode for detailed description. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com AVDD (5 /8 )AVDD 3R ( 5 /8 ) AVDD AVDD GND 2R ( 3 /8 )AVDD ( 3 /8 )AVDD 3R To parallel pin GND Figure 6. Simple Scheme to Configure Parallel Pins 16 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The first 8 bits form the register address and the remaining 8 bits the register data. The interface can work with SCLK frequency from 20 MHz down to low speeds (few Hertz), and also with a non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers must be initialized to their default values. This can be done in one of two ways: 1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as shown in Figure 7. OR 2. By applying software reset. Using the serial interface, set the bit to high. This initializes internal registers to their default values and then self-resets the bit to low. In this case the RESET pin is kept low. SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V, unless otherwise noted. PARAMETER MIN TYP MAX UNIT 20 MHz > DC fSCLK SCLK frequency tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDS SDATA setup time 25 ns tDH SDATA hold time 25 ns REGISTER DATA REGISTER ADDRESS SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 tSCLK D5 D4 tDSU D3 D2 D1 D0 tDH SCLK tSLOADS tSLOADH SEN RESET Figure 7. Serial Interface Timing Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 17 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Serial Register Readout (only when CMOS interface is used) The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. 1. First, set register bit = 1. This also disables any further writes into the registers. 2. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. 3. The device outputs the contents (D7-D0) of the selected register on the SDOUT pin. 4. The external controller can latch the contents at the falling edge of SCLK. 5. To enable register writes, reset register bit =0. The serial register readout works only with CMOS interface; with LVDS interface, pin 56 functions as CLKOUTM. When is disabled, SDOUT pin is forced low or high by the device (and not put in high-impedance). If serial readout is not used, SDOUT pin must be floated. A) Enable serial read back ( = 1) (Serial register writes are disabled) R EGIST ER A DDR ESS (A7:A0) = 0x00 SDA TA 0 0 0 0 0 0 0 REGISTER DAT A (D7:D 0) = 0x01 0 0 0 0 0 0 0 0 1 SC LK SEN SDOUT Pin SD OU T is NOT in hig h-im ped ance state; it is forced low o r h ig h b y th e de vice ( = 0) B) Read contents of register 0x14. This register has been initialized with 0xB0 (over-ride bit set, LVDS interface, 3.5dB coarse gain, internal reference, normal operation) REGISTER ADD RESS (A 7:A 0) = 0x14 SDA TA A7 A6 A5 A4 A3 A2 A1 R EGIST ER D ATA (D 7:D 0) = XX (do n’ t care) A0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 0 0 0 0 SC LK SEN SDOUT Pin SDOUT fu nc tio ns as serial reado u t ( = 1) Figure 8. Serial Readout 18 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise noted. PARAMETER CONDITIONS t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse width t3 Register write delay tPO Power-up time Delay from power-up of AVDD and DRVDD to output stable MIN TYP MAX UNIT 5 ms Pulse width of active RESET signal 10 ns Delay from RESET disable to SEN active 25 ns 7 ms NOTE: : A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 9. Reset Timing Diagram Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 19 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com SERIAL REGISTER MAP Table 7. Summary of Functions Supported by Serial Interface REGISTER ADDRESS REGISTER FUNCTIONS A7–A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 Software Reset 0 0 0 0 0 0 10 LVDS buffer current double 0 0 12 0 0 13 0 0 0 0 14 Over-ride bit 0 LVDS or CMOS interface 3.5 dB gain Internal/External reference and MUX mode 16 0 0 0 2s complement or straight binary Bit/Byte wise (LVDS only) 17 0 0 0 0 19 0 0 1A 1B Other correction enable 0 In-built or custom coefficients Enable decimation 1D 0 0 0 0 0 Internal termination programmability 0 0 0 0 to 6 dB gain in 0.5 dB steps Lower 5bits 0 0 0 Upper 6 bits Offset correction time constant 1E to 2F (1) LVDS buffer current programmability 11 18 20 (1) 0 to 0.5 dB, steps of 0.05 dB Decimate by 2, 4, 8 0 12 coefficients, each 12 bit signed Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com DESCRIPTION OF SERIAL REGISTERS Table 8. A7–A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 Software Reset D1 1 Software reset applied – resets all internal registers and self-clears to 0. D0 1 0 Serial readout disabled. SDOUT pin is forced low or high by the device ( and not put in high-impedance state) Serial readout enabled, SDOUT functions as serial data readout pin. Table 9. A7–A0 (hex) 10 D7–D6 01 00 11 10 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D1 D0 Output clock buffer drive strength control WEAKER than default drive DEFAULT drive strength STRONGER than default drive strength (recommended for load capacitances > 5 pF) MAXIMUM drive strength (recommended for load capacitances > 5 pF) Table 10. A7–A0 (hex) D7 D6 11 0 0 D5 D4 LVDS buffer current double D3 D2 LVDS CURRENT> LVDS buffer current programmability D1–D0 01 00 11 10 Output data buffer drive strength control WEAKER than default drive DEFAULT drive strength STRONGER than default drive strength (recommended for load capacitances > 5 pF) MAXIMUM drive strength (recommended for load capacitances > 5 pF) D3–D2 00 01 10 11 LVDS Current programmability 3.5 mA 2.5 mA 4.5 mA 1.75 mA D5–D4 00 01 10 11 CURRENT DOUBLE> LVDS Current double control default current, set by LVDS clock buffer current is doubled, 2x LVDS data and clock buffers current are doubled, 2x unused DATAOUT STRENGTH> Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 21 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Table 11. A7–A0 (hex) 12 D7 D6 0 0 D5 D4 D3 D2 D1 D0 Internal termination programmability D5–D3 000 001 010 011 100 101 110 111 Internal termination control for data outputs No internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω D2–D0 000 001 010 011 100 101 110 111 Internal termination control for clock output No internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω Table 12. A7–A0 (hex) 13 D4 0 1 22 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Offset correction becomes inactive and the last estimated offset value is used to cancel the offset Offset correction active Offset correction inactive Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Table 13. A7–A0 (hex) D7 14 Over-ride bit D6 D5 D4 D3 0 LVDS or CMOS interface 3.5 dB gain Internal / External reference D2 D1 D0 D2-D0 000 001 010 011 100 101 110 111 Normal operation Channel A output buffer disabled Channel B output buffer disabled Channel A and B output buffers disabled Global power down Channel A standby Channel B standby Multiplexed mode, MUX– (only with CMOS interface) Channel A and B data is multiplexed and output on DB10 to DB0 pins. D3 0 1 Reference mode Internal reference enabled External reference enabled D4 0 1 Coarse gain control 0 dB coarse gain 3.5 dB coarse gain D5 0 1 Output interface selection Parallel CMOS data outputs DDR LVDS data outputs D7 Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins. By setting = 1, register bits LVDS and will over-ride the settings of the parallel pins. Disable over-ride Enable over-ride 0 1 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 23 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Table 14. A7–A0 (hex) D7 D6 D5 D4 D3 16 0 0 0 DATA FORMAT> 2s complement or straight binary Bit / Byte wise (LVDS only) D2 D1 D0 D2–D0 000 001 010 011 100 101 110 111 Test Patterns to verify capture Normal ADC operation Outputs all zeros Outputs all ones Outputs toggle pattern Outputs digital ramp Outputs custom pattern Unused Unused D3 Bit-wise/Byte-wise selection (DDR LVDS mode ONLY) 0 1 Bit wise – Odd bits (D1, D3, D5, D7, D9) on CLKOUT rising edge and Even bits (D0, D2, D4, D6, D8, D10) on CLKOUT falling edge Byte wise – Lower 7 bits (D0-D6) at CLKOUT rising edge and Upper 4 bits (D7-D10) at CLKOUT falling edge D4 0 1 Data format selection 2s complement Straight binary Table 15. A7–A0 (hex) 17 D7 D6 D5 D4 0 0 0 0 D3 D2 D1 D0 0 to 6 dB gain in 0.5 dB steps Gain programmability in 0.5 dB steps 0 dB gain, default after reset 0.5 dB gain 1.0 dB gain 1.5 dB gain 2.0 dB gain 2.5 dB gain 3.0 dB gain 3.5 dB gain 4.0 dB gain 4.5 dB gain 5.0 dB gain 5.5 dB gain 6.0 dB gain Unused D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Others Table 16. A7–A0 (hex) 18 19 D7 0 D6 D5 D4 Lower 5bits 0 D3 0 Upper 6 bits D7-D4 5 lower bits of custom pattern available at the output instead of ADC data. D5-D0 6 upper bits of custom pattern available at the output instead of ADC data. 24 D2 Submit Documentation Feedback D1 D0 0 0 Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Table 17. A7–A0 (hex) D7 1A D6 D5 D4 D3 Offset correction time constant D2 D1 D0 0 to 0.5 dB, steps of 0.05 dB D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels) 0 dB gain, default after reset +0.5 dB gain +0.10 dB gain +0.15 dB gain +0.20 dB gain +0.25 dB gain +0.30 dB gain +0.35 dB gain +0.40 dB gain +0.45 dB gain +0.5 dB gain D6-D4 000 001 010 011 100 101 110 111 Time constant of offset correction in number of clock cycles (seconds, for sampling frequency = 125MSPS) 227 (1.1 s) 226 (0.55 s) 225 (0.27 s) 224 (0.13 s) 228 (2.15 s) 229 (4.3 s) 227 (1.1 s) 227 (1.1 s) D7 0 1 Default latency, 13 clock cycles Low latency enabled, 9 clock cycles – Digital Processing Block is bypassed. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 25 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Table 18. A7–A0 (hex) D7 1B Offset correction enable D6 D5 D4 D3 D2 0 In-built or custom coefficients Enable decimation D2-D0 000 001 011 100 Decimation filters Decimate by 2 (pre-defined or user coefficients can be used) Decimate by 4 (pre-defined or user coefficients can be used) No decimation (Pre-defined coefficients are disabled, only custom coefficients are available) Decimate by 8 (Only custom coefficients are available) D3 0 1 Even taps enabled (24 coefficients) 0 Odd taps enabled (23 coefficients) D4 0 1 Decimation disabled 0 Decimation enabled D5 0 1 Pre-defined coefficients are loaded in the filter User-defined coefficients are loaded in the filter (coefficients have to be loaded in registers – to - ) D7 0 1 Offset correction disabled Offset correction enabled D1 D0 Decimate by 2,4,8 Table 19. A7–A0 (hex) 1D D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 00 01 10, 11 Decimation filters With decimate by 2, = 000: Low pass filter (–6 dB frequency at Fs/4) High pass filter (–6 dB frequency at Fs/4) Unused 00 01 10 11 With decimate by 4, = 001: Low pass filter (-3 dB frequency at Fs/8) Band pass filter (center frequency at 3Fs/16) Band pass filter (center frequency at 5Fs/16) High pass filter (-3 dB frequency at 3Fs/8) D1-D0 26 Submit Documentation Feedback D1 D0 Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com NC DRGND DRVDD CLKOUT SDOUT DA10 DA9 DA8 DA7 DA6 DA5 63 62 61 60 59 58 57 56 55 54 53 52 51 50 DRGND NC 64 1 NC DRVDD DB0 DRGND PIN DESCRIPTION (CMOS INTERFACE) 49 48 DRVDD DB1 2 47 DA4 DB2 3 46 DA3 DB3 4 45 DA2 DB4 5 44 DA1 DB5 6 43 DA0 DB6 7 42 NC DB7 8 41 NC DB8 9 40 NC DB9 10 39 DRGND DB10 11 38 DRVDD RESET 12 37 CTRL3 SCLK 13 36 CTRL2 SDATA 14 35 CTRL1 SEN 15 34 AVDD AVDD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 32 AGND AGND INM_B INP_B AGND AGND VCM AGND CLKP CLKM AGND AGND INM_A INP_A AGND AGND AVDD PAD (Connected to DRGND ) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 27 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (CMOS INTERFACE) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS AVDD Analog power supply 16, 33, 34 3 AGND Analog ground 17, 18, 21, 22, 24, 27, 28, 31, 32 9 CLKP, CLKM Differential input clock 25, 26 2 INM_A, INP_A Differential input signal – channel A. When not used, the analog input pins (INM_A, INP_A) MUST be tied to VCM and CANNOT be floated. 29, 30 2 INM_B, INP_B Differential input signal – channel B. When not used, the analog input pins (INM_B, INP_B) MUST be tied to VCM and CANNOT be floated. 19, 20 2 VCM Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the ADC internal references. 23 1 RESET Serial interface RESET input. In serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset (refer to Serial Interface section). In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100 kΩ pull-down resistor. 12 1 SCLK This pin functions as serial interface clock input when RESET is low. It functions as analog control pin when RESET is tied high & controls coarse gain and internal/external reference selection. See Table 4 for details. The pin has an internal pull-down resistor to ground. 13 1 SDATA This pin functions as serial interface data input when RESET is low. The pin has an internal pull-down resistor to ground. 14 1 SEN This pin functions as serial interface enable input when RESET is low. It functions as analog control pin when RESET is tied high & controls the output interface (LVDS/CMOS) and data format selection. See Table 5 for details. The pin has an internal pull-up resistor to AVDD. 15 1 CTRL1 These are digital logic input pins. Together they control various power down and multiplexed mode. see Table 6 for details 35 1 36 1 CTRL2 CTRL3 37 1 DA0 to DA10 Channel A 11-bit data outputs, CMOS 43 - 47, 50 55 11 DB0 to DB10 Channel B 11-bit data outputs, CMOS 63, 2 - 11 11 CLKOUT CMOS Output clock 57 1 DRVDD Digital supply 1, 38, 48, 58 4 DRGND Digital ground 39, 49, 59, 64 and PAD 4 PAD Digital ground. Solder the pad to the digital ground on the board using multiple vias for good electrical and thermal performance. – 1 SDOUT It functions as serial data readout pin ONLY when =1. When = 0, SDOUT pin is forced low or high by the device (and not put in high-impedance state). If serial readout is not used, SDOUT pin has to be floated & should not be connected on the board. 56 1 NC Do not connect 40, 41, 42, 60, 61, 62 7 28 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com DB2M 2 DB2P 3 DB4M NC DRGND DRVDD CLKOUTP CLKOUTM DA10P DA10M DA8P DA8M DA6P DA6M 63 62 61 60 59 58 57 56 55 54 53 52 51 50 DRGND NC 64 1 DB0M DRVDD DB0P DRGND PIN DESCRIPTION (LVDS INTERFACE) 49 48 DRVDD 47 DA4P 46 DA4M 4 45 DA2P DB4P 5 44 DA2M DB6M 6 43 DA0P DB6P 7 42 DA0M DB8M 8 41 NC DB8P 9 40 NC DB10M 10 39 DRGND DB10P 11 38 DRVDD RESET 12 37 CTRL3 SCLK 13 36 CTRL2 SDATA 14 35 CTRL1 SEN 15 34 AVDD AVDD 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 32 AGND INM_B INP_B AGND AGND VCM AGND CLKP CLKM AGND AGND INP_A AGND AGND INM_A 16 17 AGND AVDD PAD (Connected to DRGND ) Pin Assignments (LVDS INTERFACE) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS AVDD Analog power supply 16, 33, 34 3 AGND Analog ground 17, 18, 21, 22, 24, 27, 28, 31,32 9 CLKP, CLKM Differential input clock 25, 26 2 INM_A, INP_A Differential input signal – Channel A. When not used, the analog input pins (INM_A, INP_A) MUST be tied to VCM and CANNOT be floated. 29, 30 2 INM_B, INP_B Differential input signal – Channel B. When not used, the analog input pins (INM_B, INP_B) MUST be tied to VCM and CANNOT be floated. 19, 20 2 VCM Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the ADC internal references. 23 1 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 29 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (LVDS INTERFACE) (continued) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS RESET Serial interface RESET input. In serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset (refer to Serial Interface section). In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100 kΩ pull-down resistor. 12 1 SCLK This pin functions as serial interface clock input when RESET is low. It functions as analog control pin when RESET is tied high & controls coarse gain and internal/external reference selection. See Table 4 for details. The pin has an internal pull-down resistor to ground. 13 1 SDATA This pin functions as serial interface data input when RESET is low. The pin has an internal pull-down resistor to ground. 14 1 SEN This pin functions as serial interface enable input when RESET is low. It functions as analog control pin when RESET is tied high & controls the output interface (LVDS/CMOS) and data format selection. See Table 5 for details. The pin has an internal pull-up resistor to AVDD. 15 1 CTRL1 These are digital logic input pins. Together they control various power down and multiplexed mode. See Table 6 for details. 35 1 36 1 37 1 40, 41, 60, 61 4 CTRL2 CTRL3 NC Do not connect DA0P Channel A Differential output data 0 and D0 multiplexed, true 43 1 DA0M Channel A Differential output data 0 and D0 multiplexed, complement 42 1 DA2P Channel A Differential output data D1 and D2 multiplexed, true 45 1 DA2M Channel A Differential output data D1 and D2 multiplexed, complement 44 1 DA4P Channel A Differential output data D3 and D4 multiplexed, true 47 1 DA4M Channel A Differential output data D3 and D4 multiplexed, complement 46 1 DA6P Channel A Differential output data D5 and D6 multiplexed, true 51 1 DA6M Channel A Differential output data D5 and D6 multiplexed, complement 50 1 DA8P Channel A Differential output data D7 and D8 multiplexed, true 53 1 DA8M Channel A Differential output data D7 and D8 multiplexed, complement 52 1 DA10P Channel A Differential output data D9 and D10 multiplexed, true 55 1 DA10M Channel A Differential output data D9 and D10 multiplexed, complement 54 1 CLKOUTP Differential output clock, true 57 1 CLKOUTM Differential output clock, complement 56 1 DB0P Channel B Differential output data 0 and D0 multiplexed, true 63 1 DB0M Channel B Differential output data 0 and D0 multiplexed, complement 62 1 DB2P Channel B Differential output data D1 and D2 multiplexed, true 3 1 DB2M Channel B Differential output data D1 and D2 multiplexed, complement 2 1 DB4P Channel B Differential output data D3 and D4 multiplexed, true 5 1 DB4M Channel B Differential output data D3 and D4 multiplexed, complement 4 1 DB6P Channel B Differential output data D5 and D6 multiplexed, true 7 1 DB6M Channel B Differential output data D5 and D6 multiplexed, complement 6 1 DB8P Channel B Differential output data D7 and D8 multiplexed, true 9 1 DB8M Channel B Differential output data D7 and D8 multiplexed, complement 8 1 DB10P Channel B Differential output data D9 and D10 multiplexed, true 11 1 DB10M Channel B Differential output data D9 and D10 multiplexed, complement 10 1 DRVDD Digital supply 1, 38, 48, 58 4 30 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (LVDS INTERFACE) (continued) PIN NAME DESCRIPTION DRGND Digital ground PAD Digital ground. Solder the pad to the digital ground on the board using multiple vias for good electrical and thermal performance. PIN NUMBER NUMBER OF PINS 39, 49, 59, 64 and PAD 4 – 1 TYPICAL CHARACTERISTICS All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless otherwise noted). SPECTRUM FOR 20MHZ INPUT SIGNAL SPECTRUM FOR 70MHZ INPUT SIGNAL 0 0 SFDR = 88.8 dBc SINAD = 67 dBFS SNR = 67.1 dBFS THD = 88 dBc −40 −60 −80 −40 −60 −80 −100 −100 −120 −120 −140 −140 0 10 20 30 40 50 60 f − Frequency − MHz 0 10 20 30 40 50 60 f − Frequency − MHz G001 G002 Figure 10. Figure 11. SPECTRUM FOR 190MHZ INPUT SIGNAL SPECTRUM FOR 2-TONE INPUT SIGNAL (INTERMODULATION DISTORTION) 0 0 SFDR = 79.1 dBc SINAD = 66.4 dBFS SNR = 66.7 dBFS THD = 77.5 dBc −20 −40 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –88.8 dBFS SFDR = –96 dBFS −20 Amplitude − dB Amplitude − dB SFDR = 86.7 dBc SINAD = 67 dBFS SNR = 67 dBFS THD = 85.1 dBc −20 Amplitude − dB Amplitude − dB −20 −60 −80 −40 −60 −80 −100 −100 −120 −120 −140 −140 0 10 20 30 40 f − Frequency − MHz 50 60 0 G003 Figure 12. 10 20 30 40 50 60 f − Frequency − MHz G004 Figure 13. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 31 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless otherwise noted). SFDR vs INPUT FREQUENCY (CMOS INTERFACE) SNR vs INPUT FREQUENCY (CMOS INTERFACE) 70 94 92 88 SNR − dBFS SFDR − dBc 69 Gain = 3.5 dB 90 86 84 68 Gain = 0 dB 67 Gain = 3.5 dB 66 82 80 Gain = 0 dB 65 78 76 64 0 25 50 75 100 125 150 175 0 200 fIN − Input Frequency − MHz 25 50 75 100 125 150 175 fIN − Input Frequency − MHz G005 Figure 14. 200 G006 Figure 15. SFDR vs INPUT FREQUENCY (LVDS INTERFACE) SNR vs INPUT FREQUENCY (LVDS INTERFACE) 95 70 93 69 Gain = 3.5 dB 89 SNR − dBFS SFDR − dBc 91 87 85 83 68 Gain = 0 dB 67 81 Gain = 3.5 dB Gain = 0 dB 79 66 77 75 65 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz 0 25 50 75 G007 Figure 16. SFDR vs INPUT FREQUENCY ACROSS GAINS 150 175 200 G008 SINAD vs INPUT FREQUENCY ACROSS GAINS 72 Input adjusted to get −1dBFS input Input adjusted to get −1dBFS input 70 2 dB 3 dB 0 dB 5 dB 4 dB SINAD − dBFS 95 SFDR − dBc 125 Figure 17. 100 90 85 80 6 dB 1 dB 0 dB 1 dB 68 2 dB 66 64 3 dB 5 dB 4 dB 62 75 6 dB 60 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 0 G009 Figure 18. 32 100 fIN − Input Frequency − MHz 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 G010 Figure 19. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless otherwise noted). PERFORMANCE vs AVDD SUPPLY PERFORMANCE vs DRVDD SUPPLY 88 88 69.0 87 87 68.5 SFDR 69.0 fIN = 70.1 MHz AVDD = 3.31 V 68.5 85 67.5 SNR 84 3.1 3.2 3.3 3.4 AVDD − Supply Voltage − V 67.5 SNR 84 67.0 83 66.5 82 1.8 66.0 3.6 3.5 85 2.0 2.2 2.4 PERFORMANCE vs TEMPERATURE 87 68.5 85 67.5 SNR 84 67.0 83 SFDR − dBc 68.0 66.5 80 T − Temperature − °C 90 SFDR 80 50 75 SNR 40 65 20 60 10 55 50 −50 −40 −10 0 G014 PERFORMANCE vs INPUT CLOCK DUTY CYCLE 92 73 fIN = 20.1 MHz 72 SFDR 71 fIN = 20.1 MHz 90 70 88 70 86 69 84 68 SNR 82 67 80 66 1.5 2.0 Input Clock Amplitude − VPP 65 2.5 SFDR − dBc 71 SNR − dBFS SFDR − dBc −20 Figure 23. PERFORMANCE vs INPUT CLOCK AMPLITUDE 1.0 −30 Input Amplitude − dBFS G013 94 0.5 70 30 Figure 22. 78 0.0 85 60 0 −60 66.0 60 95 fIN = 20.1 MHz 70 SNR − dBFS SFDR − dBc 86 90 G012 80 SFDR 92 66.0 3.6 100 90 40 3.4 PERFORMANCE vs INPUT AMPLITUDE fIN = 70.1 MHz 20 3.2 100 69.0 0 3.0 Figure 21. 88 −20 2.8 DRVDD − Supply Voltage − V G011 Figure 20. 82 −40 2.6 SNR − dBFS 82 3.0 66.5 fIN = 70.1 MHz DRVDD = 3.31 V 68.0 88 69 SFDR 86 68 SNR 84 67 82 66 80 SNR − dBFS 83 67.0 86 SNR − dBFS 68.0 SFDR − dBc 86 SNR − dBFS SFDR − dBc SFDR 65 35 40 G015 Figure 24. 45 50 55 60 65 Input Clock Duty Cycle − % G016 Figure 25. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 33 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless otherwise noted). OUTPUT NOISE HISTOGRAM (INPUTS TIED TO COMMON-MODE) PERFORMANCE IN EXTERNAL REFERENCE MODE 70 93 75 fIN = 20.1 MHz External Reference Mode 60 73 40 30 SFDR 89 SNR − dBFS SFDR − dBc Occurence − % 91 50 71 87 69 20 SNR 85 67 10 0 83 1.30 1018 1019 1020 1021 1022 1023 1024 1025 Output Code 1.40 1.45 1.50 1.55 1.60 1.65 65 1.70 VVCM − VCM Voltage − V G017 G018 Figure 27. COMMON-MODE REJECTION RATIO vs FREQUENCY POWER DISSIPATION vs SAMPLING FREQUENCY (DDR LVDS AND CMOS) 0 1.0 −10 0.9 PD − Power Dissipation − W Figure 26. −20 −30 CMRR − dBc 1.35 −40 −50 −60 −70 −80 fIN = 2.5 MHz CL = 5 pF 0.8 LVDS 0.7 0.6 0.5 CMOS 0.4 0.3 0.2 0.1 −90 0.0 −100 0 25 50 75 100 125 150 175 0 200 f − Frequency − MHz 25 50 75 100 fS − Sampling Frequency − MSPS G019 Figure 28. 125 G020 Figure 29. DRVDD CURRENT vs SAMPLING FREQUENCY ACROSS LOAD CAPACITANCE (CMOS) 70 3.3 V, No Load DRVDD Current − mA 60 1.8 V, 5 pF 50 1.8 V, 10 pF 3.3 V, 5 pF 40 3.3 V, 10 pF 30 20 10 1.8 V, No Load 0 0 25 50 75 100 fS − Sampling Frequency − MSPS 125 G021 Figure 30. 34 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ADS62P15 is a low power 11-bit dual channel pipeline ADC family fabricated in a CMOS process using switched capacitor techniques. The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline resulting in a data latency of 14 clock cycles. The output is available as 11-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary 2s complement format. ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology results in very good AC performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available on VCM pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5V and VCM – 0.5V, resulting in a 2VPP differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.5V nominal) and REFM (0.5V, nominal). Sampling switch Lpkg~ 2 nH Sampling capacitor RCR Filter INP 25 E Cbond ~ 1 pF Cpar2 1 pF 50 E Resr 100 E 3.2 pF 25 E Resr 100 E Ron 10 E Ron 15 E INM Cbond ~ 1 pF Csamp 4.0 pF Cpar1 0.8 pF 50 E Lpkg~ 2 nH Ron 15 E Csamp 4.0 pF Sampling capacitor Cpar2 1 pF Sampling switch Figure 31. Analog Input Equivalent Circuit The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins to the sampled voltage). Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 35 ADS62P15 SLAS572C – OCTOBER 2007 – REVISED FEBRUARY 2012 www.ti.com 1 0 Magnitude − dB −1 −2 −3 −4 −5 −6 −7 0 100 200 300 400 500 fI − Input Frequency − MHz 600 G022 Figure 32. ADC Analog Bandwidth Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A