ADS7871IDBR

 SLAS370C − APRIL 2002 − REVISED OCTOBER 2004     


      

  
   

  FEATURES DESCRIPTION D PGA Gains: 1, 2, 4, 5, 8, 10, 16, 20 V/V D Programmable Input (Up to 4-Channel D D D D D D D D D Differential/Up to 8-Channel Single-Ended or Some Combination) 1.15-V, 2.048-V, or 2.5-V Internal Reference SPI/DSP Compatible Serial Interface (≤ 20 MHz) Throughput Rate: 48 kSamples/sec Error Overload Indicator Programmable Output 2s Complement/Binary 2.7-V to 5.5-V Single Supply Operation 4-Bit Digital I/O Via Serial Interface Pin-Compatible With ADS7870 SSOP-28 Package Portable Battery-Powered Systems Low-Power Instrumentation Low-Power Control Systems Smart Sensor Applications LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7 I/O0 I/O1 I/O2 I/O3 For many low-level signals, no external amplification or impedance buffering is needed between the signal source and the A/D input. The offset voltage of the PGA is auto-zeroed. Gains of 1, 2, 4, 5, 8, 10, 16, and 20 V/V allow signals as low as 125 mV to produce full-scale digital outputs. The serial interface allows the use of SPI, QSPI, Microwire, and 8051-family protocols, without glue logic. BUFIN REF VREF The programmable-gain amplifier provides high input impedance, excellent gain accuracy, good common-mode rejection, and low noise. The ADS7871 contains an internal reference, which is trimmed for high initial accuracy and stability vs temperature. Drift is typically 10 ppm/°C. An external reference can be used in situations where multiple ADS7871s share a common reference. APPLICATIONS D D D D The ADS7871 (US patents 6140872, 6060874) is a complete low power data acquisition system on a single chip. It consists of a 4-channel differential/8-channel single-ended multiplexer, precision programmable gain amplifier, 14-bit successive approximation analog-todigital (A/D) converter, and a precision voltage reference. BUFOUT/REFIN Oscillator CCLK OSC ENABLE MUX + PGA _ BUSY 14-BIT A/D CONVERT RESET RISE/FALL Digital I/O Registers Serial Interface CS SCLK DIN DOUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.   

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 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ADS7871 SSOP-28 Surface Mount DB −40°C to +85°C PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS7871 ADS7871IDB Rails, 48 ADS7871 ADS7871IDBR Tape and Reel, 1000 (1) For the most current package and ordering information, see the package option addendum located at the end of this data sheet. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage, VDD 5.5 V Momentary Analog inputs Input current Input voltage Operating free-air temperature range, TA Storage temperature range, TSTG Continuous 100 mA 10 mA VDD + 0.5 V to GND − 0.5 V −40°C to 85°C −65°C to 150°C Junction temperature (TJ max) 150°C Lead temperature, (10 sec) 300°C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 
 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS For the Total System (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Input voltage (LNx inputs) Input capacitance (2) Input impedance (2) Linear operation −0.2 VDD + 0.2 9.7 4 Common mode 6 Differential 7 Channel-to-channel crosstalk VI = 2 VPP, 60 Hz (3) Maximum leakage current V pF MΩ 100 dB 100 pA 14 Bits Static Accuracy Resolution No missing codes G = 1 to 20 V/V 13 Integral linearity G = 1 to 20 V/V −4 ±2 Differential linearity G = 1 to 20 V/V −2 Offset error G = 1 to 20 V/V −24 Ratiometric configuration or external reference (4) Full-scale gain error Internal reference DC common-mode rejection ratio, RTI Power supply rejection ratio, RTI G = 1 to 10 V/V Bits 4 LSB ±0.5 4 LSB ±1 24 LSB −0.2 0.2 %FSR G = 16 and 20 V/V −0.25 0.25 %FSR G = 1 to 10 V/V −0.35 0.35 %FSR 0.4 %FSR G = 16 and 20 V/V −0.4 VI = −0.2 V to 5.2 V, G = 20 V/V VDD = 5 V ±10%, G = 20 V/V 80 dB 88 dB Dynamic Characteristics Throughput rate Continuous mode One channel 48 Address mode Different channels 48 External clock, CCLK (5) 0.1 Internal oscillator frequency 20 2.5 Serial interface clock, SCLK ksample/s MHz MHz 20 MHz Data setup time 10 ns Data hold time 10 ns Digital Inputs Low-level input voltage, VIL Logic levels High-level input voltage, VIH 0.8 VDD ≤ 3.6 V VDD > 3.6 V 2 V V 3 V Low-level input current, IIL 1 High-level input current, IIH 1 µA A (1) The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate the performance of the individual functions in the ADS7871. (2) The ADS7871 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that the input capacitance at any selected LNx pin changes during the conversion cycle. (3) One channel on with its inputs grounded. All other channels off with sinewave voltage applied to their inputs. (4) Ratiometric configuration exists when the input source is configured such that changes in the reference cause corresponding changes in the input voltage. The same accuracy applies when a perfect external reference is used. (5) The CCLK is divided by the DF value specified by the contents of register 3, A/D Control register, bits D0 and D1 to produce DCLK. The maximum value of DCLK is 2.5 MHz. 3 
 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS For the Total System (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Outputs Data coding Binary 2s complement Low-level output voltage, VOL ISINK = 5 mA ISINK = 16 mA High-level output voltage, VOH ISOURCE = 0.5 mA ISOURCE = 5 mA Logic levels Leakage current 0.4 V 0.8 VDD − 0.4 V 4.6 Hi-Z state, VO = 0 V to VDD 1 Output capacitance 5 µA pF Voltage Reference Bandgap voltage reference VREF = 2.048 V, 2.5 V VREF = 1.15 V Pin 26 used as output, Use internal OSC or external CCLK as conversion clock −0.25 Output drive ±0.05 0.25 %FSR 1.15 V ±0.6 µA Reference Buffer Input voltage, BUFIN 0.9 Input impedance, BUFIN At pin 27 Input offset Output voltage accuracy vs temperature, BUFOUT/REFIN (2) (3) Pin 28 used as output, VREF = 2.048 V and 2.5 V VDD − 0.2 1000||3 V GΩ||pF −10 ±1 10 −0.25 ±0.05 0.25 %FSR 10 50 ppm/°C Output drive, BUFOUT/REFIN 20 mV mA Power Supply Requirements Supply voltage Power supply current (2) Power dissipation (2) 2.7 5.5 1-kHz Sample rate REF and BUF on, Internal oscillator on 1.2 48-kHz Sample rate REF and BUF on, External CCLK 1.7 Power down REF, BUF, Internal oscillator off 1-kHz Sample rate REF and BUF on, Internal oscillator on 48-kHz Sample rate REF and BUF on, External CCLK Power down REF and BUF off mA 2 mA 1 µA 6 8.5 V mW 11 mW 5 µW Temperature Range Operating free-air −40 85 °C Storage range −65 150 °C Thermal resistance, QJA 65 °C/W (1) The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate the performance of the individual functions in the ADS7871. (2) REF and BUF contribute 190 µA and 150 µA (950 µW and 750 µW) respectively. At initial power up the default condition for both REF and BUF functions is power off. They can be turned on under software control by writing a 1 to D3 and D2 of register 7, REF/OSCILLATOR CONTROL register. (3) For VDD < 3 V, VREF = 2.5 V is not usable. 4 
 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS For Internal Functions (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Multiplexer On resistance 100 Off resistance Off channel leakage current On channel leakage current Ω 1 GΩ 100 pA On channel = 0 V, Off channel = 5.2 V 100 pA On channel = 5.2 V, Off channel = 0 V 100 pA On channel = 0 V, Off channel = 5.2 V 100 pA On channel = 5.2 V, Off channel = 0 V VLNx = 5.2 V PGA Amplifier Offset voltage 100 Small signal bandwidth Settling time 5/Gain µV MHz G=1 0.3 µs G = 20 6.4 µs Analog-To-Digital Converter DC Characteristics Resolution 14 Bits Integral linearity error ±2 LSB ±0.5 LSB Differential linearity error No missing codes Offset error REFIN = 2.5 V Full-scale (gain) error Common mode rejection, RTI of A/D 14 Bits ±2 LSB ±0.02 % 60 dB 60 dB Power supply rejection, RTI of ADS7871 External reference, VDD = 5 V ±10% PGA Plus A/D Converter Sampling Dynamics Throughput rate fCCLK = 2.5 MHz, DF = 1 50 CCLK cycles 50 kHz Conversion time 14 CCLK cycles 5.6 µs Acquisition time 28 CCLK cycles 9.6 µs Auto zero time 8 CCLK cycles 3.2 µs Aperture delay 36 CCLK cycles 12.8 Small signal bandwidth Step response 5 µs MHz 1 Complete Conversion Cycle (1) The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate the performance of the individual functions in the ADS7871. 5 
 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 PIN ASSIGNMENTS SSOP-28 PACKAGE (TOP VIEW) LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7 RESET RISE/FALL I/O0 I/O1 I/O2 I/O3 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 BUFOUT/REFIN BUFIN VREF GND VDD CS DOUT DIN SCLK CCLK OSC ENABLE BUSY CONVERT GND Terminal Functions TERMINAL NO. 1−8 6 NAME I/O DESCRIPTION LN0−LN7 AI MUX input lines 0−7 9 RESET DI Master reset, zeros all registers 10 RISE/FALL DI Sets the active edge for SCLK. 0 sets SCLK active on falling edge. 1 sets SCLK active on rising edge. 11−14 I/O0−I/O3 DIO Digital input or output signal 15 GND − Connect to ground. (This pin is grounded internally on the ADS7871. It has a weak pulldown on the ADS7870). 16 CONVERT DI 0 to 1 transition starts a conversion cycle. 17 BUSY DO 1 indicates converter is busy 18 OSC ENABLE DI 0 sets CCLK as an input, 1 sets CCLK as an output and turns the oscillator on. 19 CCLK DIO If OSC ENABLE = 1, then the internal oscillator is output to this pin. If OSC ENABLE = 0, then this is the input pin for an external conversion clock. 20 SCLK DI Serial data input/output transfer clock. Active edge set by the RISE/FALL pin. If RISE/FALL is low, SCLK is active on the falling edge. 21 DIN DIO Serial data input. In the 3-wire mode, this pin is used for serial data input. In the 2-wire mode, serial data output appears on this pin as well as the DOUT pin. 22 DOUT DO Serial data output. This pin is driven when CS is low and is high impedance when CS is high. This pin behaves the same in both 3-wire and 2-wire modes. 23 CS DI Chip select. When CS is low, the serial interface is enabled. When CS is high, the serial interface is disabled, the DOUT pin is high impedance, and the DIN pin is an input. The CS pin only affects the operation of the serial interface. It does not directly enable/disable the operation of the signal conversion process. 24 VDD − Power supply voltage, 2.7 V to 5.5 V 25 GND − Power supply ground 26 VREF AO 2.048-/2.5-V on-chip voltage reference 27 BUFIN AI Input to reference buffer amplifier 28 BUFOUT/REFIN AIO Output from reference buffer amplifier and reference input to ADC 
 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OFFSET ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 16 12 16 VDD = 5 V, CCLK = 2.5 MHz, REFIN = 2.5 V (ext) 12 8 4 Offset Error − LSB Gain Error − LSB 8 VDD = 5 V, CCLK = 2.5 MHz, REFIN = 2.5 V (ext) Gain = 1 Gain = 8 0 −4 Gain = 20 4 Gain = 1 0 −4 Gain = 8 −8 −8 Gain = 20 −12 −16 −50 −12 −25 0 25 50 75 100 −16 −50 125 TA − Free-Air Temperature − °C −25 0 25 50 75 TA − Free-Air Temperature − °C Figure 1 INTERNAL OSCILLATOR FREQUENCY vs FREE-AIR TEMPERATURE 2.70 0.0025 VDD = 5 V, CCLK = 2.5 MHz Internal Oscillator Frequency − MHz VBG 1.15 V 0.0005 BufVBG 1.15 V 0 −0.0005 BufVREF 2.048 V VREF 2.048 V −0.0015 BufVREF 2.5 V VREF 2.5 V −25 0 25 50 75 100 TA − Free-Air Temperature − °C Figure 3 VDD = 5 V 2.65 0.0015 Voltage Reference Error − V 125 Figure 2 VOLTAGE REFERENCE ERROR vs FREE-AIR TEMPERATURE −0.0025 −50 100 2.60 2.55 +3 sigma 2.50 Oscillator 2.45 2.40 −3 sigma 2.35 125 2.30 −50 −25 0 25 50 75 TA − Free-Air Temperature − °C 100 125 Figure 4 7 
 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 OUTPUT OFFSET ERROR vs COMMON-MODE VOLTAGE OUTPUT OFFSET ERROR vs POWER SUPPLY VOLTAGE 24 8 Output Offset Error − LSB 16 Gain = 20 8 Gain = 8 0 Gain = 1 −8 −16 −24 Gain = 20, TA = 25°C, CCLK = 2.5 MHz 6 Output Offset Error − LSB VDD = 5 V, TA = 25°C, CCLK = 2.5 MHz 4 2 VREF = 2.048 V 0 −2 −4 −6 −8 0 1 2 3 Common-Mode Voltage − V 4 5 2.5 3 Figure 5 3.5 4 4.5 Power Supply Voltage − V 5 5.5 Figure 6 REFERENCE OUTPUT CHARACTERISTIC BUFFER OUTPUT CHARACTERISTIC 2.65 5.5 2.6 ZO = 2Ω Sourcing Current, VDD = 5 V, REFIN = 2.5 V, TA = 25°C 5 4.5 VO − Output Voltage − V 2.625 VO − Output Voltage − V VREF = 2.5 V 2.575 2.55 2.525 2.5 VDD = 5 V, CCLK = 2.5 MHz, TA = 25°C 4 3.5 3 2.5 2 1.5 1 2.475 0.5 2.45 −20 −18 −16 −14 −12 −10 −8 −6 −4 IO − Output Current − mA Figure 7 8 −2 0 0 −2 −1.5 −1 −0.5 0 0.5 1 IO − Output Current − µA Figure 8 1.5 2 
 www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 TYPICAL INPUT RANGE PGA OUTPUT 6 6 VDD = 5 V, TA = 25°C VI x GAIN