ADS8515
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SLAS460D – JUNE 2007 – REVISED SEPTEMBER 2010
16-Bit 250-kSPS Sampling CMOS ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS8515
FEATURES
DESCRIPTION
•
•
•
•
•
The ADS8515 is a complete 16-bit sampling
analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 16-bit,
capacitor-based, SAR A/D converter with sample and
hold (S/H), reference, clock, interface for
microprocessor use, and 3-state output drivers.
1
2
•
•
•
•
•
Standard ±10-V Input Range
90-dB Min SNR with 20-kHz Input
±2.0 LSB Max INL
±1 LSB Max DNL, 16 Bits, No Missing Code
5-V Analog Supply, Flexible I/O Supply Voltage
at 1.65 V to 5.25 V
Pin-Compatible with ADS7805/10 (Low Speed),
and 12-Bit ADS7804/8504
Uses Internal or External Reference
Full Parallel Data Output
100-mW Typ Power Dissipation at 250 kSPS
28-Pin SSOP Package
The ADS8515 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide an industry standard ±10-V input range, while
the innovative design allows operation from a single
+5-V supply, with power dissipation under 100 mW.
The ADS8515 is available in a 28-pin SSOP package
and is fully specified for operation over the industrial
–40°C to 85°C temperature range.
APPLICATIONS
•
•
•
•
•
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
Clock
Successive Approximation Register and Control Logic
R/C
CS
BYTE
BUSY
CDAC
7 kΩ
± 10 V Input
2 kΩ
25.67 kΩ
Comparator
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
CAP
Buffer
Internal
+4.096 V Ref
4 kΩ
REF
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2010, Texas Instruments Incorporated
ADS8515
SLAS460D – JUNE 2007 – REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MINIMUM
INL
(LSB)
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGELEAD
PACKAGE
DESIGNATOR
ADS8515IB
±2
16 Bits
89
–40°C to 85°C
SSOP-28
DB
ADS8515I
±3
16 Bits
87
–40°C to 85°C
SSOP-28
DB
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
ADS8515IBDB
Tube, 50
ADS8515IBDBR
Tape and Reel, 2000
ADS8515IDB
Tube, 50
ADS8515IDBR
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
ADS8515 product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range (unless otherwise noted)
ADS8515
VIN
Analog inputs
±25V
CAP
+VANA + 0.3 V to AGND2 – 0.3 V
REF
Indefinite short to AGND2, momentary short to VANA
DGND, AGND1, AGND2
Ground voltage differences
6V
VDIG
6V
Digital inputs
–0.3 V to +VDIG + 0.3 V
Maximum junction temperature
165°C
Internal power dissipation
(1)
(2)
2
±0.3 V
VANA
825 mW
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
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SLAS460D – JUNE 2007 – REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS
At TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, and using internal reference (unless otherwise noted).
ADS8515I
PARAMETER
ADS8515IB
TEST CONDITIONS
UNIT
MIN
TYP
Resolution
MAX
MIN
TYP
16
MAX
16
Bits
ANALOG INPUT
Voltage range
Impedance
Capacitance
±10
±10
8.885
8.885
kΩ
V
75
75
pF
THROUGHPUT SPEED
Conversion cycle time
Acquire and convert
Throughput rate
4
250
4
ms
250
kHz
DC ACCURACY
INL
Integral linearity error
–3
3
–2
2
LSB (1)
DNL
Differential linearity error
–1
2
–1
1
LSB (1)
No missing codes
16
Transition noise (2)
Full-scale error (3)
0.67
(4)
Int. Ref.
Full-scale error drift
Int. Ref.
Full-scale error (3)
(4)
Ext. 4.096-V Ref.
Full-scale error drift
Ext. 4.096-V Ref.
–0.5
0.5
–0.25
–0.25
0.25
–4
–8
95
0.25
–0.1
4
0.1
–2
%FSR
ppm/°C
2
±2
8
%FSR
ppm/°C
±2
±2
+4.75 V < VD < +5.25 V
LSB
±7
±2
Bipolar zero error drift
Bits
0.67
±7
Bipolar zero error (3)
Power supply sensitivity
(VDIG = VANA = VD)
16
–8
mV
ppm/°C
8
LSB
AC ACCURACY
SFDR
Spurious-free dynamic range
fI = 20 kHz
THD
Total harmonic distortion
fI = 20 kHz
SINAD
Signal-to-(noise+distortion)
–100
fI = 20 kHz
87
–60-dB Input
SNR
Signal-to-noise ratio
102
97
–94
91
–100
89
30
fI = 20 kHz
88
Full-power bandwidth (6)
92
90
500
dB (5)
102
–96
dB
91
dB
32
dB
92
dB
500
kHz
SAMPLING DYNAMICS
Aperture delay
Transient response
5
FS Step
5
2
Overvoltage recovery (7)
ns
2
150
ms
150
ns
REFERENCE
Internal reference voltage
4.076
4.096
4.116
4.076
4.096
4.116
V
Internal reference source current (must
use external buffer)
1
1
mA
Internal reference drift
8
8
ppm/°C
External reference voltage range for
specified linearity
External reference current drain
3.9
4.096
Ext. 4.096-V Ref.
4.2
3.9
100
4.096
4.2
V
100
mA
V
DIGITAL INPUTS
Logic levels
VIL
Low-level input voltage
VDIG = 1.65 V – 5.25 V
–0.3
0.8
–0.3
0.35*VDIG
VIH
High-level input voltage
VDIG = 1.65 V – 5.25 V
0.65*VDIG
VDIG+0.3 V
0.65*VDIG
VDIG+0.3 V
V
IIL
Low-level input current
VIL = 0 V
±10
±10
mA
IIH
High-level input current
VIH = 5 V
±10
±10
mA
DIGITAL OUTPUTS
(1)
(2)
(3)
(4)
(5)
(6)
(7)
LSB means least significant bit. For the 16-bit, ±10-V input ADS8515, one LSB is 305 mV.
Typical rms noise at worst case transitions and temperatures.
As measured with fixed resistors shown in Figure 22. Adjustable to zero with external potentiometer.
Full-scale error is the worst case of –full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of offset error.
All specifications in dB are referred to a full-scale ±10-V input.
Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of
accuracy.
Recovers to specified performance after 2 x FS input overvoltage.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, and using internal reference (unless otherwise noted).
ADS8515I
PARAMETER
ADS8515IB
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Data format (parallel 16 bits)
Data coding (binary twos complement)
VOL
Low-level output voltage
ISINK = 1.6 mA
VOH
High-level output voltage
ISOURCE = 500 mA
0.4
0.4
V
Leakage current
Hi-Z state, VOUT = 0 V to VDIG
±5
±5
mA
Output capacitance
Hi-Z state
15
15
pF
Bus access timing
83
83
ns
Bus relinquish timing
83
83
ns
5.25
V
0.8×VDIG
0.8×VDIG
V
DIGITAL TIMING
POWER SUPPLIES
VDIG
Digital input voltage
1.65
VANA
Analog input voltage
4.75
IDIG
Digital input current
IANA
Analog input current
Power dissipation
Must be ≤ VANA
fS = 250 kHz
5.25
1.65
5
5.25
4.75
0.1
1
5
5.25
0.1
1
V
mA
20
25
20
25
mA
100
125
100
125
mW
TEMPERATURE RANGE
Specified performance
–40
+85
–40
+85
°C
Derated performance (8)
–55
+125
–55
+125
°C
Storage
–65
+150
–65
+150
°C
THERMAL RESISTANCE (ΘJA)
SSOP
(8)
67
67
°C/W
The internal reference may not be started correctly beyond the industrial temperature range (–40°C to +85°C); therefore, use of an
external reference is recommended.
PIN CONFIGURATION
DB PACKAGE
SSOP-28
(TOP VIEW)
VIN 1
AGND1 2
27 VANA
REF 3
26 BUSY
CAP 4
25 CS
AGND2 5
D15 (MSB) 6
4
28 VDIG
24 R/C
23 BYTE
D14 7
22 D0 (LSB)
D13 8
21 D1
D12 9
20 D2
D11 10
19 D3
D10 11
18 D4
D9 12
17 D5
D8 13
16 D6
DGND 14
15 D7
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SLAS460D – JUNE 2007 – REVISED SEPTEMBER 2010
PIN DESCRIPTIONS
PIN
DIGITAL
I/O
NAME
NO.
AGND1
2
Analog ground. Used internally as ground reference point.
DESCRIPTION
AGND2
5
Analog ground.
BUSY
26
O
At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
BYTE
23
I
Selects 8 most significant bits (low) or 8 least significant bits (high).
CAP
4
Reference buffer capacitor. 2.2-mF tantalum capacitor to ground.
CS
25
DGND
14
I
Internally ORed with R/C. If R/C low, a falling edge on CS initiates a new conversion.
D15 (MSB)
6
O
Data bit 15. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high, or
when R/C is low.
D14
7
O
Data bit 14. Hi-Z state when CS is high, or when R/C is low.
D13
8
O
Data bit 13. Hi-Z state when CS is high, or when R/C is low.
D12
9
O
Data bit 12. Hi-Z state when CS is high, or when R/C is low.
D11
10
O
Data bit 11. Hi-Z state when CS is high, or when R/C is low.
D10
11
O
Data bit 10. Hi-Z state when CS is high, or when R/C is low.
D9
12
O
Data bit 9. Hi-Z state when CS is high, or when R/C is low.
D8
13
O
Data bit 8. Hi-Z state when CS is high, or when R/C is low.
D7
15
O
Data bit 7. Hi-Z state when CS is high, or when R/C is low.
D6
16
O
Data bit 6. Hi-Z state when CS is high, or when R/C is low.
D5
17
O
Data bit 5. Hi-Z state when CS is high, or when R/C is low.
D4
18
O
Data bit 4. Hi-Z state when CS is high, or when R/C is low.
D3
19
O
Data bit 3. Hi-Z state when CS is high, or when R/C is low.
D2
20
O
Data bit 2. Hi-Z state when CS is high, or when R/C is low.
D1
21
O
Data bit 1. Hi-Z state when CS is high, or when R/C is low.
D0 (LSB)
22
O
Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high, or
when R/C is low.
R/C
24
I
With CS low and BUSY high, a falling edge on R/C initiates a new conversion. With CS
low, a rising edge on R/C enables the parallel output.
REF
3
Reference input/output. 2.2-mF tantalum capacitor to ground.
VANA
27
Analog supply input. Nominally +5 V. Decouple to ground with 0.1-mF ceramic and 10-mF
tantalum capacitors.
VDIG
28
Digital supply input. Can be connected directly to pin 27.
VIN
1
Analog input. See Figure 24.
Digital ground.
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
95
95
90
85
80
75
70
1
10
100
fi - Input Frequency - kHz
80
75
10
100
fi - input frequency - kHz
1000
85
80
75
70
1
10
100
fi - input frequency - kHz
Figure 2.
Figure 3.
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE AND
DISTORTION
vs
FREE-AIR TEMPERATURE
100
95
90
85
80
75
95
SINAD - Signal to Noise and Distortion - dB
100
SNR - Signal-to-Noise Ratio - dB
fs = 250 KSPS
fi = 20 kHz
90
85
80
75
70
70
1
10
100
fi - input frequency - kHz
-55 -40 -25-10 5 20 35 50 65 80 95 110 125
TA - Free-Air-Temperature - °C
1000
1000
100
fs = 250 KSPS
fi = 20 kHz
95
90
85
80
75
70
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TA - Free-Air-Temperature - °C
Figure 4.
Figure 5.
Figure 6.
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
100
90
85
80
fs = 250 KSPS
fi = 20 kHz
70
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TA - Free-Air-Temperature - °C
Figure 7.
THD - Total Harmonic Distortion - dB
95
75
4.1
-70
-75
fs = 250 KSPS
fi = 20 kHz
VREF - Internal Reference Voltage - V
SFDR - Spurious Free Dynamic Range
85
90
Figure 1.
105
SFDR - Spurious Free Dynamic Range - dB
90
70
1
1000
95
SINAD - Signal to Noise and Distortion - dB
SNR - Signal-to-Noise Ratio - dB
THD - Total Harmonic Distortion - dB
100
6
SIGNAL-TO-NOISE AND
DISTORTION
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
-80
-85
-90
-95
-100
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TA - Free-Air-Temperature - °C
Figure 8.
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4.099
4.098
4.097
4.096
4.095
4.094
4.093
4.092
4.091
4.09
-40
-25 -10
5
20 35 50 65
TA - Free-Air-Temperature - °C
80
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
NEGATIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
0.25
4
0.2
3
2
1
0
-1
-2
-3
-4
-5
-40
-25 -10 5
20 35 50 65
TA - Free-Air-Temperature - °C
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-25
-10
5
20
35
50
65
0.08
External Reference
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
-40
80
-25
-10
5
20
35
50
65
Figure 10.
Figure 11.
Figure 12.
POSITIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
POSITIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.1
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-25
-10
5
20
35
50
65
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
80
0.023
0.021
0.019
0.017
-0.08
-0.1
-40
-0.25
-40
0.025
External Reference
0.08
IDD - Supply Current - mA
PFS - Positive Full-Scale Error - %FSR
Internal Reference
0.2
80
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
0.25
PFS - Positive Full-Scale Error - %FSR
0.1
Internal Reference
-0.25
-40
80
NEGATIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
NFS - Negative Full-Scale Error - %FSR
5
NFS - Negative Full-Scale Error - %FSR
BPZ - Bipolar Zero Error - mV
BIPOLAR ZERO ERROR
vs
FREE-AIR TEMPERATURE
-25
TA - Free-Air-Temperature - °C
-10
5
20
35
50
65
80
TA - Free-Air-Temperature - °C
Figure 13.
Figure 14.
0.015
-40
-25
-10
5
20
35
50
65
80
TA - Free-Air-Temperature - °C
Figure 15.
HISTOGRAM
4500
4103
4000
3645
3500
Count
3000
2500
2000
1500
1000
335
500
0
0
109
0
0
0
65529
65531
65533
65535
65530
65532
65534
65536
Code
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
INL
2
1.5
1
INL - lsb
0.5
0
-0.5
-1
-1.5
-2
0
10000
20000
30000
40000
50000
60000
70000
Code
Figure 17.
DNL
2
1.5
DNL - lsb
1
0.5
0
-0.5
-1
-1.5
-2
0
10000
20000
30000
40000
50000
60000
70000
Code
Figure 18.
8
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SLAS460D – JUNE 2007 – REVISED SEPTEMBER 2010
BASIC OPERATION
Figure 19 shows a basic circuit to operate the ADS8515 with a full parallel data output. Taking R/C (pin 24) low
for a minimum of 40 ns initiates a conversion. BUSY (pin 26) goes low and stays low until the conversion is
completed and the output registers are updated. Data are output in binary twos complement with the MSB on pin
6. BUSY going high can be used to latch the data.
The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 ms between convert
commands assures accurate acquisition of a new signal.
1
28
2
27
3
26
4
25
5
24
D15 (MSB)
6
23
D14
7
D13
+
2.2 µF
2.2 µF
+
+
0.1 µF
+5V
+
10 µF
BUSY
Convert Pulse
R/C
22
D0 (LSB)
8
21
D1
D12
9
20
D2
D11
10
19
D3
D10
11
18
D4
D9
12
17
D5
D8
13
16
D6
14
15
D7
ADS8515
40 ns Min
Figure 19. Basic Operation
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STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) held low for a minimum of 40 ns immediately puts the
sample/hold of the ADS8515 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low
until conversion n is completed and the internal output register has been updated.
The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 ms between convert
commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY
states and Figure 21, Figure 22, and Figure 23 for the timing diagrams.
CS and R/C are internally ORed and level triggered. There is no requirement regarding which input goes low first
when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less
critical input is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The
parallel output becomes active whenever R/C goes high. Refer to the Reading Data section.
Table 1. Control Line Functions for Read and Convert
(1)
CS
R/C
BUSY
1
X
X
None. Databus is in Hi-Z state.
OPERATION
↓
0
1
Initiates conversion n. Databus remains in Hi-Z state.
0
↓
1
Initiates conversion n. Databus enters Hi-Z state.
0
1
↑
Conversion n completed. Valid data from conversion n on the databus.
↓
1
1
Enables databus with valid data from conversion n.
↓
1
0
Enables databus with valid data from conversion –1
(1)
0
↑
0
Enables databus with valid data from conversion –1
(1)
0
0
↑
New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C
must be high when BUSY goes high.
X
X
0
Conversion n in progress.
. Conversion n in progress.
. Conversion n in progress.
See Figure 21 and Figure 22 for constraints on data valid from conversion n – 1.
READING DATA
The ADS8515 outputs full or byte-reading parallel data in binary twos complement data output format. The
parallel output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C
3-states the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on
pins 6 to 13 and pins 15 to 22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle.
Refer to Table 2 for ideal output codes and Figure 20 for bit locations relative to the state of BYTE.
Table 2. Ideal Input Voltages and Output Codes
10
DESCRIPTION
ANALOG INPUT
Full-scale range
±10 V
Least significant bit (LSB)
305 mV
Full scale (10 V – 1 LSB)
Midscale
DIGITAL OUTPUT BINARY TWOS COMPLEMENT
BINARY CODE
HEX CODE
9.999695 V
0111 1111 1111 1111
7FFF
0V
0000 0000 0000 0000
0000
One LSB below midscale
–305 mV
1111 1111 1111 1111
FFFF
–Full scale
–10 V
1000 0000 0000 0000
8000
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PARALLEL OUTPUT (After a Conversion)
After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion n are available on D15 to D0 (pins 6 to 13 and 15 to 22). BUSY going high can be used to
latch the data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion n has been initiated, valid data from conversion –1 can be read and are valid up to t2 after the
start of conversion n. Do not attempt to read data from t2 after the start of conversion n until BUSY (pin 26) goes
high; this may result in reading invalid data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing
specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading the converter performance.
The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate
conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 21.
Table 3. Conversion Timing
SYMBOL
DESCRIPTION
tw1
Pulse duration, convert
ta
Access time, data valid after R/C low
MIN
TYP
MAX
UNITS
0.8
1.2
ms
6
20
ns
2
ms
40
ns
tpd
Propagation delay time, BUSY from R/C low
tw2
Pulse duration, BUSY low
td1
Delay time, BUSY after end of conversion
5
ns
td2
Delay time, aperture
5
ns
tconv
Conversion time
tacq
Acquisition time
2
tdis
Disable time, bus
10
15
td3
Delay time, BUSY after data valid
35
50
ns
tv
Valid time, previous data remains valid after R/C low
1.5
2
ms
tconv + tacq
2
ms
ms
83
Throughput time
4
ns
ms
tsu
Setup time, R/C to CS
10
ns
tc
Cycle time between conversions
4
ms
ten
Enable time, bus
10
15
30
ns
td4
Delay time, BYTE
10
15
30
ns
BYTE LOW
BYTE HIGH
+5 V
Bit 15 (MSB) 6
23
Bit 7 6
22 Bit 0 (LSB)
Bit 6 7
Bit 13 8
21 Bit 1
Bit 5 8
21 Bit 9
Bit 12 9
20 Bit 2
Bit 4 9
20 Bit 10
Bit 11 10
19 Bit 3
Bit 3 10
19 Bit 11
Bit 10 11
18 Bit 4
Bit 2 11
18 Bit 12
Bit 9 12
17 Bit 5
Bit 1 12
17 Bit 13
Bit 8 13
16 Bit 6
Bit 0 (LSB) 13
16 Bit 14
14
15 Bit 7
14
Bit 14 7
ADS8515
23
ADS8515
22 Bit 8
15 Bit 15 (MSB)
Figure 20. Bit Locations Relative to State of BYTE (Pin 23)
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tw1
R/C
tc
ta1
tw2
BUSY
tpd
td2
td1
Acquire
MODE
Convert
Acquire
tconv
DATA BUS
Previous
Data Valid
Previous
Data Valid
Hi−Z
Convert
tacq
Not Valid
Data Valid
Hi−Z
Data Valid
td3
tdis
tv
Figure 21. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low)
tsu
tsu
tsu
tsu
R/C
tw1
CS
tpd
tw2
BUSY
td2
MODE Acquire
Convert
Acquire
tconv
Hi−Z State
DATA BUS
Data Valid
ten
Hi−Z State
tdis
Figure 22. Using CS to Control Conversion and Read Timing
tsu
tsu
R/C
CS
BYTE
Pins 6 − 13 Hi−Z
Pins 15 − 22 Hi−Z
High Byte
Low Byte
ten
td4
Low Byte
High Byte
Hi−Z
tdis
Hi−Z
Figure 23. Using CS and BYTE to Control Data Bus
12
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ADC RESET
The ADC reset function of the ADS8515 can be used to terminate the current conversion cycle. Bringing R/C low
for at least 40 ns while BUSY is low will initiate the ADC reset. To initiate a new conversion, R/C must return to
the high state and remain high long enough to acquire a new sample (see Table 3, tc) before going low to initiate
the next conversion sequence. In applications that do not monitor the BUSY signal, it is recommended that the
ADC reset function be implemented as part of a system initialization sequence.
INPUT RANGES
The ADS8515 offers a standard ±10-V input range. Figure 24 shows the necessary circuit connections for the
ADS8515 with and without hardware trim. Offset and full-scale error specifications are tested and specified with
the fixed resistors shown in Figure 25(b). Full-scale error includes offset and gain errors measured at both +FS
and –FS. Adjustments for offset and gain are described in the Calibration section of this data sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
The nominal input impedance of 6.35 kΩ results from the combination of the internal resistor network shown on
the front page of the product data sheet. The input resistor divider network provides inherent overvoltage
protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not compromise the
accuracy or drift of the converter. They have little influence relative to the internal resistors, and tighter tolerances
are not required.
The input signal must be referenced to AGND1. This minimizes the ground loop problem typical to analog
designs. The analog signal should be driven by a low impedance source. A typical driving circuit using an
OPA627 or OPA132 is shown in Figure 24.
+15V
2.2 mF
22 pF
ADS8515
100 nF
VIN
GND
2 kW
Pin 7
2 kW
Vin
Pin 2
22 pF
Pin3
Pin 1
−
OPA 627
or
OPA 132
+
REF
2.2 mF
Pin 6
AGND1
Pin4
GND
CAP
2.2 mF
GND
100 nF
2.2 mF
DGND
GND
AGND2
GND
−15 V
GND
Figure 24. Typical Driving Circuit (±10 V, No Trim)
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APPLICATION INFORMATION
CALIBRATION
The gain of the ADS8515 can be trimmed in software. To achieve optimum performance, several iterations may
be required.
Hardware Calibration
To calibrate the gain of the ADS8515, install the resistors and potentiometer as shown in Figure 25(a). The
calibration range is approximately ±100 mV.
Software Calibration
The offset and gain of the ADS8515 is calibrated with software. See Figure 25(b) for the circuit connections.
1
±10 V
2
+5 V
2.2 µF +
3
VIN
1
±10 V
2
AGND1
2.2 µF +
3
REF
VIN
AGND1
REF
175 kΩ
4
20 kΩ
+
Gain
2.2 µF
30 kΩ
4
CAP
CAP
+
2.2 µF
5
AGND2
(a) ±10 V With Hardware Trim
5
AGND2
(b) ±10 V Without Hardware Trim
Note: Use 1% metal film resistors.
Figure 25. Circuit Diagram For Software Trim
REFERENCE
The ADS8515 can operate with its internal 4.096-V reference or an external reference. By applying an external
reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally
with the output on CAP (pin 4).
The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade).
REF
REF (pin 3) is an input for an external reference or the output for the internal 4.096-V reference. A 2.2-mF
capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of
REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more
noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc
loads.
The range for the external reference is 3.9 V to 4.2 V and determines the actual LSB size. Increasing the
reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
14
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CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-mF capacitor should be placed as close to the
CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and
compensation for the output of the internal buffer. Using a capacitor any smaller than 1 mF can cause the output
buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 mF have
little affect on improving performance. The ESR (equivalent series resistance) of these compensation capacitors
is also critical. Keep the total ESR under 3 Ω. See the Typical Characteristics section for how the worst case INL
is affected by ESR.
The output of the buffer is capable of driving up to 2 mA of current to a dc load, but any external load from the
CAP pin may degrade the linearity of the ADS8515. Using an external buffer allows the internal reference to be
used for larger dc loads and ac loads. Do not attempt to directly drive an ac load with the output voltage on CAP.
This causes performance degradation of the converter. The ESR (equivalent series resistance) of these
compensation capacitors is also critical. Keep the total ESR under 3 Ω. See the Typical Characteristics section
concerning how ESR affects performance.
LAYOUT
POWER
The analog power pin (VANA) and digital power pin (VDIG) can be tied together from the same +5V power supply,
or from two different power-supply sources. The ADS8515 uses 90% of its power from the analog circuitry, and
therefore should be considered as an analog component. Care must be taken to ensure that both the analog and
digital power supplies power on before any voltage is applied to the analog input pin. Failure to do so may create
a latch-up condition. There is no power sequencing requirement between VANA and VDIG.
GROUNDING
Three ground pins are present on the ADS8515. DGND is the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals internal to the A/D converter are referenced. AGND1 is
more susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D converter should be tied to the analog ground plane, separated from the system
digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to
the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground
currents from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS8515, compared to
the FET switches on other CMOS A/D converters, releases 5% to 10% of the charge. There is also a resistive
front end which attenuates any charge which is released. The end result is a minimal requirement for the
antialias filter on the front end. Any op amp sufficient for the signal in an application is sufficient to drive the
ADS8515.
The resistive front end of the ADS8515 also provides an assured ±25-V overvoltage protection. In most cases,
this eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS8515 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to
isolate the A/D converter from other peripherals on the same bus. The 3-state outputs can also be used when
the A/D converter is the only peripheral on the data bus.
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8515 has an internal LSB size of
38 mV. Transients from fast switching signals on the parallel port, even when the A/D converter is 3-stated, can
be coupled through the substrate to the analog circuitry causing degradation of converter performance.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2010) to Revision D
Page
•
Deleted row from Absolute Maximum Ratings regarding VDIG to VANA ................................................................................. 2
•
Deleted text regarding VANA from the pin 28 description in the Pin Description table .......................................................... 5
•
Changed text in first and second sentences of the Power section ..................................................................................... 15
Changes from Revision B (June 2010) to Revision C
Page
•
Updated document format to current standards ................................................................................................................... 1
•
Added text to end of Power section .................................................................................................................................... 15
16
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS8515IBDB
ACTIVE
SSOP
DB
28
50
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS8515I
B
Samples
ADS8515IBDBR
ACTIVE
SSOP
DB
28
2000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS8515I
B
Samples
ADS8515IDB
ACTIVE
SSOP
DB
28
50
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS8515I
Samples
ADS8515IDBR
ACTIVE
SSOP
DB
28
2000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS8515I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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