ADS8326IDRBT

Burr Brown Products from Texas Instruments ADS8326 SBAS343 – MAY 2007 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES • • • 16 Bits No Missing Codes (Full-Supply Range, High or Low Grade) Very Low Noise: 3LSBPP Excellent Linearity: ±1LSB typ, ±1.5LSB max INL ±0.6LSB typ, ±1LSB max DNL ±1mV max Offset ±12LSB typ Gain Error microPower: 10mW at 5V, 250kHz 4mW at 2.7V, 200kHz 2mW at 2.7V, 100kHz 0.2mW at 2.7V, 10kHz MSOP-8 Package (SON-8 package available Q4, 2007; package size same as 3x3 QFN) 16-Bit Upgrade to the 12-Bit ADS7816 and ADS7822 Pin-Compatible with the ADS7816, ADS7822, ADS7826, ADS7827, ADS7829, ADS8320, and ADS8325 Serial (SPI™/SSI) Interface APPLICATIONS • • • • • • • Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multichannel Systems Industrial Controls Robotics Vibration Analysis • DESCRIPTION The ADS8326 is a 16-bit, sampling, analog-to-digital (A/D) converter specified for a supply voltage range from 2.7V to 5.5V. It requires very little power, even when operating at the full data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode. For example, the average power dissipation is less than 0.2mW at a 10kHz data rate. The ADS8326 offers excellent linearity and very low noise and distortion. It also features a synchronous serial (SPI/SSI-compatible) interface and a differential input. The reference voltage can be set to any level within the range of 0.1V to VDD. Low power and small size make the ADS8326 ideal for portable and battery-operated systems. It is also a perfect fit for remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS8326 is available in an MSOP-8 package. • • • • SAR REF ADS8326 DOUT +IN CDAC -IN S/H Amp Comparator CS/SHDN Serial Interface DCLOCK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS8326 www.ti.com SBAS343 – MAY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) MAXIMUM INTEGRAL LINEARITY ERROR (LSB) (2) NO MISSING CODES ERROR (LSB) SPECIFIED TEMPERATURE RANGE TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 PRODUCT PACKAGELEAD PACKAGE DESIGNATOR PACKAGE MARKING ORDERING NUMBER ADS8326IDGKT ADS8326I ±3 16 MSOP-8 DGK –40°C to +85°C D26 ADS8326IDGKR ADS8326IBDGKT ADS8326IB ±1.5 16 MSOP-8 DGK –40°C to +85°C D26 ADS8326IBDGKR ADS8326IDRBT ADS8326I (3) ±3 16 SON-8 (3) DRB –40°C to +85°C D26 ADS8326IDRBR ADS8326IBDRBT ADS8326IB (3) ±1.5 16 SON-8 (3) DRB –40°C to +85°C D26 ADS8326IBDRBR (1) (2) (3) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. Maximum Integral Linearity Error specifies a 5V power supply and reference voltage. DRB (SON-8) package available Q4, 2007. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) ADS8326 Supply voltage, VDD to GND Analog input voltage (2) Reference input voltage (2) Digital input voltage (2) Input current to any pin except supply Power dissipation Operating virtual junction temperature range, TJ Operating free-air temperature range, TA Storage temperature range, TSTG Lead Temperature 1.6mm (1/16 inch) from case for 10sec (1) (2) –0.3 to +7 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –20 to +20 See Dissipation Ratings Table –40 to +150 –40 to +85 –65 to +150 +260 °C °C °C °C UNIT V V V V mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to ground terminal. 2 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 DISSIPATION RATINGS PACKAGE DGK DRB (1) (1) RθJC +39.1°C/W +5°C/W RθJA +206.3°C/W +45.8°C/W DERATING FACTOR ABOVE TA = +25°C 4.847mW/°C 3.7mW/°C TA ≤ +25°C POWER RATING 606mW 370mW TA = +70°C POWER RATING 388mW 204mW TA = +85°C POWER RATING 315mW 148mW DRB (SON-8) package available Q4, 2007. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, GND to VDD Supply voltage, GND to VDD Reference input voltage –IN to GND Analog input voltage Operating junction temperature, TJ +IN to GND +IN – (–IN) Low-voltage levels 5V logic levels 2.7 4.5 0.1 –0.3 –0.3 0 –40 0 5.0 TYP MAX 3.6 5.5 VDD 0.5 VDD + 0.2 VREF +125 V °C UNIT V V V V ELECTRICAL CHARACTERISTICS: VDD = +5V At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 250kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER ANALOG INPUT Full-scale range Operating common-mode signal Input resistance Input capacitance Input leakage current Differential input capacitance Full-power bandwidth DC ACCURACY Resolution No missing codes Integral linearity error Differential linearity error Offset error Offset error drift Gain error Gain error drift Noise Power-supply rejection SAMPLING DYNAMICS Conversion time (16 DCLOCKs) Acquisition time (4.5 DCLOCKs) Throughput rate (22 DCLOCKs) Clock frequency fDCLOCK 0.024 tCONV 24kHz ≤ fDCLOCK ≤ 6MHz tAQ fDCLOCK = 6MHz 2.667 0.75 250 6 0.024 666.7 2.667 0.75 250 6 666.7 µs µs kSPS MHz 4.75V ≤ VDD ≤ 5.25V NMC INL DNL VOS TCVOS GERR TCGERR –24 ±0.3 30 0.5 16 16 –3 –1 –1.5 ±2 ±0.5 ±0.75 ±0.2 +24 –12 ±0.3 30 0.5 +3 +2 +1.5 16 16 –1.5 –1 –1 ±1 ±0.4 ±0.5 ±0.2 +12 +1.5 +1 +1 Bits Bits LSB LSB mV ppm/°C LSB ppm/°C µVRMS LSB RON –IN = GND, off –IN = GND, on –IN = GND, during sampling –IN = GND +IN to –IN, during sampling FS sinewave, SINAD = FSBW –60dB FSR +IN – (–IN) 0 –0.3 5 50 48 ±50 20 500 100 VREF 0.5 0 –0.3 5 50 48 ±50 20 500 100 VREF 0.5 V V GΩ Ω pF nA pF kHz TEST CONDITIONS MIN TYP MAX MIN ADS8326IB TYP MAX UNIT Submit Documentation Feedback 3 ADS8326 www.ti.com SBAS343 – MAY 2007 ELECTRICAL CHARACTERISTICS: VDD = +5V (continued) At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 250kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER AC ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio THD 5VPP sinewave at 2kHz 5VPP sinewave at 10kHz 5VPP sinewave at 2kHz 5VPP sinewave at 10kHz 5VPP sinewave at 2kHz 5VPP sinewave at 10kHz 5VPP sinewave at 2kHz 5VPP sinewave at 10kHz 5VPP sinewave at 2kHz 5VPP sinewave at 10kHz 0.1 CS = GND, fSAMPLE = 0Hz CS = VDD fS = 250kHz fS = 200kHz Reference input current fS = 100kHz fS = 10kHz CS = VDD DIGITAL INPUTS (1) Logic family High-level input voltage Low-level input voltage Input current Input capacitance DIGITAL OUTPUTS (1) Logic family High-level output voltage Low-level output voltage High-impedance state output current Output capacitance Load capacitance Data format VOH VDD = 4.5V, IOH = –100µA VOL VDD = 4.5V, IOL = 100µA IOZ CS = VDD, VI = VDD or GND CO CL Straight binary –50 5 30 Straight binary 4.44 0.5 +50 –50 5 30 CMOS 4.44 0.5 +50 CMOS V V nA pF pF VIH VIL IIN VI = VDD or GND CI 0.7 × VDD –0.3 –50 5 CMOS VDD + 0.3 0.3 × VDD +50 0.7 × VDD –0.3 –50 5 CMOS VDD + 0.3 0.3 × VDD +50 V V nA pF 5 5 24 170 140 70 11 0.1 220 180 90 14 –98 –90 102 94 91 91 90 87.5 14.69 14.28 –99 –91 103 95 91.5 91.5 91 88 14.86 14.35 dB dB dB dB dB dB dB dB Bits Bits TEST CONDITIONS MIN TYP MAX MIN ADS8326IB TYP MAX UNIT SFDR SNR Signal-to-noise + distortion SINAD Effective number of bits VOLTAGE REFERENCE INPUT Reference voltage Reference input resistance Reference input capacitance ENOB VDD 0.1 5 5 24 170 140 70 11 0.1 VDD V GΩ GΩ pF 220 180 90 14 µA µA µA µA µA (1) Applies for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. 4 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 ELECTRICAL CHARACTERISTICS: VDD = +2.7V At –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 200kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER ANALOG INPUT Full-scale range Operating common-mode signal Input resistance Input capacitance Input leakage current Differential input capacitance Full-power bandwidth DC ACCURACY Resolution No missing code Integral linearity error Differential linearity error Offset error Offset error drift Gain error Gain error drift Noise Power-supply rejection SAMPLING DYNAMICS Conversion time (16 DCLOCKs) Acquisition time (4.5 DCLOCKs) Throughput rate (22 DCLOCKs) Clock frequency AC ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio THD 2.5VPP sinewave at 2kHz 2.5VPP sinewave at 10kHz 2.5VPP sinewave at 2kHz 2.5VPP sinewave at 10kHz 2.5VPP sinewave at 2kHz 2.5VPP sinewave at 10kHz 2.5VPP sinewave at 2kHz 2.5VPP sinewave at 10kHz 2.5VPP sinewave at 2kHz 2.5VPP sinewave at 10kHz 0.1 CS = GND, fSAMPLE = 0Hz CS = VDD fS = 200kHz Reference input current fS = 100kHz fS = 10kHz CS = VDD 5 5 24 70 25 5 0.1 90 33 7 –88 –75 91 77.5 86.5 86 85 74.5 13.86 12.12 –88.5 –75.5 91.5 78 87 86.5 85.5 75 13.94 12.20 dB dB dB dB dB dB dB dB Bits Bits fDCLOCK 0.024 tCONV 24kHz ≤ fDCLOCK ≤ 4.8MHz tAQ fDCLOCK = 4.8MHz 3.333 0.9375 200 4.8 0.024 666.7 3.333 0.9375 200 4.8 666.7 µs µs kSPS MHz 2.7V ≤ VDD ≤ 3.6V NMC INL DNL VOS TCVOS GERR TCGERR 16 16 –3 –1 –1.5 ±2 ±0.5 ±0.75 ±0.2 ±33 ±0.3 30 0.5 +3 +2 +1.5 16 16 –2.5 –1 –1 ±1 ±0.4 ±0.5 ±0.2 ±16 ±0.3 30 0.5 +2.5 +1 +1 Bits Bits LSB LSB mV ppm/°C LSB ppm/°C µVRMS LSB RON –IN = GND, off –IN = GND, on –IN = GND, during sampling –IN = GND +IN to –IN, during sampling FS sinewave, SINAD = FSBW –60dB FSR +IN – (–IN) 0 –0.3 5 100 48 ±50 20 60 150 VREF 0.5 0 –0.3 5 100 48 ±50 20 60 150 VREF 0.5 V V GΩ Ω pF nA pF kHz TEST CONDITIONS MIN TYP MAX MIN ADS8326IB TYP MAX UNIT SFDR SNR Signal-to-noise + distortion SINAD Effective number of bits VOLTAGE REFERENCE INPUT Reference voltage Reference input resistance Reference input capacitance ENOB VDD 0.1 5 5 24 70 25 5 0.1 VDD V GΩ GΩ pF 90 33 7 µA µA µA µA Submit Documentation Feedback 5 ADS8326 www.ti.com SBAS343 – MAY 2007 ELECTRICAL CHARACTERISTICS: VDD = +2.7V (continued) At –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 200kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER DIGITAL INPUTS (1) Logic family High-level input voltage Low-level input voltage Input current Input capacitance DIGITAL OUTPUTS (1) Logic family High-level output voltage Low-level output voltage High-impedance state output current Output capacitance Load capacitance Data format VOH VDD = 2.7V, IOH = -100µA VOL VDD = 2.7V, IOL = 100µA IOZ CS = VDD, VI = VDD or GND CO CL Straight binary –50 5 30 Straight binary VDD– 0.2 0.2 +50 –50 5 30 LVCMOS VDD– 0.2 0.2 +50 LVCMOS V V nA pF pF VIH VDD = 3.6V VIL VDD = 2.7V IIN VI = VDD or GND CI 2 –0.3 –50 5 LVCMOS VDD + 0.3 0.8 +50 2 –0.3 –50 5 LVCMOS VDD + 0.3 0.8 +50 V V nA pF TEST CONDITIONS MIN TYP MAX MIN ADS8326IB TYP MAX UNIT (1) Applies for 3.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V. ELECTRICAL CHARACTERISTICS At –40°C to +85°C, –IN = GND, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER ANALOG INPUT Power supply VDD Low-voltage levels 5V logic levels VDD = 2.7V, fS = 10kHz, fDCLOCK = 4.8MHz VDD = 2.7V, fS = 100kHz, fDCLOCK = 4.8MHz Operating supply current IDD VDD = 2.7V, fS = 200kHz, fDCLOCK = 4.8MHz VDD = 5V, fS = 200kHz, fDCLOCK = 6MHz VDD = 5V, fS = 250kHz, fDCLOCK = 6MHz Power-down supply current IDD VDD = 2.7V VDD = 5V VDD = 2.7V, fS = 10kHz, fDCLOCK = 4.8MHz VDD = 2.7V, fS = 100kHz, fDCLOCK = 4.8MHz Power dissipation VDD = 2.7V, fS = 200kHz, fDCLOCK = 4.8MHz VDD = 5V, fS = 200kHz, fDCLOCK = 6MHz VDD = 5V, fS = 250kHz, fDCLOCK = 6MHz Power dissipation in power-down VDD = 2.7V, CS = VDD VDD = 5V, CS = VDD 2.7 4.5 0.065 0.69 1.38 1.9 2.0 0.1 0.2 0.18 1.86 3.73 9.5 10 0.3 0.6 0.23 2.7 5.4 13.5 15 3.6 5.5 0.085 1.0 2.0 2.7 3.0 2.7 4.5 0.065 0.69 1.38 1.9 2.0 0.1 0.2 0.18 1.86 3.73 9.5 10 0.3 0.6 0.23 2.7 5.4 13.5 15 3.6 5.5 0.085 1.0 2.0 2.7 3.0 V V mA mA mA mA mA µA µA mW mW mW mW mW µW µW TEST CONDITIONS MIN TYP MAX MIN ADS8326IB TYP MAX UNIT 6 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 PIN CONFIGURATION DGK PACKAGE MSOP-8 (TOP VIEW) REF +IN -IN GND 1 2 ADS8326 3 4 6 5 DOUT CS/SHDN 8 7 VDD DCLOCK DRB PACKAGE(1)(2) SON-8 (TOP VIEW) REF +IN -IN GND 1 2 ADS8326 3 4 (Thermal Pad) 8 7 6 5 VDD DCLOCK DOUT CS/SHDN (1) (2) DRB package (SON-8) available Q4, 2007. The DRB package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN ASSIGNMENTS PIN NAME REF +IN –IN GND CS/SHDN DOUT DCLOCK VDD NO. 1 2 3 4 5 6 7 8 I/O Analog input Analog input Analog input Power-supply connection Digital input Digital output Digital input Power-supply connection DESCRIPTION Reference input Noninverting input Inverting analog input Ground Chip select when low; Shutdown mode when high. Serial output data word Data clock synchronizes the serial data transfer and determines conversion speed. Power supply Equivalent Input Circuit (VDD = 5.0V) VDD RON 50W ANALOG IN C(SAMPLE) 48pF REF VDD RON 50W 24pF I/O VDD GND Diode Turn-On Voltage: 0.35V Equivalent Analog Input Circuit GND GND Equivalent Reference Input Circuit Equivalent Digital Input/Output Circuit Submit Documentation Feedback 7 ADS8326 www.ti.com SBAS343 – MAY 2007 TIMING INFORMATION tCYC CS/SHDN Sample tSUCS DCLOCK tCSD DOUT Conversion Power Down Use positive clock edge for data transfer Hi-Z 0 B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B7 B6 B5 B4 B3 B2 B1 B0 (LSB) (1) Hi-Z tSMPL NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown. If CS remains low at the end of conversion, a new data stream is shifted out with LSB-first data followed by zeroes indefinitely. tCYC CS/SHDN tSUCS DCLOCK tCSD DOUT Hi-Z Null Bit Power Down B15 B14 B13 B12 B11 B6 (MSB) B5 B4 B3 B2 B1 tSMPL tCONV B0 B1 (LSB) B2 B3 B4 B5 B0 B11 B12 B13 B14 B15 (MSB) (2) Hi-Z NOTE: (2) After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeroes indefinitely. 1.4V 3kW DOUT 100pF CLOAD Test Point DOUT tr tf 90% 10% Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK tdDO DOUT thDO Voltage Waveforms for DOUT Delay Times, tdDO DOUT 3kW 100pF CLOAD Load Circuit for tdis and ten VDD tdis Waveform 2, ten tdis Waveform 1 CS/SHDN 90% CS/SHDN DOUT Waveform 1(3) tdis DOUT Waveform 2(4) Voltage Waveforms for tdis 90% DCLOCK 1 4 5 10% DOUT ten Voltage Waveforms for ten B15 NOTES: (3) Waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (4) Waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. Figure 1. Timing Diagrams and Test Circuits for the Paramters in Table 1 8 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 TIMING INFORMATION (continued) Table 1. Timing Characteristics SYMBOL tSMPL tCONV tCYC tCSD tSUCS tHDO tDIS tEN tF tR DESCRIPTION Analog input sample time Conversion time Complete cycle time CS falling to DCLOCK low CS falling to DCLOCK rising DCLOCK falling to current DOUT not valid CS rising to DOUT tri-state DCLOCK falling to DOUT enabled DOUT fall time DOUT rise time 20 5 15 70 20 5 7 100 50 25 25 22 0 MIN 4.5 16 TYP MAX 5.0 UNIT DCLOCKs DCLOCKs DCLOCKs ns ns ns ns ns ns ns Submit Documentation Feedback 9 ADS8326 www.ti.com SBAS343 – MAY 2007 TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. INTEGRAL LINEARITY ERROR vs CODE 3 2 1 0 -1 -2 -3 0000h 3 2 1 DIFFERENTIAL LINEARITY ERROR vs CODE DLE(LSB) 4000h 8000h Output Code C000h FFFFh ILE (LSB) 0 -1 -2 -3 0000h 4000h 8000h Output Code C000h FFFFh Figure 2. CHANGE IN OFFSET vs TEMPERATURE 0.50 0.25 0.50 Figure 3. CHANGE IN GAIN vs TEMPERATURE Delta from +25°C (LSB) 0 -0.25 -0.50 -0.75 -1.00 -50 -25 0 25 50 75 100 Temperature (°C) Delta from +25°C (LSB) 0.25 0 -0.25 -0.50 -0.75 -50 -25 0 25 50 75 100 Temperature (°C) Figure 4. CHANGE IN OFFSET vs COMMON-MODE VOLTAGE 30 30 Figure 5. CHANGE IN GAIN vs COMMON-MODE VOLTAGE Delta Relative to VCM = 0V (LSB) 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 Delta Relative to VCM = 0V (LSB) 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 VCM (V) VCM (V) Figure 6. Figure 7. 10 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. FREQUENCY SPECTRUM (8192 point FFT, fIN = 1.9836kHz, –0.2dB) 0 -20 -40 0 -20 -40 FREQUENCY SPECTRUM (8192 point FFT, fIN = 9.9792kHz, –0.2dB) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 25 50 75 Frequency (kHz) 100 125 Amplitude (dB) -60 -80 -100 -120 -140 -160 0 25 50 75 Frequency (kHz) 100 125 Figure 8. SIGNAL-TO-NOISE AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 100 SNR 95 105 100 95 Figure 9. SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQEUNCY -105 SFDR -100 -95 SNR and SINAD (dB) 90 SFDR (dB) 85 80 75 70 65 1 10 Frequency (kHz) 100 200 SINAD 85 80 75 70 NOTE: (1) First nine harmonics of the input frequency. 65 1 10 Frequency (kHz) 100 200 THD(1) -85 -80 -75 -70 -65 Figure 10. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 16.0 15.0 14.0 13.0 12.0 11.0 10.0 1 10 Frequency (kHz) 100 200 0.25 0.20 Figure 11. CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE fIN = 1.98364kHz, -0.2dB Delta from +25°C (dB) 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -50 -25 0 25 50 75 100 Temperature (°C) ENOB (Bits) Figure 12. Figure 13. Submit Documentation Feedback THD (dB) 90 -90 11 ADS8326 www.ti.com SBAS343 – MAY 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL 100 90 80 fIN = 1.98364kHz, -0.2dB 100 200 PEAK-TO-PEAK NOISE FOR A DC INPUT vs REFERENCE VOLTAGE SINAD (dB) 70 60 50 40 30 20 10 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Level (dB) Peak-to-Peak Noise (LSB) 10 1 0.1 1 Reference Voltage (V) 5 Figure 14. SUPPLY CURRENT vs TEMPERATURE 1.84 10 Figure 15. SUPPLY CURRENT vs SAMPLING RATE 1.83 Supply Current (mA) 1.82 Supply Current (mA) 1 0.1 1.81 1.80 0.01 1.79 -50 -25 0 25 50 75 100 Temperature (°C) 0.001 1 10 Sampling Rate (kHz) 100 250 Figure 16. REFERENCE CURRENT vs SAMPLING RATE 1000 30 28 26 24 22 20 18 1 10 Sampling Rate (kHz) 100 250 -50 -25 0 Figure 17. POWER-DOWN CURRENT vs TEMPERATURE Refernce Current (mA) 100 10 1 0.1 Power-Down Current (nA) 25 50 75 100 Temperature (°C) Figure 18. Figure 19. 12 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) 6990 NEED TITLE 592 0 7FFC 0 7FFD 7FFE 7FFF Code 610 0 8000 8001 0 8002 Figure 20. Submit Documentation Feedback 13 ADS8326 www.ti.com SBAS343 – MAY 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. INTEGRAL LINEARITY ERROR vs CODE 3 2 1 0 -1 -2 -3 0000h 3 2 1 DIFFERENTIAL LINEARITY ERROR vs CODE DLE (LSB) 4000h 8000h Output Code C000h FFFFh ILE (LSB) 0 -1 -2 -3 0000h 4000h 8000h Output Code C000h FFFFh Figure 21. CHANGE IN OFFSET vs TEMPERATURE 0.50 0.25 0.50 0.25 Figure 22. CHANGE IN GAIN vs TEMPERATURE Delta from +25°C (LSB) 0 -0.25 -0.50 -0.75 -1.00 -50 -25 0 25 50 75 100 Temperature (°C) Delta from +25°C (LSB) 0 -0.25 -0.50 -0.75 -1.00 -50 -25 0 25 50 75 100 Temperature (°C) Figure 23. CHANGE IN OFFSET vs COMMON-MODE VOLTAGE 30 30 Figure 24. CHANGE IN GAIN vs COMMON-MODE VOLTAGE Delta Relative to VCM = 0V (LSB) 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 Delta Relative to VCM = 0V (LSB) 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 VCM (V) VCM (V) Figure 25. Figure 26. 14 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. FREQUENCY SPECTRUM (8192 point FFT, fIN = 1.9775kHz, –0.2dB) 0 -20 -40 0 -20 -40 FREQUENCY SPECTRUM (8192 point FFT, fIN = 9.9854kHz, –0.2dB) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 10 20 30 40 50 60 70 80 90 100 Frequency (kHz) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 10 20 30 40 50 60 70 80 90 100 Frequency (kHz) Figure 27. SIGNAL-TO-NOISE AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 95 90 SNR 100 95 90 85 80 75 70 65 60 55 50 45 40 1 10 Frequency (kHz) 100 200 1 Figure 28. SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQEUNCY -100 -95 -90 SFDR -85 -80 -75 -70 THD(1) -65 -60 -55 -50 NOTE: (1) First nine harmonics of the input frequency. 10 Frequency (kHz) 100 200 -45 -40 SNR and SINAD (dB) 85 80 75 70 65 60 55 50 55 SINAD SFDR (dB) Figure 29. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 15 14 0.4 Figure 30. CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE fIN = 1.97754kHz, -0.2dB 0.2 Delta from +25°C (dB) 13 ENOB (Bits) 12 11 10 9 8 7 1 10 Frequency (kHz) 100 200 0 -0.2 -0.4 -0.6 -0.8 -50 -25 0 25 50 75 100 Temperature (°C) Figure 31. Figure 32. 15 Submit Documentation Feedback THD (dB) ADS8326 www.ti.com SBAS343 – MAY 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL 100 90 80 fIN = 1.97754kHz, -0.2dB 1.38 1.37 SUPPLY CURRENT vs TEMPERATURE SINAD (dB) 70 60 50 40 30 20 10 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Level (dB) Supply Current (mA) 1.36 1.35 1.34 1.33 1.32 1.31 1.30 -50 -25 0 25 50 75 100 Temperature (°C) Figure 33. SUPPLY CURRENT vs SAMPLING RATE 10 1000 Figure 34. REFERENCE CURRENT vs SAMPLING RATE Reference Current (mA) 100 200 1 Supply Current (mA) 100 0.1 10 0.01 0.001 1 0.0001 1 10 Sampling Rate (kHz) 0.1 1 10 Sampling Rate (kHz) 100 200 Figure 35. OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) Figure 36. 4791 NEED TITLE 1665 1643 0 7FFC 53 7FFD 7FFE 7FFF Code 8000 40 8001 0 8002 Figure 37. 16 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 THEORY OF OPERATION The ADS8326 is a classic Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The architecture is based on capacitive redistribution that inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µ CMOS process. The architecture and process allow the ADS8326 to acquire and convert an analog signal at up to 250,000 conversions per second while consuming less than 10mW from VDD. Differential linearity for the ADS8326 is factory-adjusted via a package-level trim procedure. The state of the trim elements is stored in non-volatile memory and is continuously updated after each acquisition cycle, just prior to the start of the successive approximation operation. This process ensures that one complete conversion cycle always returns the part to its factory-adjusted state in the event of a power interruption. The ADS8326 requires an external reference, an external clock, and a single power source (VDD). The external reference can be any voltage between 0.1V and VDD. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8326. The external clock can vary between 24kHz (1kHz throughput) and 6.0MHz (250kHz throughput). The duty cycle of the clock is essentially unimportant, as long as the minimum high and low times are at least 200ns (VDD = 4.75V or greater). The minimum clock frequency is set by the leakage on the internal capacitors to the ADS8326. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially (most significant bit first) on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress–there is no pipeline delay. It is possible to continue to clock the ADS8326 after the conversion is complete and to obtain the serial data least significant bit first. See the Timing Information section for more information. Submit Documentation Feedback 17 ADS8326 www.ti.com SBAS343 – MAY 2007 ANALOG INPUT The analog input of ADS8326 is differential. The +IN and –IN input pins allow for a differential input signal. The amplitude of the input is the difference between the +IN and –IN input, or (+IN) – (–IN). Unlike some converters of this type, the –IN input is not resampled later in the conversion cycle. When the converter goes into Hold mode or conversion, the voltage difference between +IN and –IN is captured on the internal capacitor array. Common Voltage Range (V) 0V to +VREF Peak-to-Peak Common-Mode Voltage ADS8326 Figure 38. Methods of Driving the ADS8326 The range of the –IN input is limited to –0.3V to +0.5V. As a result of this limitation, the differential input could be used to reject signals that are common to both inputs in the specified range. Thus, the –IN input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The general method for driving the analog input of the ADS8326 is shown in Figure 38 and Figure 40. The –IN input is held at the common-mode voltage. The +IN input swings from –IN (or common-mode voltage) to –IN + VREF (or common-mode voltage + VREF ), and the peak-to-peak amplitude is +VREF . The value of VREF determines the range over which the common-mode voltage may vary, as shown in Figure 39. Figure 6 and Figure 7 (+5V), and Figure 25 and Figure 26 (+2.7V) illustrate the typical change in gain and offset as a function of the common-mode voltage applied to the –IN pin. Common-Mode Voltage + VREF +VREF +IN 1 VDD = 5V 0.5 0 -0.3 -1 2 2.5 3 4 VREF (V) 4.8 5 6 Figure 39. +IN Analog Input: Common-Mode Voltage Range vs VREF Common-Mode Voltage -IN = Common-Mode Voltage t NOTE: The maximum differential voltage between +IN and –IN of the ADS8326 is VREF. See Figure 39 for a further explanation of the common-mode voltage range for differential inputs. Figure 40. Differential Input Mode of the ADS8326 18 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 The input current required by the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS8326 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (48pF) to a 16-bit settling level within 4.5 clock cycles (0.750µs). When the converter goes into Hold mode, or while it is in Power-Down mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –IN input should not drop below GND – 0.3V or exceed GND + 0.5V. The +IN input should always remain within the range of GND – 0.3V to VDD + 0.3V, or –IN to –IN + VREF , whichever limit is reached first. Outside of these ranges, the converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Often, a small capacitor (20pF) between the positive and negative inputs helps to match their impedance. To obtain maximum performance from the ADS8326, the input circuit from Figure 41 is recommended. Single-Ended 10W OPA365 1000pF ADS8326 -IN 50W 48pF +IN 50W 48pF Differential 10W OPA365 1000pF 1nF 10W OPA365 1000pF -IN ADS8326 50W 48pF 50W 48pF +IN Figure 41. Single-Ended and Differential Methods of Interfacing the ADS8326 Submit Documentation Feedback 19 ADS8326 www.ti.com SBAS343 – MAY 2007 REFERENCE INPUT ADS8326 The external reference sets the analog input range. The ADS8326 operates with a reference in the range of 0.1V to VDD. There are several important implications to this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the least significant bit (LSB) size and is equal to the reference voltage divided by 65,536. This means that any offset or gain error inherent in the A/D converter will appear to increase (in terms of LSB size) as the reference voltage is reduced. For a reference voltage of 2.5V, the value of the LSB is 38.15µV, and for a reference voltage of 5V, the LSB is 76.3µV. The noise inherent in the converter will also appear to increase with a lower LSB size. With a 5V reference, the internal noise of the converter typically contributes only 1.5LSB peak-to-peak of potential error to the output code. When the external reference is 2.5V, the potential error contribution from the internal noise will be two times larger (3LSB). The errors arising from the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, see Figure 15, Peak-to-Peak Noise for a DC Input vs Reference Voltage. Note that the Effective Number Of Bits (ENOB) figure is calculated based on the converter signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 × ENOB + 1.76 VREF OPA350 47mF 50W 24pF Figure 42. Input Reference Circuit and Interface When the ADS8326 is in Power-Down mode, the input resistance of the reference pin will have a value of 5GΩ. Since the input capacitors must be recharged before the next conversion starts, an operational amplifier with good dynamic characteristics must be used to buffer the reference input. Noise The transition noise of the ADS8326 itself is extremely low, as shown in Figure 20 (+5V) and Figure 37 (+2.7V); it is much lower than competing A/D converters. These histograms were generated by applying a low-noise DC input and initiating 8192 conversions. The digital output of the A/D converter will vary in output code because of the internal noise of the ADS8326. This is true for all 16-bit, SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6, which yields the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8326, with < 3 output codes for the ±3σ distribution, yields < ±0.5LSB of transition noise. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. Averaging The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√n , where n is the number of averages. For example, averaging four conversion results reduces the transition noise from ±0.5LSB to ±0.25LSB. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signal-to-noise ratio improves by 3dB. With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Due to the lower LSB size, the converter is also more sensitive to external sources of error, such as nearby digital signals and electromagnetic interference. The equivalent input circuit for the reference voltage is presented in Figure 42. During the conversion process, an equivalent capacitor of 24pF is switched on. To obtain optimum performance from the ADS8326, special care must be taken in designing the interface circuit to the reference input pin. To ensure a stable reference voltage, a 47µF tantalum capacitor with low ESR should be connected as close as possible to the input pin. If a high output impedance reference source is used, an additional operational amplifier with a current-limiting resistor must be placed in front of the capacitors. 20 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 DIGITAL INTERFACE Signal Levels The ADS8326 has a wide range of power-supply voltage. The A/D converter, as well as the digital interface circuit, is designed to accept and operate from 2.7V up to 5.5V. This voltage range will accommodate different logic levels. When the ADS8326 power-supply voltage is in the range of 4.5V to 5.5V (5V logic level), the ADS8326 can be connected directly to another 5V, CMOS-integrated circuit. When the ADS8326 power-supply voltage is in the range of 2.7V to 3.6V (3V logic level), the ADS8326 can be connected directly to another 3.3V LVCMOS integrated circuit. Serial Interface The ADS8326 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as illustrated in the Timing Information section. The DCLOCK signal synchronizes the data transfer, with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a low value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data, but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken high and returned low. Data Format The output data from the ADS8326 is in Straight Binary format, as shown in Figure 43. This figure represents the ideal output code for a given input voltage and does not include the effects of offset, gain error, or noise. Submit Documentation Feedback 21 ADS8326 www.ti.com SBAS343 – MAY 2007 Straight Binary 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 65535 65534 65533 Digital Output Code 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 32769 32768 32767 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 2 1 0 VZ = VCM = 0V 38.15mV 2.499962V 2.500038V VFS = VCM + VREF = 5V VFS - 1LSB = 4.999924V VMS = VCM + VREF/2 = 2.5V 76.29mV 152.58mV Unipolar Analog Input Voltage 4.999847V 1LSB = 76.29mV VCM = 0V 16- BIT Zero Code Midscale Code Full- Scale Code Straight Binary Output VZ = 0000h VMS = 8000h VFS = FFFFh Unipolar Analog Input VCODE = VCM VCODE = VCM + VREF/2 VCODE = (VCM + VREF) - 1LSB VREF = 5V Figure 43. Ideal Conversion Characteristics (Conditions: VCM = 0V, VREF = 5V) 22 Submit Documentation Feedback Step ADS8326 www.ti.com SBAS343 – MAY 2007 POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS8326 to convert at up to a 250kHz rate while requiring very little power. However, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS8326 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS8326 goes into Power-Down mode under two conditions: when the conversion is complete and whenever CS is high (see the Timing Information section). Ideally, each conversion should occur as quickly as possible, preferably at a 6.0MHz clock rate. This way, the converter spends the longest possible time in Power-Down mode. This is very important because the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously until Power-Down mode is entered. Figure 17 and Figure 18 (+5V), and Figure 35 and Figure 36 illustrate the current consumption of the ADS8326 versus sample rate. For these graphs, the converter is clocked at maximum speed regardless of the sample rate. CS is held high during the remaining sample period. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is high. CS low will only shut down the analog section. The digital section is completely shut down only when CS is high. Thus, if CS is left low at the end of a conversion, and the converter is continually clocked, the power consumption will not be as low as when CS is high. Short Cycling Another way to save power is to use the CS signal to short-cycle the conversion. The ADS8326 places the latest data bit on the DOUT line as it is generated; therefore, the converter can easily be short-cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS high) after the 14th bit has been clocked out. This technique can also be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system because they spend more time in Power-Down mode. Submit Documentation Feedback 23 ADS8326 www.ti.com SBAS343 – MAY 2007 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8326 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At a 250kHz conversion rate, the ADS8326 makes a bit decision every 167ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level, all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few potential sources. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter DCLOCK signal because the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8326 should be clean and well-bypassed. A 0.1µF ceramic bypass capacitor should be placed as close as possible to the ADS8326 package. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. The reference should be similarly bypassed with a 47µF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS8326 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instruments' OPA365 op amp provides optimum performance for buffering the signal inputs; the OPA350 can be used to effectively buffer the reference input. Also, keep in mind that the ADS8326 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out, as described in the previous paragraph, voltage variation resulting from the line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin on the ADS8326 should be placed on a clean ground point. In many cases, this will be the analog ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. 24 Submit Documentation Feedback ADS8326 www.ti.com SBAS343 – MAY 2007 APPLICATION CIRCUITS Figure 44 and Figure 45 show two examples of a basic data acquisition system. The ADS8326 input range is connected to 2.5V or 4.096V. The 5Ω resistor and 1µF to 10µF capacitor filters the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of noise. Operational amplifiers and voltage reference are connected to analog power supply, AVDD. DVDD 2.7V to 3.6V 0.1mF AVDD 2.7V to 5V REF3225 10W IN 0.47mF GND OUT 2.2mF OPA350 47mF ADS8326 DSP 10W OPA365 VCM + (0V to 2.5V) 1000pF 1nF 10W OPA365 VCM 1000pF -IN +IN CS DOUT DCLOCK GND GND TMS320C6xx or TMS320C5xx or TMS320C2xx REF VDD 0.1mF 5W + 10mF + 10mF Figure 44. Basic Data Acquisition System: Example 1 DVDD 4.5V to 5.5V 0.1mF AVDD 4.3V to 5.5V REF3240 10W IN 0.47mF OUT 2.2mF GND OPA350 47mF ADS8326 REF VDD 0.1mF 5W + 10mF + 10mF 10W OPA365 0V to 4.096V 1000pF CS DOUT DCLOCK -IN GND +IN Microcontroller or DSP GND Figure 45. Basic Data Acquisition System: Example 2 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2007 PACKAGING INFORMATION Orderable Device ADS8326IBDGKR ADS8326IBDGKRG4 ADS8326IBDGKT ADS8326IBDGKTG4 ADS8326IDGKR ADS8326IDGKRG4 ADS8326IDGKT ADS8326IDGKTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type MSOP MSOP MSOP MSOP MSOP MSOP MSOP MSOP Package Drawing DGK DGK DGK DGK DGK DGK DGK DGK Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2007 Device Package Pins Site Reel Diameter (mm) 330 330 330 330 Reel Width (mm) 12 12 12 12 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8 8 8 8 W Pin1 (mm) Quadrant 12 12 12 12 NONE NONE NONE NONE ADS8326IBDGKR ADS8326IBDGKT ADS8326IDGKR ADS8326IDGKT DGK DGK DGK DGK 8 8 8 8 TAI TAI TAI TAI 5.3 5.3 5.3 5.3 3.4 3.4 3.4 3.4 1.4 1.4 1.4 1.4 TAPE AND REEL BOX INFORMATION Device ADS8326IBDGKR ADS8326IBDGKT ADS8326IDGKR ADS8326IDGKT Package DGK DGK DGK DGK Pins 8 8 8 8 Site TAI TAI TAI TAI Length (mm) 346.0 346.0 346.0 346.0 Width (mm) 346.0 346.0 346.0 346.0 Height (mm) 29.0 29.0 29.0 29.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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