AFE030AIRGZR

Order Now Product Folder Support & Community Tools & Software Technical Documents AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 AFE030 Powerline Communications Analog Front-End 1 Features 3 Description • The AFE030 is a low-cost, integrated, powerline communications (PLC) analog front-end (AFE) device that is capable of capacitive- or transformer-coupled connections to the powerline while under the control of a digital signal processor (DSP) or microcontroller. It is ideal for driving low-impedance lines that require up to 1 A into reactive loads. The integrated receiver is able to detect signals down to 20 μVRMS and is capable of a wide range of gain options to adapt to varying input signal conditions. This monolithic integrated circuit provides high reliability in demanding powerline communications applications. 1 • • • • • • • • • • • • • • • Integrated powerline driver with thermal and overcurrent protection Conforms to EN50065-1 Pin-compatible to AFE031 Large output swing: 13 VPP at 1 A (15-V supply) Low power consumption: 15 mW (receive mode) Programmable Tx and Rx filters Supports EN50065 CENELEC bands A, B, C, D Supports OFDM, FSK, and S-FSK Supports IEC 61334 Receive sensitivity: 20 μVRMS, typical Programmable Tx/Rx gain control Four-wire serial peripheral interface Two integrated zero crossing detectors Two-wire transceiver buffer Package: QFN-48 PowerPAD™ Extended junction temperature range: –40°C to +125°C The AFE030 transmit power amplifier operates from a single supply in the range of 7 V to 26 V. At maximum output current, a wide output swing provides a 12-VPP (IOUT = 1 A) capability with a nominal 15-V supply. The analog and digital signal processing circuitry operates from a single 3.3-V power supply. Device Information(1) PART NUMBER PACKAGE AFE030 VQFN (48) BODY SIZE (NOM) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • eMetering Lighting Solar Pilot wire E_Rx_OUT PA_OUT E_Rx_IN PA_GND TSENSE PA_VS ZC_IN1 ZC_IN2 PA_ISET ZC_OUT2 ZC_OUT1 REF1 DVDD DGND AGND1 AVDD1 AGND2 AVDD2 REF2 Block Diagram E_Tx_CLK ZC1 Bias E_Tx_IN ZC2 E_Tx_OUT Two-Wire Rx/Tx RxPGA_1 SCLK DI DO Digital Interface (SPI) Rx_PGA1_IN Power Amplifier CS Rx_PGA1_OUT Rx_F_IN DAC SD Tx_FLAG Rx_FLAG Rx_C1 Control Register Rx_C2 INT Rx Filter Rx_F_OUT RxPGA_2 Digital-to-Analog Converter TxPGA Tx Filter Rx_PGA2_IN Rx_PGA2_OUT Tx_F_OUT PA_IN Tx_F_IN2 TX_PGA_OUT Tx_F_IN1 Tx_PGA_IN Device 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description, continued .......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6 7.1 Absolute Maximum Ratings ...................................... 6 7.2 ESD Ratings.............................................................. 6 7.3 Thermal Information .................................................. 6 7.4 Electrical Characteristics: Transmitter (Tx), Tx_DAC...................................................................... 7 7.5 Electrical Characteristics: Transmitter (Tx), Tx_PGA...................................................................... 7 7.6 Electrical Characteristics: Transmitter (Tx), Tx_FILTER................................................................. 8 7.7 Electrical Characteristics: Power Amplifier (PA) ...... 9 7.8 Electrical Characteristics: Receiver (Rx), Rx PGA1........................................................................ 10 7.9 Electrical Characteristics: Receiver (Rx), Rx Filter 11 7.10 Electrical Characteristics: Receiver (Rx), Rx PGA2........................................................................ 12 7.11 Electrical Characteristics: Digital.......................... 13 7.12 Electrical Characteristics: Two-Wire Interface ..... 14 7.13 Electrical Characteristics: Zero-Crossing Detector.................................................................... 14 7.14 Electrical Characteristics: Internal Bias Generator ................................................................. 15 7.15 Electrical Characteristics: Power Supply ............. 15 7.16 Typical Characteristics .......................................... 16 8 Parameter Measurement Information ................ 19 8.1 Timing Requirements .............................................. 19 8.2 Timing Diagrams ..................................................... 20 9 Detailed Description ............................................ 22 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Power Supplies ....................................................... Pin Descriptions ...................................................... Calibration Modes ................................................... Serial Interface ........................................................ 22 22 23 38 39 41 42 10 Application and Implementation........................ 46 10.1 10.2 10.3 10.4 10.5 Application Information.......................................... Typical Application ................................................ Line-Coupling Circuit............................................. Circuit Protection................................................... Thermal Considerations ........................................ 46 46 48 48 49 11 Device and Documentation Support ................. 53 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 53 53 54 54 54 54 54 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2011) to Revision B Page • Deleted Package/Ordering Information table; see Package Option Addendum at the end of the data sheet ....................... 1 • Deleted ESD specifications from Absolute Maximum Ratings table. Moved to separate ESD Ratings table. ...................... 6 • Moved content from Application and Implementation ......................................................................................................... 23 • Deleted references to Tx PGA calibration in Calibration Modes ......................................................................................... 41 • Deleted reference to Tx PGA calibration in Table 15 .......................................................................................................... 44 • Deleted Packaging/Mechanicals section; information appended to end of data sheet ....................................................... 52 Changes from Original (December 2011) to Revision A Page • Changed product status to Production Data .......................................................................................................................... 1 • Added cross-reference to footnote 2 to Output short-circuit (PA) parameter in Absolute Maximum Ratings table ............... 6 2 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 5 Description, continued The AFE030 is internally protected against overtemperature and short-circuit conditions. It also provides an adjustable current limit. An interrupt output is provided that indicates both current limit and thermal limit. There is also a shutdown pin that can be used to quickly put the device into its lowest power state. Through the four-wire serial peripheral interface, or SPI™, each functional block can be enabled or disabled to optimize power dissipation. The AFE030 is housed in a thermally-enhanced, surface-mount PowerPAD package (QFN-48). Operation is specified over the extended industrial junction temperature range of –40°C to +125°C. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 3 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 6 Pin Configuration and Functions PA_GND2 ZC_IN1 ZC_IN2 ZC_OUT1 40 39 38 37 PA_OUT2 PA_GND1 43 41 PA_OUT1 44 42 PA_VS1 PA_VS2 45 Tx_FLAG PA_ISET 47 46 Rx_FLAG 48 RGZ Package 48-Pin VQFN Top View DGND 1 36 ZC_OUT2 DVDD 2 35 E_Tx_CLK SCLK 3 34 E_Tx_IN DIN 4 33 E_Tx_OUT DOUT 5 32 E_Rx_IN CS 6 31 E_Rx_OUT Thermal Pad DAC 7 30 AVDD2 SD 8 29 AGND2 INT 20 21 22 23 Rx_PGA2_IN Rx_F_OUT Rx_C2 24 19 REF1 Rx_PGA2_OUT Rx_C1 17 Rx_F_IN 18 25 PA_IN 12 16 AGND1 Tx_F_IN2 Rx_PGA1_OUT Tx_F_OUT 26 15 11 14 AVDD1 Tx_F_IN1 Rx_PGA1_IN Tx_PGA_OUT REF2 27 13 28 10 Tx_PGA_IN 9 TSENSE Pin Functions PIN I/O DESCRIPTION NAME NO. AGND1 12 — Analog ground AGND2 29 — Analog ground AVDD1 11 — Analog supply AVDD2 30 — Analog supply CS 6 — SPI digital chip select DAC 7 — DAC mode select DIN 4 I DGND 1 — Digital ground DOUT 5 O SPI digital output DVDD 2 — Digital supply E_Rx_IN 32 I Two-wire receiver input E_Rx_OUT 31 O Two-wire receiver output E_Tx_CLK 35 I Two-wire transmitter clock input E_Tx_IN 34 I Two-wire transmitter input E_Tx_OUT 33 O Two-wire transmitter output INT 9 — Interrupt on overcurrent or thermal limit PA_GND1 41 — Power amplifier ground PA_GND2 40 — Power amplifier ground 4 SPI digital input Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. PA_IN 18 I PA_ISET 46 — Power amplifier current limit set PA_OUT1 43 O Power amplifier output PA_OUT2 42 O Power amplifier output PA_VS1 45 — Power amplifier supply PA_VS2 44 — Power amplifier supply REF1 19 — Power amplifier noise reducing capacitor REF2 28 — Receiver noise reducing capacitor Rx_C1 24 — Receiver external frequency select Rx_C2 23 — Receiver external frequency select Rx_F_IN 25 I Receiver filter input Rx_F_OUT 22 O Receiver filter output Rx_FLAG 48 — Receiver ready flag Rx PGA1_IN 27 I Receiver PGA(1) input Rx PGA1_OUT 26 O Receiver PGA(1) output Rx PGA2_IN 21 I Receiver PGA(2) input Rx PGA2_OUT 20 O Receiver PGA(2) output SCLK 3 — SPI serial clock SD 8 — System shutdown TSENSE 10 — Temp sensing diode (anode) Tx_F_IN1 15 I Transmit filter input 1 Tx_F_IN2 16 I Transmit filter input 2 Tx_F_OUT 17 O Transmit filter output Tx_FLAG 47 — Transmitter ready flag Tx_PGA_IN 13 I Transmit PGA input Tx_PGA_OUT 14 O Transmit PGA output ZC_IN1 39 I Zero-crossing detector input ZC_IN2 38 I Zero-crossing detector input ZC_OUT1 37 O Zero-crossing detector output ZC_OUT2 36 O Zero-crossing detector output Power amplifier input Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 5 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX Supply voltage, PA_VS Pins 18,19 (2) Signal input terminals Voltage Voltage limit PA_GND – 0.4 PA_VS + 0.4 Pins 13, 15, 16, 21, 23-25, 28, 32, 34, 35, 38, 39, 46 (2) AGND – 0.4 AVDD + 0.4 Pins 3, 4, 6, 7, 8 (2) DGND – 0.4 DVDD + 0.4 Pin 27 Current 10 Pins 13, 15, 16, 21, 23-25, 28, 32, 34, 35, 38, 39, 46 (2) –10 10 Pins 3, 4, 6, 7, 8 (2) –10 10 Signal output terminals Output short circuit (PA) Pins 42, 43 Current limit Pin 10 (2) (3) (4) (3) (4) mA Continuous Continuous –10 10 –40 150 Junction, TJ 150 Storage, Tstg (2) 5.5 –10 Operating, TA (4) (1) 10 Pins 18,19 (2) Pins 5, 9, 14, 17, 20, 22, 26, 31, 33, 36, 37, 47, 48 (2) V 5.5 DVDD Signal input terminals Temperature –10 AVDD Supply voltage UNIT 26 –55 °C 125 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.4 V beyond the supply rails should be current limited to 10 mA or less. Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.4 V beyond the supply rails should be current limited to 10 mA or less. Short-circuit to ground. The AFE030 automatically goes into shutdown at junction temperatures that exceed 165°C. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 3000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Thermal Information AFE030 THERMAL METRIC (1) RGZ (VQFN) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 27.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 12.1 °C/W RθJB Junction-to-board thermal resistance 7.5 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 7.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com 7.4 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Electrical Characteristics: Transmitter (Tx), Tx_DAC At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS Output range Resolution Total harmonic distortion at 62.5 kHz (1) THD MIN GND + 0.1 MAX UNIT AVDD – 0.1 V 1024 steps, 10-bit DAC 3.2 mV Second-harmonic distortion –73 dB Third-harmonic distortion –56 dB Fourth-harmonic distortion –94 dB 1.5 MSPS Data rate (1) TYP Total harmonic distortion measured at output of Tx_PGA configured in a gain of 1 V/V with an amplitude of 3 VPP, at a 1-MHz sample rate. 7.5 Electrical Characteristics: Transmitter (Tx), Tx_PGA At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range RI Input resistance GND – 0.1 AVDD + 0.1 V G = 1 V/V 58 kΩ G = 0.707 V/V 68 kΩ G = 0.5 V/V 77 kΩ G = 0.25 V/V 92 kΩ G = 1 V/V 8 MHz G = 0.707 V/V 9 MHz G = 0.5 V/V 10 MHz G = 0.25 V/V 12 MHz RLOAD = 10 kΩ, connected to AVDD/2 10 Sourcing 25 mA Sinking 25 mA 1 Ω FREQUENCY RESPONSE DAC mode enabled BW Bandwidth OUTPUT VO Voltage output swing from AGND or AVDD IO Maximum continuous current, dc RO Output resistance f = 100 kHz Gain error For all gains Gain error drift TJ = –40°C to +125°C 100 mV GAIN –1% ±0.1% 6 +1% ppm/°C Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 7 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 7.6 www.ti.com Electrical Characteristics: Transmitter (Tx), Tx_FILTER At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range RI GND – 0.1 Input resistance (Tx_F_IN1 and Tx_F_IN2) AVDD + 0.1 V 43 kΩ 95 kHz FREQUENCY RESPONSE CENELEC A Mode Passband frequency –3 dB Stop band attenuation –50 Stop band frequency Filter gain –60 dB 910 kHz 0 dB 145 kHz CENELEC B/C/D MODES Passband frequency –3 dB Stop band attenuation –50 Stop band frequency Filter gain –60 dB 870 kHz 0 dB OUTPUT VO Voltage output swing from AGND or AVDD IO Maximum continuous current, dc RO Output resistance RLOAD = 10 kΩ, connected to AVDD/2 10 Sourcing 25 mA Sinking 25 mA 1 Ω f = 100 kHz 100 mV TRANSMITTER NOISE Integrated noise at PA output (1) (1) 8 CENELEC Band A (40 kHz to 90 kHz) Noise-reducing capacitor = 1 nF from pin 19 to ground 435 μVRMS CENELEC Bands B/C/D (95 kHz to 140 kHz) Noise-reducing capacitor = 1 nF from pin 19 to ground 460 μVRMS Includes DAC, Tx_PGA, Tx_Filter, PA, and REF1 bias generator. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com 7.7 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Electrical Characteristics: Power Amplifier (PA) At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range RI GND – 0.1 Input resistance PA_VS + 0.1 V 20 kΩ FREQUENCY RESPONSE BW Bandwidth ILOAD = 0 670 kHz SR Slew rate 10-V step 19 V/μs Full-power bandwidth VOUT = 10 VPP 300 kHz AC PSRR f = 50 kHz 14 dB IO = 300 mA, sourcing 0.3 1 V OUTPUT From PA_VS VO Voltage output swing From PA_Gnd IO RO IO = 1.0 A, sourcing IO = 300 mA, sinking IO = 1.0 A, sinking 1 1.5 V 0.3 1 V 1 1.5 V Maximum continuous current, dc PA_ISET (pin 46) connected to ground Maximum peak current, ac TJ = –40°C to +125°C, f = 50 kHz 1.0 A Output resistance IO = 1.0 A 0.1 Ω PA disabled Output impedance, f = 100 kHz, REF1 enabled 1.0 145 ll 120 Output current limit range Current limit equation Solved for RSET (current limit) A kΩ ll pF ±0.4 to ±1.0 A ILIM = 20 k × [1.2 V/(RSET + 15 kΩ)] A RSET = [(20 k × 1.2 V/ILIM) – 15 kΩ] Ω GAIN (RLOAD = 1 kΩ) G Nominal gain 6.5 Gain error Gain error drift –1% TJ = –40°C to +125°C 0.1% ±1 V/V +1% ppm/°C TSENSE DIODE η Diode ideality factor 1.033 THERMAL SHUTDOWN Junction temperature at shutdown Hysteresis Return to normal operation +165 °C 20 °C +145 °C Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 9 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 7.8 www.ti.com Electrical Characteristics: Receiver (Rx), Rx PGA1 At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range RI Input resistance 10 VPP G = 2 V/V 10 kΩ G = 1 V/V 15 kΩ G = 0.5 V/V 20 kΩ G = 0.25 V/V 24 kΩ G = 2 V/V 6 MHz G = 1 V/V 10 MHz G = 0.5 V/V 13 MHz G = 0.25 V/V 15 MHz RLOAD = 6 kΩ, connected to AVDD/2 10 Sourcing 25 mA Sinking 25 mA 1 Ω FREQUENCY RESPONSE BW Bandwidth OUTPUT VO Voltage output swing from AGND or AVDD IO Maximum continuous current, dc RO Output resistance G = 1, f = 100 kHz 100 mV GAIN Gain error Gain error drift 10 G = 0.25 V/V –1% ±0.1% +1% G = 0.5 V/V –1% ±0.1% +1% G = 1 V/V –1% ±0.1% +1% G = 2 V/V –2% ±0.2% +2% TJ = –40°C to +125°C Submit Documentation Feedback 1 ppm/°C Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com 7.9 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Electrical Characteristics: Receiver (Rx), Rx Filter At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range RIN GND – 0.1 Input resistance AVDD + 0.1 V 6 kΩ 90 kHz FREQUENCY RESPONSE, CENELEC A MODE (Rx_C1 = 680 pF, Rx_C2 = 680 pF) Passband frequency –3 dB Stop band attentuation –25 Stop band frequency Filter gain –33 dB 270 kHz 0 dB 145 kHz FREQUENCY RESPONSE, CENELEC B/C/D MODES (Rx_C1 = 270 pF, Rx_C2 = 560 pF) Passband frequency –3 dB Stop band attentuation –25 Stop band frequency Filter gain –35 dB 350 kHz 0 dB OUTPUT VO Voltage output swing from AGND or AVDD IO Maximum continuous current, dc RO Output resistance RLOAD = 10 kΩ, connected to AVDD/2 10 Sourcing 25 mA Sinking 25 mA 5 Ω f = 100 kHz 100 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 mV 11 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 7.10 www.ti.com Electrical Characteristics: Receiver (Rx), Rx PGA2 At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range RI Input impedance GND – 0.1 AVDD + 0.1 V G = 64 V/V 1.7 kΩ G = 16 V/V 6.3 kΩ G = 4 V/V 21 kΩ G = 1 V/V 53 kΩ G = 64 V/V 300 kHz G = 16 V/V 800 kHz G = 4 V/V 1.4 MHz G = 1 V/V 4 MHz FREQUENCY RESPONSE BW Bandwidth OUTPUT VO Voltage output swing from AGND or AVDD IO Maximum continuous current, dc RO Output impedance RLOAD = 10 kΩ, connected to AVDD/2 10 Sourcing 25 mA Sinking 25 mA 1 Ω G = 1, f = 100 kHz 100 mV GAIN Gain error Gain error drift G = 1 V/V –2% ±1% 2% G = 4 V/V –2% ±1% 2% G = 16 V/V –2% ±1% 2% G = 64 V/V –4% ±1% 4% TJ = –40°C to +125°C 6 ppm/°C Rx SENSITIVITY Integrated noise, RTI (1) (1) 12 CENELEC Band A (40 kHz to 90 kHz) Noise-reducing capacitor = 1 μF from pin 28 to ground 14 μVRMS CENELEC Bands B/C/D (95 kHz to 140 kHz) Noise-reducing capacitor = 1 μF from pin 28 to ground 11 μVRMS Includes Rx PGA1, Rx_Filter, Rx PGA2, and REF2 bias generator. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com 7.11 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Electrical Characteristics: Digital At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX –1 0.01 1 UNIT DIGITAL INPUTS (SCLK, DIN, CS, DAC, SD) 0 ≤ VIN ≤ DVDD Leakage input current VIH High-level input voltage VIL Low-level input voltage 0.7 × DVDD μA V 0.3 × DVDD SD pin high SD > 0.7 × DVDD AFE030 in shutdown SD pin low SD < 0.3 × DVDD AFE030 in normal operation DAC pin high DAC > 0.7 × DVDD SPI access to DAC Registers DAC pin low DAC < 0.3 × DVDD SPI access to Command and Data Registers V DIGITAL OUTPUTS (DO, ZC_OUT) VOH High-level output voltage IOH = 3 mA VOL Low-level output voltage IOL = –3 mA DVDD – 0.4 DVDD V GND GND + 0.4 V 1 μA DIGITAL OUTPUTS (INT, Tx_Flag, Rx_Flag) IOH High-level output current VOH = 3.3 V VOL Low-level output voltage IOL = 4 mA IOL Low-level output current VOL = 400 mV INT pin high (open drain) INT pin low (open drain) (1) INT sink current < 1 μA INT < 0.4 V Tx_Flag high (open drain) Tx_Flag sink current < 1 μA Tx_Flag low (open drain) Tx_Flag < 0.4 V Rx_Flag high (open drain) Rx_Flag sink current < 1 μA Rx_Flag low (open drain) Rx_Flag < 0.4 V 0.4 4 V mA Normal operation μs Indicates an interrupt has occurred μs Indicates Tx block is not ready μs Indicates Tx block is ready μs Indicates Rx block is not ready μs Indicates Rx block is ready μs DIGITAL TIMING Gain select time 0.2 μs Shutdown mode, enable time 4.0 μs Shutdown mode, disable time 2.0 μs 50 μs Power-on reset (POR) power-up time (1) DVDD ≥ 2 V When an interrupt is detected (INT pin low), the contents of the I_Flag and T_Flag Registers can be read to determine the reason for the interrupt. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 13 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 7.12 www.ti.com Electrical Characteristics: Two-Wire Interface At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TWO-WIRE TRANSMITTER Frequency range (1) Leakage input current (E_Tx_In, E_Tx_Clk) 50 0 ≤ VIN ≤ DVDD –1 0.01 kHz 1 μA INPUT LOGIC LEVELS (E_Tx_In, E_Tx_Clk) VIH High-level input voltage VIL Low-level input voltage 0.7 × DVDD V 0.3 × DVDD V AVDD – 0.4 AVDD V GND GND + 0.4 V OUTPUT LOGIC LEVELS (E_Tx_Out) VOH High-level output voltage IOH = 3 mA VOL Low-level output voltage IOL = –3 mA TWO-WIRE RECEIVER Gain –4.5 dB Frequency range 300 kHz 25 mA Maximum sink current Maximum source current Input terminal offset 25 Referenced to VAVDD/2 –100 10 Input impedance (1) mA 100 78 mV kΩ The two-wire transmitter circuit is tested at Tx_CLK = 10 MHz. 7.13 Electrical Characteristics: Zero-Crossing Detector At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER TEST CONDITIONS MIN MAX Input voltage range AVDD – 0.4 AVDD + 0.4 Input current range –10 10 Input capacitance 3 UNIT V mA pF Rising threshold 0.45 0.9 1.35 V Falling threshold 0.25 0.5 0.75 V Hysteresis 0.20 0.4 0.60 Jitter 14 TYP 50 Hz, 240 VRMS Submit Documentation Feedback 10 V ns Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com 7.14 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Electrical Characteristics: Internal Bias Generator At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REF1 (Pin 19) Bias voltage RI Input resistance PA_VS/2 V 4 kΩ Turn-on time Noise-reducing capacitor = 1 nF from pin 19 to ground 20 ms Turn-off time Noise-reducing capacitor = 1 nF from pin 19 to ground 20 ms REF2 (Pin 28) Bias voltage RI Input resistance 7.15 VAVDD/2 V 4 kΩ Turn-on time Noise-reducing capacitor = 1 μF from pin 28 to ground 20 ms Turn-off time Noise-reducing capacitor = 1 μF from pin 28 to ground 20 ms Electrical Characteristics: Power Supply At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING SUPPLY RANGE PA_VS Power amplifier supply voltage 7 24 V DVDD AVDD Digital supply voltage 3.0 3.6 V Analog supply voltage 3.0 3.6 V 55 mA QUIESCENT CURRENT SD pin low IQPA_VS IQDVDD Power amplifier current Digital supply current IO = 0 A, PA = On (1) 40 IO = 0 A, PA = Off (2) 10 μA Tx configuration (3) 1.2 mA 5 μA Rx configuration (4) All blocks disabled (5) 5 Tx configuration (3) IQAVDD Analog supply current Rx configuration (4) All blocks disabled (5) μA 2.8 3.7 mA 3.6 5.3 mA 30 μA SHUTDOWN (SD) PA_VS Power amplifier supply voltage SD pin high 75 150 μA DVDD Digital supply voltage AVDD Analog supply voltage SD pin high 5 10 μA SD pin high 15 40 μA 125 °C TEMPERATURE Specified range (1) (2) (3) (4) (5) –40 Enable1 Register = 00100011, Enable2 Register = 00001110. Enable1 Register = 00000100, Enable2 Register = 00000110. In the Tx configuration, the following blocks are enabled: DAC, Tx, PA, REF1, and REF2. All other blocks are disabled. Enable1 Register = 00100011, Enable2 Register = 00001110. In the Rx configuration, the following blocks are enabled: Rx, REF1, and REF2. All other blocks are disabled. Enable1 Register = 00000100, Enable2 Register = 00000110. Enable1 Register = 00000000, Enable2 Register = 00000000. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 15 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 7.16 Typical Characteristics At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. 20 20 CENELEC A CENELEC B,C,D 0 0 −10 −10 −20 −30 −20 −30 −40 −40 −50 −50 −60 10k 100k Frequency (Hz) CENELEC A CENELEC B,C,D 10 Gain (dB) Gain (dB) 10 −60 10k 1M Figure 1. Tx Filter Gain vs Frequency Maximum PA Output Voltage (VPP) 40 Gain (dB) 30 20 10 0 −10 −20 −30 100k 1M Frequency (Hz) 15 10 5 1k 10k G003 100k Frequency (Hz) 1M 10M G004 Figure 4. Maximum PA Output Voltage vs Frequency 40 40 Gain = 1 V/V Gain = 0.707 V/V Gain = 0.5 V/V Gain = 0.25 V/V 30 20 20 10 0 −10 10 0 −10 −20 −20 −30 −30 100k 1M Frequency (Hz) Gain = 2 V/V Gain = 1 V/V Gain = 0.5 V/V Gain = 0.25 V/V 30 Gain (dB) Gain (dB) PA Supply = 24V PA Supply = 15V PA Supply = 12V 20 0 10M Figure 3. PA Gain vs Frequency 10M 20M −40 10k G005 Figure 5. Tx PGA Gain vs Frequency 16 G002 25 50 −40 10k 1M Figure 2. Rx Filter Gain vs Frequency 60 −40 10k 100k Frequency (Hz) G001 Submit Documentation Feedback 100k 1M Frequency (Hz) 10M 100M G006 Figure 6. Rx PGA1 Gain vs Frequency Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Typical Characteristics (continued) At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. 20 60 Gain = 64 V/V Gain = 16 V/V Gain = 4 V/V Gain = 1 V/V 50 40 0 20 Gain (dB) Gain (dB) 30 10 10 0 −10 −20 −10 −20 −30 −30 −40 10k 100k 1M Frequency (Hz) 10M −40 10k 100M G007 Figure 7. Rx PGA2 Gain vs Frequency G008 0.4 CENELEC BCD, Tx and Rx CENELEC A, Tx and Rx 175 0.3 0.2 150 Gain Error (%) Cutoff Frequency (kHz) 1M Figure 8. Two-Wire Receiver Gain vs Frequency 200 125 100 0.1 0 −0.1 −0.2 75 −0.3 50 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 −0.4 −40 −25 −10 110 125 G009 Figure 9. Filter Cutoff vs Temperature 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0 −0.1 G010 0 −0.3 −0.3 95 110 125 −0.1 −0.2 5 20 35 50 65 80 Junction Temperature (°C) 95 0.1 −0.2 −0.4 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) Figure 10. Tx PGA Gain Error vs Temperature Gain Error (%) Gain Error (%) 100k Frequency (Hz) 110 125 −0.4 −40 −25 −10 G011 Figure 11. PA Gain Error vs Temperature 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 G012 Figure 12. Rx PGA1 Gain Error vs Temperature Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 17 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Typical Characteristics (continued) At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. 0.4 60 0.3 Supply Current (mA) Gain Error (%) 0.2 0.1 0 −0.1 −0.2 40 30 20 10 −0.3 −0.4 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 0 −40 −25 −10 110 125 G013 Figure 13. Rx PGA2 Gain Error vs Temperature PA Current Limit (A) PA Current AVDD Current DVDD Current 100 50 0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 G014 1.5 1 0.5 0 110 125 0 G015 5 10 15 20 25 30 RSET (kΩ) 35 40 45 50 G016 Figure 16. PA Current Limit vs RSET 0.2 0.2 Tx Filter CENELEC A Tx Filter CENELEC B 0.15 0.15 0.1 0.1 0.05 0.05 Voltage (V) Voltage (V) 110 125 +3σ Typical −3σ Figure 15. Supply Current (Shutdown) vs Temperature 0 −0.05 0 −0.05 −0.1 −0.1 −0.15 −0.15 −0.2 0 10 µs/div (dB) 0 G017 Figure 17. Tx Filter Pulse Response 18 95 2 All blocks disabled AVDD = 3.3V DVDD = 3.3V PA_VS = 15V 150 −0.2 5 20 35 50 65 80 Junction Temperature (°C) Figure 14. Quiescent Supply Current vs Temperature 200 Supply Current (µA) PA Current (PA Enabled) AVDD Current (RX Mode) AVDD Current (TX Mode) 50 Submit Documentation Feedback 1 µs/div (dB) G018 Figure 18. PA Pulse Response Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Typical Characteristics (continued) At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. 0.2 Rx Filter CENELEC A Rx Filter CENELEC B 0.15 Voltage (V) 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 0 10 µs/div (dB) G019 Figure 19. Rx Pulse Response 8 Parameter Measurement Information 8.1 Timing Requirements Table 1. SPI Timing Requirements PARAMETER CONDITION MIN Input capacitance Input rise/fall time TYP MAX UNIT 1 pF tRFI CS, DIN, SCLK 2 ns Output rise/fall time tRFO DOUT 10 ns CS high time tCSH CS SCLK edge to CS fall setup time 20 ns ns tCS0 10 CS fall to first SCLK edge setup time tCSSC 10 SCLK frequency fSCLK ns 20 MHz SCLK high time tHI 20 ns SCLK low time tLO 20 ns tSCCS 10 ns SCLK last edge to CS rise setup time CS rise to SCLK edge setup time tCS1 10 ns DIN setup time tSU 10 ns DIN hold time tHD 5 SCLK to DOUT valid propagation delay tDO 20 ns CS rise to DOUT forced to Hi-Z tsoz 20 ns ns Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 19 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 8.2 Timing Diagrams tCSH CS tCSSC tSCCS tLO tCS1 tCS0 tHI SCLK tSU 1/fSCLK tHD DIN tSOZ tDO Hi-Z Hi-Z DOUT Figure 20. SPI Mode 0,0 tCSH CS tCSSC tSCCS tHI tCS1 tCS0 tLO SCLK tSU tHD 1/fSCLK DIN tSOZ tDO Hi-Z Hi-Z DOUT Figure 21. SPI Mode 1,1 CS SDI SDO W0 XX W1 W3 W2 XX XX XX W - Command of Write Register N XX - Don’t care; undefined. Figure 22. Write Operation in Stand-Alone Mode 20 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Timing Diagrams (continued) CS SDI SDO R0 R1 D0 XX R2 D1 Any Command R3 D3 D2 R - Command of Read Register N Read D - Data from Register N XX - Don’t care; undefined. Figure 23. Read Operation in Stand-Alone Mode Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 21 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 9 Detailed Description 9.1 Overview The AFE030 is an integrated powerline communication analog front-end (AFE) device built from a variety of functional blocks that work in conjunction with a microcontroller. The AFE030 provides the interface between the microcontroller and a line coupling circuit. The AFE030 delivers high performance and is designed to work with a minimum number of external components. Consisting of a variety of functional and configurable blocks, the AFE030 simplifies design efforts and reduces the time to market of many applications. The AFE030 includes three primary functional blocks: • Power Amplifier (PA) • Transmitter (Tx) • Receiver (Rx) The AFE030 also consists of other support circuitry blocks that provide zero crossing detection, an additional two-wire communications channel, and power-saving biasing blocks (see the Functional Block Diagram). All of these functional blocks are digitally controlled by the microcontroller through the serial interface (SPI). DVDD DGND AGND1 AVDD1 AGND2 AVDD2 E_Rx_OUT E_Rx_IN PA_OUT TSENSE PA_GND PA_VS PA_ISET ZC_IN1 ZC_IN2 REF2 ZC_OUT2 ZC_OUT1 REF1 9.2 Functional Block Diagram E_Tx_CLK ZC1 Bias E_Tx_IN ZC2 E_Tx_OUT Two-Wire Rx/Tx RxPGA_1 SCLK DI DO Digital Interface (SPI) Rx_PGA1_IN Power Amplifier CS Rx_PGA1_OUT Rx_F_IN DAC SD Tx_FLAG Rx_FLAG Rx_C1 Control Register Rx_C2 INT Rx Filter Rx_F_OUT RxPGA_2 Digital-to-Analog Converter TxPGA Tx Filter 22 Submit Documentation Feedback Rx_PGA2_IN Rx_PGA2_OUT Tx_F_OUT PA_IN Tx_F_IN2 TX_PGA_OUT Tx_F_IN1 Tx_PGA_IN Device Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 9.3 Feature Description 9.3.1 PA Block Figure 24 shows a typical powerline communications application system diagram. Table 2 is a complete list of the sections within the AFE030. C2000 MCU Device Line Coupling Interface DAC PGA PA + N1 LPF + N2 Phase Neutral Serial Interface Serial Interface Bandpass Filter PGA PGA LPF Figure 24. Typical Powerline Communications System Diagram Table 2. Block Descriptions BLOCK DESCRIPTION PA The PA block includes the power amplifier and associated pedestal biasing circuitry Tx The Tx block includes the Tx_Filter and the Tx_PGA Rx The Rx block includes the Rx PGA1, the Rx Filter, and the Rx PGA2 ERx The ER block includes the two-wire receiver ETx The ER block includes the two-wire transmitter DAC The DAC block includes a digital-to-analog converter ZC The ZC block includes both zero crossing detectors REF1 The REF1 block includes the internal bias generator for the PA block REF2 The REF2 block includes the internal bias generators for the Tx, Rx, ERx, and ETx blocks The power amplifier (PA) block consists of a high slew rate, high-voltage, and high-current operational amplifier. The PA is configured with an inverting gain of 6.5 V/V, has a low-pass filter response, and maintains excellent linearity and low distortion. The PA is specified to operate from 7 V to 26 V and can deliver up to ±1 A of continuous output current over the specified junction temperature range of –40°C to +125°C. Figure 25 illustrates the PA block. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 23 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com PA_VS1 PA_VS2 T_SENSE Inside the AFE030 PA_OUT1 Power Amplifier PA_IN PA_OUT2 PA_GND1 PA_GND1 PA_ISET Figure 25. PA Block Equivalent Circuit Connecting the PA in a typical PLC application requires only two additional components: an ac coupling capacitor, CIN, and the current limit programming resistor, RSET. Figure 26 shows the typical connections to the PA block. + PA Supply 47 mF 100 nF PA_VS1 PA_VS2 T_SENSE Inside the AFE030 PA_OUT1 CIN Power Amplifier PA_IN PA_OUT2 PA_GND1 PA_GND1 PA_ISET RSET Figure 26. Typical Connections to the PA The external capacitor, CIN, introduces a single-pole, high-pass characteristic to the PA transfer function; combined with the inherent low-pass transfer function, this characteristic results in a passband response. The value of the high-pass cutoff frequency is determined by CIN reacting with the input resistance of the PA circuit, and can be found from Equation 1: 1 CIN = (2 ´ p ´ 20 kW ´ fHP) (1) Where: 24 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com • • SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 CIN = external input capacitor fHP = desired high-pass cutoff frequency For example, setting CIN to 3.3 nF results in a high-pass cutoff frequency of 2.4 kHz. The voltage rating for CIN should be determined to withstand operation up to the PA power-supply voltage. When the transmitter is not in use, the output can be disabled and placed into a high-impedance state by writing a '0' to the PA-OUT bit in the Enable2 Register. Additional power savings can be realized by shutting down the PA when not in use. Shutting down the PA for power savings is accomplished by writing a '0' to the PA bit in the Enable1 Register. Shutting down the PA also results in the PA output entering a high-impedance state. When the PA shuts down, it consumes only 2 mW of power. The PA_ISET pin (pin 46) provides a resistor-programmable output current limit for the PA block. Equation 2 determines the value of the external RSET resistor attached to this pin. 1.2 V - 15 kW RSET = 20 k ´ ILIM (2) ( ( Where: • RSET = the value of the external resistor connected between pin 46 and ground. • ILIM = the value of the desired current limit for the PA. Note that to ensure proper design margin with respect to manufacturing and temperature variations, a 30% increase in the value used in Equation 2 for ILIM over the nominal value of ILIM is recommended. See Figure 16, PA Current Limit vs RSET. For maximum output current, PA_ISET (pin 46) may be connected directly to ground. 9.3.2 Tx Block The Tx block consists of the Tx PGA and Tx Filter. The Tx PGA is a low-noise, high-performance, programmable gain amplifier. In DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the Tx PGA operates as the internal digital-to-analog converter (DAC) output buffer with programmable gain. In PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the Tx PGA operates as a stand-alone programmable gain amplifier. The Tx PGA gain is programmed through the serial interface. The Tx PGA gain settings are 0.25 V/V, 0.5 V/V, 0.707 V/V, and 1 V/V. The Tx Filter is a unity-gain, fourth-order low-pass filter. The Tx Filter cutoff frequency is selectable between CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD) determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band; setting Control1 Register bit location 3 to '1' selects CENELEC B, C, and D bands. The AFE030 supports both DAC inputs or PWM inputs for the Tx signal path. DAC mode is recommended for best performance. In DAC mode, no external components in the Tx signal path are required to meet regulatory signal emissions requirements. When in DAC mode, the AFE030 accepts serial data from the microprocessor and writes that data to the internal DAC registers. When in DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the Tx PGA output must be directly coupled to the Tx_FIN1 input and the unused Tx_FIN2 input must be grounded. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 25 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com The proper connections for the Tx signal path for DAC mode operation are shown in Figure 27. Operating in DAC mode results in the lowest distortion signal injected onto the ac mains. No additional external filtering components are required to meet CENELEC requirements for A, B, C or D bands when operating in DAC mode. Inside the AFE030 MCU SCLK PA_OUT1 DIN DOUT SPI DAC PGA PA LPF PA_OUT2 CS Tx_PGA_ OUT Tx_F_ IN1 Tx_F_ IN2 Tx_F_ OUT PA_IN Tx_PGA_IN C C= 1 See Note 1 2 ´ p ´ f ´ 22 kW (1) For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance. Figure 27. Recommended Tx Signal Chain Connections Using DAC Mode In PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the microprocessor general-purpose input/output (GPIO) can be connected directly to either one of the Tx Filter inputs; the unused input should remain unconnected. A lower distortion PWM signal generated from two PWM signals shifted in phase by 90 degrees can be also be input to the Tx Filter through the use of both inputs. Figure 28 and Figure 29 show the proper connections for single PWM and dual PWM operating modes, respectively. Inside the AFE030 MCU Tx_F_IN1 PA_OUT1 GPIO Tx_F_IN2 PGA LPF PA PA_OUT2 See Note 1 Tx_F_OUT Tx_PGA_ Tx_PGA_ OUT IN PA_IN C C= 1 See Note 2 2 ´ p ´ f ´ 22 kW (1) Leave unused Tx Filter input unconnected. (2) For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance. Figure 28. Recommended Tx Signal Chain Connections in PWM Mode Using One PWM Signal 26 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 See Note 1 Inside the AFE030 MCU 43 kW Tx_F_IN1 PA_OUT1 GPIO PGA LPF Tx_F_IN2 PA GPIO PA_OUT2 43 kW Tx_F_OUT Tx_PGA_ Tx_PGA_ IN OUT PA_IN C C= 1 See Note 2 2 ´ p ´ f ´ 22 kW (1) When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response. (2) For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance. Figure 29. Recommended Tx Signal Chain Connections in PWM Mode Using Two PWM Signals In PWM mode, there is inherently more distortion from the PWM signal than from the internal DAC. To achieve the best results in PWM mode, add passive RC filters to increase the low-pass filtering. Figure 30 and Figure 31 illustrate the recommended locations of these RC filters. Inside the AFE030 MCU Tx_F_IN1 PA_OUT1 GPIO Tx_F_IN2 PGA LPF PA PA_OUT2 See Note 1 Tx_F_OUT 510 W Tx_PGA_ Tx_PGA_ IN OUT PA_IN 510 W C C C C= 1 2 ´ p ´ f ´ 22 kW See Note 3 See Note 2 (1) Leave unused Tx Filter input unconnected. (2) Refer to Table 3. (3) For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance. Figure 30. Recommended Tx Signal Chain Connections in PWM Mode Using One PWM Signal and Additional RC Filters Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 27 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com See Note 1 Inside the AFE030 MCU 43 kW Tx_F_IN1 PA_OUT1 GPIO Tx_F_IN2 PGA LPF PA GPIO PA_OUT2 43 kW Tx_F_OUT 510 W Tx_PGA_ Tx_PGA_ IN OUT PA_IN 510 W C C C C= 1 See Note 3 2 ´ p ´ f ´ 22 kW See Note 2 (1) When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response. (2) Refer to Table 3. (3) For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance. Figure 31. Recommended Tx Signal Chain Connections in PWM Mode Using Two PWM Signals and Additional RC Filters For the capacitors listed in Table 3, it is recommended that these components be rated to withstand the full AVDD power-supply voltage. Table 3. Recommended External R and C Values to Increase Tx Filter Response Order in PWM Applications FREQUENCY BAND R (Ω) C (nF) SFSK: 63 kHz, 74 kHz 510 2.7 CENELEC A 510 1.5 CENELEC B, C, D 510 1 The Tx PGA and Tx Filter each have the inputs and outputs externally available in order to provide maximum system design flexibility. Care should be taken when laying out the PCB traces from the inputs or outputs to avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or from the outputs to ground, less than 100 pF is recommended. 9.3.3 Rx Block The Rx block consists of Rx PGA1, the Rx Filter, and Rx PGA2. Both Rx PGA1 and Rx PGA2 are highperformance programmable gain amplifiers. Rx PGA1 can be configured through the SPI to operate as either an attenuator or in gain. The gain steps of the Rx PGA1 are 0.25 V/V, 0.5 V/V, 1 V/V, and 2 V/V. The gain steps of the Rx PGA2 are 1 V/V, 4 V/V, 16 V/V, and 64 V/V. Configuring the Rx PGA1 as an attenuator (at gains less than 1 V/V) is useful for applications where the presence of large interference signals are present within the signal band. Attenuating the large interference allows these signals to pass through the analog Rx signal chain without causing an overload; the interference signal can then be processed and removed within the microprocessor as necessary. The Rx Filter is a very low noise, unity-gain, fourth-order low-pass filter. The Rx Filter cutoff frequency is selectable between CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD) determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band; setting Control1 Register bit location 3 to '1' selects the CENELEC B, C, and D bands. Because the Rx Filter is a very low noise analog filter, two external capacitors are required to properly configure the Rx Filter. Table 4 shows the proper capacitance values for CENELEC A, B, C, and D bands. Capacitor Rx C1 is connected between pin 24 and ground, and Rx C2 is connected between pin 23 and ground. For the capacitors shown, it is recommended that these components be rated to withstand the full AVDD power-supply voltage 28 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Table 4. Recommended External Capacitors Required for Rx Filter FREQUENCY BAND Rx C1, PIN 24 Rx C2, PIN 23 CUTOFF FREQUENCY (kHz) CENELEC A 680 pF 680 pF 90 CENELEC B, C, D 270 pF 560 pF 145 Figure 32 illustrates the recommended connections for the Rx signal chain. Inside the AFE030 C1 330 W From Line-Coupling Circuit or Passive Bandpass Filter PGA LPF Rx_PGA1_ IN C1 = To ADC Input on MCU PGA Rx_PGA2_ OUT 1 2 ´ p ´ f ´ RIN,PGA1 See Note 1 Rx_C1 Rx_C2 Rx_F_ OUT Rx_F_IN Rx_PGA1_OUT Rx C1 PA_IN Rx C2 C2 = C2 1 2 ´ p ´ f ´ RIN,PGA2 See Note 2 See Note 3 (1) For capacitor value C1, f is the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1. (2) For capacitor value C2, f is the desired lower cutoff frequency and RIN,PGA2 is the input resistance of Rx PGA2. (3) Refer to Table 4. Figure 32. Recommended Connections for Rx Signal Chain As Figure 33 shows, a fourth-order passive passband filter is optional but recommended for applications where high performance is required. The external passive passband filter removes any unwanted, out-of-band signals from the signal path, and prevents them from reaching the active internal filters within the AFE030. From Line-Coupling Circuit C1 R1 C L1 To Rx PGA1 R2 C2 L2 C= 1 2 ´ p ´ f ´ RIN,PGA1 See Note 1 (1) For capacitor value C, f is the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1. Refer to Table 4. Figure 33. Passive Bandpass Rx Filter Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 29 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com The following steps can be used to quickly design the passive passband filter. (Note that these steps produce an approximate result.) 1. Choose the filter characteristic impedance, ZC: – For –6-db passband attenuation: R1 = R2 = ZC – For 0-db passband attenuation: R1 = ZC, R2 = 10 × ZC 2. Calculate values for C1, C2, L1, and L2 using the following equations: 1 C1 = (2 ´ p ´ f ´ Z ) 1 C 1 C2 = (2 ´ p ´ f ´ Z ) 2 C L1 = ZC (2 ´ p ´ f2) L2 = ZC (2 ´ p ´ f1) Table 5 and Table 6 shows standard values for common applications. Table 5. Recommended Component Values for Fourth-Order Passive Bandpass Filter (0-db Passband Attenuation) FREQUENCY RANGE (kHz) CHARACTERISTIC IMPEDANCE (Ω) R1 (Ω) R2 (Ω) C1 (nF) C2 (nF) L1 (μH) L2 (μH) CENELEC A 35 to 95 1k 1k 10k 4.7 1.5 1500 4700 CENELEC B, C, D 95 to 150 1k 1k 10k 1.7 1 1200 1500 SFSK 63 to 74 1k 1k 10k 2.7 2.2 2200 2200 FREQUENCY BAND Table 6. Recommended Component Values for Fourth-Order Passive Bandpass Filter (–6-db Passband Attenuation) FREQUENCY RANGE (kHz) CHARACTERISTIC IMPEDANCE (Ω) R1 (Ω) R2 (Ω) C1 (nF) C2 (nF) L1 (μH) L2 (μH) CENELEC A 35 to 95 1k 1k 1k 4.7 1.5 1500 4700 CENELEC B, C, D 95 to 150 1k 1k 1k 1.7 1 1200 1500 SFSK 63 to 74 1k 1k 1k 2.7 2.2 2200 2200 FREQUENCY BAND 30 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 The Rx PGA1, Rx Filter, and Rx PGA2 components have all inputs and outputs externally available to provide maximum system design flexibility. Care should be taken when laying out the PCB traces from the inputs or outputs to avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or outputs to ground, below 100 pF is recommended. Figure 34 shows the complete Rx signal path, including the optional passive passband filter. C1 = 1 2 ´ p ´ f ´ RIN,PGA1 Inside the AFE030 See Note 1 From Line-Coupling Circuit R2 C3 C1 L1 330 W PGA R3 C4 L2 LPF PGA Rx_PGA1_ IN Rx_PGA2_OUT Rx_C1 Rx_PGA1_OUT Rx_C2 Rx_F_ OUT Rx_F_IN Rx C1 To ADC Input on MCU PA_IN Rx C2 C2 C2 = 1 2 ´ p ´ f ´ RIN,PGA2 See Note 2 See Note 3 (1) For capacitor value C1,f is the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1. (2) For capacitor value C2,f is the desired lower cutoff frequency and RIN,PGA2 is the input resistance of Rx PGA2. (3) Refer to Table 4. Figure 34. Complete Rx Signal Path (with Optional Bandpass Filter) 9.3.4 DAC Block The DAC block consists only of the 10-bit DAC. The use of the DAC is recommended for best performance. The serial interface is used to write directly to the DAC registers when the DAC pin (pin 7) is driven high. Placing the DAC pin into a high state configures the SPI for direct serial interface to the DAC. Use the following sequence to write to the DAC: • Set CS low. • Set the DAC pin (pin 7) high. • Write a 10-bit word to DIN. The DAC register is left-justified and truncates more than 10 bits. • CS high updates the DAC. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 31 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Refer to Figure 35 for an illustration of this sequence. CS DAC DIN SCLK Time Figure 35. Writing to the DAC Register Table 7 lists the DAC Register configurations. Table 7. DAC Registers DAC PIN HIGH: DAC REGISTER 32 BIT NAME LOCATION (0 = LSB) DEFAULT R/W FUNCTION DAC 0 — W Truncated DAC 1 — W Truncated DAC 2 — W Truncated DAC 3 — W Truncated DAC 4 — W Truncated DAC 5 — W Truncated DAC 6 — W DAC bit 0 = DAC LSB DAC 7 — W DAC bit 1 DAC 8 — W DAC bit 2 DAC 9 — W DAC bit 3 DAC 10 — W DAC bit 4 DAC 11 — W DAC bit 5 DAC 12 — W DAC bit 6 DAC 13 — W DAC bit 7 DAC 14 — W DAC bit 8 DAC 15 — W DAC bit 9 = DAC MSB Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 9.3.5 REF1 and REF2 Blocks The REF1 and REF2 blocks create midscale power-supply biasing points used internally to the AFE030. Each reference divides its respective power-supply voltage in half with a precision resistive voltage divider. REF1 provides a PA_VS/2 voltage at the output of the PA, while REF2 provides an AVDD/2 voltage at the outputs of the Tx PGA, Tx Filter, Rx PGA1, Rx Filter, and Rx PGA2. Each REF block has its output brought out to an external pin that can be used for filtering and noise reduction. Figure 36 and Figure 37 show the proper connections of the external noise-reducing capacitors. These capacitors are optional, but are recommended for best performance. PA_VS Inside the AFE030 R 4 kW REF1 R Internal PA_VS Bias 2 External 1-mF Noise Reduction Capacitor PA_GND Figure 36. REF1 Functional Diagram AVDD Inside the AFE030 R 4 kW REF2 R Internal AVDD Bias 2 External 1-nF Noise Reduction Capacitor AGND Figure 37. REF2 Functional Diagram Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 33 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 9.3.6 Zero Crossing Detector Block The AFE030 includes two zero crossing detectors. Zero crossing detectors can be used to synchronize communications signals to the ac line or sources of noise. Typically, in single-phase applications, only a single zero crossing detector is used. In three-phase applications, both zero crossing detectors can be used; one component detects phase A, and one detects phase B. Phase C zero crossings can then be inferred from the data gathered from the other phases. Figure 38 shows the AFE030 configured for non-isolated zero crossing detection. + AVDD 3.3 V ZLLS410 or Equivalent 330 kW 330 kW 120 VAC to 240 VAC 50/60 Hz AVDD 330 kW ZCIN ZCOUT Zero Crossing ZLLS410 or Equivalent AGND Inside the AFE030 Figure 38. Non-Isolated Zero Crossing Detection Using the AFE030 120 VAC to 240 VAC 50 Hz to 60 Hz Non-isolated zero crossing waveforms are shown in Figure 39. 350 0 -350 ZCOUT 3.3 0.0 0 50 100 Time (5 ms/div) Figure 39. Non-Isolated Zero Crossing Waveforms 34 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 For maximum protection of the AFE030 against line transients, it is recommended to use Schottky diodes as indicated in Figure 38. These diodes should limit the ZC_IN pins (pins 38 and 39) to within the maximum rating of (AVDD + 0.4 V) and (AGND – 0.4 V). Some applications may require an isolated zero crossing detection circuit. With a minimal amount of components, the AFE030 can be configured for isolated zero crossing detection, as Figure 40 shows. + AVDD 3.3 V AVDD ZCIN ZCOUT Zero Crossing 120 VAC to 240 VAC 50/60 Hz AGND Inside the AFE030 PS2505-1A Opto Isolator or Equivalent Figure 40. Isolated Zero Crossing Detection Using the AFE030 120 VAC to 240 VAC 50 Hz to 60 Hz Isolated zero crossing waveforms are shown in Figure 41. 350 0 -350 ZCOUT 3.3 0.0 0 50 100 Time (5 ms/div) Figure 41. Isolated Zero Crossing Waveforms Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 35 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 9.3.7 ETx and ERx Blocks The AFE030 contains a two-wire transmitter block, ETx, and a two-wire receiver block, ERx. These blocks support communications that use amplitude shift keying (ASK) with on-off keying (OOK) modulation. The ETx block is a gated driver that allows for transmission of a carrier input signal and modulating input signal. For typical applications, a 50-kHz square wave carrier signal is applied to E_Tx_Clk while the modulating signal is applied to E_Tx_In. The output (E_Tx_Out) is then in a high-impedance state when E_Tx_In is '1'. Figure 42 shows the relationship between E_Tx_Clk, E_Tx_In, and E_Tx_Out. 3.3 E_Tx_Clk 0 3.3 E_Tx_In 0 3.3 E_Tx_Out 0 Time (s) Figure 42. ETx Block Transfer Function The ERx Block consists of a low-pass analog filter configured in an inverting gain of –4.5 db. This block, along with an external capacitor, can be used to create a passband filter response as shown in Figure 43. Gain (dB) 0 -20 High-pass cutoff determined by: fHP = 1 2p·RIN·CEXT where: RIN = Input resistance of ERx = 78 kW CEXT = External capacitance -40 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 43. ERx Block Frequency Response 36 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 The E_Rx_Out pin can be directly connected to either an available analog-to-digital converter (ADC) input or GPIO on the host microcontroller. Figure 44 illustrates a typical two-wire application for ETx and ERx. Device Internal Configuration E_Tx_In TMS320F28x E_Tx_Out GPIO Flexible PLC Software Engine CEXT E_Rx_In E_Tx_CLK GPIO + N1 + N2 Two-Wire Bus E_Rx_Out GND GPIO Figure 44. Typical Two-Wire Application for ETx and ERx Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 37 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 9.4 Power Supplies The AFE030 has two low-voltage analog power-supply pins and one low-voltage digital supply pin. Internally, the two analog supply pins are connected to each other through back-to-back electrostatic discharge (ESD) protection diodes. These pins must be connected to each other on the application printed circuit board (PCB). It is also recommended to connect the digital supply pin and the two analog supply pins together on the PCB. Both low-voltage analog ground pins are also connected internally through back-to-back ESD protection diodes. These ground pins should also be connected to the digital ground pin on the PCB. It is recommended to bypass the low-voltage power supplies with a parallel combination of a 10-μf and 100-nf capacitor. The PA block is biased separately from a high-voltage, high-current supply. Two PA power supply pins and two PA ground pins are available to provide a path for the high currents associated with driving the low impedance of the ac mains. Connecting the two PA supply pins together as close as possible to the AFE030 is recommended. It is also recommended to place a bypass capacitor of 47 μF to 100 μF in parallel with 100 nF as close as possible to the AFE030. Care must be taken when routing the high current ground lines on the PCB to avoid creating voltage drops in the PCB ground that may vary with changes in load current. The AFE030 has many options to enable or disable the functional blocks to allow for flexible power-savings modes. Table 8 shows the specific power supply that each functional block draws power from, as well as the typical amount of power drawn from the associated power supplies for both the enabled and disabled states. For additional information on power-supply requirements refer to Application Report Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031, literature number SBOA130 (available for download at www.ti.com). Table 8. Power Consumption with Enable and Disable Times (Typical) BLOCK PA Tx Rx ERx ETx DAC ZC REF1 REF2 38 DISABLE TIME AVDD SUPPLY CURRENT DVDD SUPPLY CURRENT PA SUPPLY CURRENT 10 μs — — — 40 mA — 10 μs — — 70 μA 10 μs — 3.7 mA — — Off — 10 μs 1 μA — — On 10 μs — 5.3 mA — — Off — 10 μs 1 μA — — On 10 μs — 900 μA — — Off — 10 μs 1 μA — — On 10 μs — 1.2 mA — — Off — 10 μs 1 μA — — On 10 μs — — 16 μA — Off — 10 μs — 1 μA — On 10 μs — 25 μA — — Off — 10 μs 1 μA — — On 10 μs — — — 26 μA Off — 10 μs — — 8 μA On 10 μs — 25 μA — — Off — 10 μs 4 μA — — STATUS ENABLE TIME On Off On Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 9.5 Pin Descriptions DAC (Pin 7) The DAC pin is used to configure the SPI to either read or write data to the Command and Data Registers, or to write data to the DAC registers. Setting the DAC pin high allows access to the DAC registers. Setting the DAC pin low allows access to the Command and Data Registers. SD (Pin 8) The Shutdown pin (SD) can be used to shut down the entire AFE030 for maximum power savings. When the SD pin is low, normal operation of the AFE030 occurs. When the SD pin is high, all circuit blocks within the AFE030, including the serial interface, are placed into the lowest-power operating modes. In this condition, the entire AFE030 draws only 95 μA of current. All register contents at the time the AFE030 is placed into shutdown mode are saved; upon re-enabling the AFE030, the register contents retain the respective saved values. INT (Pin 9) The Interrupt pin (INT) can be used to signal the microprocessor of an unusual operating condition that results from an anomaly on the ac mains. The INTpin can be triggered by two external circuit conditions, depending upon the Enable Register settings. The AFE030 can be programmed to issue an interrupt on these conditions: • Current overload • Thermal overload 9.5.1 Current Overload The maximum output current allowed from the Power Amplifier can be programmed with the external RSET resistor connected between PA_ISET (pin 46) and ground. If a fault condition should occur and cause an overcurrent event for the PA, the PA goes into current limit and the I_FLAG bit (location 6 in the RESET Register) is set to a '1' if the I_Flag_EN bit (location 6 in the Control2 Register) is enabled. This configuration results in an interrupt signal at the INT pin. The I_FLAG bit remains set to '1' even after the device returns to normal operation. The I_FLAG bit remains at '1' until it is reset by the microprocessor. If the I_FLAG_EN bit (location 6 in the Control2 Register) is disabled and a current overload condition occurs, the PA goes into current-limit mode to protect the AFE030; however, the contents of the I_FLAG bit (location 6 in the RESET Register) remain at the respective previous values (presumably '0' for normal operation), and the AFE030 does not issue an interrupt at the INT pin. 9.5.2 Thermal Overload The AFE030 contains internal protection circuitry that automatically disables the PA output stage if the junction temperature exceeds +165°C. If a fault condition occurs that causes a thermal overload, and if the T_FLAG_EN bit (location 5 in the Control2 Register) is enabled, the T_FLAG bit (location 5 in the RESET Register) is set to a '1'. This configuration results in an interrupt signal at the INT pin. The AFE030 includes a thermal hysteresis and allows the PA to resume normal operation when the junction temperature reduces to 145°C. The T_FLAG bit remains set to a '1' even after the device returns to normal operation. The T_FLAG bit remains '1' until it is reset by the microprocessor. If the T_FLAG_EN bit (location 5 in the Control2 Register) is disabled and a thermal overload condition occurs, the PA continues to go into thermal limit and protect the AFE030, but the contents of the T_FLAG bit (location 5 in the RESET Register) remain at the previous value (presumably '0' for normal operation), and the AFE030 does not issue an interrupt at the INT pin. Once an interrupt is signaled (that is, INT goes low), the contents of the I_FLAG and T_FLAG bits can be read by the microprocessor to determine the type of interrupt that occurred. Using the Control2 Register, each interrupt type (current or thermal) can be individually enabled or disabled, allowing full user customization of the INT function. For proper operation of the interrupt pin it is recommended to configure the interrupt enable registers in the Control2 Register by writing to bit locations 5, 6, and 7 following the information in Table 9 after each time the AFE030 is powered on. Failure to properly configure bit locations 5, 6, and 7 after power on may result in unexpected interrupt signals. Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 39 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Pin Descriptions (continued) Table 9 lists the register contents associated with each interrupt condition. Table 9. Register Contents to Configure the Interrupt Pin CONTROL2 REGISTER CONTENTS: DETERMINE INTERRUPT PIN FUNCTIONALITY I_FLAG_EN (CURRENT OVERLOAD) T_FLAG_EN (THERMAL OVERLOAD) FUNCTION D7 D6 D5 POR (default values) undefined 0 0 No interrupt 0 0 0 Interrupt on thermal overload only 0 0 1 Interrupt on current overload only 0 1 0 Interrupt on thermal or current overload 0 1 1 TSENSE Pin (10) The TSENSE pin is internally connected to the anode of a temperature-sensing diode located within the PA output stage. Figure 45 shows a remote junction temperature sensor circuit that can be used to measure the junction temperature of the AFE030. Measuring the junction temperature of the AFE030 is optional and not required. +3.3 V 0.1 mF 1 Device V+ SCL 50 W 2 TSENSE 50 pF 3 D+ 10 kW (typ) 10 kW (typ) 10 kW (typ) 10 kW (typ) 8 TMP411 SDA 7 SMBus Controller DALERT/THERM2 THERM 6 4 Over-Temperature Fault GND 5 Figure 45. Interfacing the TMP411 to the AFE030 Tx_FLAG (Pin 47) The Tx_FLAG pin is an open drain output that indicates the readiness of the Tx signal path for transmission. When the Tx_FLAG pin is high, the transmit signal path is enabled and ready for transmission. When the Tx_FLAG pin is low, the transmit path is not ready for transmission. Rx_FLAG (Pin 48) The Rx_FLAG pin is an open drain output that indicates the readiness of the Rx signal path for transmission. When the Rx_FLAG pin is high, the transmit signal path is enabled and ready for transmission. When the Rx_FLAG pin is low, the transmit path is not ready for transmission. 40 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 9.6 Calibration Modes The AFE030 can be configured for two different calibration modes: Tx Calibration and Rx Calibration. Calibration values can be determined during the calibration process and stored in system memory. A one-time calibration can be performed the first time that the system powers on; this calibration remains valid over the full temperature range and operating life of the AFE030, independent of the number of power-on/power-off cycles, as long as the calibration factors remain in the system memory. Calibration mode is accessed through the Control1 Register. Note that calibration is not required. 9.6.1 Tx Calibration Mode The Tx PGA + Tx Filter ac gain can be calibrated in Tx Calibration Mode. Figure 46 shows the signal path during Tx Calibration mode. C2000 MCU AFE030 Line-Coupling Interface DAC PGA PA LPF SPI SPI PGA PGA LPF Figure 46. Tx Calibration Mode Configuration 9.6.2 Rx Calibration Mode The Tx PGA + Rx PGA1 + Rx Filter + Rx PGA2 ac gain can be calibrated in Rx Calibration mode. Figure 47 shows the signal path during Rx Calibration mode. C2000 MCU Device DAC Line-Coupling Interface PGA PA LPF SPI SPI PGA PGA LPF Figure 47. Rx Calibration Mode Configuration Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 41 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 9.7 Serial Interface The AFE030 is controlled through a serial interface that allows read/write access to the control and data registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid host SPI communications protocol. Table 10 through Table 19 show the complete register information. Table 10. Data Register ADDRESS DEFAULT ENABLE1 REGISTER 01h 00h Block enable or disable FUNCTION GAIN SELECT 02h 32h Rx and Tx gain select ENABLE2 03h 00h Block enable or disable CONTROL1 04h 00h Frequency select and calibration, Tx and Rx status CONTROL2 05h 01h Interrupt enable RESET 09h 00h Interrupt status and device reset DIE_ID 0Ah 01h Die name REVISION 0Bh 02h Die revision Table 11. Command Register LOCATION (15 = MSB) R/W 8 W Register address bit ADDR9 9 W Register address bit ADDR10 10 W Register address bit ADDR11 11 W Register address bit ADDR12 12 W Register address bit ADDR13 13 W Register address bit ADDR14 14 W Register address bit R/W 15 W Read/write: read = 1, write = 0 BIT NAME ADDR8 FUNCTION Table 12. Enable1 Register: Address 00h Default: 00h Enable1 Register BIT NAME LOCATION (0 = LSB) DEFAULT R/W FUNCTION PA 0 0 R/W This bit is used to enable/disable the PA block. 0 = Disabled 1 = Enabled TX 1 0 R/W This bit is used to enable/disable the Tx block. 0 = Disabled 1 = Enabled RX 2 0 R/W This bit is used to enable/disable the Rx block. 0 = Disabled 1 = Enabled ERX 3 0 R/W This bit is used to enable/disable the ERx block. 0 = Disabled 1 = Enabled ETX 4 0 R/W This bit is used to enable/disable the ETx block. 0 = Disabled 1 = Enabled DAC 5 0 R/W This bit is used to enable/disable the DAC block. 0 = DAC disabled; switch is connected to Tx_PGA_IN pin. 1 = DAC enabled; switch is connected to DAC output. — 6 0 — Reserved — 7 0 — Reserved 42 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Table 13. Gain Select Register: Address 02h Default: 32h Gain Select Register BIT NAME RX1G-0, RX1G-1 RX2G-0, RX2G-1 TXG-0, TXG-1 LOCATION (0 = LSB) 0, 1 2, 3 DEFAULT 0, 1 0, 0 R/W FUNCTION R/W This bit is used to set the gain of the Rx PGA1. 00 = 0.25 V/V 01 = 0.5 V/V 10 = 1 V/V 11 = 2 V/V R/W This bit is used to set the gain of the Rx PGA2. 00 = 1 V/V 01 = 4 V/V 10 = 16 V/V 11 = 64 V/V This bit is used to set the gain of the Tx PGA. 00 = 0.25 V/V 01 = 0.5 V/V 10 = 0.707 V/V 11 = 1 V/V 4, 5 1, 1 R/W — 6 0 — Reserved — 7 0 — Reserved Table 14. Enable2 Register: Address 03h Default: 00h Enable2 Register BIT NAME LOCATION (0 = LSB) DEFAULT R/W FUNCTION ZC 0 0 R/W This bit is used to enable/disable the ZC block. 0 = Disabled 1 = Enabled REF1 1 0 R/W This bit is used to enable/disable the REF1 block. 0 = Disabled 1 = Enabled REF2 2 0 R/W This bit is used to enable/disable the REF2 block. 0 = Disabled 1 = Enabled This bit is used to enable/disable the PA output stage. When the PA output stage is enabled it functions normally with a low output impedance, capable of driving heavy loads. When the PA output stage is disabled it is placed into a high impedance state. 0 = Disabled 1 = Enabled PA_OUT 3 0 R/W — 4 0 — Reserved — 5 0 — Reserved — 6 0 — Reserved — 7 0 — Reserved Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 43 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Table 15. Control1 Register: Address 04h Default: 00h Control1 Register BIT NAME LOCATION (0 = LSB) DEFAULT R/W FUNCTION TX_CAL 0 0 R/W This bit is used to enable/disable the TX calibration mode. 0 = Disabled 1 = Enabled RX_CAL 1 0 R/W This bit is used to enable/disable the RX calibration mode. 0 = Disabled 1 = Enabled — 2 0 — CA_CBCD Reserved This bit is used to select the frequency response of the Tx filter and Rx filter. 0 = CENELEC A 1 = CENELEC B, C, D 3 0 R/W — 4 0 — Reserved — 5 0 — Reserved TX_FLAG 6 0 R This bit is used to indicate the status of the Tx block. 0 = Tx block is not ready for transmission 1 = Tx block is ready for transmission RX_FLAG 7 0 R This bit is used to indicate the status of the Rx block. 0 = Rx block is not ready for reception 1 = Rx block is ready for reception Table 16. Control2 Register: Address 05h Default: 01h Control2 Register BIT NAME LOCATION (0 = LSB) DEFAULT R/W — 0 0 — Reserved — 1 0 — Reserved — 2 0 — Reserved — 3 0 — Reserved — 4 0 — Reserved T_FLAG_EN I_FLAG_EN — 44 5 0 FUNCTION R/W This bit is used to enable/disable the T_flag bit in the RESET Register. 0 = Disabled 1 = Enabled This bit is used to enable/disable the I_flag bit in the RESET Register. 0 = Disabled 1 = Enabled 6 0 R/W 7 X — Reserved Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Table 17. RESET Register: Address 09h Default: 00h Reset Register BIT NAME LOCATION (0 = LSB) DEFAULT R/W -- 0 0 -- Reserved -- 1 0 -- Reserved 2, 3, 4 0, 0, 0 W These bits are used to perform a software reset of the ENABLE1, ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT registers. Writing '101' to these registers performs a software reset. R/W This bit is used to indicate the status of a PA thermal overload. 0 = On read, indicates that no thermal overload has occurred since the last reset. 0 = On write, resets this bit. 1 = On read, indicates that a thermal overload has occurred since the last reset. Remains latched until reset. This bit is used to indicate the status of a PA output current overload. 0 = On read indicates that no current overload has occurred since the last reset. 0 = On write, resets this bit. 1 = On read indicates that a current overload has occurred since the last reset. Remains latched until reset. SOFTRST0, SOFTRST1, SOFTRST2 T_FLAG 5 I_FLAG — 0 6 0 R/W 7 0 — FUNCTION Reserved Table 18. DieID Register: Address 0Ah Default: 01h DieID Register BIT NAME LOCATION (0 = LSB) DEFAULT R/W DIE ID 0 1 R The DieID Register is hard-wired. DIE ID 1 0 R The DieID Register is hard-wired. DIE ID 2 0 R The DieID Register is hard-wired. DIE ID 3 0 R The DieID Register is hard-wired. DIE ID 4 0 R The DieID Register is hard-wired. DIE ID 5 0 R The DieID Register is hard-wired. DIE ID 6 0 R The DieID Register is hard-wired. DIE ID 7 0 R The DieID Register is hard-wired. FUNCTION Table 19. Revision Register: Address 0Bh Default: 02h Revision Register BIT NAME LOCATION (0 = LSB) DEFAULT R/W REVISION ID 0 0 R The Revision Register is hard-wired. REVISION ID 1 1 R The Revision Register is hard-wired. REVISION ID 2 0 R The Revision Register is hard-wired. REVISION ID 3 0 R The Revision Register is hard-wired. REVISION ID 4 0 R The Revision Register is hard-wired. REVISION ID 5 0 R The Revision Register is hard-wired. REVISION ID 6 0 R The Revision Register is hard-wired. REVISION ID 7 0 R The Revision Register is hard-wired. FUNCTION Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 45 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The AFE030 is an integrated powerline communication analog front-end (AFE) device built from a variety of functional blocks that work in conjunction with a microcontroller. The AFE030 provides the interface between the microcontroller and a line coupling circuit. The AFE030 delivers high performance and is designed to work with a minimum number of external components. Consisting of a variety of functional and configurable blocks, the AFE030 simplifies design efforts and reduces the time to market of many applications. 10.2 Typical Application Figure 48 shows the AFE030 configured in a typical PLC analog front-end application. The schematic shows the connections to the microprocessor and ac line. The values of the passive components in Figure 48 are suitable for a single-phase powerline communications application in the CENELEC A band, connected to a 120-VAC or 240-VAC, 50-Hz or 60-Hz ac line. 46 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 +15 V C5 C13 C15 C14 10 mF 10 mF 3.3 V C16 10 mF 10 mF D1 100 nF C6 10 mF D2 R1 R2 33 kW 1.5:1 Coilcraft DA2302-AL 33 kW D3 GPIO + N1 R12 4.7 W 38 L2 15 mH Phase + N2 Neutral D4 TVS C17 10 nF 37 40 39 41 43 42 44 46 3.3 V 45 R6 through R9 48 3.3 V TMS320F28x 47 GPIO C18 470 nF 10 kW each C3 10 mF Flexible PLC Software Engine R3 33 kW SPI 35 3 34 5 SPI SPI DAC Registers SPI GPIO Two-Wire Support Circuitry DAC 6 GPIO R4 10 kW C7 3.3 V Rx LPF 31 30 29 Rx PGA1 Power Amplifier 11 10 kW 32 8 10 R5 Tx Filter Tx PGA 12 C19 4.7 nF 33 Tx 7 9 GPIO 36 2 4 SPI Line Coupling Circuit Zero Crossing 1 3.3 V C12 1 mF 28 L3 1.5 mH R13 1 kW 25 kHz to 95 kHz Fourth-Order Passive Passband Filter 27 26 Rx Filter Rx PGA2 LPF 25 C11 L4 10 nF 4.7 mH C20 1.5 nF R14 1 kW LPF ADC IN C8 3.3 nF 23 C9 1 nF C10 Test Point 24 22 21 20 19 18 17 15 16 13 C4 10 mF 14 10 nF 10 nF C2 C1 See Note 1 R11 330 W (1) Recommended values for C1 and C2: 1. 2. C1: – CENELEC A: 680 pF – CENELEC B, C, D: 270 pF C2: – CENELEC A: 680 pF – CENELEC B, C, D: 560 pF Figure 48. Typical Powerline Communications Modem Application Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 47 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com 10.3 Line-Coupling Circuit The line-coupling circuit is one of the most critical circuits in a powerline modem. The line-coupling circuit has two primary functions: first, to block the low-frequency signal of the mains (commonly 50 Hz or 60 Hz) from damaging the low-voltage modem circuitry; second, to couple the modem signal to and from the ac mains. A typical line-coupling circuit is shown in Figure 49. Power Amplifier Low-Voltage Capacitor High-Voltage Capacitor + N1 L Phase + N2 Neutral Copyright © 2017, Texas Instruments Incorporated Figure 49. Simplified Line Coupling Circuit For additional information on line-coupling interfaces with the AFE030, refer to Application Report SBOA130 Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031 (available for download at www.ti.com). 10.4 Circuit Protection Powerline communications are often located in operating environments that are harsh for electrical components connected to the ac line. Noise or surges from electrical anomalies such as lightning, capacitor bank switching, inductive switching, or other grid fault conditions can damage high-performance integrated circuits if they are not properly protected. The AFE030 can survive even the harshest conditions if several recommendations are followed. First, dissipate as much of the electrical disturbance before it reaches the AFE030 with a multi-layer approach using metal-oxide varistors (MOVs), transient voltage suppression diodes (TVSs), Schottky diodes, and a Zener diode. Figure 50 shows the recommended strategy for transient overvoltage protection. PA Power Supply D1 Device D2 Low-Voltage Capacitor High-Voltage Capacitor Phase + N1 + N2 MOV D3 Power Amplifier Neutral TVS Figure 50. Transient Overvoltage Protection for AFE030 Note that the high-voltage coupling capacitor must be able to withstand pulses up to the clamping protection provided by the MOV. A metalized polypropylene capacitor, such as the 474MKP275KA from Illinois Capacitor, Inc., is rated for 50 Hz to 60 Hz, 250 VAC to 310 VAC, and can withstand 24 impulses of 2.5 kV. 48 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Circuit Protection (continued) Table 20 lists several recommended transient protection components. Table 20. Recommended Transient Protection Devices 120 VAC, 60 Hz COMPONENT DESCRIPTION MANUFACTURER MFR PART NO (OR EQUIVALENT) D1 Zener diode Diodes, Inc. 1SMB59xxB (1) D2, D3 Schottky diode Diodes, Inc. 1N5819HW TVS Transient voltage suppressor Diodec Semiconductor P6SMBJxxC (2) MOV Varistor LittleFuse TMOV20RP140E HV Cap High-voltage capacitor Illinois Capacitor, Inc 474MKP275KA (3) COMPONENT DESCRIPTION MANUFACTURER MFR PART NO (OR EQUIVALENT) D1 Zener diode Diodes, Inc. 1SMB59xxB (1) D2, D3 Schottky diode Diodes, Inc. 1N5819HW TVS Transient voltage suppressor Diodec Semiconductor P6SMBJxxC (2) 240 VAC, 50 Hz (1) (2) (3) MOV Varistor LittleFuse TMOV20RP300E HV Cap High-voltage capacitor Illinois Capacitor, Inc 474MKP275KA (3) Select the Zener breakdown voltage at the lowest available rating beyond the normal power-supply operating range. Select the TVS breakdown voltage at or slightly greater than (0.5 × PA_VS). A common value for the high-voltage capacitor is 470 nF. Other values may be substituted depending on the requirements of the application. Note that when making a substitution, it is important in terms of reliability that the capacitor be selected from the same familiy or equivalent family of capacitors rated to withstand high-voltage surges. 10.5 Thermal Considerations In a typical powerline communications application, the AFE030 dissipates 1 W of power when transmitting into the low impedance of the ac line. This amount of power dissipation can increase the junction temperature, which in turn can lead to a thermal overload that results in signal transmission interruptions if the proper thermal design of the PCB has not been performed. Proper management of heat flow from the AFE030 as well as good PCB design and construction are required to ensure proper device temperature, maximize performance, and extend device operating life. The AFE030 is assembled into a 7-mm2 x 7-mm2, 48-lead, QFN package. As Figure 51 shows, this QFN package has a large area exposed thermal pad on the underside that is used to conduct heat away from the AFE030 and into the underlying PCB. Figure 51. QFN Package with Large Area Exposed Thermal Pad Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 49 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Thermal Considerations (continued) Some heat is conducted from the silicon die surface through the plastic packaging material and is transferred into the ambient environment. Because plastic is a relatively poor conductor of heat, however, this route is not the primary thermal path for heat flow. Heat also flows across the silicon die surface to the bond pads, through the wire bonds, into the package leads, and finally into the top layer of the PCB. While both of these paths for heat flow are important, the majority (nearly 80%) of the heat flows downward, through the silicon die, into the thermally-conductive die attach epoxy, and into the exposed thermal pad on the underside of the package (as shown in Figure 52). Minimizing the thermal resistance of this downward path to the ambient environment maximizes the life and performance of the device. Less than 1% ~20% ~20% ~80% Figure 52. Heat Flow in the QFN Package The exposed thermal pad must be soldered to the PCB thermal pad. The thermal pad on the PCB should be the same size as the exposed thermal pad on the underside of the QFN package. Refer to Application Report, QFN/SON PCB Attachment, literature number SLUA271A, for recommendations on attaching the thermal pad to the PCB. Figure 53 illustrates the direction of heat spreading into the PCB from the device. AFE030 Figure 53. Heat Spreading into PCB 50 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 Thermal Considerations (continued) The heat spreading into the PCB is maximized if the thermal path is uninterrupted. Best results are achieved if the heat-spreading surfaces are filled with copper to the greatest extent possible, maximizing the percent area covered on each layer. As an example, a thermally robust, multilayer PCB design may consist of four layers with copper (Cu) coverage of 60% in the top layer, 85% and 90% in the inner layers, respectively, and 95% on the bottom layer. Increasing the number of layers in the PCB, using thicker copper, and increasing the PCB area are all factors that improve the spread of heat. Figure 54 through Figure 56, respectively, show thermal resistance performance as a function of each of these factors. THERMAL RESISTANCE vs NUMBER OF PCB LAYERS 36 2 PCB Area = 3 in , 2 oz Cu (Results are from thermal simulations) Thermal Resistance (°C/W) 34 32 30 28 26 24 22 20 1 2 4 3 5 6 7 8 Number of Layers Figure 54. Thermal Resistance as a Function of the Number of Layers in the PCB THERMAL RESISTANCE vs BOARD AREA 28 Four-Layer PCB, 2 oz Cu (Results are from thermal simulations) Thermal Resistance (°C/W) 26 24 22 20 18 16 14 12 10 2 4 6 8 10 12 14 2 PCB Area (in ) Figure 55. Thermal Resistance as a Function of PCB Area Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 51 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Thermal Considerations (continued) 35 Four-Layer PCB, PCB 2 Area = 4.32 in , 2 oz Cu (Results are from thermal simulations) Thermal Resistance (°C/W) 33 31 29 27 25 23 21 19 17 15 0.5 1 1.5 2 2.5 Cu Thickness (oz) Figure 56. Thermal Resistance as a Function of Copper Thickness For additional information on thermal PCB design using exposed thermal pad packages, refer to Application Report SBOA130, Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031 and Application Report SLMA002E, PowerPAD™ Thermally-Enhanced Package (both available for download at www.ti.com). 52 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 AFE030 www.ti.com SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.2 TI Precision Designs TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. 11.1.1.3 WEBENCH® Filter Designer WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes. 11.1.2 Powerline Communications Developer’s Kit A PLC developer’s kit (TMDSPLCKIT-V3) is available to order at www.ti.com/plc. This kit offers complete hardware and software solutions for introducing flexible, efficient, and reliable networking capabilities to a wide variety of applications. With unique modular hardware architecture and flexible software framework, TI’s PLC solutions are the only PLC-based technology capable of supporting multiple protocol standards and modulation schemes with a single platform. This technology enables designers to leverage product lines across global markets. The flexibility of the platform also allows developers to optimize hardware and software performance for specific environmental operating conditions while simplifying end-to-end product design. Based on TI’s powerful C2000™ microcontroller architecture and the AFE031, developers can select the correct blend of processing capacity and peripherals to either add powerline communications to an existing design or implement a complete application with PLC communications. The C2000 Powerline Modem Developer's Kit enables easy development of software-based PLC modems. The kit includes two PLC modems based on the C2000 TMS320F28069 controlCARD and the AFE031. The included PLC SUITE software supports several communication techniques, including OFDM (PRIME/G3 and FlexOFDM) and SFSK. The kit also includes onboard USB JTAG emulation and Code Composer Studio. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following application reports and publications (available for download from www.ti.com): Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 53 AFE030 SBOS588B – DECEMBER 2011 – REVISED JUNE 2019 www.ti.com Documentation Support (continued) • • • TINA Simulation Schematic of a Two-Node, Power-Line Communication System (SBOU133) Microcontrollers in Data Concentrators (SLAT142) The Signal e-book: A compendium of blog posts on op amp design topics (SLYT701) 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks PowerPAD, TINA-TI, C2000, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. TINA, DesignSoft are trademarks of DesignSoft, Inc. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 54 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: AFE030 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) AFE030AIRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AFE030AI AFE030AIRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AFE030AI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of