AFE4404YZPT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 AFE4404 Ultra-Small, Integrated AFE for Wearable, Optical, Heart-Rate Monitoring and Bio-Sensing 1 Features 2 Applications • • • • • • 1 • • • • • • • • Transmitter: – Supports Common Anode LED Configuration – Dynamic Range: 100 dB – 6-Bit Programmable LED Current to 50 mA (Extendable to 100 mA) – Programmable LED On-Time – Simultaneous Support of 3 LEDs for Optimized SpO2, HRM, or Multi-Wavelength HRM Receiver: – 24-Bit Representation of the Current Input from a Photodiode in Twos Complement Format – Individual DC Offset Subtraction DAC at TIA Input for Each LED and Ambient Phase – Digital Ambient Subtraction at ADC Output – Programmable Transimpedance Gain: 10 kΩ to 2 MΩ – Dynamic Range: 100 dB – Average Current Less Than 200 μA for PPG Signal Acquisition Pulse Frequency: 10 SPS to 1000 SPS Flexible Pulse Sequencing and Timing Control Flexible Clock Options: – External Clocking: 4-MHz to 60-MHz Input Clock – Internal Clocking: 4-MHz Oscillator I2C Interface Operating Temperature Range: –20°C to 70°C 2.6-mm × 1.6-mm DSBGA Package, 0.5-mm Pitch Supplies: Rx: 2 V to 3.6 V, Tx: 3 V to 5.25 V, IO: 1.8 V to 3.6 V Optical Heart-Rate Monitoring (HRM) Heart-Rate Variability (HRV) Pulse Oximetry (SpO2 Measurement) VO2 Max Calorie Expenditure 3 Description The AFE4404 is an analog front-end (AFE) for optical bio-sensing applications, such as heart-rate monitoring (HRM) and saturation of peripheral capillary oxygen (SpO2). The device supports three switching light-emitting diodes (LEDs) and a single photodiode. The current from the photodiode is converted into voltage by the transimpedance amplifier (TIA) and digitized using an analog-to-digital converter (ADC). The ADC code can be read out using an I2C interface. The AFE also has a fullyintegrated LED driver with a 6-bit current control. The device has a high dynamic range transmit and receive circuitry that helps with the sensing of very small signal levels. Device Information(1) PART NUMBER AFE4404 PACKAGE DSBGA (15) BODY SIZE (NOM) 2.60 mm × 1.60 mm(2) (1) For all available packages, see the orderable addendum at the end of the datasheet. (2) Refers to dimensions D × E in Figure 99. Simplified Block Diagram TX_SUP RX_SUP Offset Cancellation DAC TX_SUP TX1 TX2 TX3 LDO I-V Amplifier (TIA) Cf LED Driver ILED IO_SUP INP INM CLK Rf Buffer I2C_CLK NoiseReduction Filter ADC I2C Interface I2C_DAT RESETZ Rf Cf IO Buffer Internal, External Clock Timing Engine ADC_RDY GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 6 6 6 6 7 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ............................................... Typical Characteristics .............................................. Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 29 8.5 Register Map........................................................... 33 9 Application and Implementation ........................ 68 9.1 Application Information............................................ 68 9.2 Typical Application .................................................. 68 10 Power Supply Recommendations ..................... 75 11 Layout................................................................... 77 11.1 Layout Guidelines ................................................. 77 11.2 Layout Example .................................................... 77 12 Device and Documentation Support ................. 78 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 78 78 78 78 78 13 Mechanical, Packaging, and Orderable Information ........................................................... 78 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2016) to Revision D Page • Changed last sub-bullet of Receiver Features bullet ............................................................................................................. 1 • Changed test conditions of dynamic power-down mode rows in Current Consumption subsection of Electrical Characteristics table ............................................................................................................................................................... 8 Changes from Revision B (October 2015) to Revision C Page • Changed specifications of t1 and t4 rows in Table 7 to improve rejection of ambient light................................................... 24 • Changed Description column in Table 10 ........................................................................................................................... 26 • Changed Table 11 ................................................................................................................................................................ 27 • Changed Table 12 ................................................................................................................................................................ 28 • Added Reducing Sensitivity to Ambient Light Modulation section........................................................................................ 70 Changes from Revision A (August 2015) to Revision B Page • Changed TX_SUP pin number to E3 in Pin Functions table ................................................................................................. 5 • Added Figure 9 ..................................................................................................................................................................... 10 • Added Decimation Mode section ......................................................................................................................................... 32 • Added rows 3Dh, 3Fh, and 40h to Table 16 ........................................................................................................................ 35 • Added Register 3Dh description to Register Map section.................................................................................................... 66 • Added Register 3Fh and Register 40h descriptions to Register Map section...................................................................... 67 • Added System-Level ESD Considerations section ............................................................................................................. 69 • Added input-referred current paragraph associated to Figure 9 in Application Curves section........................................... 72 2 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 Changes from Original (June 2015) to Revision A Page • Deleted Diagnostics Mode section ....................................................................................................................................... 31 • Changed bit 2 of address 00h to 0 in Table 16 ................................................................................................................... 33 • Deleted row 30h from Table 16 ........................................................................................................................................... 34 • Changed bit 2 name and description in Register 0h ........................................................................................................... 36 • Deleted Register 30h ........................................................................................................................................................... 59 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 3 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com 5 Device Comparison Table PRODUCT PACKAGE-LEAD LED DRIVE CONFIGURATION LED DRIVE CURRENT (mA, Max) OPERATING TEMPERATURE RANGE AFE4400 VQFN-40 H-bridge, common anode 50 0°C to 70°C AFE4490 VQFN-40 H-bridge, common anode 200 –40°C to 85°C Clinical-grade pulse oximeters AFE4403 DSBGA-36 H-bridge, common anode 100 –20°C to 70°C Clinical pulse oximeter patches, wearables Common anode (1) –20°C to 70°C Wearable optical bio-sensing AFE4404 (1) DSBGA-15 50 OPTIMIZED APPLICATION Finger-clip pulse oximeters Mode that doubles the range to 100 mA with additional restrictions. 6 Pin Configuration and Functions YZP Package 15-Ball DSBGA Bottom View I2C_DAT I2C_CLK TX_SUP RESETZ TX2 GND DNC CLK TX3 INP ADC_RDY TX1 INM RX_SUP IO_SUP 1 2 3 E D C B A 4 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 Pin Functions PIN I/O DESCRIPTION NAME NO. ADC_RDY B2 Digital ADC ready interrupt signal (output) CLK C2 Digital Clock input or output, selectable based on register. Default is input (external clock mode). Can be set via a register to output the clock when the oscillator is enabled. (1) (2) DNC C1 GND D3 Ground Common ground for transmitter and receiver I2C_CLK E2 Digital I2C clock input, external pullup resistor to IO_SUP (for example, 10 kΩ) I2C_DAT E1 Digital I2C data, external pullup resistor to IO_SUP (for example, 10 kΩ) INM A1 Analog Connect only to anode of photodiode (3) INP B1 Analog Connect only to cathode of photodiode (3) IO_SUP A3 Supply Separate supply for digital I/O. Must be less than or equal to RX_SUP. Can be tied to RX_SUP. RESETZ D1 Digital RESETZ or PWDN: function based on (active low) duration of RESETZ pulse (4). A 25-µs to 50-µs duration = RESETZ active. A > 200-µs duration = PWDN active. RX_SUP A2 Supply Receiver supply; 1-µF decapacitor to GND TX1 B3 Analog Transmit output, LED1 TX2 D2 Analog Transmit output, LED2 TX3 C3 Analog Transmit output, LED3 TX_SUP E3 Supply Transmitter supply; 1-µF decapacitor to GND (1) (2) (3) (4) Do not connect (leave floating) Depending on whether external clock mode or internal oscillator mode is used, extra series or shunt resistors are recommended on the CLK pin. For more details, see the Typical Application section. In both hardware power-down (PWDN) and software power-down (PDNAFE) modes, the CLK pin is driven by the AFE to 0 V. Therefore, if operating in external clock mode, take care to shut off the external clock to the AFE when in these power-down modes. Maintain the indicated polarity of photodiode connections to the AFE input pins. A RESET pulse must be applied after power-up to ensure that the registers are all reset to their default values. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 5 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range MIN MAX RX_SUP to GND –0.3 4 IO_SUP to GND –0.3 4 RX_SUP-IO_SUP –0.3 TX_SUP to GND UNIT V –0.3 6 Voltage applied to analog inputs Max [–0.3, (GND – 0.3)] Min [4, (RX_SUP + 0.3)] V Voltage applied to digital inputs Max [–0.3, (GND – 0.3)] Min [4, (IO_SUP + 0.3)] V Maximum duty cycle (cumulative): sum of all LED phase durations as a function of the total period 50-mA LED current mode (ILED_2X = 0) 10% 100-mA LED current mode (ILED_2X = 1) 3% Storage temperature, Tstg (1) –60 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) RX_SUP Receiver supply IO_SUP Input/output supply TX_SUP Transmitter supply 50-mA LED current mode (ILED_2X = 0) 100-mA LED current mode (ILED_2X = 1) MAX 2 3.6 UNIT V 1.7 Min (3.6, RX_SUP) V (1) 3.0 or (0.5 + VLED) , whichever is greater 5.25 V (1) 3.0 or (1.0 + VLED) , whichever is greater 5.25 Digital inputs 0 IO_SUP Analog inputs 0 RX_SUP V –20 70 °C Operating temperature range (1) MIN V VLED refers to the maximum voltage drop across the external LED (at maximum LED current). This value is usually governed by the forward drop voltage (VFB) of the LED. 7.4 Thermal Information AFE4404 THERMAL METRIC (1) YZP (DSBGA) UNIT 15 BALLS RθJA Junction-to-ambient thermal resistance 67.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.5 °C/W RθJB Junction-to-board thermal resistance 12.9 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 12.9 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 7.5 Electrical Characteristics Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. TX_SUP = 4 V, RX_SUP = IO_SUP = 3 V, 100-Hz PRF, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2), detector CIN = 50 pF, and CLKDIV_PRF set to 1, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PULSE REPETITION FREQUENCY PRF (1) 10 (2) Pulse repetition frequency 1000 SPS RECEIVER Offset cancellation DAC current range Offset cancellation DAC current step TIA gain setting Cf setting µA 0.47 µA 10k to 2M Ω 2.5 to 25 pF 2.5 (3) Switched RC filter bandwidth ADC averages Detector capacitance –7 to 7 Differential capacitance between INP, INN kHz 1 16 10 200 pF TRANSMITTER LED current range ILED_2X = 0 0 to 50 ILED_2X = 1 0 to 100 LED current resolution mA 6 Bits 4 MHz CLOCKING (Internal Oscillator) Frequency Accuracy Room temperature Frequency drift with temperature Full temperature range ±1% ±0.5% Jitter (RMS) Output clock high level Output clock low level Output clock rise and fall times 10% to 90%, 15-pF load capacitance on CLK pin 100 ps IO_SUP V 0 V < 30 ns CLOCKING (External Clock) Frequency range (4) 4 Input clock high level Input clock low level Input capacitance of CLK pin 60 MHz IO_SUP Capacitance to ground V 0 V 200 µs. To simplify system design, keeping the pulse duration fixed across use cases is easiest. Set the LED current to the highest value that can be afforded by the system power budget. Initialize the TIA gain to the lowest gain setting of 10 kΩ and use the initial calibration routine to determine the optimum gain. Set the ADC in averaging mode with the number of averages being the maximum afforded by the choice of pulse repetition period and pulse duration. Eight ADC averages is usually sufficient to obtain good SNR. For power-critical, battery-operated applications, choose a sampling pulse duration between 50 µs to 100 µs and operate the device at a high TIA gain setting (for example, 1 MΩ). Set the ADC in averaging mode with four to eight averages. Initialize the LED current to the desired lowest setting (of a few milliamps) and use the initial calibration routine to determine the optimum LED current setting up to the highest value allowed by the system power budget. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 73 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com Typical Application (continued) For pulse-oximeter applications using red and IR LEDs, the target dc level can be typically set to 50% of positive full-scale. For HRM applications, the offset cancellation DAC can be additionally used such that the dc offset can be subtracted from the signal, thereby allowing for a larger TIA gain to be applied without saturating the signal. The calibration routine must be designed in a manner that does not rely on the accuracy of the LED current, TIA gain, and offset cancellation DAC, thus allowing for device-to-device variations. Specifically, the offset cancellation DAC is not trimmed at production and can have a significant device-to-device variation (±20%). If the calibration routine requires an accurate estimate of the offset cancellation DAC, then the PD_DISCONNECT mode can be used to estimate the offset cancellation DAC range on a given unit. The PD_DISCONNECT mode disconnects the photodiode from the TIA inputs. In this mode IPD = 0 and, thus, the effective input current to the TIA comes solely from the offset cancellation DAC (Ieff = I_OFFDAC). As a result, the offset cancellation DAC value can be directly estimated from the AFE output code. When the calibration loop is in the process of converging to the steady state, the device settings can continue to be refreshed to new values. Ideally, a time equal to tCHANNEL is provided for the AFE to settle to any change in signal-chain settings. However, this time can lead to unacceptably large delays in the convergence of the calibration routine. Therefore, during the transient (when the calibration routine is in the transient phase), the wait times can be reduced to as low as tCHANNEL / 10. After the calibration routine converges to the final settings, a wait time of tCHANNEL can then be applied before high-accuracy data are read out from the AFE. 74 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 10 Power Supply Recommendations The guidelines for power-supply sequencing and device initialization are shown in Figure 96, Figure 97, and Table 79. RX_SUP t1 IO_SUP t2 TX_SUP t3 RESETZ t4 t5 t7 t6 t4 t5 t6 Device Settings Device Settings I2C Interface t8 ADC_RDY Reset CLK (External Clock Mode) Device State High-Accuracy Operation Hardware PowerDown (PWDN) High-Accuracy Operation Reset Figure 96. Power-Supply Sequencing, Device Initialization, and Hardware Power-Down Timing RX_SUP t1 IO_SUP t2 TX_SUP t3 RESETZ t4 t5 t6 t6 Device Settings I2C Interface PDNAFE =1 PDNAFE =0 ADC_RDY Device State Reset CLK (External Clock Mode) High-Accuracy Operation Software Power-Down (PDNAFE) High-Accuracy Operation Figure 97. Power-Supply Sequencing, Device Initialization, and Software Power-Down Timing Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 75 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com Table 79. Timing Parameters for Power Supply Sequencing, Device Initialization, and Power-Down Timing VALUE t1 Time between RX_SUP and IO_SUP ramping up Ramp up RX_SUP before or at the same time as IO_SUP. Keep t1 as small as possible (for example,10 ms). t2 Time between RX_SUP and TX_SUP ramping up Keep t2 as small as possible (for example,10 ms). t3 Time between all supplies stabilizing and start of the RESETZ lowgoing pulse t4 RESETZ pulse duration for the device to get reset t5 Time between resetting the device and issuing of I2C commands t6 Time between I2C commands and the ADC_RDY pulse that corresponds to valid data t7 RESETZ pulse duration for the device to enter PWDN (power-down) mode > 200 µs t8 Time from exiting power-down mode and subsequently resetting the device > 10 ms (1) 76 > 10 ms Between 25 µs and 50 µs > 1 ms tCHANNEL (1) The tCHANNEL parameter is specified in the Electrical Characteristics table. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 11 Layout 11.1 Layout Guidelines Two key layout guidelines are: 1. TX1, TX2, and TX3 are fast-switching lines and must be routed away from sensitive lines (such as the INP, INN inputs). 2. The device can draw high-switching currents from the TX_SUP pin. A decoupling capacitor must be electrically close to the pin. 11.2 Layout Example Figure 98. Example Layout Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 77 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 78 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 YZP0015 DSBGA - 0.5 mm max height SCALE 7.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER E = 1.6 mm D = 2.6 mm D C 0.5 MAX SEATING PLANE 0.19 0.13 0.05 C BALL TYP 1 TYP 0.5 TYP E D SYMM 2 TYP C B 0.5 TYP A 0.25 0.21 C A B 1 2 3 15X 0.015 SYMM 4221665/A 09/2014 NanoFree Is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. TM 3. NanoFree package configuration. Figure 99. Package Outline Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 79 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com EXAMPLE BOARD LAYOUT YZP0015 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 15X ( 0.23) 1 3 2 A (0.5) TYP B SYMM C D E SYMM LAND PATTERN EXAMPLE SCALE:30X 0.05 MAX ( 0.23) METAL METAL UNDER SOLDER MASK 0.05 MIN ( 0.23) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221665/A 09/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). Figure 100. Example Board Layout 80 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 EXAMPLE STENCIL DESIGN YZP0015 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP (R0.05) TYP 15X ( 0.25) 1 2 3 A (0.5) TYP B METAL TYP SYMM C D E SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4221665/A 09/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. Figure 101. Example Stencil Design Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: AFE4404 81 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) AFE4404YZPR ACTIVE DSBGA YZP 15 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -20 to 70 AFE4404 AFE4404YZPT ACTIVE DSBGA YZP 15 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -20 to 70 AFE4404 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of