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AFE5401-Q1
SBAS619A – MARCH 2014 – REVISED JUNE 2017
AFE5401-Q1 Quad-Channel, Analog Front-End for Automotive Radar Baseband Receiver
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Integrated Analog Front-End Includes:
– Quad LNA, Equalizer, PGA, Antialiasing Filter,
and ADC
Input-Referred Noise with 30-dB PGA Gain:
– 2.9-nV/√Hz for 15-dB LNA Gain
– 2.0-nV/√Hz for 18-dB LNA Gain with
HIGH_POW_LNA Mode
Simultaneous Sampling Across Channels
Programmable LNA Gain:
12 dB, 15 dB, 16.5 dB, and 18 dB
Programmable Equalizer Modes
Built-In Diagnostic Modes
Temperature Sensor
Programmable-Gain Amplifiers (PGAs):
– 0 dB to 30 dB in 3-dB Steps
Programmable, Third-Order, Antialiasing Filter:
– 7 MHz, 8 MHz, 10.5 MHz, and 12 MHz
Analog-to-Digital Converter (ADC):
– Quad Channel, 12 Bits, 25 MSPS per Channel
– No External Decoupling Required for
References
Parallel CMOS Outputs
64-mW Total Core Power per Channel at
25 MSPS per Channel
Supplies: 1.8 V and 3.3 V
Package: 9-mm × 9-mm VQFN-64
Automotive Radar
Data Acquisition
SONAR™
3 Description
The AFE5401-Q1 is an analog front-end (AFE),
targeting applications where the level of integration is
critical. The device includes four channels, with each
channel comprising a low-noise amplifier (LNA), a
programmable equalizer (EQ), a programmable gain
amplifier (PGA), and an antialias filter followed by a
high-speed, 12-bit, analog-to-digital converter (ADC)
at 25 MSPS per channel.
Each of the four differential input pairs are amplified
by an LNA and are followed by a PGA with a
programmable gain range from 0 dB to 30 dB. An
antialias, low-pass filter (LPF) is also integrated
between the PGA and ADC for each channel.
Each LNA, PGA, and antialiasing filter output is
differential (limited to 2 VPP). The antialiasing filter
drives the on-chip, 12-bit, 25-MSPS ADC. The four
ADC outputs are multiplexed on a 12-bit, parallel,
CMOS output bus.
The device is available in a 9-mm × 9-mm, VQFN-64
package and is specified over a temperature range of
–40°C to +105°C. For more information, contact
AFE5401_info@list.ti.com.
Device Information(1)
PART NUMBER
AFE5401-Q1
PACKAGE
VQFN (64)
BODY SIZE (NOM)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SDOUT
SDATA
RESET
DVDD18
SEN
AVDD18
STBY
DRVDD
SCLK
Simplified Schematic
AVDD3
Serial Interface
PGA
LNA
EQ
Antialiasing
Filter
Channel 1 of 4
EQ
ADC 1
BUF
4:1 MUX
CMOS Output Driver
INx
INx_AUX
D [11:0]
D_GPO [1:0]
1x
ADC_CLK
CMOS, DIFF
Support
4x
DCLK
AFE_CLK
CLKINP
CLKINM
Clock + Timing Generator
DSYNC1
Serialization Factor
TRIG
DSYNC2
AVSS
DRVSS
AVSS
DVSS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AFE5401-Q1
SBAS619A – MARCH 2014 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Digital Characteristics ............................................... 8
Timing Requirements: Output Interface .................... 9
Timing Requirements: RESET.................................. 9
Timing Requirements: Serial Interface Operation... 10
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 21
7.1 Timing Requirements: Across Output Serialization
Modes ...................................................................... 21
8
Detailed Description ............................................ 23
8.1 Overview ................................................................. 23
8.2 Functional Block Diagram ....................................... 24
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
25
32
41
44
Application and Implementation ........................ 64
9.1 Application Information............................................ 64
9.2 Typical Application .................................................. 64
10 Power Supply Recommendations ..................... 68
10.1 Power Supply Sequencing .................................... 68
10.2 Power Supply Decoupling ..................................... 68
11 Layout................................................................... 68
11.1 Layout Guidelines ................................................. 68
11.2 Layout Example .................................................... 69
12 Device and Documentation Support ................. 71
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
71
71
71
71
71
71
13 Mechanical, Packaging, and Orderable
Information ........................................................... 71
4 Revision History
Changes from Original (March 2014) to Revision A
Page
•
Added automotive Features bullets ....................................................................................................................................... 1
•
First public release ................................................................................................................................................................ 1
•
Changed Device Information table to current standards ....................................................................................................... 1
•
Changed order of Pin Functions table to be sorted by pin name instead of pin number....................................................... 4
•
Changed ESD Rating table title and format, moved Storage temperature parameter to Absolute Maximum Ratings table . 5
•
Added Receiving Notification of Documentation Updates and Community Resources sections ......................................... 71
2
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SBAS619A – MARCH 2014 – REVISED JUNE 2017
5 Pin Configuration and Functions
VCM
AVSS
AVDD18
AVSS
NC
STBY
NC
RESET
SCLK
SDATA
SEN
SDOUT
DVSS
DVDD18
DRVDD
DRVSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RGC Package
VQFN-64
Top View
IN1P_AUX
1
48
D_GPO[1]
IN1M_AUX
2
47
D_GPO[0]
IN1P
3
46
D[11]
IN1M
4
45
D[10]
IN2P_AUX
5
44
D[9]
IN2M_AUX
6
43
D[8]
IN2P
7
42
D[7]
IN2M
8
41
D[6]
Thermal Pad
32
DRVDD
DRVDD
33
31
16
DRVSS
IN4M
30
DCLK
DVDD18
34
29
15
DVSS
IN4P
28
D[0]
DVDD18
35
27
14
DSYNC2
IN4M_AUX
26
D[1]
DSYNC1
36
25
13
TRIG
IN4P_AUX
24
D[2]
AVDD18
37
23
12
AVSS
IN3M
22
D[3]
CLKINM
38
21
11
CLKINP
IN3P
20
D[4]
AVSS
39
19
10
AVDD18
IN3M_AUX
18
D[5]
AVDD3
40
17
9
VCM
IN3P_AUX
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Pin Functions
PIN
NAME
DESCRIPTION
NO
D[11:0]
35-46
CMOS outputs for channels 1 to 4
D_GPO[1:0]
47, 48
General-purpose CMOS output
AVDD3
18
3.3-V analog supply voltage
AVDD18
19, 24, 62
1.8-V analog supply voltage
AVSS
20, 23, 61, 63
Analog ground
CLKINM
22
Negative differential clock input pin. A single-ended clock is also supported.
CLKINP
21
Positive differential clock input pin. A single-ended clock is also supported.
DCLK
34
CMOS output clock
DRVDD
32, 33, 50
CMOS output driver supply
DRVSS
31, 49
CMOS output driver ground
DSYNC1
26
Data synchronization clock 1
DSYNC2
27
Data synchronization clock 2
DVDD18
28, 30, 51
1.8-V digital supply voltage
DVSS
29, 52
IN1M
4
Negative differential analog input pin for channel 1
IN1P
3
Positive differential analog input pin for channel 1
IN1M_AUX
2
Negative differential auxiliary analog input pin for channel 1
IN1P_AUX
1
Positive differential auxiliary analog input pin for channel 1
IN2M
8
Negative differential analog input pin for channel 2
IN2P
7
Positive differential analog input pin for channel 2
IN2M_AUX
6
Negative differential auxiliary analog input pin for channel 2
IN2P_AUX
5
Positive differential auxiliary analog input pin for channel 2
IN3M
12
Negative differential analog input pin for channel 3
IN3P
11
Positive differential analog input pin for channel 3
IN3M_AUX
10
Negative differential auxiliary analog input pin for channel 3
IN3P_AUX
9
Positive differential auxiliary analog input pin for channel 3
IN4M
16
Negative differential analog input pin for channel 4
IN4P
15
Positive differential analog input pin for channel 4
IN4P_AUX
13
Positive differential auxiliary analog input pin for channel 4
14
Negative differential auxiliary analog input pin for channel 4
IN4M_AUX
NC
58, 60
Digital ground
Do not connect
RESET
57
Hardware reset pin (active high). This pin has an internal 150-kΩ pull-down resistor.
SCLK
56
Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA
55
Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT
53
Serial interface data readout
SEN
54
Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.
STBY
59
Standby control input. This pin has an internal 150-kΩ pull-down resistor.
TRIG
25
Trigger for DSYNC1 and DSYNC2. This pin has an internal 150-kΩ pull-down resistor.
VCM
17, 64
Thermal pad
4
Pad
Output pins for common-mode bias voltage of the auxiliary input signals
Located on bottom of package, internally connected to AVSS. Connect to ground plane on the
board.
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SBAS619A – MARCH 2014 – REVISED JUNE 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
DRVDD to DRVSS
–0.3
+3.8
AVDD3 to AVSS
–0.3
+3.8
AVDD18 to AVSS
–0.3
+2.2
DVDD18 to DVSS
–0.3
+2.2
AVSS and DVSS
–0.3
+0.3
AVSS and DRVSS
–0.3
+0.3
DVSS and DRVSS
–0.3
+0.3
Clock input pins (CLKINP and CLKINM) to AVSS
–0.3
minimum (2.2, AVDD18 + 0.3)
V
Analog input pins (INIP, INIM, INIP_AUX, and INIM_AUX) to AVSS
–0.3
minimum (2.2, AVDD18 + 0.3)
V
–0.3
+3.6
V
+125
°C
+150
°C
Voltage range
Voltage between
Digital control pins to DVSS
STBY, RESET, SCLK, SDATA,
SEN, TRIG
Maximum operating junction temperature, TJ max
Storage temperature, Tstg
(1)
–60
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
Charged-device model (CDM), per AEC Q100-011
±1000
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
+105
°C
TEMPERATURE
TA
Ambient temperature range
–40
DRVDD
Output driver supply
1.7
AVDD3
3-V analog supply voltage
AVDD18
DVDD18
SUPPLIES
3.6
V
3
3.3
3.6
V
1.8-V analog supply voltage
1.7
1.8
1.9
V
1.8-V digital supply voltage
1.7
1.8
1.9
V
CLOCK INPUT
Default mode (DIV_EN disabled)
CLKIN
Input clock frequency
12.5
25
With DIV_EN, DIV_FRC enabled and DIV_REG = 1
25
50
With DIV_EN, DIV_FRC enabled and DIV_REG = 2
37.5
75
With DIV_EN, DIV_FRC enabled and DIV_REG = 3
50
100
12.5
50
With decimate-by-2 or decimate-by-4 modes enabled
(DIV_EN disabled) (1)
VCLKINP – VCLKINM
Input clock amplitude
differential
Sine wave, ac-coupled
0.2
1.5
LVPECL, ac-coupled
0.2
1.6
LVDS, ac-coupled
0.2
0.7
Single-ended CMOS clock on CLKINP with CLKINM connected to AVSS
Input clock duty cycle
VPP
1.8
40%
MHz
V
60%
DIGITAL OUTPUT
CLOAD
(1)
Tolerable external load capacitance from each output pin to DRVSS
5
pF
In decimation mode, input clock frequency (CLKIN) can be scaled up to maximum of 200 MHz with the input divider.
6.4 Thermal Information
AFE5401-Q1
THERMAL METRIC
(1)
RGC (VQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
24.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
8.7
°C/W
RθJB
Junction-to-board thermal resistance
3.9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
3.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.5
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V,
AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with a 0.1-µF capacitor, AFE_CLK =
25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise
noted. Typical values are at TNOM = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FULL-CHANNEL CHARACTERISTICS
LNA gain = 12 dB
Maximum differential input signal
amplitude on INIP and INIM
0.5
LNA gain = 15 dB (default)
0.35
LNA gain = 16.5 dB
LNA gain = 18 dB
Input resistance, from each input to
internal dc bias level
Default
CI
Input capacitance
Differential input capacitance
VVCM
VCM output voltage
Voltage on VCM pins
VCM output current capability
For 50-mV drop in VCM voltage
VPP
0.3
0.25
1 ± 20%
TERM_INT_20K_LNA / TERM_INT_20K_AUX = 1
kΩ
10 ± 20%
5.5
pF
1.45
V
3
mA
Gain matching
Across channels and devices
0.15
1
EG
Gain error
PGA gain = 30 dB
± 0.6
± 1.4
EO
Offset error
PGA gain = 30 dB, 1 sigma value
± 120
Input-referred noise voltage
fIN = 3 MHz, idle channel, PGA gain = 30 dB (default)
2.9
fIN = 3 MHz, idle channel, PGA gain = 30 dB
(HIGH_POW_LNA mode)
2.5
fIN = 3 MHz, main channel
65
SNR
Signal-to-noise ratio
SFDR
Spurious-free dynamic range
THD
Total harmonic distortion
fIN = 3 MHz, main channel
IMD
Intermodulation distortion
fIN1 = 1.5 MHz, fIN2 = 2 MHz, AIN1 and AIN2 = –7 dBFS
PSRR
Power-supply rejection ratio
For a 50-mVPP signal on AVDD18 up to 10 MHz, no input
applied to analog inputs
fIN = 3 MHz, AUX channel
57
fIN = 3 MHz, main channel (HPL_EN mode)
3.8
67.7
66
74
56
Number of bits in the ADC
dB
LSB
69.2
fIN = 3 MHz, main channel (default)
dB
nV/√Hz
dBFS
dBc
65
dBc
83
dBFS
> 50
dB
12
Bits
Crosstalk, main channel to main channel
Aggressor channel: fIN = 2 MHz, 1 dB below ADC full-scale.
Victim channel: fIN= 3 MHz, 1 dB below ADC full-scale.
70
dB
Maximum channel gain
LNA gain = 18 dB, PGA gain = 30 dB
48
dB
Minimum channel gain
LNA gain = 12 dB, PGA gain = 0 dB
12
dB
3
dB
30
dB
2
VPP
PGA gain resolution
PGA gain range
Maximum PGA gain – minimum PGA gain
Differential input voltage range for AUX
channel
ANTIALIAS FILTER (Third-Order Elliptic)
FILTER_BW = 0 (default)
fC
3-dB filter corner frequency
7
FILTER_BW = 2
10.5
FILTER_BW = 3
3-dB filter corner frequency tolerance
ATT2FC
ATTSTPBND
RPPSBND
Filter attenuation
8
FILTER_BW = 1
For all FILTER_BW settings
12
±5%
At 2 × fC
30
Stop-band attenuation (fIN > 2.25 × fC)
40
Ripple in pass band
1.5
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dBc
dB
7
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Electrical Characteristics (continued)
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V,
AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with a 0.1-µF capacitor, AFE_CLK =
25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise
noted. Typical values are at TNOM = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
Total core power, per channel
IAVDD18
AVDD18 current consumption
IAVDD3
AVDD3 current consumption
IDVDD18
DVDD18 current consumption
Idle channel, excluding DRVDD power
64
Default mode
131
With HIGH_POW_LNA mode enabled
153
With HPL_EN mode enabled
135
5-pF load, toggle data test pattern mode
IDRVDD
DRVDD current consumption
15-pF load, toggle data test pattern mode
mW
145
mA
1.5
3.5
mA
8
12
mA
DRVDD = 3.3 V
14
DRVDD = 1.8 V
8.5
DRVDD = 3.3 V
36
DRVDD = 1.8 V
20
mA
Power-down
5
mW
STBY power
15
mW
6.6 Digital Characteristics
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD
= 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted. Typical values are at TNOM =
+25°C.
PARAMETER
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (STBY, RESET, SCLK, CLKIN, SDATA, SEN, TRIG) (1)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
10
µA
IIL
Low-level input current
10
µA
CI
Input capacitance
VIL_CLKINP
Input clock CMOS single-ended (VCLKINP), VCLKINM
connected to AVSS
VIH_CLKINP
1.4
V
0.4
4
V
pF
0.25 × AVDD18
0.75 × AVDD18
V
V
DIGITAL OUTPUTS
VOH
High-level output voltage
VOL
Low-level output voltage
(1)
8
DRVDD – 0.2
DRVDD
0
V
0.2
V
The SEN pin has an internal 150-kΩ pull-up resistor. The STBY, RESET, SCLK, SDATA, and TRIG pins have an internal 150-kΩ pulldown resistor.
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6.7 Timing Requirements: Output Interface
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V,
AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with 0.1 µF, AFE_CLK = 25 MHz, LNA
gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise noted.
Typical values are at TNOM = +25°C.
MIN
tADLY
Aperture delay between the rising edge of the input sampling clock and the
actual time at which the sampling occurs
Wake-up time
tLAT
Data setup time
tHO
Data hold time
tR, tF
CMOS output data and
clock rise and fall time
MAX
UNIT
3
ns
Time to valid data after coming out of
STANDBY mode
500
µs
Time to valid data after coming out of
GLOBAL_PDN mode
2
ms
Time to valid data after stopping and
restarting the input clock
500
µs
10.5
tAFE_CLK
cycles
ADC latency (default, after reset)
tSU
NOM
Data valid (1) to 50% of DCLK rising edge,
DRVDD = 3.3 V, load = 5 pF, 4x
serialization, STR_CTRL_CLK and
STR_CTRL_CLK_DATA = 0
4.1
ns
Data valid (1) to 50% of DCLK rising edge,
DRVDD =1.8 V, load = 5 pF, 4x serialization,
STR_CTRL_CLK and
STR_CTRL_CLK_DATA = 5
3.7
ns
50% of DCLK rising edge to data becoming
invalid (1), DRVDD = 3.3 V, load = 5 pF, 4x
serialization, STR_CTRL_CLK and
STR_CTRL_CLK_DATA = 0
2.8
ns
50% of DCLK rising edge to data becoming
invalid (1), DRVDD = 1.8 V, load = 5 pF, 4x
serialization, STR_CTRL_CLK and
STR_CTRL_CLK_DATA = 5
2.7
ns
DRVDD = 3.3 V, load = 5 pF, 10% to 90%,
STR_CTRL_CLK and
STR_CTRL_CLK_DATA = 0
1.2
ns
DRVDD = 1.8 V, load = 5 pF, 10% to 90%,
STR_CTRL_CLK and
STR_CTRL_CLK_DATA = 5
1.1
ns
tOUT
Delay from CLKIN rising edge to DCLK rising edge, zero-crossing of input
clock to 50% of DCLK rising edge, DRVDD = 3.3 V, load = 5 pF, 4x
serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0
tS_TRIG
TRIG setup time, TRIG pulse duration ≥ tAFE_CLK
4
ns
tH_TRIG
TRIG hold time, TRIG pulse duration ≥ tAFE_CLK
3
ns
(1)
6.7
9.5
ns
Data valid refers to a logic high of 0.7 × DRVDD and a logic low of 0.3 × DRVDD.
6.8 Timing Requirements: RESET
Typical values are at TA = +25°C. Minimum and maximum specifications are across the full temperature range of TMIN =
–40°C to TMAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
t1
Power-on to reset delay
Delay from power-up of AVDD18 and
DVDD18 to RESET pulse active
t2
Reset pulse duration
Pulse duration of active RESET signal
t3
Register write delay
Delay from RESET disable to SEN active
MIN
TYP
MAX
1
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ms
40
ns
100
ns
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6.9 Timing Requirements: Serial Interface Operation
Minimum specifications are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V, AVDD3 =
3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, CLOAD on SDOUT = 5 pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNIT
t1
SCLK period
50
ns
t2
SCLK high time
20
ns
t3
SCLK low time
20
ns
t4
Data setup time
5
ns
t5
Data hold time
5
ns
t6
SEN falling to SCLK rising
8
ns
t7
Time between last SCLK rising edge to SEN rising edge
8
t8
Delay from SCLK falling edge to SDOUT valid
7
ns
11
15
ns
tLAT
tADLY
INIP, INIM
N
tCLK(1)
N+1
N+3
N+4
N+5
N+6
N+7
CLKIN
tOUT
tHO
DCLK
tSU
D[11:0]
CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4
(1) tCLK = 1 / fCLKIN
Figure 1. Output Interface Timing Diagram
A high pulse on the RESET pin is required for register initialization through the reset pin. Figure 2 shows the
timing requirement for reset after power-up.
Power Supply
(AVDD18, DVDD18,
AVDD3, DRVDD)
t1
t2
RESET
t3
SEN
Figure 2. Reset Timing
10
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SEN
End Sequence
t6
t1
SCLK
t7
Data latched on rising edge of SCLK
t2
t3
A[7]
SDATA
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
t4
t5
SDOUT
Figure 3. Serial Interface Register Write Timing Diagram
SEN
End Sequence
t6
t1
SCLK
t7
t2
t3
A[7]
SDATA
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
X
X
t4
t5
t8
X
X
X
X
X
X
X
X
X
X
X
X
D[3]
D[2]
X
X
SDOUT to be latched externally on rising
edge
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[1]
D[0]
SDOUT
Figure 4. Serial Interface Register Readout Timing Diagram
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6.10 Typical Characteristics
0
±10
±20
±30
±40
±50
±60
±70
±80
±90
±100
±110
±120
±130
±140
0
±10
±20
±30
±40
±50
±60
±70
±80
±90
±100
±110
±120
±130
±140
Amplitude (dBFS)
Amplitude (dBFS)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
0
2.5
5
7.5
10
Frequency (MHz)
SNR = 67.7 dBFS
12.5
0
5
SFDR = 65.7 dBc
THD = 65.2 dBc
7.5
10
12.5
Frequency (MHz)
SNR = 53.3 dBFS
Figure 5. FFT for 3-MHz, –1-dBFS Input Signal,
0-dB PGA Gain (Sample Rate = 25 MSPS)
C002
SFDR = 63.7 dBc
THD = 63.6 dBc
Figure 6. FFT for 3-MHz, –1-dBFS Input Signal,
30-dB PGA Gain (Sample Rate = 25 MSPS)
0
±10
±20
±30
±40
±50
±60
±70
±80
±90
±100
±110
±120
±130
±140
85
PGA Gain = 0 dB
PGA Gain = 30 dB
80
SFDR (dBc)
Amplitude (dBFS)
2.5
C002
75
70
65
60
0
2.5
5
7.5
10
Frequency (MHz)
fIN1 = 1.5 MHz
fIN2 = 2 MHz
12.5
1
2
3
4
Input Signal Frequency (MHz)
C001
5
C006
Each Tone at –7-dBFS Amplitude
Two-Tone IMD = –83 dBFS
Figure 7. FFT with Two-Tone Signal
Figure 8. Spurious-Free Dynamic Range vs
Input Signal Frequency
53.5
68.3
68.2
53.3
SNR (dBFS)
SNR (dBFS)
68.1
68
67.9
67.8
67.7
53.1
52.9
52.7
67.6
52.5
67.5
1
2
3
Input Signal Frequency (MHz)
4
5
Figure 9. Signal-to-Noise Ratio vs Input Signal Frequency
(PGA Gain = 0 dB)
12
1
2
3
Input Signal Frequency (MHz)
C005
4
5
C050
Figure 10. Signal-To-Noise Ratio vs Input Signal Frequency
(PGA Gain = 30 dB)
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Typical Characteristics (continued)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
80
68
Default Mode
66
77
HPL_EN = 1
SFDR (dBc)
SNR (dBFS)
64
62
60
58
74
71
68
56
65
54
52
62
3
6
9
12
15
18
21
24
27
0
30
PGA Gain (dB)
6
9
12
15
18
21
24
27
30
PGA Gain (dB)
Figure 11. Signal-to-Noise Ratio vs PGA Gain
C008
Figure 12. Spurious-Free Dynamic Range vs PGA Gain
90
54
90
68.7
80
53.8
80
68.4
70
53.6
60
53.4
70
68.1
60
SFDR (dBFS)
67.8
50
SFDR (dBc)
67.5
SFDR (dBFS, dBc)
69
SNR (dBFS)
100
SFDR (dBFS, dBc)
3
C007
53.2
50
SFDR (dBFS)
40
SNR (dBFS)
67.2
-45
-40
-35
-30
-25
-20
-15
-10
-5
52.6
20
0
Input Signal Amplitude (dBFS)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Amplitude (dBFS)
C001
Figure 13. Signal-to-Noise Ratio,
Spurious-Free Dynamic Range vs
Input Signal Amplitude (PGA Gain = 0 dB)
C001
Figure 14. Signal-to-Noise Ratio,
Spurious-Free Dynamic Range vs
Input Signal Amplitude (PGA Gain = 30 dB)
69
67
68.6
66.6
SFDR (dBc)
SNR (dBFS)
52.8
SNR (dBFS)
40
-50
53
SFDR (dBc)
30
SNR (dBFS)
0
68.2
67.8
67.4
66.2
65.8
65.4
67
65
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Input Clock Amplitude, Differential (VPP)
2
2.2
0.2
Figure 15. Signal-to-Noise Ratio vs Input Clock Amplitude
(PGA Gain = 0 dB)
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Input Clock Amplitude, Differential (VPP)
C011
2.2
C012
Figure 16. Spurious-Free Dynamic Range vs
Input Clock Amplitude (PGA Gain = 0 dB)
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Typical Characteristics (continued)
68
67
67.6
66.6
SFDR (dBc)
SNR (dBFS)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
67.2
66.8
66.4
66.2
65.8
65.4
66
65
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
35
50
55
SNR (dBFS)
68.1
67.9
53
52.5
15
17.5
20
22.5
Sampling Frequency (MHz)
52
12.5
25
15
17.5
20
22.5
Sampling Frequency (MHz)
C045
Figure 19. Signal-to-Noise Ratio vs Sampling Frequency
(PGA Gain = 0 dB)
25
C046
Figure 20. Signal-to-Noise Ratio vs Sampling Frequency
(PGA Gain = 30 dB)
78
78
Default Mode
76
Default Mode
76
HPL_EN = 1
HPL_EN = 1
74
SFDR (dBc)
74
SFDR (dBc)
C014
53.5
67.7
72
70
68
72
70
68
66
66
64
15
17.5
20
Sampling Frequency (MHz)
22.5
25
62
12.5
15
17.5
20
Sampling Frequency (MHz)
C047
Figure 21. Spurious-Free Dynamic Range vs Sampling
Frequency (PGA Gain = 0 dB)
14
65
54
68.3
64
12.5
60
Figure 18. Spurious-Free Dynamic Range vs
Input Clock Amplitude (PGA Gain = 0 dB)
68.5
SNR (dBFS)
45
Input Clock Duty Cycle (%)
Figure 17. Signal-to-Noise Ratio vs Input Clock Duty Cycle
(PGA Gain = 0 dB)
67.5
12.5
40
C013
22.5
25
C048
Figure 22. Spurious-Free Dynamic Range vs Sampling
Frequency (PGA Gain = 30 dB)
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Typical Characteristics (continued)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
53.8
68.5
AVDD18 = 1.7 V
AVDD18 = 1.7 V
53.5
AVDD18 = 1.9 V
53.2
SNR (dBFS)
SNR (dBFS)
68.2
AVDD18 = 1.8 V
67.9
67.6
67.3
AVDD18 = 1.8 V
AVDD18 = 1.9 V
52.9
52.6
52.3
67
-40
-25.5
-11
3.5
18
32.5
47
61.5
76
90.5
52
-40.0 -25.5 -11.0
105
Temperature (ƒC)
3.5
18.0 32.5 47.0 61.5 76.0 90.5 105.0
Temperature (ƒC)
C015
Figure 23. Signal-to-Noise Ratio vs AVDD18 and
Temperature (PGA Gain = 0 dB)
Figure 24. Signal-to-Noise Ratio vs AVDD18 and
Temperature (PGA Gain = 30 dB)
72
70
AVDD18 = 1.7 V
AVDD18 = 1.7 V
AVDD18 = 1.8 V
70
AVDD18 = 1.8 V
68
AVDD18 = 1.9 V
SFDR (dBc)
SFDR (dBc)
AVDD18 = 1.9 V
68
66
64
66
64
62
62
60
-40
-25.5
-11
3.5
18
32.5
47
61.5
76
90.5
105
Temperature (ƒC)
-40
-25.5
-11
3.5
18
32.5
47
61.5
76
90.5
105
Temperature (ƒC)
C017
Figure 25. Spurious-Free Dynamic Range vs AVDD18 and
Temperature (PGA Gain = 0 dB, Default Mode)
C018
Figure 26. Spurious-Free Dynamic Range vs AVDD18 and
Temperature (PGA Gain = 30 dB, Default Mode)
78
78
AVDD18 = 1.7 V
AVDD18 = 1.7 V
AVDD18 = 1.8 V
76
AVDD18 = 1.8 V
76
AVDD18 = 1.9 V
SFDR (dBc)
SFDR (dBc)
C016
74
72
AVDD18 = 1.9 V
74
72
70
70
-40
-25.5
-11
3.5
18
32.5
47
61.5
Temperature (ƒC)
76
90.5
105
-40
-25.5
Figure 27. Spurious-Free Dynamic Range vs AVDD18 and
Temperature (PGA Gain = 0 dB, HPL_EN = 1)
-11
3.5
18
32.5
47
61.5
76
90.5
Temperature (ƒC)
C051
105
C052
Figure 28. Spurious-Free Dynamic Range vs AVDD18 and
Temperature (PGA Gain = 30 dB, HPL_EN = 1)
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Typical Characteristics (continued)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
56
65
Default Mode
55
HIGH_POW_LNA = 1
64.5
SFDR (dBc)
SNR (dBFS)
Default Mode
HIGH_POW_LNA = 1
54
53
64
63.5
52
51
63
12
13
14
15
16
17
18
LNA Gain (dB)
12
,QSXW
5HIHUUHG 1RLVH
+]
Input-Referred
Noise Q9
(nV\¥+]
,QSXW
5HIHUUHG 1RLVH Q9
+]
Input-5HIHUUHG
Q9 ¥+]
Default Mode
HIGH_POW_LNA = 1
3.5
3
2.5
2
14
15
16
17
17
18
C020
HIGH_POW_LNA = 1
0
3
6
9
12
15
18
21
24
27
PGA Gain (dB)
30
C022
Figure 32. Input-Referred Noise vs PGA Gain
500
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Default Mode
Temperature = -40°C
Temperature = 25°C
Temperature = 105°C
2XWSXW 5HIHUUHG 1RLVH
1RLVH Q9
+]
Output-5HIHUUHG
Q9 ¥+]
,QSXW 5HIHUUHG Noise
1RLVH (nV\¥+]
Q9 +]
Input-Referred
16
Default Mode
C021
Figure 31. Input-Referred Noise vs LNA Gain
(PGA Gain = 30 dB)
450
HIGH_POW_LNA = 1
400
350
300
250
200
150
100
50
0
3
6
9
12
15
18
21
24
PGA Gain (dB)
27
30
0
3
6
9
12
15
18
21
24
27
PGA Gain (dB)
C023
Figure 33. Input-Referred Noise vs
PGA Gain and Temperature
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
18
LNA Gain (dB)
15
Figure 30. Spurious-Free Dynamic Range vs LNA Gain
(PGA Gain = 30 dB)
4
13
14
LNA Gain (dB)
Figure 29. Signal-to-Noise Ratio vs LNA Gain
(PGA Gain = 30 dB)
12
13
C019
30
C024
Figure 34. Output-Referred Noise vs PGA Gain
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Typical Characteristics (continued)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
3000
500
2500
Temperature = 25°C
400
Temperature = 105°C
350
Occurrences
2XWSXW
5HIHUUHG 1RLVH
Q9 +]
Output-Referred
Noise (nv\¥+]
Temperature = -40°C
450
300
250
200
150
2000
1500
1000
500
100
0
50
0
3
6
9
12
15
18
21
24
27
30
-0.75
-0.65
-0.55
-0.45
-0.35
-0.25
-0.15
C056
C025
Figure 36. Gain Error Histogram for PGA Gain = 30 dB
Figure 35. Output-Referred Noise vs
PGA Gain and Temperature
150
450
Device = 1
400
100
Output Offset (LSB)
350
Occurrences
-0.85
Gain Error (dB)
PGA Gain (dB)
300
250
200
150
100
Device = 2
50
0
±50
±100
50
0
±150
0
0.05
0.1
0.15
0.2
0.25
0.3
Gain Matching ( dB)
0.35
0
0.4
3
12
15
18
21
24
27
3000
20
2500
10
2000
1500
1000
500
30
C027
Figure 38. Channel Offset vs
PGA Gain for Two Typical Devices
Channel Gain (dB)
Occurrences
9
PGA Gain (dB)
Figure 37. Gain Matching Histogram (Maximum Gain
Difference Among the Four Channels within a Device)
0
6
C057
0
±10
±20
FCF_7 MHz
±30
FCF_8 MHz
±40
FCF_10.5 MHz
FCF_12 MHz
-600 -500 -400 -300 -200 -100 0
100 200 300 400 500 600
Offset Error ( LSB)
±50
0.1
10
fIN (MHz)
C058
Figure 39. Offset Error Histogram at PGA Gain = 30 dB
C028
Figure 40. Antialias Filter Response vs
FILTER_BW Settings (PGA Gain = 0 dB)
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Typical Characteristics (continued)
50
20
40
10
30
0
Channel Gain (dB)
Channel Gain (dB)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
20
10
FCF_7 MHz
0
FCF_8 MHz
FCF_10.5 MHz
±10
±10
±20
±30
AVDD18 = 1.7 V
AVDD18 = 1.8 V
±40
FCF_12 MHz
AVDD18 = 1.9 V
±20
±50
0.1
1
10
fIN (MHz)
0.1
10
20
0
Channel Gain (dB)
Channel Gain (dB)
30
±10
±20
±40
Temperature = 25ƒC
10
0
±10
±20
Default Mode (Eq_Dis)
±30
Eq_EN
±40
Temperature = 105ƒC
Eq_EN_LOW_FC
±50
±50
0.1
1
0.1
10
fIN (MHz)
20
Channel Gain (dB)
Channel Gain (dB)
30
30
20
10
Default Mode (Eq_Dis)
Eq_EN
±10
C001
Figure 44. Antialias Filter Response for Equalizer Modes
(PGA Gain = 0 dB)
50
40
10
fIN (MHz)
60
0
1
C053
Figure 43. Antialias Filter Response vs Temperature (PGA
Gain = 0 dB, FILTER_BW = 8 MHz)
10
0
±10
Eq_EN, Temperature = -40ƒC
±20
Eq_EN, Temperature = 105ƒC
±30
Eq_EN_LOW_FC, Temperature = -40ƒC
Eq_EN_LOW_FC
Eq_EN_LOW_FC, Temperature = 105ƒC
±40
±20
0.1
1
10
fIN (MHz)
0.1
1
10
fIN (MHz)
C001
Figure 45. Antialias Filter Response for Equalizer Modes
(PGA Gain = 30 dB)
18
C030
Figure 42. Antialias Filter Response vs AVDD18
(PGA Gain = 0 dB, FILTER_BW = 8 MHz)
20
Temperature = -40ƒC
10
fIN (MHz)
Figure 41. Antialias Filter Response vs
FILTER_BW Settings (PGA Gain = 30 dB)
±30
1
C002
C035
Figure 46. Antialias Filter Response for
Equalizer Modes across Temperature (PGA Gain = 0 dB)
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Typical Characteristics (continued)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
60
40
Amplitude (dBFS)
Channel Gain (dB)
50
30
20
Eq_EN, Temperature = -40ƒC
10
Eq_EN, Temperature = 105ƒC
0
Eq_EN_LOW_FC, Temperature = -40ƒC
±10
0
±10
±20
±30
±40
±50
±60
±70
±80
±90
±100
±110
±120
±130
±140
0
Eq_EN_LOW_FC, Temperature = 105ƒC
3
±20
0.1
1
5
8
10
Frequency (MHz)
10
SNR = 69.2 dBFS
fIN (MHz)
13
C049
SFDR = 69.8 dBc
THD = 69.7 dBc
C036
Figure 48. FFT for AUX Channel
(3-MHz, –1-dBFS Input Signal, Sample Rate = 25 MSPS)
Figure 47. Antialias Filter Response for
Equalizer Modes across Temperature (PGA Gain = 30 dB)
20
10
10
0
Channel Gain (dB)
Channel Gain (dB)
0
±10
±20
±30
±40
±50
±60
Default Mode
±70
±20
±30
±40
±50
DECIMATE_4_EN = 1, Set 2
±60
DECIMATE_2_EN = 1
DECIMATE_4_EN = 1, Set 1
±80
±70
0.1
1
10
0.1
fIN (MHz)
1
fIN (MHz)
C037
Figure 49. Decimate-by-2 Filter Response (Sampling
Frequency = 50 MHz)
120
131
105
130.5
90
130
75
129.5
60
45
30
15
C038
Figure 50. Decimate-by-4 Filter Response (Sampling
Frequency = 12.5 MHz)
Current (mA)
Read Temperature (ƒC)
±10
Current_AVDD18
129
128.5
128
127.5
0
±15
127
±30
126.5
±45
±45
±30
±15
0
15
30
45
60
75
90
Set Temperature (ƒC)
105
126
12.5
Figure 51. Temperature Sensor Response
15
17.5
20
22.5
Sampling Frequency (MHz)
C054
25
C039
Figure 52. AVDD18 Supply Current vs Sampling Frequency
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Typical Characteristics (continued)
Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled
with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner
frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
7
2
Current_DVDD18
Current_AVDD3
1.8
Current (mA)
Current (mA)
6
5
4
3
12.5
1.6
1.4
1.2
15
17.5
20
22.5
Sampling Frequency (MHz)
1
12.5
25
15
Figure 53. DVDD18 Supply Current vs Sampling Frequency
17.5
20
22.5
Sampling Frequency (MHz)
C040
25
C041
Figure 54. AVDD3 Supply Current vs Sampling Frequency
40
64
DRVDD = 3.3 V
DRVDD = 1.8 V
63
30
Power (mW)
Current (mA)
35
25
20
15
17.5
20
Sampling Frequency (MHz)
22.5
25
59
12.5
15
17.5
20
Sampling Frequency (MHz)
C042
Figure 55. DRVDD Supply Current vs Sampling Frequency
(15-pF Load with Toggle Test Mode)
20
61
60
15
10
12.5
62
22.5
25
C044
Figure 56. AFE Core Power, Channel Excluding DRVDD
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7 Parameter Measurement Information
7.1 Timing Requirements: Across Output Serialization Modes
Table 1 and Table 2 provide details for the 4x serialization timing requirements for DRVDD = 3.3 V and DRVDD
= 1.8 V, respectively. Table 3 and Table 4 provide details for the 3x serialization timing requirements for DRVDD
= 3.3 V and DRVDD = 1.8 V, respectively. Table 5 provides the details for the 2x and 1x serialization timing
requirements for DRVDD = 1.8 V to 3.3 V.
Table 1. Timing Requirements: 4x Serialization (DRVDD = 3.3 V)
OUTPUT
CLOCK (DCLK)
FREQUENCY
(MHz)
TEST CONDITIONS
12.5
50
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
9.1
7.9
6.7
9.5
15
60
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
7.1
6.1
6.7
9.5
20
80
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
5.3
4.1
6.7
9.5
25
100
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
4.1
2.8
6.7
9.5
25
100
CLOAD = 15 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 6
3.5
2.6
6.4
9.0
INPUT CLOCK
FREQUENCY
(MHz)
SETUP TIME (ns)
tSU
HOLD TIME (ns)
tHO
MIN
MIN
TYP
MAX
TYP
MAX
tOUT (ns)
MIN
TYP
MAX
Table 2. Timing Requirements: 4x Serialization (DRVDD = 1.8 V)
INPUT CLOCK
FREQUENCY
(MHz)
OUTPUT
CLOCK (DCLK)
FREQUENCY
(MHz)
TEST CONDITIONS
SETUP TIME (ns)
tSU
HOLD TIME (ns)
tHO
MIN
MIN
12.5
50
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
9.2
7.9
5.6
10.6
15
60
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
7.2
6.1
5.6
10.6
20
80
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
5.3
3.9
5.6
10.6
25
100
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
3.7
2.7
5.6
10.6
25
100
CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 14
2.6
2.7
5.3
10.0
TYP
MAX
TYP
MAX
tOUT (ns)
MIN
TYP
MAX
Table 3. Timing Requirements: 3x Serialization (DRVDD = 3.3 V)
OUTPUT
CLOCK (DCLK)
FREQUENCY
(MHz)
TEST CONDITIONS
12.5
37.5
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
12.4
11.8
20.1
23.2
15
45
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
9.9
9.1
17.4
20.4
20
60
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
7.2
6.3
15.1
18.0
25
75
CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0
5.7
4.1
13.4
16.0
25
75
CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 6
5.1
3.8
12.8
15.3
INPUT CLOCK
FREQUENCY
(MHz)
SETUP TIME (ns)
tSU
HOLD TIME (ns)
tHO
MIN
MIN
TYP
MAX
TYP
MAX
tOUT (ns)
MIN
TYP
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Table 4. Timing Requirements: 3x Serialization (DRVDD = 1.8 V)
INPUT CLOCK
FREQUENCY
(MHz)
OUTPUT
CLOCK (DCLK)
FREQUENCY
(MHz)
TEST CONDITIONS
SETUP TIME (ns)
tSU
HOLD TIME (ns)
tHO
MIN
MIN
12.5
37.5
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
12.5
11.9
19.2
23.6
15
45
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
10.0
9.3
16.6
20.1
20
60
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
7.3
6.4
14.0
18.4
25
75
CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5
5.7
4.7
12.4
16.7
25
75
CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 14
4.7
4
12.1
16.4
TYP
MAX
TYP
MAX
tOUT (ns)
MIN
TYP
MAX
Table 5. Timing Requirements: 2x and 1x Serialization (DRVDD = 1.8 V to 3.3 V)
INPUT CLOCK
FREQUENCY
(MHz)
25
25
22
OUTPUT
CLOCK (DCLK)
FREQUENCY
(MHz)
TEST CONDITIONS
SETUP TIME (ns)
tSU
HOLD TIME (ns)
tHO
MIN
MIN
50
2x Serialization mode: CLOAD = 5 pF.
For DRVDD = 1.8 V, STR_CTRL_CLK and
STR_CTRL_DATA = 5.
For DRVDD = 3.3 V, STR_CTRL_CLK and
STR_CTRL_DATA = 0.
7.3
8.0
5.5
10.5
25
1x Serialization mode: CLOAD = 5 pF.
For DRVDD = 1.8 V, STR_CTRL_CLK and
STR_CTRL_DATA = 5.
For DRVDD = 3.3 V, STR_CTRL_CLK and
STR_CTRL_DATA = 0.
18.5
17.5
25.2
30.1
TYP
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TYP
MAX
tOUT (ns)
MIN
TYP
MAX
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8 Detailed Description
8.1 Overview
The AFE5401-Q1 is a very low-power, CMOS, monolithic, quad-channel, analog front-end (AFE). The signal path
of each channel consists of a differential low-noise amplifier (LNA) followed by a differential programmable gain
amplifier (PGA) in series with a differential antialias filter. The antialiasing filter output is sampled by a 12-bit,
pipeline, analog-to-digital converter (ADC) based on a switched-capacitor architecture. Each ADC can also be
differentially driven from INIP_AUX, INIM_AUX through an on-chip buffer (thus bypassing the LNA, PGA, and
antialiasing filter).
Each block in the channel operates with a maximum 2-VPP output swing. Each PGA has a programmable gain
range from 0 dB to 30 dB, with a resolution of 3 dB.
After the input signals are captured by the sampling circuit, the samples are sequentially converted by a series of
low-resolution stages inside the pipeline ADC at the clock rising edge. The outputs of these stages are combined
in a digital logic block to form the final 12-bit word with a latency of 10.5 tAFE_CLK clock cycles. The 12-bit words of
all active channels are multiplexed and output as parallel CMOS levels. In addition to the data streams, a CMOS
clock (DCLK) is also output. This clock must be used by the digital receiver [such as a digital signal processor
(DSP)] to latch the AFE output parallel CMOS data.
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VCM
SDOUT
RESET
SDATA
SEN
SCLK
STBY
DRVDD
DVDD18
AVDD18
AVDD3
8.2 Functional Block Diagram
Reference
Serial Interface
PGA
LNA
AAF
EQ
IN1
EQ
ADC 1
IN1_AUX
BUF
EQ
IN2
EQ
BUF
4:1 MUX
EQ
IN3
EQ
D [11:0]
D_GPO [1:0]
ADC 3
IN3_AUX
CMOS Output Driver
ADC 2
IN2_AUX
BUF
EQ
IN4
EQ
ADC 4
IN4_AUX
BUF
1x
ADC_CLK
CMOS, Diff
Support
CLKINP
fCLKIN
4x
DSYNC1
CLKINM
Serialization Factor
Clock + Timing Generator
DSYNC2
TRIG
AVSS
24
DCLK
Input
Clock Divider
AFE_CLK
DVSS
DRVSS
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8.3 Feature Description
8.3.1 Low-Noise Amplifier (LNA)
The analog input signal is buffered and amplified by an on-chip LNA. LNA gain is programmable with the
LNA_GAIN register, as shown in Table 6.
Table 6. LNA_GAIN Register
LNA_GAIN
DESCRIPTION (dB)
LNA_GAIN_Linear
0
15
5.5
1
18
8
2
12
4
3
16.5
6.5
The LNA output is internally limited to 2 VPP. Thus, the maximum-supported input peak-to-peak swing is set by 2
V / LNA_GAIN_Linear.
Input-referred noise in default mode is 2.9 nV/√Hz at 30-dB PGA gain and 15-dB LNA gain. Input-referred noise
can be further improved to 2.5 nV/√Hz by enabling the HIGH_POW_LNA register bit. However, this noise
reduction results in increased power dissipation.
8.3.2 Programmable Gain Amplifier (PGA)
The PGA amplifies the analog input signal by a programmable gain. Gain can be programmed using the
PGA_GAIN register, common to all channels, in 3-dB steps with a gain range of 30 dB. In default mode, PGA
gain ranges from 0 dB to 30 dB. In equalizer mode, PGA gain ranges from 15 dB to 45 dB. PGA_GAIN register
settings are listed in Table 7. Figure 57 shows the typical SNR values across PGA gain.
Table 7. PGA_GAIN Register Settings
PGA_GAIN Settings
PGA GAIN IN DEFAULT MODE (dB)
PGA GAIN IN EQUALIZER MODE (dB)
0 (0 dB)
0.0
15.0
1 (3 dB)
2.9
17.9
2 (6 dB)
6.0
21.0
3 (9 dB)
8.8
23.8
4 (12 dB)
11.9
26.9
5 (15 dB)
14.8
29.8
6 (18 dB)
17.9
32.9
7 (21 dB)
20.8
35.8
8 (24 dB)
23.9
38.9
9 (27 dB)
26.8
41.8
10 (30 dB)
29.9
44.9
68
66
SNR (dBFS)
64
62
60
58
56
54
52
0
3
6
9
12
15
18
21
24
PGA Gain (dB)
27
30
C007
Figure 57. SNR Across PGA Gain
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8.3.3 Antialiasing Filter
The device introduces a third-order, elliptic, active, antialias, low-pass filter (LPF) in the analog signal path. The
filter –3-dB corner frequency can be configured using the FILTER_BW register, as shown in Table 8. The
corresponding frequency response plots are shown in Figure 58 and Figure 59.
FILTER_BW
CORNER FREQUENCY (MHz)
0
8
1
7
2
10.5
3
12
20
50
10
40
0
30
Channel Gain (dB)
Channel Gain (dB)
Table 8. FILTER_BW Register
±10
±20
FCF_7 MHz
±30
FCF_8 MHz
±40
FCF_10.5 MHz
20
10
FCF_7 MHz
0
FCF_8 MHz
FCF_10.5 MHz
±10
FCF_12 MHz
FCF_12 MHz
±20
±50
0.1
0.1
10
fIN (MHz)
1
Figure 58. Filter Response Across Modes
(PGA Gain = 0 dB)
10
fIN (MHz)
C028
C002
Figure 59. Filter Response Across Modes
(PGA Gain = 30 dB)
8.3.4 Analog-to-Digital Converter (ADC)
The filtered analog input signal is sampled and converted into a digital equivalent code using a high-speed, lowpower, 12-bit, pipeline ADC. The digital output of the device has a latency of 10.5 tAFE_CLK cycles because of the
pipeline nature of the ADC. The digitized output of the device is in binary twos complement (BTC) format. The
output format can be changed to offset binary format with the OFF_BIN_DATA_FMT register bit.
8.3.5 Digital Gain
The ADC output can be incremented digitally using a digital gain block. Digital gain is common for all channels
and can be configured by enabling MULT_EN and applying the desired DIG_GAIN. Channel gain is given by
Equation 1:
where:
•
26
(DIG_GAIN + 32) is the mod 128 number.
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Y Axis
Figure 60 shows the typical digital gain curve for different DIG_GAIN values.
(95, 127/32)
Channel Gain
4
(127, 31/32)
1
0
DIG_GAIN
96
128
X Axis
Figure 60. Digital Gain Graph
8.3.6 Input Clock Divider
The device clock input is passed through a clock divider block that can divide the input clock by a factor of 1, 2,
3, or 4. This divided clock (AFE_CLK) is used for simultaneously sampling the four ADC inputs. In default mode,
a division factor of 1 is used where the AFE_CLK frequency is the same as the input clock frequency. The clock
divider block can be enabled using the DIV_EN register bit and, when enabling this bit, the AFE_CLK frequency
is automatically determined by the serialization factor set by the CH_OUT_DIS register bits (Table 12). The
division factor can also be manually specified by enabling the DIV_FRC and DIV_REG register bits. Care must
be taken to ensure that the input clock frequency is within the recommended operating range specified in the
Recommended Operating Conditions.
After device reset, the divider is reset at the first pulse applied on the TRIG pin. This configuration is especially
useful when using multiple devices in the system, where the sampling instants of all ADCs in the system must be
synchronized. Figure 61 illustrates the TRIG timing diagram and the various divided-down AFE_CLK signals.
Figure 62 provides the TRIG input setup and hold time with respect to the device clock input. Bit settings for the
DIV_EN register, DIV_FRD register, and DIV_REG register are provided in Table 9, Table 10, and Table 11,
respectively.
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TRIG
CLKIN
TRIG_INT
AFE_CLK (÷ 2)
AFE_CLK (÷ 3)
AFE_CLK (÷ 4)
Figure 61. Input Clock Divider
CLKIN
TRIG
tS_TRIG
tH_TRIG
Figure 62. TRIG CLKIN Setup and Hold
Table 9. DIV_EN Register
DIV_EN
DESCRIPTION
0
Divider disabled and bypassed
1
Divider enabled
Table 10. DIV_FRC Register
DIV_FRC
(1)
DESCRIPTION
0
Input divider ratio = serialization factor (1) (automatically set)
1
Input divider ratio = DIV_REG (manually set)
The divider ratio is automatically calculated to the serialization factor value based on the CH_OUT_DIS[1:4] register bits; see Table 12.
Table 11. DIV_REG Register
DIV_REG
28
DESCRIPTION
0
Divider disabled and bypassed
1
Divide-by-2
2
Divide-by-3
3
Divide-by-4
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8.3.7 Data Output Serialization
The input signals are digitized by the dedicated channel ADCs. Digitized signals are multiplexed and output on
D[11:0] as parallel data.
The output data rate and the DCLK speed are automatically calculated based on the CH_OUT_DIS[1:4] bits. The
number of zeroes in these four bits is equal to the serialization factor for the output data. When the register bit is
set to 1, the output for the respective channel is disabled. The channels are arranged in ascending order, with
the lowest active channel output first and the highest active channel output last. CH_OUT_DIS[1:4] controls only
the output serialization and does not power-down individual channels. Table 12 lists the register values with the
respective serialization factors and output sequence.
Table 12. CH_OUT_DIS Register
CH_OUT_DIS[1]
CH_OUT_DIS[2]
CH_OUT_DIS[3]
CH_OUT_DIS[4]
SERIALIZATION
FACTOR
0
0
0
0
4
CH1 → CH2 → CH3 → CH4
1
0
0
0
3
CH2 → CH3 → CH4
0
1
0
0
3
CH1 → CH3 → CH4
1
1
0
0
2
CH3 → CH4
0
0
1
0
3
CH1 → CH2 → CH4
1
0
1
0
2
CH2 → CH4
0
1
1
0
2
CH1 → CH4
1
1
1
0
1
CH4
0
0
0
1
3
CH1 → CH2 → CH3
1
0
0
1
2
CH2 → CH3
0
1
0
1
2
CH1 → CH3
1
1
0
1
1
CH3
0
0
1
1
2
CH1 → CH2
1
0
1
1
1
CH2
0
1
1
1
1
CH1
1
1
1
1
1
Not supported
OUTPUT
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8.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
8.3.8.1 Main Channels
The device analog input consists of a differential LNA. The common-mode for the LNA inputs is internally set
using two internal, programmable, single-ended resistors, as shown in Figure 63.
INIP
RINTTERM_LNA
1k
LNA
RINTTERM_LNA
1k
INIM
Internal Voltage
Reference
CM_LNA Buffer
Device
Figure 63. Common-Mode Biasing of LNA Input Pins
These resistors can be programmed to a higher value using the TERM_INT_20K_LNA register setting as
described in Table 13.
Table 13. Internal Termination Register Setting (LNA)
TERM_INT_20K_LNA
DESCRIPTION
0
RINTTERM_LNA = 1 kΩ
1
RINTTERM_LNA = 10 kΩ
Hence, for proper operation, the input signal must be ac-coupled. Note that external input ac-coupling capacitors
form a high-pass filter (HPF) with RINTTERM_LNA. Therefore, the capacitor values should allow the lowest
frequency of interest to pass with minimum attenuation. For typical frequencies greater than 1 MHz, a value of 50
nF or greater is recommended. The maximum input swing is limited by the LNA gain setting. LNA output swing is
limited to 2 VPP before the output becomes saturated or distorted.
Single ended mode of operation is also possible by connecting non-driven input pin to ground through a
capacitor of 100 nF. However, this will result in reduced linearity.
30
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8.3.8.2 Auxiliary Channel
The auxiliary analog inputs (INIP_AUX, INIM _AUX) can be enabled instead of the INIP, INIM inputs using the
AUX_CHI_EN bits (Table 14). The auxiliary analog input signal path consists of an input unity-gain buffer
followed by an ADC. The LNA, PGA, equalizer, and antialiasing filter are bypassed and powered down in this
mode. Figure 64 shows the internal block diagram for auxiliary channel mode. When this mode is enabled, the
maximum input swing is limited to 2 VPP before the input becomes saturated or distorted.
Table 14. AUX_CHI_EN Register
AUX_CHI_EN
DESCRIPTION
0
INIP, INIM active, analog
1
INIP _AUX, INIM_AUX
INIP_AUX
RINTTERM_AUX
1k
BUF
RINTTERM_AUX
1k
INIM_AUX
Internal Voltage
Reference
VCM
CM_AUX Buffer
Device
NOTE: Dashed area denotes one of four channels.
Figure 64. Common-Mode Biasing of Auxiliary Channel Input Pins
The dc common-mode on the INIP_AUX, INIM _AUX pins are internally biased to the optimum voltage (referred
to as VCM).
The dc common-mode biasing is set with two internal, programmable, single-ended resistors (RINTTERM_AUX).
These resistors can be programmed to a higher value using the TERM_INT_20K_AUX register setting as
described in Table 15.
Table 15. Internal Termination Register Setting (AUX)
TERM_INT_20K_AUX
DESCRIPTION
0
RINTTERM_AUX = 1 kΩ
1
RINTTERM_AUX = 10 kΩ
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The auxiliary inputs can also be ac-coupled as a result of the internal common-mode setting. The external input
ac-coupling capacitors form a high-pass filter with RINTTERM_AUX. Therefore, the capacitor values should allow
the lowest frequency of interest to pass with minimum attenuation.
For typical frequencies greater than 1 MHz, a value of 50 nF or greater is recommended. For instances where
the input signal cannot be ac-coupled because of system requirements, it is recommended to use the VCM
output to set the dc common-mode of the input signal. The driving capability of VCM is limited. A 100-nF
capacitor should be connected on each VCM input to AVSS.
8.4 Device Functional Modes
8.4.1 Equalizer Mode
In some applications, the input signal power linearly decreases with signal frequency. Such types of input
spectrum can be equalized using a first-order signal equalizer. The device can be configured in two different
equalizer modes: EQ_EN and EQ_EN_LOW_FC. Table 16 lists the register settings for these modes.
• EQ_EN mode: In this mode, a high-pass filter (HPF) is added to the analog signal path between the LNA
output and PGA input.
• EQ_EN_LOW_FC mode: In this mode, attenuation from the HPF is limited to unity in the pass-band
frequency range.
Table 16. EQ_EN and EQ_EN_LOW_FC Registers
EQ_EN
EQ_EN_LOW_FC
0
0
Default mode
DESCRIPTION
0
1
Default mode
1
0
Equalizer enabled
1
1
Equalizer with low-corner frequency enabled
30
60
20
50
10
40
Channel Gain (dB)
Channel Gain (dB)
The HPF and LPF cutoff frequencies (of the antialiasing filter) are the same as per the FILTER_BW setting. In
this mode, overall channel gain increases by an additional fixed gain of 15 dB from the HPF block. Typical
frequency response plots showing different equalizer modes along with the default mode are shown in Figure 65
and Figure 66.
0
±10
±20
Default Mode (Eq_Dis)
±30
Eq_EN
±40
30
20
10
Default Mode (Eq_Dis)
0
Eq_EN
±10
Eq_EN_LOW_FC
Eq_EN_LOW_FC
±50
±20
0.1
1
10
fIN (MHz)
Figure 65. Filter Response (PGA Gain = 0 dB)
32
0.1
1
10
fIN (MHz)
C001
C001
Figure 66. Filter Response (PGA Gain = 30 dB)
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8.4.2 Data Output Mode
The functionality of DSYNC1, DSYNC2, DCLK, and D[11:0] are controlled by selecting the data output mode.
The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins for 4x serialization modes are shown
in Figure 67 and Figure 68. Any event on the TRIG pin triggers the DSYNC1 and DSYNC2 signals. The DSYNC1
period is determined by the COMP_DSYNC1 register value and the DSYNC2 period is determined by the
SAMPLE_COUNT register value. When OUT_MODE_EN = 0, data output is continuous. When OUT_MODE_EN
= 1, data is active only during the sample phase. Output pins are configured using the registers described in
Table 17 through Table 21.
CLKIN
INPUT
TRIG
CYCLE RESET
TRIG_INT
Pixel = 0
INTERNAL
Pixel = 1
Pixel = 2
tAFE_CLK
Pixel = 3
AFE_CLK
tOUT
Pixel = 0
D[11:0]
OUT_MODE_EN = 0
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
D[11:0]
OUT_MODE_EN = 1
CH1 CH2 CH3 CH4
CH1
CH1 CH2 CH3
(0)
(0)
(0)
CH4
(0)
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
Pixel = 1
CH1 CH2 CH3
(1)
(1)
(1)
Pixel = 2
CH4
(1)
Pixel = 3
CH1 CH2 CH3 CH4
(2)
(2)
(2)
(2)
CH1 CH2 CH3 CH4
(3)
(3)
(3)
(3)
CH1 CH2 CH3 CH4
(4)
(4)
(4)
(4)
CH1 CH2 CH3 CH4
(5)
(5)
(5)
(5)
CH1 CH2 CH3 CH4
(6)
(6)
(6)
(6)
CH1 CH2
CH1 CH2
CH1 CH2 CH3
(7)
(7)
(7)
CH3 CH4 CH1 CH2
CH3
CH4
(7)
CH1 CH2
(8)
(8)
CH3 CH4
(8)
(8)
CH4
CH1 CH2
CH3 CH4 CH1 CH2
CH1 CH2
(8)
(8)
CH3 CH4 CH1 CH2
(8)
(8)
(9)
(9)
CH3
(9)
DCLK
COMP_DSYNC1
COMP_DSYNC1
DSYNC1_HIGH
DSYNC1
OUTPUT
DSYNC2_LOW
SAMPLE PHASE
DSYNC2
DELAY PHASE
SAMPLE PHASE
DELAY PHASE
BLANKING PHASE
SAMPLE COUNT = N
TTRIG_DSYNC2_LAT
SAMPLE COUNT = N
tDSYNC2 = (N+1) * tAFE_CLK
tDSYNC2 = (N+1) * tAFE_CLK
Figure 67. Data Output Timing Diagram (4x Serialization)
CLKIN
Input
TRIG
TRIG_INT
Internal
Pixel = 0
Pixel = 1
Pixel = 2
tAFE_CLK
Pixel = 3
AFE_CLK
tOUT
Pixel = 0
D[11:0]
OUT_MODE_EN = 0
D[11:0]
OUT_MODE_EN = 1
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
Pixel = 1
Pixel = 2
Pixel = 3
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2
CH1 CH2 CH3 CH4
(0)
(0)
(0)
(0)
CH1
(1)
CH2 CH3
(1)
(1)
CH4
(1)
CH1 CH2 CH3 CH4
(2)
(2)
(2)
(2)
CH1 CH2 CH3 CH4
(3)
(3)
(3)
(3)
CH1 CH2
(4)
(4)
CH3 CH4
(4)
(4)
CH1 CH2 CH3 CH4
(5)
(5)
(5)
(5)
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2
CH1 CH2 CH3 CH4
(0)
(0)
(0)
(0)
CH1
(1)
CH2 CH3
(1)
(1)
CH4
(1)
CH1 CH2 CH3 CH4
(2)
(2)
(2)
(2)
CH1 CH2 CH3 CH4
(3)
(3)
(3)
(3)
CH1 CH2
(4)
(4)
CH3 CH4
(4)
(4)
CH1 CH2 CH3 CH4
(5)
(5)
(5)
(5)
CH1 CH2 CH3 CH4
(6)
(6)
(6)
(6)
CH1 CH2 CH3
(7)
(7)
(7)
CH4
(7)
CH1 CH2
(8)
(8)
CH3 CH4
(8)
(8)
DCLK
Output
DSYNC1 COMP_DSYNC1 = 2
DSYNC2
SAMPLE_COUNT = N
tDSYNC2 = (N+1) x tAFE_CLK
Figure 68. Data Output Timing Diagram (4x Serialization, Input Divider Enabled)
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Table 17. Register Functions
REGISTER
DELAY_COUNT[23:0]
FUNCTION
From a TRIG event, the sample phase is delayed for a DELAY_COUNT number of tAFE_CLK cycles
SAMPLE_COUNT[23:0]
From the end of DELAY_PHASE, the sample phase duration is the SAMPLE_COUNT number of
tAFE_CLK cycles
COMP_DSYNC1[15:0]
DSYNC1 period in number of tAFE_CLKcycles
Table 18. DSYNC1_START_LOW Register
DSYNC1_START_LOW
DESCRIPTION
0
DSYNC1 is high at the sample phase start
1
DSYNC1 is low at the sample phase start
Table 19. OUT_MODE_EN Register
OUT_MODE_EN
DESCRIPTION
0
Data always active
1
Data active in sample phase
Table 20. DSYNC_EN Register
DSYNC_EN
DESCRIPTION
0
Disable DSYNC generation
1
Enable DSYNC generation
Table 21. OUT_BLANK_HIZ Register
OUT_BLANK_HIZ
DESCRIPTION
0
D[11:0] is low during inactive phase
1
D[11:0] is high impedance during inactive phase
NOTE
The signal processing blocks in the device are always active and are not controlled by
output mode configuration settings.
34
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The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins with the input divider enabled for 3x
serializations is shown in Figure 69.
CLKIN
INPUT
TRIG
TRIG_INT
Pixel = 0 Pixel = 1 Pixel = 2 Pixel = 3
INTERNAL
tAFE_CLK
AFE_CLK
D[11:0]
OUT_MODE_EN = 0
Pixel = 0 Pixel = 1 Pixel = 2 Pixel = 3
CH1 CH2
CH3
CH1 CH2
CH3
CH1 CH2 CH3
CH1 CH2 CH3
D[11:0]
OUT_MODE_EN = 1
CH1 CH2 CH3
CH1 CH2 CH3
CH1
CH2 CH3
CH1 CH2 CH3
(0)
(0)
(0)
CH1 CH2 CH3
(1)
(1)
(1)
CH1 CH2
(2)
(2)
CH3
(2)
CH1 CH2 CH3
(3)
(3)
(3)
CH1 CH2 CH3
(4)
(4)
(4)
CH1 CH2 CH3
(5)
(5)
(5)
CH1 CH2 CH3
(6)
(6)
(6)
CH1 CH2 CH3
(7)
(7)
(7)
CH1 CH2 CH3
CH1 CH2 CH3
CH1
CH2 CH3
CH1 CH2 CH3
(0)
(0)
(0)
CH1 CH2 CH3
(1)
(1)
(1)
CH1 CH2
(2)
(2)
CH3
(2)
CH1 CH2 CH3
(3)
(3)
(3)
CH1 CH2 CH3
(4)
(4)
(4)
CH1 CH2 CH3
(5)
(5)
(5)
CH1 CH2 CH3
(6)
(6)
(6)
CH1 CH2 CH3
(7)
(7)
(7)
CH1 CH2
(8)
(8)
CH3 CH1
(8)
(9)
CH2 CH3
(9)
(9)
CH1 CH2 CH3
(10) (10) (10)
CH1 CH2 CH3
(11) (11) (11)
CH1 CH2 CH3
(12) (12) (12)
CH1
(13)
DCLK
OUTPUT
DSYNC1
COMP_DSYNC1=2
DSYNC2
SAMPLE COUNT = N
tDSYNC2 = (N+1)* tAFE_CLK
Figure 69. Data Output Timing (3x Serialization, Input Divider Enabled)
The TRIG to DSYNC2 latency is given by Table 22.
Table 22. TRIG to DSYNC2 Latency across Serialization Modes for AFE_CLK = 25 MHz
(1)
Serialization Modes
TTRIG_DSYNC2_LAT (1)
Units
4x
230
ns
3x
230
ns
2x
240
ns
1x
250
ns
The TRIG_DSYNC2_LAT delay can vary by ± 8 ns.
8.4.2.1 Header
Each channel has an associated 12-bit header register. These registers can be written by an SPI write. The
content of this register can be read out on the CMOS data output (D[11:0]) by configuring the HEADER_MODE
register, as shown in Table 23.
Table 23. HEADER_MODE Register
HEADER_MODE
DESCRIPTION
0
ADC data at output
1
Header data at output
2
[Temperature data, diagnostic data, mean, noise, (-1), (-1), (-1), (-1)]. This data sequence is repeated.
3
Header data, temperature data, diagnostic data, mean, noise, ADC data
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In HEADER_MODE = 3, the header mode data output is shown in Figure 70.
In this mode, header data is transmitted with a latency with respect to the TRIG input. This latency is given by
Equation 2:
TRIG to Header Latency (TTRIG_HEADER_LAT) = tAFE_CLK + TTRIG_DSYNC2_LAT
(2)
TRIG
CLKIN
AFE_CLK
TRIG_INT
ADC
CH4
ADC
CH3
ADC
CH1
ADC
CH2
Noise
CH3
Noise
CH4
Noise
CH1
Noise
CH2
Mean
CH4
Mean
CH3
Mean
CH2
Mean
CH1
DIAG
DIAG
DIAG
DIAG
Temp
Data
Temp
Data
Temp
Data
Temp
Data
Header
CH4
Header
CH3
DATA
Header
CH2
Header
CH1
DCLK
TTRIG_DSYNC2_LAT
DSYNC2
TTRIG_HEADER_LAT
Figure 70. Header Mode Data Output (HEADER_MODE = 3)
8.4.2.2 Test Pattern Mode
In order to check the interface between the AFE and the receiver system, a test pattern can be directly
programmed on the CMOS output. As shown in Table 24, different test patterns can be selected by setting the
TST_PAT_MODE register.
Table 24. TST_PAT_MODE Register (1)
TST_PAT_MODE
(1)
36
DESCRIPTION
0
Normal ADC output data
1
SYNC pattern (D[11:0] = 111111000000)
2
Deskew pattern (D[11:0] = 010101010101)
3
Custom pattern as per CUSTOM_PATTERN[11:0] register bits
4
All 1s
5
Toggle data (output toggles between all 0s and all 1s)
6
All 0s
7
Full-scale ramp data
In decimate-by-2 mode, alternate samples are dropped and thus output data D0 does not toggle for full-scale ramp data and output data
D[11:0] does not toggle for toggle data.
Similarly, in decimate-by-4 mode, three samples are dropped and thus output data D0 and D1 do not toggle for full-scale ramp data and
output data D[11:0] does not toggle for toggle data.
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8.4.3 Parity
Parity for each output sample of an active channel can be read on the D_GPO[1:0] pins by configuring these pins
with the DGPO1_MODE, DGPO0_MODE register, as shown in Table 25. Parity generation can be enabled using
the D_GPO_EN bit, as shown in Table 26. The type of parity generation can be configured to odd or even based
on the PARITY_ODD bit, as shown in Table 27.
Table 25. DGPO0_MODE, DGPO1_MODE Register
DGPO0_MODE, DGPO1_MODE
DESCRIPTION
0
Low
1
Parity
2
Overload
3
D[11]
Table 26. D_GPO_EN Register
D_GPO_EN
DESCRIPTION
0
D_GPO[x] pins are disabled
1
D_GPO[x] pins are enabled
Table 27. PARITY_ODD Register
PARITY_ODD
DESCRIPTION
0
Even
1
Odd
8.4.4 Standby, Power-Down Mode
The device can be put into standby mode with the STDBY register bit. In this mode, all blocks except the ADC
reference blocks are powered down. In GLOBAL_PDN mode, all blocks including the ADC reference blocks are
powered down. However, in both modes, the serial interface is active.
8.4.5 Digital Filtering to Improve Stop-Band Attenuation
The device introduces a standard 11-tap, symmetric finite impulse response (FIR) digital filter for additional stopband attenuation in decimate-by-2 and decimate-by-4 modes. In both modes, the FIR digital filter coefficients (C1
to C6) must be configured to obtain the desired filter characteristics. However, set 1 coefficients are loaded by
default at device reset.
In this mode, device power consumption increases and the DSYNC period scales according to the decimation
mode (the DSYNC period increases by 2x in decimate-by-2 mode and 4x in decimate-by-4 mode when
compared to normal mode). Maximum AFE_CLK frequency supported in the decimation modes is 50 MHz.
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8.4.5.1 Decimate-by-2 Mode
In this mode, the DECIMATE_2_EN and FILT_EN register bits must be set, and the filter coefficients should be
configured. Figure 71 shows typical filter response in decimate-by-2 mode for the filter coefficient of set 1
(default). Note that the output data rate is reduced by a factor of 2 as compared to default mode for the given
clock input frequency.
20
10
Channel Gain (dB)
0
±10
±20
±30
±40
±50
±60
Default Mode
±70
DECIMATE_2_EN = 1
±80
0.1
1
10
fIN (MHz)
C037
Figure 71. Decimate-by-2 Filter Response (fS = 50 MHz)
8.4.5.2 Decimate-by-4 Mode
In this mode, the DECIMATE_2_EN, DECIMATE_4_EN, and FILT_EN register bits must be set, and the filter
coefficients should be configured. Figure 72 shows a typical filter response in decimate-by-4 mode for the filter
coefficient of set 1 (default) and set 2. Note that the output data rate is reduced by a factor of 4 as compared to
default mode for the given clock input frequency.
10
Channel Gain (dB)
0
±10
±20
±30
±40
±50
DECIMATE_4_EN = 1, Set 2
±60
DECIMATE_4_EN = 1, Set 1
±70
0.1
1
fIN (MHz)
C038
(1) Set 1: C1 = 5, C2 = 2, C3 = –13, C4 = –2, C5 = 38, and C6 = 66. Set 2: C1 = –5, C2 = –2, C3 = 7, C4 = 19, C5 = 30, and C6 = 34.
Figure 72. Decimate-by-4 Filter Response (fS = 12.5 MHz)
8.4.6 Diagnostic Mode
The device offers various diagnostic modes to check proper device operation at a system level. These modes
can be enabled using the SPI and the outputs of these modes are stored in diagnostic read-only registers.
1. Internal reference status check: In this mode, the on-chip band-gap voltage, ADC reference, and clock
generation are verified for functionality. Reading a 0 on these bits indicates that these blocks are functioning
properly. The DIAG_MODE_EN register bit must be set to 1. The DIG_REG register bits for this mode are:
– DIG_REG[0] for ADC references,
– DIG_REG[1] for band gap, and
– DIG_REG[2] for clock generation.
38
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2. DC input force: In this mode, a dc voltage can be internally forced at the LNA input to test the entire signal
chain. During this test, the device analog inputs should be left floating. This mode can be asserted by setting
the DC_INP_EN bit to 1 and programming the DC_INP_PROG[0:2] bits. In this mode, the equalizer is
disabled internally.
3. Variance (noise) and mean measurement: Variance and mean of the ADC output can be analyzed using the
on-chip STAT module. The STAT_EN, STAT_CALC_CYCLE, and STAT_CH_SEL, STAT_CH_AUTO_SEL
options should be set to compute the variance and mean. These values can be monitored using channelspecific, read-only registers. Alternatively, these values can also be read using HEADER_MODE. Output
variance and mean calculation is determined by Equation 3.
(3)
STAT_CALC_CYCLE must be set to a large value to obtain better accuracy. Mean provides the average dc
value of the ADC output (mid code). The STAT module integration time is defined by: tAFE_CLK ×
2(STAT_CALC_CYCLE+1) when the STAT_CH_SEL option is selected. When STAT_CH_AUTO_SEL is enabled,
the STAT module integration time is defined by: 4 × tAFE_CLK × 2(STAT_CALC_CYCLE+1).
4. Temperature sensor: The device junction temperature measurement can be enabled and monitored using
TEMP_SENS_EN and TEMP_CONV_EN. The temperature output is saved in a diagnostic read-only
register, TEMP_DATA. Alternatively, this data can also be read using HEADER_MODE. The TEMP_DATA
value is a 9-bit, twos complement data in degrees Celsius. The temperature data is internally updated as per
Equation 4:
Temperature Data Update Cycle = 1024 × TAFE_CLK × 16
(4)
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8.4.7 Signal Chain Probe
To enhance system-level debug capabilities, the device offers a mode where the output of each block in the
signal chain can be connected to the ADC input. With this mode, internal signals can be easily monitored to
ensure that each block output is not saturated. Figure 73 shows the device signal chain block diagram. Figure 74
and Figure 75 show typical frequency response plots at the output of each stage.
LNA
AMP 1
AMP 2
AMP 3
MUX
PGA + Antialiasing Filter
ADC
VOUT_ON_ADC[1:0]
20
45
15
40
10
35
Channel Gain (dB)
Channel Gain (dB)
Figure 73. Signal Chain Block Diagram
5
0
±5
±10
AMP1_OUT_ADC
±15
20
15
10
AMP1_OUT_ADC
AMP2_OUT_ADC
0
LNA_OUT_ADC
±25
LNA_OUT_ADC
±5
0.1
1
0.1
10
fIN (MHz)
1
10
fIN (MHz)
C001
Figure 74. Frequency Response for
VOUT_ON_ADC Settings (PGA Gain = 0 dB)
40
25
5
AMP2_OUT_ADC
±20
30
C001
Figure 75. Frequency Response for
VOUT_ON_ADC Settings (PGA Gain = 30 dB)
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8.5 Programming
8.5.1 Serial Interface
Different modes can be programmed through the serial interface formed by the SEN (serial interface enable),
SCLK (serial interface clock), SDATA (serial interface data) and RESET pins. SCLK and SDATA have a 150-kΩ
pull-down resistor to ground and SEN has a 150-kΩ pull-up resistor to DVDD18. Serially shifting bits into the
device is enabled when SEN is low. SDATA serial data bits are latched at every SCLK rising edge when SEN is
active (low). Serial data bits are loaded into the register at every 24th SCLK rising edge when SEN is low. If the
word length exceeds a multiple of 24 bits, the excess bits are ignored. Data bits can be loaded in multiples of 24bit words within a single active SEN pulse (an internal counter counts groups of 24 clocks after the SEN falling
edge). The interface can function with SCLK frequencies from 20 MHz down to very low speeds and even with a
non-50% duty-cycle SCLK. Data bits are divided into two main portions: a register address (8 bits, A[7:0]) and
data (16 bits, D[15:0]).
8.5.2 Register Initialization
After power up, the internal registers must be initialized to the default value (0). Initialization can be accomplished
in one of two ways:
• Either through a hardware reset, by applying a positive pulse to the RESET pin, or
• Through a software reset with the serial interface, by setting the SW_RST bit high. Setting this bit initializes
the internal registers to the respective default values (all 0s) and then self-resets the SW_RST bit low. In this
case, the RESET pin can stay low (inactive).
•
•
•
NOTE
No damage occurs to the part by applying voltage to the RESET pin while device
power is off.
For correct device operation, a positive pulse must be applied to the RESET pin. This
pulse sets the internal control registers to 0. However, no power-supply sequencing is
required.
Reset only affects the digital registers and places the device in a default state. Reset
does not function as a power-down and, therefore, all internal blocks are functional.
During a register write through the SPI, the effects on data propagate through the pipe while the internal registers
change values. At the same time, some glitches may be present on the output because of the transition of
register values (for instance, if any output-controlling modes change). The signal on the RESET pin must be low
in order to write to the internal registers because reset is level-sensitive and asynchronous with the input clock.
Although only 40 ns are required after the RESET rising edge to change the registers, the output data may take
up to 20 clock cycles (worst-case) to be considered stable. For more information on RESET, see the Timing
Requirements: RESET.
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Programming (continued)
8.5.2.1 Register Write Mode
In register write mode, the REG_READ_EN bit must be set to 0. In this mode, the SDOUT signal outputs 0.
Figure 76 shows this process.
SEN
End Sequence
t6
t1
SCLK
t7
Data latched on rising edge of SCLK
t2
t3
A[7]
SDATA
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
t4
t5
SDOUT
Figure 76. Serial Interface Register Write
8.5.2.2 Register Read Mode
In register readout mode, the REG_READ_EN bit must be set to 1. Then, a serial interface cycle should be
initiated, specifying the address of the register (A[7:0]) whose content must be read out of the device. The data
bits are don’t care. The device outputs the contents (D[15:0]) of the selected register on the SDOUT pin. The
external controller latches the data on SDOUT at the SCLK rising edge. Figure 77 shows this process.
The timing specifications for the serial interface operation is listed in the Timing Requirements: Serial Interface
Operation.
SEN
End Sequence
t6
t1
t7
t2
SCLK
t3
A[7]
SDATA
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
X
X
t4
t5
t8
X
X
X
X
X
X
X
X
X
X
X
X
D[3]
D[2]
X
X
SDOUT to be latched externally on rising
edge
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[1]
D[0]
SDOUT
Figure 77. Serial Interface Register Readout Enable
42
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Programming (continued)
8.5.3 CMOS Output Interface
The digital data from the four channels are multiplexed and output over a 12-bit parallel CMOS bus to reduce the
device pin count. In addition to the data, a CMOS clock (DCLK) is also output, which can be used by the digital
receiver to latch the AFE output data. The output data and clock buffers can typically drive a 5-pF load
capacitance in default mode. To drive larger loads (10 pF to 15 pF), the strength of the CMOS output buffers can
be increased using the STR_CTRL_CLK and STR_CTRL_DATA register bits. Note that the setup and hold time
of the output data (with respect to DCLK) degrade with higher load capacitances. See Table 1, which provides
timings for 5-pF and 15-pF load capacitances.
8.5.3.1 Synchronization and Triggering
While the digital data from the four channels is multiplexed on the output bus, some mechanism is required to
identify the data from the individual channels. Other than the output data and DCLK, the device also outputs
DSYNCx signals that can be used for channel identification.
The DSYNCx output signals function with the TRIG input signal. Every time that a trigger pulse is received on the
TRIG pin, the device outputs the DSYNC1 and DSYNC2 signals. The DSYNCx signals can be configured in the
following ways:
• The delay between the arrival of the TRIG signal and the DSYNCx signal becoming active is programmable in
a number of AFE_CLK cycles (using the DELAY_COUNT register bit).
• The period of the DSYNC1 signal is programmable in terms of AFE_CLK clock cycles by using the
COMP_DSYNC1 register bits.
• The active time of the DSYNC2 signal is programmable using the SAMPLE_COUNT register bits.
The rising edge of the DSYNC1 signal coincides with the channel 1 data, as shown in Figure 78. This occurrence
can be used by the receiving device to identify individual channels.
The sample phase period corresponds to the period when valid data is available from the device when
OUT_MODE_EN = 1.
CLKIN
INPUT
TRIG
CYCLE RESET
TRIG_INT
Pixel = 0
INTERNAL
Pixel = 1
Pixel = 2
tAFE_CLK
Pixel = 3
AFE_CLK
tOUT
Pixel = 0
D[11:0]
OUT_MODE_EN = 0
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
D[11:0]
OUT_MODE_EN = 1
CH1 CH2 CH3 CH4
CH1
CH1 CH2 CH3
(0)
(0)
(0)
CH4
(0)
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
CH1 CH2 CH3 CH4
Pixel = 1
CH1 CH2 CH3
(1)
(1)
(1)
CH4
(1)
Pixel = 2
CH1 CH2 CH3 CH4
(2)
(2)
(2)
(2)
Pixel = 3
CH1 CH2 CH3 CH4
(3)
(3)
(3)
(3)
CH1 CH2 CH3 CH4
(4)
(4)
(4)
(4)
CH1 CH2 CH3 CH4
(5)
(5)
(5)
(5)
CH1 CH2 CH3 CH4
(6)
(6)
(6)
(6)
CH1 CH2
CH1 CH2
CH1 CH2 CH3
(7)
(7)
(7)
CH3 CH4 CH1 CH2
CH3
CH4
(7)
CH1 CH2
(8)
(8)
CH3 CH4
(8)
(8)
CH4
CH1 CH2
CH3 CH4 CH1 CH2
CH1 CH2
(8)
(8)
CH3 CH4 CH1 CH2
(8)
(8)
(9)
(9)
CH3
(9)
DCLK
COMP_DSYNC1
COMP_DSYNC1
DSYNC1_HIGH
DSYNC1
OUTPUT
SAMPLE PHASE
DSYNC2
DELAY PHASE
DSYNC2_LOW
BLANKING PHASE
SAMPLE PHASE
DELAY PHASE
SAMPLE COUNT = N
TTRIG_DSYNC2_LAT
SAMPLE COUNT = N
tDSYNC2 = (N+1) * tAFE_CLK
tDSYNC2 = (N+1) * tAFE_CLK
Figure 78. DSYNCx Timing Diagram
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8.6 Register Maps
8.6.1 Functional Register Map
Table 28 shows the register map for the AFE5401 registers.
Table 28. Register Map
REGISTER
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
0 (00h)
0
0
0
0
0
0
0
0
0
1 (01h)
0
0
0
0
0
STDBY
0
0
DECIMATE
_4_EN
DIV_REG
0
0
0
DGPO0_MODE
2 (02h)
0
0
0
3 (03h)
0
TST_PAT_MODE
0
0
0
0
0
4 (04h)
OUT_
BLANK_HIZ
OUT_
MODE_EN
DCLK_
INVERT
TEMP_
CONV_EN
TEMP_
SENS_EN
0
0
BIT 4
BIT 3
BIT 1
BIT 0
SW_RST
0
0
0
REG_
READ_EN
DIV_FRC
DECIMATE
_2_EN
DIV_EN
SE_CLK_
MODE
GLOBAL_
PDN
0
0
0
0
0
0
0
DGPO1_MODE
TEMP_DATA
0
5 (05h)
0
0
0
0
0
OFF_BIN_
DATA_FMT
0
CUSTOM_PAT
6 (06h)
7 (07h)
0
0
D_GPO_EN
PARITY_
ODD
0
0
STAT_ EN
DCP_INP_
EN
0
0
0
DCP_INP_PROG
0
0
0
0
0
DIAG_
MODE_EN
0
0
0
0
DIAG_REG
FILTER_BW
8 (08h)
C2_FIR
DIG_GAIN_C1_FIR
9 (09h)
C4_FIR
C3_FIR
10 (0Ah)
C6_FIR
15 (0Fh)
0
0
19 (13h)
0
OB_
DISABLE
0
0
0
0
0
0
0
STR_CTRL_DATA
0
0
0
0
0
0
0
0
0
0
0
0
DELAY_COUNT[23:16]
SAMPLE_COUNT[23:16]
22 (16h)
DELAY_COUNT[15:0]
23 (17h)
24 (18h)
HEADER_MODE
C5_FIR
FAST_
DGPO
STR_CTRL_CLK
21 (15h)
SAMPLE_COUNT[15:0]
TRIG_FALL
DSYNC1_
START_
LOW
25 (19h)
0
DSYNC_EN
0
COMP_DSYNC1[15:6]
COMP_DSYNC1[5:0]
0
26 (1Ah)
0
0
DSYNC2_LOW[23:16]
DSYNC2_LOW[15:0]
27 (1Bh)
DSYNC1_HIGH
29 (1Dh)
OFFSET_
DIS
0
STAT_CH_SEL
0
0
30 (1Eh)
0
0
0
0
0
0
32 (20h)
0
0
0
0
33 (21h)
CH_OUT_
DIS1
AUX_CH1_
EN
PDN_CH1
INVERT_
CH1
34 (22h)
0
0
MEAN_CH1
35 (23h)
0
0
NOISE_CH1
36 (24h)
0
0
44
BIT 2
0
STAT_CALC_CYCLE
0
MULT_EN
FILT_EN
0
0
0
0
0
0
STAT_CH_
AUTO_SEL
0
0
0
0
0
HEADER_CH1
0
0
OFFSET_CH1
0
HEADER_CH2
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
37 (25h)
CH_OUT_
DIS2
AUX_CH2_
EN
PDN_CH2
INVERT_
CH2
0
0
BIT 9
BIT 8
BIT 7
BIT 6
38 (26h)
0
0
MEAN_CH2
39 (27h)
0
0
NOISE_CH2
0
0
0
0
41 (29h)
CH_OUT_
DIS3
AUX_CH3_
EN
PDN_CH3
INVERT_
CH3
42 (2A)
0
0
MEAN_CH3
43(2B)
0
0
NOISE_CH3
0
0
0
0
0
CH_OUT_
DIS4
AUX_CH4_
EN
PDN_CH4
INVERT_
CH4
46(2Eh)
0
0
MEAN_CH4
47(2Fh)
0
0
NOISE_CH4
65 (41h)
0
0
69 (45h)
TERM_INT_
20K_LNA
70 (46h)
0
71(47h)
0
100(64h)
0
0
0
0
0
HF_AFE_CLK_EN
BIT 0
OFFSET_CH4
TERM_INT_
20K_AUX
0
0
0
PGA_GAIN
0
BIT 1
HEADER_CH4
0
LNA_GAIN
0
BIT 2
OFFSET_CH3
45 (2Dh)
HPL_EN
BIT 3
HEADER_CH3
0
44 (2Ch)
0
BIT 4
OFFSET_CH2
40 (28h)
0
BIT 5
0
0
0
0
0
0
0
0
0
0
0
0
EQ_EN
0
0
0
0
0
0
0
0
0
0
0
VOUT_ON_ADC
EQ_
EN_LOW
_FC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HIGH_
POW_LNA
0
0
0
0
0
0
0
0
0
0
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8.6.2 Register Descriptions
Figure 79. Register 0 (00h)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
0
0
0
0
0
0
0
1
REG_READ_
EN
Bits 15:2
Must write 0
Bit 1
REG_READ_EN: Register read mode
SW_RST
0 = Write (default)
1 = Enable register read
Bit 0
SW_RST: Software reset
This bit is the software reset for the entire device. This bit is self-clearing.
Figure 80. Register 1 (01h)
15
0
14
0
13
0
12
0
11
0
10
STDBY
9
0
8
0
7
DECIMATE_4_
EN
6
5
4
3
DECIMATE_2_
EN
2
1
SE_CLK_
MODE
0
DIV_REG
DIV_FRC
Bits 15:11
Must write 0
Bit 10
STDBY: Full device standby
DIV_EN
GLOBAL_PDN
0 = Normal (default)
1 = Standby
Bits 9:8
Must write 0
Bit 7
DECIMATE_4_EN
0 = Decimate-by-4 mode not enabled
1 = Decimate-by-4 mode enabled
The DECIMATE_2_EN and FILT_EN bits must be set.
FIR filter coefficients (C1 to C6) must be written for proper operation.
If the AFE_CLK frequency > 25 MHz, then HF_AFE_CLK_EN must be set.
Bits 6:5
Bit 4
DIV_REG: Input clock divider ratio in DIV_FRC mode
DIV_REG
fAFE_CLK
0
CLKIN ÷ 1
1
CLKIN ÷ 2
2
CLKIN ÷ 3
3
CLKIN ÷ 4
Input divider disabled and bypassed
DIV_FRC: Force input divider ratio
0 = Auto computed based on CH_OUT_DISx (default). For more details, refer to Table 12.
1 = AFE clock frequency is based on DIV_REG settings
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Bit 3
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DECIMATE_2_EN
0 = Normal mode
1 = Decimate-by-2 mode enabled
The FILT_EN bit must be set for proper operation.
FIR filter coefficients (C1 to C6) must be written for proper operation.
If the AFE_CLK frequency > 25 MHz, then HF_AFE_CLK_EN must also be set.
Bit 2
DIV_EN: Enable CLKIN divider
0 = Disabled and bypassed (default)
1 = Enabled
Bit 1
SE_CLK_MODE: Single-ended input clock configuration
0 = Differential (default)
1 = Single-ended
Bit 0
GLOBAL_PDN: Full device power-down
0 = Normal (default)
1 = Global PDN
Figure 81. Register 2 (02h)
15
14
TST_PAT_MODE
13
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
0
1
0
0
0
Bits 15:13
DGPO0_MODE
DGPO1_MODE
TST_PAT_MODE: Test pattern for CMOS output
0
1
2
3
4
5
6
7
=
=
=
=
=
=
=
=
Normal (default)
SYNC
Deskew
Custom register 5[15:0]
All 1s
Toggle
All 0s
Ramp
Bits 12:7
Must write 0
Bits 6:5
DGPO0_MODE: DGPO0 mode configuration
0
1
2
3
Bits 4:3
Low (default)
Parity
Overload
D[11]
DGPO1_MODE: DGPO1 mode configuration
0
1
2
3
Bits 2:0
=
=
=
=
=
=
=
=
Low (default)
Parity
Overload
D[11]
Must write 0
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Figure 82. Register 3 (03h)
15
0
14
0
13
0
12
0
7
6
5
4
11
0
10
0
9
8
3
2
1
0
8
0
TEMP_DATA
TEMP_DATA
Bits 15:10
Ignore bits
Bits 9:0
TEMP_DATA: Read-only temperature readout register
Data is 9-bit, twos complement format in degrees Celsius.
Figure 83. Register 4 (04h)
15
OUT_BLANK_
HIZ
14
OUT_MODE_
EN
7
6
0
0
Bit 15
13
12
TEMP_CONV_
EN
11
TEMP_SENS_
EN
10
9
0
0
5
4
2
1
0
0
3
OFF_BIN_
DATA_FMT
0
0
DCLK_INVERT
0
0
OUT_BLANK_HIZ: Output status during blanking phase
0 = D[11:0] and D_GPO[1:0] are low (default) if EN_OUT_MODE = 1
1 = D[11:0] and D_GPO[1:0] are Hi-Z if EN_OUT_MODE = 1
For more details, refer to Figure 67.
Bit 14
OUT_MODE_EN: Enables output mode gating with DSYNC2
0 = CMOS data is always active (default)
1 = Output mode enabled. Data is transmitted only during sample phase.
Bit 13
DCLK_INVERT: Invert DCLK
0 = DCLK rising edge at the center of data (default)
1 = DCLK falling edge at the center of data
Bit 12
TEMP_CONV_EN: Enable Temperature Sensor output to digital conversion
0 = Hold conversion
1 = Convert
Bit 11
TEMP_SENS_EN: Enable temperature sensor block
0 = Disable temperature sensor
1 = Enable temperature sensor
Bits 10:4
Must write 0
Bit 3
OFF_BIN_DATA_FMT: Output data format
0 = Twos complement (default)
1 = Offset binary
Bits 2:0
48
Must write 0
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Figure 84. Register 5 (05h)
15
14
13
12
11
CUSTOM_PAT
10
9
8
7
6
5
4
2
1
0
3
CUSTOM_PAT
Bits 15:0
CUSTOM_PAT: Custom pattern data
These bits set the custom data pattern.
Figure 85. Register 6 (06h)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
DIAG_REG[2:0]
0
10
DC_INP_PROG
9
8
DIAG_MODE_
EN
Bits 15:3
Ignore bits
Bits 2:0
DIAG_REG: Read only diagnostic readout register
DIAG_REG[0] = 0: ADC references are correct
DIAG_REG[1] = 0: Indicates band gap is correct
DIAG_REG[2] = 0: Indicates clock generation is correct
Figure 86. Register 7 (07h)
15
D_GPO_EN
14
PARITY_ODD
13
STAT_EN
12
DC_INP_EN
11
7
0
6
0
5
0
4
0
3
Bit 15
2
1
0
HEADER_MODE
FILTER_BW
D_GPO_EN: Enable D_GPO functionality
0 = D_GPO[x] pins are disabled (default)
1 = D_GPO[x] pins are enabled
Bit 14
PARITY_ODD: Parity type
0 = Even (default)
1 = Odd
Bit 13
STAT_EN: Enable noise and mean calculation of ADC output
0 = Default
1 = Enables noise and mean computation if STAT_CALC_CYCLE is set.
Bit 12
DC_INP_EN: Enable dc analog voltage at LNA input. In this mode, equalizer is
disabled automatically.
0 = Normal
1 = DC input force is controlled by DC_INP_PROG.
Bits 11:9
DC_INP_PROG: DC Input programmability
0
1
2
3
=
=
=
=
0 mV
0 mV
50 mV
–50 mV
4
5
6
7
=
=
=
=
100 mV
–100 mV
100 mV
–100 mV
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Bit 8
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DIAG_MODE_EN: Enable diagnostic mode
0 = Disable diagnostic circuit
1 = Enable diagnostic circuit
Bits 7:4
Must write 0
Bits 3:2
FILTER_BW: Filter corner frequency
0
1
2
3
Bits 1:0
=
=
=
=
8 MHz (default)
7 MHz
10.5 MHz
12 MHz
HEADER_MODE: Header output mode
0 = ADC data at output (default)
1 = Header data at output
2 = [Temperature data, diagnostic data, mean, noise, (-1), (-1), (-1), (-1)]. This data
sequence is repeated.
3 = Header data, temperature data, diagnostic data, mean, noise, ADC data.
Refer to Figure 70 for more information.
Figure 87. Register 8 (08h)
15
14
13
12
11
10
9
8
4
3
DIG_GAIN_C1_FIR
2
1
0
C2_FIR
7
Bits 15:8
6
5
C2_FIR: Coefficient C2 for FIR digital filter
(1)
2 = Default value
Bit 7:0
DIG_GAIN_C1_FIR: Digital Gain common for all channels, coefficient C1 for
decimation filter
where:
•
(DIG_GAIN + 32) is Mod (2) 128.
(5)
Refer to Figure 60 for more information.
Mode
C1 Functionality
With MULT_EN
DIG_GAIN
With DECIMATE_X _EN
Coefficient C1 for FIR digital filter
5 = Default value
(1)
(2)
50
C1 to C6 FIR filter coefficients are in twos complement form.
Mod = Remainder of the division.
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Figure 88. Register 9 (09h)
15
14
13
12
11
10
9
8
3
2
1
0
11
10
9
8
3
2
1
0
C4_FIR
7
6
5
4
C3_FIR
Bits 15:8
C4_FIR: Coefficient C4 for FIR digital filter (1)
–2 = Default value
Bit 7:0
C3_FIR: Coefficient C3 for FIR digital filter (1)
–13 = Default value
(1)
C1 to C6 FIR filter coefficients are in twos complement form.
Figure 89. Register 10 (0Ah)
15
14
13
12
C6_FIR
7
6
5
4
C5_FIR
Bits 15:8
C6_FIR: Coefficient C6 for FIR digital filter (1)
66 = Default value
Bit 7:0
C5_FIR: Coefficient C5 for FIR digital filter (1)
38 = Default value
(1)
C1 to C6 FIR filter coefficients are in twos complement form.
Figure 90. Register 15 (0Fh)
15
0
14
0
13
0
12
0
11
0
10
FAST_DGPO
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Bits 15:11,
and Bits 9:0
Must write 0
Bit 10
FAST_DGPO: Fast DGPO output buffer
0 = Default strength (default)
1 = Higher drive strength on D_GPO[x] pins.
Must write 0
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Figure 91. Register 19 (13h)
15
0
14
OB_DISABLE
7
6
STR_CTRL_DATA
13
12
11
STR_CTRL_CLK
10
9
8
STR_CTRL_DATA
5
0
4
0
2
0
1
0
3
0
0
0
Bits 15, Bits 5:0 Must write 0
Bit 14
OB_DISABLE: CMOS output buffers D[11:0], DCLK disabled
0 = Active CMOS output buffers
1 = Hi-Z CMOS output Buffers
Bits 13:10
STR_CTRL_CLK: Controls strength of CMOS output DCLK
buffer
STR_CTRL_CLK
Drive Strength
DRVDD (V)
0
Default strength (CLOAD = 5 pF)
3.3
6
Maximum strength (CLOAD = 15 pF)
3.3
5
Default strength (CLOAD = 5 pF)
1.8
14
Maximum strength (CLOAD = 15 pF)
1.8
All other options are reserved.
Bit 9:6
STR_CTRL_DATA: Controls strength of CMOS output DATA
buffers
STR_CTRL_DAT
A
Drive Strength
DRVDD (V)
0
Default strength (CLOAD = 5 pF)
3.3
6
Maximum strength (CLOAD = 15 pF)
3.3
5
Default strength (CLOAD = 5 pF)
1.8
14
Maximum strength (CLOAD = 15 pF)
1.8
All other options are reserved.
Figure 92. Register 21 (15h)
15
14
13
12
11
10
9
8
2
1
0
DELAY_COUNT[23:16]
7
Bits 15:8
6
5
4
3
SAMPLE_COUNT[23:16]
DELAY_COUNT[23:16]: Delay counter, upper bits
These bits determine the delay phase in terms of tAFE_CLK.
DELAY_PHASE = (DELAY_COUNT + 1) × tAFE_CLK.
The valid range for DELAY_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
Bits 7:0
SAMPLE_COUNT[23:16]: Sample counter, upper bits
These bits determine the sample phase in terms of tAFE_CLK.
Sample phase = (SAMPLE_COUNT + 1) × tAFE_CLK.
The valid range for SAMPLE_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
52
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Figure 93. Register 22 (16h)
15
14
13
12
11
DELAY_COUNT[15:0]
10
9
8
7
6
5
4
3
DELAY_COUNT[15:0]
2
1
0
Bits 15:0
DELAY_COUNT[15:0]: Delay counter, lower bits
These bits determine the delay phase in terms of tAFE_CLK.
DELAY_PHASE = (DELAY_COUNT + 1) × tAFE_CLK.
The valid range for DELAY_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
Figure 94. Register 23 (17h)
15
14
13
12
11
SAMPLE_COUNT[15:0]
10
9
8
7
6
5
4
3
SAMPLE_COUNT[15:0]
2
1
0
Bits 15:0
SAMPLE_COUNT[15:0]: Sample counter, lower bits
These bits determine the sample phase in terms of tAFE_CLK.
Sample phase = (SAMPLE_COUNT + 1) × tAFE_CLK.
The valid range for SAMPLE_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
Figure 95. Register 24 (18h)
15
TRIG_FALL
7
Bit 15
14
DSYNC1_
START_LOW
13
12
11
0
DSYNC_EN
0
6
5
4
COMP_DSYNC1[15:6]
3
10
9
8
COMP_DSYNC1[15:6]
2
1
0
0
TRIG_FALL
0 = TRIG event on the TRIG rising edge
1 = TRIG event on the TRIG falling edge
Bit 14
DSYNC1_START_LOW: Selects DSYNC1 start level
0 = DSYNC1 starts with logic high (default)
1 = DSYNC1 starts with logic low
Bit 13
Must write 0
Bit 12
DSYNC_EN: Enable DSYNC1/2 generation
0 = Disable DSYNC1/2 signals (default - logic low)
1 = Enable DSYNC1/2 signals
Bit 11
Must write 0
Bits 10:1
COMP_DSYNC1[15:6]: DSYNC1, upper bits
These bits determine the DSYNC1 period in the number of tAFE_CLK cycles. For
COMP_DSYNC1 = 0 or 1, DSYNC1 is static.
Bit 0
Must write 0
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Figure 96. Register 25 (19h)
15
14
7
6
Bits 15:10
13
12
COMP_DSYNC1[5:0]
5
11
4
3
DSYNC2_LOW[23:16]
10
9
0
8
0
2
1
0
COMP_DSYNC1[5:0]: DSYNC1, lower bits
These bits determine the DSYNC1 period in the number of tAFE_CLK cycles. For
COMP_DSYNC1 = 0 or 1, DSYNC1 is static.
Bits 9:8
Must write 0
Bits 7:0
DSYNC2_LOW[23:16]: DSYNC2, upper bits
Low pulse duration of DSYNC2 in number of tAFE_CLK clocks.
Figure 97. Register 26 (1Ah)
15
14
13
12
11
DSYNC2_LOW[15:0]
10
9
8
7
6
5
4
3
DSYNC2_LOW[15:0]
2
1
0
Bits 15:0
DSYNC2_LOW[15:0]: DSYNC2, lower bits
Low pulse duration of DSYNC2 in number of tAFE_CLK clocks.
Figure 98. Register 27 (1Bh)
15
14
13
12
11
DSYNC1_HIGH
10
9
8
7
6
5
4
2
1
0
3
DSYNC1_HIGH
Bits 15:0
DSYNC1_HIGH: DSYNC1
High pulse duration of DSYNC1, in number of tAFE_CLK clocks.
DSYNC1 high = high for [(DSYNC1_HI + COMP_DSYNC1 ÷ 2) Mod
(1)
54
(1)
COMP_DSYNC1]
Mod = Remainder of the division
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Figure 99. Register 29 (1Dh)
15
OFFSET_DIS
7
14
0
6
STAT_CALC_CYCLE
Bit 15
13
12
STAT_CH_SEL
11
0
10
0
5
3
0
2
0
4
0
9
8
STAT_CALC_CYCLE
1
0
0
STAT_CH_AUT
O_SEL
OFFSET_DIS: Bypass OFFSET addition at channel output
0 = Default. The OFFSET_CHx register value is added to the channel output.
1 = Disable OFFSET. The OFFSET_CHx register value is not added to the channel output.
Bit 14
Always write 0
Bits 13:12
STAT_CH_SEL: Manual channel selection for computation by STAT module
0
1
2
3
=
=
=
=
Channel
Channel
Channel
Channel
1
2
3
4
Bits 11:10
Always write 0
Bits 9:5
STAT_CALC_CYCLE
Number of ADC samples used for STAT computation = 2STAT_CALC_CYCLE+1,
STAT_CALC_CYCLE range = 0 to 30
and Bits 4:1
Always write 0
Bit 0
STAT_CH_AUTO_SEL: Automatic channel selection for SNR Computation
0 = Static, computation is done based on the STAT_CH_SEL selection
1 = Auto, computation is sequentially done for all four channels
Figure 100. Register 30 (1Eh)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
MULT_EN
7
FILT_EN
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Bits 15:9
Must write 0
Bit 8
MULT_EN: Channel multiplier enable
0 = Disable multiplier
1 = Enable multiplier. For digital gain, DIG_GAIN_C1_FIR must be written.
Bit 7
FILT_EN: Digital decimation filter enable
0 = Disable filter
1 = Enable standard 11-tap, symmetric FIR digital filter.
Bits 6:0
Must write 0
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Figure 101. Register 32 (20h)
15
0
14
0
13
0
12
0
7
6
5
4
11
10
9
8
2
1
0
HEADER_CH1
3
HEADER_CH1
Bits 15:12
Must write 0
Bits 11:0
HEADER_CH1: Header information for channel 1
These bits provide the header information for channel 1.
Figure 102. Register 33 (21h)
15
CH_OUT_DIS1
14
AUX_CH1_EN
13
PDN_CH1
12
INVERT_ CH1
11
0
10
0
9
7
6
5
4
3
2
1
8
OFFSET_CH1
0
OFFSET_CH1
Bit 15
CH_OUT_DIS1: Channel 1 disable
Channel 1 is not muxed out.
0 = Channel 1 is output (default)
1 = Channel 1 is not output
Bit 14
AUX_CH1_EN: Enable auxiliary channel for channel 1
0 = Filter (default)
1 = Auxiliary
Bit 13
PDN_CH1: Power-down channel 1
0 = Active (default)
1 = Power-down
Bit 12
INVERT_CH1: Invert channel 1 output
0 = Normal ouput (default)
1 = Inverted output
Bits 11:10
Must write 0
Bits 9:0
OFFSET_CH1: Output offset of channel 1 range
Output offset value = OFFSET_CH1 ÷ 4, output offset value is added to channel output.
56
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Figure 103. Register 34 (22h)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
MEAN_CH1
4
3
MEAN_CH1
Bits 15:14
Must write 0
Bits 13:0
MEAN_CH1: Mean for channel 1 (read-only register)
These bits provide the mean information computed by STAT module for channel 1.
Figure 104. Register 35 (23h)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
NOISE_CH1
4
3
NOISE_CH1
Bits 15:14
Must write 0
Bits 13:0
NOISE_CH1: Noise for channel 1 (read-only register)
These bits provide the noise information computed by STAT module for channel 1.
Figure 105. Register 36 (24h)
15
0
14
0
13
0
12
0
7
6
5
4
11
10
9
8
1
0
HEADER_CH2
3
2
HEADER_CH2
Bits 15:12
Must write 0
Bits 11:0
HEADER_CH2: Header information for channel 2
These bits provide the header information for channel 2.
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Figure 106. Register 37 (25h)
15
CH_OUT_DIS2
14
AUX_CH2_EN
13
PDN_CH2
12
INVERT_CH2
11
0
10
0
9
7
6
5
4
3
2
1
8
OFFSET_CH2
0
OFFSET_CH2
Bit 15
CH_OUT_DIS2: Channel 2 disable
Channel 2 is not muxed out.
0 = Channel 2 is output (default)
1 = Channel 2 is not output
Bit 14
AUX_CH2_EN: Enable auxiliary channel for channel 2
0 = Filter (default)
1 = Auxiliary
Bit 13
PDN_CH2: Power-down channel 2
0 = Active (default)
1 = Power-down
Bit 12
INVERT_CH2: Invert channel 2 output
0 = Normal (default)
1 = Inverted output
Bits 11:10
Must write 0
Bits 9:0
OFFSET_CH2: Output offset of Channel 2
Output offset value = OFFSET_CH2 ÷ 4, output offset value is added to the channel output
Figure 107. Register 38 (26h)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
MEAN_CH2
4
3
MEAN_CH2
Bits 15:14
Must write 0
Bits 13:0
MEAN_CH2: Mean for channel 2 (read-only register)
These bits provide the mean information computed by the STAT module for channel 2.
58
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Figure 108. Register 39 (27h)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
NOISE_CH2
4
3
NOISE_CH2
Bits 15:14
Must write 0
Bits 13:0
NOISE_CH2: Noise for channel 2 (read-only register)
These bits provide the noise information computed by the STAT module for channel 2.
Figure 109. Register 40 (28h)
15
0
14
0
13
0
12
0
7
6
5
4
11
10
9
8
2
1
0
HEADER_CH3
3
HEADER_CH3
Bits 15:12
Must write 0
Bits 11:0
HEADER_CH3: Header information for channel 3
These bits provide the header information for channel 3.
Figure 110. Register 41 (29h)
15
CH_OUT_DIS3
14
AUX_CH3_EN
13
PDN_CH3
12
INVERT_CH3
11
0
10
0
9
7
6
5
4
3
2
1
8
OFFSET_CH3
0
OFFSET_CH3
Bit 15
CH_OUT_DIS3: Channel 3 disable
Channel 3 is not muxed out.
0 = Channel 3 is output (default)
1 = Channel 3 is not output
Bit 14
AUX_CH3_EN: Enable auxiliary channel for channel 3
0 = Filter (default)
1 = Auxiliary
Bit 13
PDN_CH3: Power-down channel 3
0 = Active (default)
1 = Power-down
Bit 12
INVERT_CH3: Invert channel 3 output
0 = Normal (default)
1 = Inverted output
Bits 11:10
Must write 0
Bits 9:0
OFFSET_CH3: Output offset of Channel 3
Output offset value = OFFSET_CH3 ÷ 4, output offset value is added to the channel output
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Figure 111. Register 42 (2Ah)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
MEAN_CH3
4
3
MEAN_CH3
Bits 15:14
Must write 0
Bits 13:0
MEAN_CH3: Mean for channel 3 (read-only register)
These bits provide the mean information computed by the STAT module for channel 3.
Figure 112. Register 43 (2Bh)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
NOISE_CH3
4
3
NOISE_CH3
Bits 15:14
Must write 0
Bits 13:0
NOISE_CH3: Noise for channel 3 (read-only register)
These bits provide the noise information computed by the STAT module for channel 3.
Figure 113. Register 44 (2Ch)
15
0
14
0
13
0
12
0
7
6
5
4
11
10
9
8
1
0
HEADER_CH4
3
2
HEADER_CH4
Bits 15:12
Must write 0
Bits 11:0
HEADER_CH4: Header information for channel 4
These bits provide the header information for channel 4.
60
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Figure 114. Register 45 (2Dh)
15
CH_OUT_DIS4
14
AUX_CH4_EN
13
PDN_CH4
12
INVERT_CH4
11
0
10
0
9
7
6
5
4
3
2
1
8
OFFSET_CH4
0
OFFSET_CH4
Bit 15
CH_OUT_DIS1: Channel 4 disable
Channel 4 is not muxed out.
0 = Channel 4 is output (default)
1 = Channel 4 is not output
Bit 14
AUX_CH4_EN: Enable auxiliary channel for channel 4
0 = Filter (default)
1 = Auxiliary
Bit 13
PDN_CH4: Power-down channel 4
0 = Active (default)
1 = Power-down
Bit 12
INVERT_CH4: Invert channel 4 output
0 = Normal (default)
1 = Inverted output
Bits 11:10
Must write 0
Bits 9:0
OFFSET_CH4: Output offset of channel 4
Output offset value = OFFSET_CH4 ÷ 4, output offset value is added to the channel output
Figure 115. Register 46 (2Eh)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
MEAN_CH4
4
3
MEAN_CH4
Bits 15:14
Must write 0
Bits 13:0
MEAN_CH4: Mean for channel 4 (read-only register)
These bits provide the mean information computed by the STAT module for channel 4.
Figure 116. Register 47 (2Fh)
15
0
14
0
13
7
6
5
12
11
10
9
8
2
1
0
NOISE_CH4
4
3
NOISE_CH4
Bits 15:14
Must write 0
Bits 13:0
NOISE_CH4: Noise for channel 4 (read-only register)
These bits provide the noise information computed by the STAT module for channel 4.
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Figure 117. Register 65 (41h)
15
14
13
12
11
0
0
0
0
0
7
0
6
0
5
0
4
0
3
0
Bits 15:11
Must write 0
Bit 10
TERM_INT_20K_AUX: Auxiliary input termination
10
TERM_INT_
20K_AUX
9
8
0
0
2
0
1
0
0
0
This bit is common for all channels. This bit provides an auxiliary input internal differential
termination of 20 kΩ.
0 = 2-kΩ differential resistance (default)
1 = 20-kΩ differential resistance
Bits 9:0
Must write 0
Figure 118. Register 69 (45h)
15
TERM_INT_
20K_LNA
14
7
PGA_GAIN
6
EQ_EN
Bit 15
13
12
11
10
LNA_GAIN
9
8
1
0
0
0
PGA_GAIN
5
0
4
0
3
0
2
0
TERM_INT_20K_LNA: LNA input termination
This bit is common for all channels. This bit provides LNA input internal differential
termination of 20 kΩ.
0 = 2-kΩ differential resistance (default)
1 = 20-kΩ differential resistance
Bits 14:13
LNA_GAIN: LNA gain
These bits are common for all channels.
0
1
2
3
Bits 12:7
=
=
=
=
15 dB (default)
18 dB
12 dB
16.5 dB
PGA_GAIN: PGA gain
These bits are common for all channels. PGA gain = 0 dB, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB,
18 dB, 21 dB, 24 dB, 27 dB, and 30 dB.
0
1
2
3
4
5
Bit 6
=
=
=
=
=
=
0 dB
3 dB
6 dB
9 dB
12 dB
15 dB
6 = 18 dB
7 = 21 dB
8 = 24 dB
9 = 27 dB
10 = 30 dB
EQ_EN: Equalizer enable
These bits are common for all channels.
0 = Disabled (default)
1 = Enabled
Bits 5:0
62
Must write 0
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Figure 119. Register 70 (46h)
15
0
14
HPL_EN
13
0
12
0
11
0
10
0
9
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
VOUT_ON_ADC
Bit 15
Must write 0
Bit 14
HPL_EN: High-performance linearity mode
8
0
0 = Default
1 = Improves linearity (HD3) with increased power dissipation
Bits 13:2
Must write 0
Bits 1:0
VOUT_ON_ADC: Check analog block output on ADC input
0
1
2
3
=
=
=
=
LNA + antialiasing filter + ADC (default)
LNA + ADC
AMP1 + ADC
AMP2 + ADC
Figure 120. Register 71 (47h)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
0
0
0
0
2
EQ_EN_LOW_
FC
1
0
3
HIGH_POW_
LNA
0
0
Bits 15:4
Must write 0
Bit 3
HIGH_POW_LNA
0 = Default mode
1 = High-power LNA improves channel input-referred noise at high LNA and PGA gains
compared to default mode. This mode increases power dissipation.
Bit 2
EQ_EN_LOW_FC: Enable Equalizer Low Frequency Corner Frequency
0 = Disable
1 = Enable; EQ_EN must also be enabled for this mode
Bits 1:0
Must write 0
Figure 121. Register 100 (64h)
15
0
14
13
HF_AFE_CLK_EN
12
0
11
0
10
0
9
0
8
0
7
0
6
0
4
0
3
0
2
0
1
0
0
0
5
0
Bits 15
Must write 0
Bits 14:13
HF_AFE_CLK_EN
0 = Default
3 = For fAFE_CLK > 25 MHz ( in decimation modes)
Bits 12:0
Must write 0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The AFE5401-Q1 is a quad-channel, analog front-end (AFE), targeting applications where the level of integration
is critical. Each channel comprises a complete base-band signal chain with:
• A low-noise amplifier (LNA),
• A programmable equalizer (EQ),
• A programmable gain amplifier (PGA), and
• An antialias filter (AAF)
• A high-speed, 12-bit, analog-to-digital converter (ADC) that samples at 25 MSPS per channel.
Having four integrated signal chain channels enables the device to be used in different end-use systems such as:
• Automotive radar (where a down-converted base-band signal from an RF front-end can be applied to the
inputs of the AFE)
• Applications where up to 12-MHz voltage signal is available from a transducer
9.2 Typical Application
As Figure 122 illustrates, the device also consists of four auxiliary channels, where the analog signal chain (LNA,
PGA) is bypassed and the analog inputs can be directly digitized. This configuration is very useful in the system
to digitize monitoring signals (such as battery voltages and temperature sensor outputs).
As the Design Requirements section describes, the device can accept a variety of input clock signals (such as
differential sine-wave, LVPECL, or LVDS). The can also functions seamlessly with a single-ended LVCMOS
(1.8 V) clock input.
The device is designed to have a simple CMOS output data interface. Used with the TRIG and DSYNCx signals,
the device can be interfaced to standard video ports of DSPs and other field-programmable gate array (FPGA)
and micro-controller based receivers.
64
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Typical Application (continued)
FPGA/DSP
STBY
SCLK
SDATA
SEN
RESET
SDOUT
VCM
AVDD3
AVSS
DRVDD
DRVSS
AVDD18
AVSS
DVDD18
DVSS
Reference
SERIAL
INTERFACE
PGA
LNA
System monitoring
signals (Battery,
Temperature, etc)
Channel 1 of 4
INx
EQ
ADC 1
INx_AUX
BUF
4:1 MUX
CMOS/DIFF
SUPPORT
Clock Input:
CMOS Signal / LVPECL /
LVDS / Sine wave
AAF
EQ
fCLKIN
CLKINP
Input
Clock
Divider
1x
ADC_CLK
4x
CMOS OUTPUT DRIVER
Baseband signal from
Front-End
D [11:0]
D_GPO [1:0]
DCLK
AFE_CLK
CLKINM
Serialization Factor
Clock + Timing
Generator
TRIG
DSYNC1
DSYNC2
Figure 122. Typical Application Diagram
9.2.1 Design Requirements
The device can operate with either single-ended (CMOS) or differential input clocks (such as sine wave,
LVPECL, and LVDS). Operating with a low-jitter differential clock is recommended for good SNR performance. In
differential mode, the clock inputs are internally biased to the optimum common-mode voltage (approximately
0.95 V). While driving with an external LVPECL or LVDS driver, TI recommends ac-coupling the clock signals
because the clock pins are internally biased to the common-mode voltage.
9.2.2 Detailed Design Procedure
For the LVDS input clock, RTERM = 100 Ω is recommended. For the LVPECL clock input, RTERM must be
determined based on the LVPECL driver recommendations. To operate using a single-ended clock, connect a
CMOS clock source to CLKINP and tie CLKINM to GND. The device automatically detects the presence of a
single-ended clock without requiring any configuration and disables internal biasing. Typical clock termination
schemes are illustrated in Figure 125, Figure 126, Figure 127, and Figure 128. Typical characteristic plots across
input clock amplitude and duty cycle are shown in Application Curves.
Figure 123 and Figure 124 illustrate the equivalent circuits of the clock input pins for Differential and SingleEnded input clock respectively.
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Typical Application (continued)
Lpkg
~ 1 nH
20
CLKINP
Ceq
Cbond
~ 1 pF
Resr
~ 100
6 pF
5k
0.95 V
To Input Divider
6 pF
5k
Lpkg
~ 1 nH
Internal
Differential
Clock Buffer
20
CLKINM
Ceq
Cbond
~ 1 pF
Resr
~ 100
Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer
Figure 123. Clock Input Equivalent Circuit (Differential Mode)
Lpkg
~ 1 nH
20
CLKINP
Ceq
Cbond
~ 1 pF
Resr
~ 100
To Input Divider
Internal
Single-Ended
Clock Buffer
Lpkg
~ 1 nH
CLKINM
Cbond
~ 1 pF
Resr
~ 100
Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer
Figure 124. Clock Input Equivalent Circuit (Single-Ended Mode)
66
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Typical Application (continued)
0.1µF
0.1µF
CLKINP
CLKINP
Differential Sine-wave
RTERM
Differential
LVPECL
clock input
clock input
CLKINM
CLKINM
0.1µF
RTERM
Figure 125. Differential Sine-Wave Clock
Driving Circuit
0.1µF
Figure 126. Differential LVPECL Clock
Driving Circuit
0.1µF
CMOS clock input
CLKINP
Differential
LVDS
clock input
CLKINP
RTERM
CLKINM
CLKINM
0.1µF
Figure 127. Differential LVDS Clock Driving Circuit
Figure 128. Single-Ended Clock Driving Circuit
69
68
68.6
67.6
SNR (dBFS)
SNR (dBFS)
9.2.3 Application Curves
68.2
67.8
67.2
66.8
66.4
67.4
66
67
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Input Clock Amplitude, Differential (VPP)
2
2.2
35
Figure 129. Signal-to-Noise Ratio vs Input Clock Amplitude
(PGA Gain = 0 dB)
40
45
50
55
60
Input Clock Duty Cycle (%)
C011
65
C013
Figure 130. Signal-to-Noise Ratio vs Input Clock Duty
Cycle (PGA Gain = 0 dB)
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10 Power Supply Recommendations
10.1 Power Supply Sequencing
During power-up, the AVDD18, DVDD18, and DRVDD supplies can appear in any sequence. All supplies are
separated in the device. Externally, they can be driven from separate supplies with suitable filtering. No power
supply sequencing is required.
10.2 Power Supply Decoupling
Minimal external decoupling can be used without loss in performance because the device already includes
internal decoupling. Note that decoupling capacitors can help filter external power-supply noise, so the optimum
number of capacitors depends on the actual application. The decoupling capacitors should be placed as close as
possible to the device supply pins.
11 Layout
11.1 Layout Guidelines
All analog inputs must be differentially and symmetrically routed to the differential input pins of the device for best
performance. CMOS outputs traces should be kept as short as possible to reduce the trace capacitance that
loads the CMOS output buffers. Multiple ground vias can be added around the CMOS output data traces,
especially when the traces are routed on more than one layer. TI recommends matching the lengths of the output
data traces (D[11:0]) to reduce the skew across data bits.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
This condition is particularly of concern because of the high gain present in the analog input channel. Digital
outputs coupling back to analog inputs can be minimized by proper separation of analog and digital areas in the
board layout. Figure 131 illustrates an example layout where the analog and digital portions are routed
separately. This example also uses splits in the ground plane to minimize digital currents from looping into
analog areas. At the same time, note that the analog and digital grounds are shorted below the device. A single
ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board
are cleanly partitioned.
The device package consists of an exposed pad. In addition to providing a path for heat dissipation, the pad is
also internally connected to the analog ground. Therefore, the exposed pad must be soldered to the ground
plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout
Guidelines and QFN/SON PCB Attachment. Figure 131 and Figure 132 illustrate the layout diagrams taken from
the AFE5401-Q1 EVM User's Guide.
68
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11.2 Layout Example
Figure 131. Layout Diagram: Signal Routing
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Layout Example (continued)
Figure 132. Layout Diagram: Ground Split
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• QFN Layout Guidelines
• QFN/SON PCB Attachment
• AFE5401-Q1 EVM User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
SONAR is a trademark of Cakewalk, Inc.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AFE5401TRGCRQ1
ACTIVE
VQFN
RGC
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AFE5401
AFE5401TRGCTQ1
ACTIVE
VQFN
RGC
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AFE5401
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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