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AFE5812
SLOS816A – MARCH 2015 – REVISED MARCH 2015
AFE5812 Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW
Mixer, and Digital I/Q Demodulator, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 180 mW/CH
1 Features
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8-Channel Complete Analog Front-End
– LNA, VCAT, PGA, LPF, ADC, and CW Mixer
Programmable Gain Low-Noise Amplifier (LNA)
– 24, 18, 15 dB Gain
– 0.25, 0.5, 0.7 VPP Linear Input Range
– 0.63, 0.7, 0.9 nV/rtHz Input Referred Noise
– Programmable Active Termination
40 dB Low Noise Voltage Controlled Attenuator
(VCAT)
24/30 dB Programmable Gain Amplifier (PGA)
3rd Order Linear Phase Low-Pass Filter (LPF)
– 10, 15, 20, 30, 35, 50 MHz
14-bit Analog to Digital Converter w/ LVDS output
– 77 dBFS SNR at 65 MSPS
Noise/Power Optimizations (Without Digital
Demodulator)
– 180 mW/CH at 0.75 nV/rtHz, 65 MSPS
– 109 mW/CH at 1.1 nV/rtHz, 40 MSPS
– 107 mW/CH at CW Mode
Excellent Device-to-Device Gain Matching
– ±0.5 dB(typical) and ±1.1 dB(max)
Programmable Digital I/Q Demodulator after ADC
– Wide Range Demodulation Frequency
– 5 MHz
or high-order harmonics. The LPF Register
51[3:1] needs to be set as 100, that is, 10 MHz.
61[15]
0x3D[15]
0
PGA_CLAMP_-6dBFS
0: Disable the –6-dBFS clamp. PGA_CLAMP is
set by Reg51[7:5].
1: Enable the –6-dBFS clamp. PGA_CLAMP
Reg51[7:5] should be set as 000 in the lownoise mode or 100 in the low-power/mediumpower mode. In this setting, PGA output HD3 will
be worsen by 3 dB at –6-dBFS ADC input. The
actual PGA output is reduced to approximately 1.5
Vpp, about 2.5 dB below the ADC full-scale input
2 Vpp . As a result, AFE5812’s LPF is not
saturated, and it can suppress harmonic signals
better at PGA output. Due to PGA output
reduction, the ADC output dynamic range is
impacted.
Note: This bit is ONLY valid when PGA=24dB.
10.6.1.4 VCA Register Description
10.6.1.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
Different LNA input impedances can be configured through the register 52[4:0]. By enabling and disabling the
feedback resistors between LNA outputs and ACTx pins, LNA input impedance is adjustable accordingly. Table 6
describes the relationship between LNA gain and 52[4:0] settings. The input impedance settings are the same for
both TGC and CW paths.
The AFE5812 also has four preset active termination impedances as described in 52[7:6]. An internal decoder is
used to select appropriate resistors corresponding to different LNA gain.
Table 6. Register 52[4:0] Description
52[4:0]/0x34[4:0]
FUNCTION
00000
No feedback resistor enabled
00001
Enables 450-Ω feedback resistor
00010
Enables 900-Ω feedback resistor
00100
Enables 1800-Ω feedback resistor
01000
Enables 3600-Ω feedback resistor
10000
Enables 4500-Ω feedback resistor
The input impedance of AFE can be programmed through Register 52[8:0]. Each bit of Register 52[4:0] controls
one active termination resistor. The following tables indicate the nominal impedance values when individual
active termination resistors are selected. See Active Termination for more details. Table 7 shows the
corresponding impedances under different Register 52[4:0] values, while Table 8 shows the Register 52[4:0]
settings under different impedances.
NOTE
Table 7 and Table 8 show nominal input impedance values. Due to silicon process
variation, the actual values can vary.
Table 7. Register 52[4:0] versus LNA Input Impedances
52[4:0]/0x34[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
LNA:15dB
High Z
118 Ω
236 Ω
79 Ω
472 Ω
94 Ω
157 Ω
67 Ω
60
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Table 7. Register 52[4:0] versus LNA Input Impedances (continued)
52[4:0]/0x34[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
LNA:18dB
High Z
90 Ω
180 Ω
60 Ω
360 Ω
72 Ω
120 Ω
51 Ω
LNA:24dB
High Z
50 Ω
100 Ω
33 Ω
200 Ω
40 Ω
66.67 Ω
29 Ω
52[4:0]/0x34[4:0]
01000
01001
01010
01011
01100
01101
01110
01111
LNA:15dB
944 Ω
105 Ω
189 Ω
73 Ω
315 Ω
86 Ω
135 Ω
63 Ω
LNA:18dB
720 Ω
80 Ω
144 Ω
55 Ω
240 Ω
65 Ω
103 Ω
48 Ω
LNA:24dB
400 Ω
44 Ω
80 Ω
31 Ω
133 Ω
36 Ω
57 Ω
27 Ω
52[4:0]/0x34[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
LNA:15dB
1181 Ω
107 Ω
197 Ω
74 Ω
337 Ω
87 Ω
139 Ω
64 Ω
LNA:18dB
900 Ω
82 Ω
150 Ω
56 Ω
257 Ω
67 Ω
106 Ω
49 Ω
LNA:24dB
500 Ω
45 Ω
83 Ω
31 Ω
143 Ω
37 Ω
59 Ω
27 Ω
52[4:0]/0x34[4:0]
11000
11001
11010
11011
11100
11101
11110
11111
LNA:15dB
525 Ω
96 Ω
163 Ω
68 Ω
249 Ω
80 Ω
121 Ω
60 Ω
LNA:18dB
400 Ω
73 Ω
124 Ω
52 Ω
189 Ω
61 Ω
92 Ω
46 Ω
LNA:24dB
222 Ω
41 Ω
69 Ω
29 Ω
105 Ω
34 Ω
51 Ω
25 Ω
Table 8. LNA Input Impedances versus Register 52[4:0]
Z (Ω) LNA:15dB
LNA:18dB
LNA:24dB
Z (Ω) LNA:15dB
LNA:18dB
LNA:24dB
10101
Z (Ω) LNA:15dB
25
11111
67
00111
139
27
10111/011
11
68
11011
29
00111/110
11
69
31
01011/100
11
72
33
00011
73
01011
34
11101
74
10011
36
01101
79
00011
37
10101
80
11101
40
00101
81
41
11001
82
44
01001
83
45
10001
86
01101
222
10101
236
143
11010
01010
00101
150
10010
11001
157
00110
163
11010
176
01001
01010
10001
10010
180
00010
189
01010
197
10010
87
48
01111
90
00001
240
49
10111
92
11110
249
00100
11000
00010
01100
11100
50
00001
94
00101
257
51
00111/111
10
96
11001
315
01100
337
10100
11011
100
01011
103
56
10011
105
00010
01110
01001
57
01110
106
59
10110
107
10001
00011
118
00001
11101
120
60
11111
61
63
01111
121
64
10111
122
10100
360
11100
10110
11100
200
11111
55
LNA:24dB
10100
144
46
52
LNA:18dB
10110
00100
400
472
11000
500
525
00110
11110
01000
00100
10000
11000
667
720
01000
900
10000
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Table 8. LNA Input Impedances versus Register 52[4:0] (continued)
Z (Ω) LNA:15dB
65
66.7
LNA:18dB
LNA:24dB
01101
Z (Ω) LNA:15dB
124
00110
133
135
62
LNA:18dB
LNA:24dB
11010
Z (Ω) LNA:15dB
944
01100
LNA:18dB
LNA:24dB
01000
1181 10000
01110
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SLOS816A – MARCH 2015 – REVISED MARCH 2015
10.6.1.4.2 Programmable Gain for CW Summing Amplifier
Different gain can be configured for the CW summing amplifier through the register 54[4:0]. By enabling and
disabling the feedback resistors between the summing amplifier inputs and outputs, the gain is adjustable
accordingly to maximize the dynamic range of CW path. Table 9 describes the relationship between the summing
amplifier gain and 54[4:0] settings.
Table 9. Register 54[4:0] Description
54[4:0]/0x36[4:0]
FUNCTION
00000
No feedback resistor
00001
Enables 250-Ω feedback resistor
00010
Enables 250-Ω feedback resistor
00100
Enables 500-Ω feedback resistor
01000
Enables 1000-Ω feedback resistor
10000
Enables 2000-Ω feedback resistor
Table 10. Register 54[4:0] vs Summing Amplifier Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
00000
00001
00010
00011
00100
00101
00110
N/A
0.50
0.50
0.25
1.00
0.33
0.33
00111
0.20
01000
01001
01010
01011
01100
01101
01110
01111
2.00
0.40
0.40
0.22
0.67
0.29
0.29
0.18
10000
10001
10010
10011
10100
10101
10110
10111
4.00
0.44
0.44
0.24
0.80
0.31
0.31
0.19
11000
11001
11010
11011
11100
11101
11110
11111
1.33
0.36
0.36
0.21
0.57
0.27
0.27
0.17
10.6.1.4.3 Programmable Phase Delay for CW Mixer
Accurate CW beamforming is achieved through adjusting the phase delay of each channel. In the AFE5812, 16
different phase delays can be applied to each LNA output. It meets the standard requirement of typical
1
λ
ultrasound beamformer, that is, 16 beamformer resolution. Table 9 describes the relationship between the
phase delays and the register 55 and 56 settings.
Table 11. CW Mixer Phase Delay vs Register Settings
CH1 to 55[3:0], CH2 to 55[7:4], CH3 to 55[11:8], CH4 to 55[15:12],
CH5 to 56[3:0], CH6 to 56[7:4], CH7 to 56[11:8], CH8 to 56[15:12]
Phase Delay
CHX_CW_MIXER_PHASE
PHASE SHIFT
Register Settings
0000
0001
0010
0011
0100
0101
0110
0111
0
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
CHX_CW_MIXER_PHASE
1000
1001
1010
1011
1100
1101
1110
1111
PHASE SHIFT
180°
202.5°
225°
247.5°
270°
292.5°
315°
337.5°
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10.6.2 Digital Demodulator Register Description
Table 12. Digital Demodulator Register Map (1) (2) (3)
Address
(HEX)
BIT [5:0]
Address
(DEC)
BIT [5:0]
00[2]
00[2]
0
1: Generate internal TX_TRIG (self clear, write only). This is an
alternative for TX_SYNC hardware pulse.
REGISTER_READOUT_EN
00[1]
ABLE
00[1]
0
1: Enables readout of register at SDOUT pin (write only)
CHIP_ID
01[4:0]
0
Unique chip ID
0
000 = Normal operation
011 = Custom pattern (set by register 05)
Note: LSB always comes out first regardless of whether 0x04[4] = 0 or
1.
111 = chipID + ramp test pattern. ChipID (5 bit) and subchip
information (3 bit) are the 8 LSBs and the ramp pattern is in the rest
MSBs. (0x0A[9] = 1).
Note: Valid only when the demodulator is enabled, i.e. ADC register
0x16=0.
11
Serialization factor (output rate)
00 = Reserved
01 = 12x
10 = 14x
11 = 16x
Note: This register is different from the ADC
SERIALIZED_DATA_RATE. The demod and ADC serialization factors
must be matched.
0
Output resolution of the demodulator. It refers to the ADC resolution
when the demodulator is bypassed.
100 = 16 bit (demod only)
000 = 14 bit
001 = 13 bit
010 = 12 bit
0
0 = LSB first
1 = MSB first
This bit does not affect the test mode: customer pattern, that is,
02[15:13] = 011B.
Note: in the CUSTOM_PATTERN mode, the output is always set as
LSB first regardless of this bit setting.
Register Name
MANUAL_TX_TRIG
OUTPUT_MODE
SERZ_FACTOR
OUTPUT_RESOLUTION
01[4:0]
02[15:13]
03[14:13]
03[11:9]
02[15:13]
03[14:13]
03[11:9]
Default
Description
MSB_FIRST
04[4]
04[4]
CUSTOM_PATTERN
05[15:0]
05[15:0]
0000
COEFF_MEM_ADDR_WR
06[7:0]
06[7:0]
0
Write address offset to coefficient memory (auto increment)
COEFF_BANK
07[111:0]
07[111:0]
—
Writes chunks of 112 bits to the coefficient memory. This RAM does
not have default values, so it is necessary to write required values to
the RAM. TI recommends to configure the RAM before other registers.
PROFILE_MEM_ADDR_W
R
08[4:0]
08[4:0]
0
Write address offset to profile memory (auto increment)
PROFILE_BANK
09 [63:0]
09 [63:0]
—
Writes chunks of 64 bits to the profile memory (effective 62 bits
because two LSBs are ignored). This RAM does not have default
values, so it is necessary to write required values to the RAM. TI
recommends to configure the RAM before other registers.
RESERVED
0A[15]
10[15]
0
Must set to 0
MODULATE_BYPASS
0A[14]
10[14]
0
Arrange the demodulator output format for I/Q data. See Table 11.
DEC_SHIFT_SCALE
0A[13]
10[13]
0
0 = No additional shift applied to the decimation filter output.
1 = Shift the decimation filter output by 2 bits additionally, that is apply
12-dB additional digital gain.
(1)
(2)
(3)
64
Custom data pattern for LVDS (0x02[15:13] = 011)
When programming the SPI, 8-bit address is required. This table and the following sections only list the Add_Bit5 to Add_Bit0. The
Add_Bit7 = SCID1_SEL and Add_Bit6 = SCID0_SEL need to be appended as 11, 10, or 01, which determines if SubChip1 or SubChip0
is being programmed. If SCID1_SEL,SCID0_SEL = 11, then both subchips get written with the same register value. See Table 3.
Reserved register bits must be programmed based on their descriptions.Unlisted register bits must be programmed as zeros.
ADC CLK is required to access the demodulation registers.
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Table 12. Digital Demodulator Register Map(1)(2)(3) (continued)
Address
(HEX)
BIT [5:0]
Address
(DEC)
BIT [5:0]
DHPF
0A[12]
OUTPUT_CHANNEL_SEL
Register Name
Default
Description
10[12]
1
0 = Enable first-order digital HPF. –3 dB cut off frequency is at 0.0225
× Fs / 2. Its transfer function equation is h(n) = a / b, where a = [1 –
7569 / 213] and b = [1 –1];
1 = Disable first-order digital HPF.
0A[11]
10[11]
0
Swap channel pairs. It is used in 4 LVDS bypass configuration to
select which of the two possible data streams to pass on. See
Table 11.
SIN_COS_RESET_ON_TX
_TRIG
0A[10]
10[10]
1
0 = Continuous phase
1 = Reset down conversion phase on TX_TRIG
FULL_LVDS_MODE
0A[9]
10[9]
0
0 = Use 4 LVDS lines (1, 3, 5, 7)
1 = Use 8 LVDS lines (1 through 8)
Note: 4 LVDS mode valid only for decimation factors ≥4. See Table 14.
RESERVED
0A[8:5]
10[8:5]
0
Must set to 0
RESERVED
0A[4]
10[4]
0
Must set to 1
DEC_BYPASS
0A[3]
10[3]
0
0 = Enable decimation filter
1 = Bypass decimation filter
DWN_CNV_BYPASS
0A[2]
10[2]
0
0 = Enable down conversion block
1 = Bypass down conversion block. Note: the decimation filter can still
be used when the down conversion block is bypassed.
RESERVED
0A[1]
10[1]
1
Must set to 1
DC_REMOVAL_BYPASS
0A[0]
10[0]
0
0 = Enable DC removal block
1 = Bypass DC removal block
SYNC_WORD
0B[15:0]
11[15:0]
0x2772
PROFILE_INDX
0E[15:11]
14[15:11]
0
Profile word selector.
The Profile Index register is a special 5-bit data register. Read value
still uses 16-bit convention, which means data will be available on LSB
0e[4:0])
0
54[13:0] → DC offset for channel 1, SCID1_SEL,SCID0_SEL = 01
94[13:0] → DC offset for channel 5, SCID1_SEL,SCID0_SEL = 10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
0
55[13:0] → DC offset for channel 2, SCID1_SEL,SCID0_SEL = 01
95[13:0] → DC offset for channel 6, SCID1_SEL,SCID0_SEL = 10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
0
56[13:0] → DC offset for channel 3, SCID1_SEL,SCID0_SEL=01
96[13:0] → DC offset for channel 7, SCID1_SEL,SCID0_SEL=10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
DC_REMOVAL_1_5
DC_REMOVAL_2_6
DC_REMOVAL_3_7
14[13:0]
15[13:0]
16[13:0]
20[13:0]
21[13:0]
22[13:0]
LVDS sync word. When MODULATE_BYPASS = 1, there is no sync
word output.
DC_REMOVAL_4_8
17[13:0]
23[13:0]
0
57[13:0] → DC offset for channel 4, SCID1_SEL,SCID0_SEL = 01
97[13:0] → DC offset for channel 8, SCID1_SEL,SCID0_SEL = 10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
DEC_SHIFT_FORCE_EN
1D[7]
29[7]
0
0 = Profile vector specifies the number of bit to shift for the decimation
filter output.
1 = Register 1D[6:4] specifies the number of bit to shift for the
decimation filter output.
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Table 12. Digital Demodulator Register Map(1)(2)(3) (continued)
Address
(HEX)
BIT [5:0]
Address
(DEC)
BIT [5:0]
DEC_SHIFT_FORCE
1D[6:4]
29[6:4]
0
Specify that the decimation filter output is right-shifted by (20 – N) bit,
N = 0x1D[6:4]. N = 0, minimal digital gain; N = 7 maximal digital gain;
additional 12-dB digital gain can be applied by setting
DEC_SHIFT_SCALE = 1, that is, 0x0A[13] = 1
TM_COEFF_EN
1D[3]
29[3]
0
1 = Set coefficient output test mode
TM_SINE_EN
1D[2]
29[2]
0
1 = Set sine output mode; the sine waveform specifications can be
configured through register 0x1E.
RESERVED
1D[1]
29[1]
0
Must set to 0
RESERVED
1D[0]
29[0]
0
Must set to 0
TM_SINE_DC
1E[15:9]
30[15:9]
0
7-bit signed value for sine wave DC offset control.
TM_SINE_AMP
1E[8:5]
30[8:5]
0
4-bit unsigned value, controlling the sine wave amplitude (powers of
two), from unity to the full scale of 14 bit, including saturation.
0 = No sine (only DC)
TM_SINE_STEP
1E[4:0]
30[4:0]
0
5-bit unsigned value, controlling the sine wave frequency with
resolution of Fs / 26, which is 0.625 MHz for 40-MHz ADC clock.
MANUAL_COEFF_START_
1F[15]
EN
31[15]
0
0 = The starting address of the coefficient RAM is set by the profile
vector, that is, the starting address is set manually.
1 = The starting address of the coefficient RAM is set by the register
0x1F[14:7].
MANUAL_COEFF_START_
1F[14:7]
ADDR
31[14:7]
0
When 0x1F[15] is set, the starting address of coefficient RAM is set by
these 8 bits.
MANUAL_DEC_FACTOR_
EN
1F[6]
31[6]
0
0 = The decimation factor is set by profile vector.
1 = The decimation factor is set by the register 0x1F[5:0].
MANUAL_DEC_FACTOR
1F[5:0]
31[5:0]
0
When 0x1F[6] is set, the decimation factor is set by these 6 bits.
Note: It is from 1 to 32.
MANUAL_FREQ_EN
20[0]
32[0]
0
0 = The down convert frequency is set by profile vector.
1 = The down convert frequency is set by the register 0x21[15:0].
MANUAL_FREQ
21[15:0]
33[15:0]
0
When 0x20[0] is set, the value of manual down convert frequency is
calculated as N × Fs / 216
Register Name
Default
Description
Table 13. Configuring Data Output:
66
Register Name
SPI Address
SERZ_FACTOR
0x03[14:13]
OUTPUT_RESOLUTION
0x03[11:9]
MSB_FIRST
0x04[4]
OUT_MODE
0x02[15:13]
CUSTOM_PATTERN
0x05[15:0]
OUTPUT_CHANNEL_SEL
0x0A[11]
MODULATE_BYPASS
0x0A[14]
FULL_LVDS_MODE
0x0A[9]
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1. Serializer configuration:
– Serialization Factor 0x03[14:13]: It can be set using demodulator register SERZ_FACTOR. Default
serialization factor for the demodulator is 16×. However, the actual LVDS clock speed can be set by the
serialization factor in the ADC SPI interface as well; the ADC serialization factor is adjusted to 14× by
default. Therefore, it is necessary to sync these two settings when the demodulator is enabled, that is, set
the ADC register 0x03[14:13] = 01.
– Output Resolution 0x03[11:9]: In the default setting, it is 14 bits. The demodulator output resolution
depends on the decimation factor. 16-bit resolution can be used when higher decimation factor is
selected.
– For RF mode (passing 14 bits only), demodulator serialization factor can be changed to 14× by setting
demodulator register 0xC3[14:13] to 10.
2. Channel selection:
– Using register MODULATE_BYPASS 0x0A[14], channel output mode can be selected as IQ modulated or
single-channel I or Q output.
– Channel output is also selected using registers OUTPUT_CHANNEL_SEL 0x0A[11] and
FULL_LVDS_MODE 0x0A[9] and decimation factor.
– Each of the two demodulator subchips in a device has four channels named A, B, C, and D.
NOTE
After decimation, the LVDS FCLK rate keeps the same as the ADC sampling rate.
Considering the reduced data amount, zeros are appended after I and Q data and ensure
the LVDS data rate matches the LVDS clock rate. For detailed information about channel
multiplexing, see Table 14. In the table, A.I refers to CHA in-phase output, and A.Q refers
to CHA quadrature output. For example, M = 3, the valid data output rate is Fs / 3 for both
I and Q channels, that is 2 × Fs / 3 bandwidth is occupied. The left Fs / 3 bandwidth is
then filled by M-2 zeros. As a result, the demod LVDS output data are A.I, A.Q, 0, A.I A.Q
0 after SYNC_WORD, FCLK = Fs and DCLK = Fs × 8. When two ADC CHs' data are
transferred by one LVDS lane, M-4 zeros are filled after A.I, A.Q, B.I, and B.Q. See more
details in Table 14 and Figure 89.
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Table 14. Channel Selection (1)
Decimation
Factor (M)
Modulate
Bypass
Output
Full LVDS Decimation
Channel Select
Mode
Factor M
LVDS Output Description
LVDS1: A.I, A.Q, (zeros)
M 6 dB of the linear input signal range), TI recommends back-to-back Schottky clamping diodes at the
input to limit the amplitude of the input signal. Refer to the LNA Input Coupling and Decoupling section for more
details.
11.3.3 Driving the VCNTL signal with an excessive noise source
Noise on the VCNTL signal gets directly modulated with the input signal and causes higher output noise and
reduction in SNR performance. Maintain a noise level for the VCNTL signal as discussed in the VoltageControlled Attenuator section.
11.3.4 Using a clock source with excessive jitter, an excessively long input clock signal trace, or having
other signals coupled to the ADC or CW clock signal trace
These situations cause the sampling interval to vary, causing an excessive output noise and a reduction in SNR
performance. For a system with multiple devices, the clock tree scheme must be used to apply an ADC or CW
clock. Refer to the ADC Clock Configurations section for clock mismatch between devices, which can lead to
latency mismatch and reduction in SNR performance. Clocks generated by FPGA may include excessive jitter
and must be evaluated carefully before driving ADC or CW circuits.
11.3.5 LVDS routing length mismatch
The routing length of all LVDS lines routing to the FPGA must be matched to avoid any timing related issue. For
systems with multiple devices, the LVDS serialized data clock (DCLKP, DCLKM) and the frame clock (FCLKP,
FCLKM) of each individual device must be used to deserialize the corresponding LVDS serialized data (DnP,
DnM).
11.3.6 Failure to provide adequate heat removal
Use the appropriate thermal parameter listed in the Thermal Information table and an ambient, board, or case
temperature in order to calculate device junction temperature. A suitable heat removal technique must be used to
keep the device junction temperature below the maximum limit of 105°C.
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12 Power Supply Recommendations
12.1 Power/Performance Optimization
The AFE5812 has options to adjust power consumption and meet different noise performances. This feature
would be useful for portable systems operated by batteries when low power is more desired. Refer to
characteristics information listed in the Electrical Characteristics as well as the Typical Characteristics.
12.2 Power Management Priority
Power management plays a critical role to extend battery life and ensure long operation time. The AFE5812 has
fast and flexible power-down and power-up control which can maximize battery life. The AFE5812 can be
powered down or up through external pins or internal registers. Table 30 indicates the affected circuit blocks and
priorities when the power management is invoked. The higher priority controls can overwrite the lower priority
controls.
In the device, all the power-down controls are logically ORed to generate final power down for different blocks.
The higher priority controls can cover the lower priority controls.
Table 30. Power Management Priority
Name
Blocks
Pin
PDN_GLOBAL
All
Priority
High
Pin
PDN_VCA
LNA + VCAT+ PGA
Medium
Register
VCA_PARTIAL_PDN
LNA + VCAT+ PGA
Low
Register
VCA_COMPLETE_PDN
LNA + VCAT+ PGA
Medium
Pin
PDN_ADC
ADC
Medium
Register
ADC_PARTIAL_PDN
ADC
Low
Register
ADC_COMPLETE_PDN
ADC
Medium
Register
PDN_VCAT_PGA
VCAT + PGA
Lowest
Register
PDN_LNA
LNA
Lowest
12.3 Partial Power-Up and Power-Down Mode
The partial power-up and power-down mode is also called fast power-up and power-down mode. In this mode,
most amplifiers in the signal path are powered down, while the internal reference circuits remain active as well as
the LVDS clock circuit, that is, the LVDS circuit still generates its frame and bit clocks.
The partial power-down function allows the AFE5812 to wake up from a low-power state quickly. This
configuration ensures that the external capacitors are discharged slowly; thus, a minimum wake-up time is
needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2
μs or 1% of the power-down duration, whichever is larger. The longest wake-up time depends on the capacitors
connected at INP and INM, because the wake-up time is the time required to recharge the capacitors to the
desired operating voltages. 0.1 μF at INP and 15 nF at INM can give a wake-up time of 2.5 ms. For larger
capacitors, this time will be longer. The ADC wake-up time is about 1 μs. Thus, the AFE5812 wake-up time is
more dependent on the VCA wake-up time. This also assumes that the ADC clock has been running for at least
50 µs before normal operating mode resumes. The power-down time is instantaneous, less than 1 µs.
This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical.
The pulse repetition frequency of an ultrasound system could vary from 50 kHz to 500 Hz, while the imaging
depth (that is, the active period for a receive path) varies from 10 μs to hundreds of µs. The power saving can be
significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC
keeps running normally to ensure minimal impact to FPGAs.
In the partial power-down mode, the AFE5812 typically dissipates only 26 mW/ch, representing an 80% power
reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA and
PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN).
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12.4 Complete Power-Down Mode
To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5812 can be placed into a complete power-down
mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN, or
PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the
AFE5812 are powered down, and the capacitors connected to the AFE5812 are discharged. The wake-up time
depends on the time needed to recharge these capacitors. The wake-up time depends on the time that the
AFE5812 spends in shutdown mode. 0.1 μF at INP and 15 nF at INM can give a wake-up time close to 2.5 ms.
NOTE
When the complete power-down mode is enabled, the digital demodulator may lose
register settings. Therefore, it is required to reconfigure the demodulator registers, filter
coefficient memory, and profile memory after exiting the complete power-down mode.
12.5 Power Saving in CW Mode
Usually, only half the number of channels in a system are active in the CW mode. Thus, the individual channel
control through ADC_PDN_CH and VCA's PDN_CH can power down unused channels and save
power consumption greatly. Under the default register setting in CW mode, the voltage controlled attenuator,
PGA, and ADC are still active. During the debug phase, both the PW and CW paths can run simultaneously. In
real operation, these blocks need to be powered down manually.
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13 Layout
13.1 Layout Guidelines
Proper grounding and bypassing, short lead length, and the use of ground and power-supply planes are
particularly important for high-frequency designs. Achieving optimum performance with a high-performance
device such as the AFE5812 requires careful attention to the PCB layout to minimize the effects of board
parasitics and optimize component placement. A multilayer PCB usually ensures best results and allows
convenient component placement. To maintain proper LVDS timing, all LVDS traces should follow a controlled
impedance design. In addition, all LVDS trace lengths should be equal and symmetrical; TI recommends to keep
trace length variations less than 150 mil (0.150 inch or 3.81 mm).
To avoid noise coupling through supply pins, it is recommended to keep sensitive input net classes,
such as INM, INP, ACT pins, away from AVDD 3.3 V, AVDD_5V, DVDD, AVDD_ADC, DVDD_LDO1/2 nets or
planes. For example, vias connected to these pins should NOT be routed across any supply plane. That
is to avoid power planes under INM, INP, and ACT pins.
In addition, appropriate delay matching should be considered for the CW clock path, especially in systems with
high channel count. For example, if clock delay is half of the 16× clock period, a phase error of 22.5° could exist.
Thus, the timing delay difference among channels contributes to the beamformer accuracy.
Additional details on BGA PCB layout techniques can be found in the TI application report MicroStar BGA
Packaging Reference Guide (SSYZ015), which can be downloaded from www.ti.com.
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13.2 Layout Example
Caps to INP, INM, ACT pins
CW I/Os
Vcntl
Decoupling caps close to
power pins
Figure 112. Layout Example
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Layout Example (continued)
No Power Plane below
INP, INM, and ACT pins
Power Planes for AVDD_5V
and AVDD_ADC
SPI pins
Figure 113. Layout Example
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Layout Example (continued)
No Power Plane below
INP, INM, and ACT pins
Power Plane
AVDD
Power Plane
AVDD_ADC
Power Plane
DVDD
Figure 114. Layout Example
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Layout Example (continued)
CW CLKs
CW I/Os
GND Fanout
CW CLKs
ADC CLK
LVDS Outputs
Figure 115. Layout Example
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14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
MicroStar BGA Packaging Reference Guide, SSYZ015
Clocking High-Speed Data Converters, SLYT075
Design for a Wideband Differential Transimpedance DAC Output, SBAA150
TI Active Filter Design Tool, WEBENCH® Filter Designer
AFE5818 Data Sheet, SBAS624
AFE5816 Data Sheet, SBAS688
CDCM7005 Data Sheet, SCAS793
CDCE72010 Data Sheet, SCAS858
TLV5626 Data Sheet, SLAS236
DAC7821 Data Sheet, SBAS365
THS413x Data Sheet, SLOS318
OPA1632 Data Sheet, SBOS286
LMK048x Data Sheet, SNAS489
OPA2211 Data Sheet, SBOS377
ADS8413 Data Sheet, SLAS490
ADS8472 Data Sheet, SLAS514
SN74AUP1T04 Data Sheet, SCES800
ISO7240 Data Sheet, SLLS868
14.2 Trademarks
All trademarks are the property of their respective owners.
14.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AFE5812ZCF
ACTIVE
NFBGA
ZCF
135
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
AFE5812
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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