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AFE5809
SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
AFE5809 Fully Integrated, 8-Channel Ultrasound Analog Front End With Passive CW
Mixer, and Digital I/Q Demodulator, 0.75 nV/rtHz, 14, 12-Bit, 65 MSPS, 158 mW/CH
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
•
8-Channel Complete Analog Front-End
– LNA, VCAT, PGA, LPF, ADC, and CW Mixer
Programmable Gain Low-Noise Amplifier (LNA)
– 24-, 18-, 12-dB Gain
– 0.25-, 0.5-, 1-VPP Linear Input Range
– 0.63-, 0.7-, 0.9-nV/rtHz Input Referred Noise
– Programmable Active Termination
40-dB Low-Noise Voltage Controlled Attenuator
(VCAT)
24-/30-dB Programmable Gain Amplifier (PGA)
Third-Order Linear Phase Low-Pass Filter (LPF)
– 10, 15, 20, 30 MHz
14-Bit Analog-to-Digital Converter (ADC)
– 77 dBFS SNR at 65 MSPS
– LVDS Outputs
Noise, Power Optimizations (Without Digital
Demodulator)
– 158 mW/CH at 0.75 nV/rtHz, 65 MSPS
– 101 mW/CH at 1.1 nV/rtHz, 40 MSPS
– 80 mW/CH at CW Mode
Excellent Device-to-Device Gain Matching
– ±0.5 dB (Typical) and ±1 dB (Maximum)
Digital I/Q Demodulator after ADC
– Wide Range Demodulation Frequency
– 41XXXX, has below additional
features which can be enabled by Register 61[15,14,13]. Existing analog performance
remains the same.
• 61[13] enables an additional voltage clamp at the V2I input of the PGA. This limits the
amount of overload signal the PGA sees.
• 61[14] enables a first-order 5-MHz LPF filter to suppress signals >5 MHz or high-order
harmonics.
• 61[15] enables a –6-dB PGA clamp setting. The actual PGA output is less than the
ADC's full-scale amplitude, 2 Vpp.
6
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SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
6 Pin Configuration and Functions
ZCF Package
135-Pin NFBGA
Bottom View
D7P
D6P
D5P
FCLKP
DVSS
DCLKP
D4P
D3P
D2P
D7M
D6M
D5M
FCLKM
DVSS
DCLKM
D4M
D3M
D2M
D8P
D8M
DVDD
DVDD_
LDO1
DVSS
DVDD
D1M
D1P
SPI_DIG
_EN
DNC
SDOUT
PDN_
ADC
SEN
R
P
DVDD_
LDO2
N
AVDD_
ADC
AVDD_
VREF_IN
ADC
REFP
DNC LDO_SETV
CLKP_
ADC
CLKM_
ADC
AVDD_
ADC
REFM
DNC
LDO_EN
VCNTLM
VHIGH
AVSS
M
TX_SYNC_
IN
L
AVDD
AVDD_5V VCNTLP
DNC AVDD_ADC SDATA
K
CW_QP_ CW_QP_
AMPINP AMPINM
AVSS
AVSS
AVSS AVDD_ADC
CW_QP_
OUTM
CW_QP_
OUTP
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
CW_IP_
OUTM
CW_IP_
OUTP
AVSS
AVSS
AVSS
AVSS
AVSS CLKP_16X
CW_IP_
AMPINP
CW_IP_
AMPINM
AVSS
AVSS
AVSS
AVSS
AVSS
AVDD
AVDD
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVDD
AVDD
AVSS
INM8
INM7
INM6
INM5
INM4
INM3
INM2
INM1
CM_BYP
ACT8
ACT7
ACT6
ACT5
ACT4
ACT3
ACT2
ACT1
AVDD
INP8
INP7
INP6
INP5
INP4
INP3
INP2
INP1
1
2
3
4
8
9
AVDD_
ADC
PDN_VCA
SCLK
Rows
J
PDN_
GLOBAL
RESET
H
CLKP_1X CLKM_1X
G
CLKM_
16X
F
E
D
C
B
A
5
6
7
Columns
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7
AFE5809
SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
www.ti.com
Pin Functions
PIN
NAME
DESCRIPTION
NO.
ACT1 to ACT8
B9 to B2
Active termination input pins for CH1 to CH8
A1
D8
D9
AVDD
E8
3.3-V analog supply for LNA, VCAT, PGA, LPF, and CWD blocks
E9
K1
AVDD_5V
K2
5-V analog supply for LNA, VCAT, PGA, LPF, and CWD blocks
J6
J7
AVDD_ADC
K8
L3
1.8-V analog power supply for ADC
M1
M2
C1
D1 to D7
E3 to E7
F3 to F7
AVSS
G1 to G7
Analog ground
H3 to H7
J3 to J5
K6
CLKM_ADC
L2
Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or
through a 0.1-µF capacitor.
CLKP_ADC
L1
Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal directly
or through a 0.1-µF capacitor.
CLKM_16X
F9
Negative input of differential CW 16× clock. Tie to GND when the CMOS clock mode is enabled. In the 4×
and 8× CW clock modes, this pin becomes the 4× or 8× CLKM input. In the 1× CW clock mode, this pin
becomes the in-phase 1× CLKM for the CW mixer. Can be floated if CW mode is not used. See register
0x36[11:10].
CLKP_16X
F8
Positive input of differential CW 16× clock. In 4× and 8× clock modes, this pin becomes the 4× and 8×
CLKP input. In the 1× CW clock mode, this pin becomes the in-phase 1× CLKP for the CW mixer. Can be
floated if CW mode is not used.See register 0x36[11:10].
CLKM_1X
G9
Negative input of differential CW 1× clock. Tie to GND when the CMOS clock mode is enabled (refer to
Figure 107 for details). In the 1× clock mode, this pin is the quadrature-phase 1× CLKM for the CW mixer.
Can be floated if CW mode is not used.
CLKP_1X
G8
Positive input of differential CW 1× clock. In the 1× clock mode, this pin is the quadrature-phase 1× CLKP
for the CW mixer. Can be floated if CW mode is not used.
CM_BYP
B1
Bias voltage and bypass to ground. TI recommends 1 µF. To suppress the ultra-low frequency noise, the
designer can use 10 µF.
E2
Negative differential input of the in-phase summing amplifier. External LPF capacitor must be connected
between CW_IP_AMPINM and CW_IP_OUTP. This pin provides the current output for the CW mixer.
This pin becomes the CH7 PGA negative output when PGA test mode is enabled. Can be floated if not
used.
CW_IP_AMPINP
E1
Positive differential input of the in-phase summing amplifier. External LPF capacitor must be connected
between CW_IP_AMPINP and CW_IP_OUTM. This pin provides the current output for the CW mixer.
This pin becomes the CH7 PGA positive output when PGA test mode is enabled. Can be floated if not
used.
CW_IP_OUTM
F1
Negative differential output for the in-phase summing amplifier. External LPF capacitor must be
connected between CW_IP_AMPINP and CW_IP_OUTPM. Can be floated if not used.
CW_IP_OUTP
F2
Positive differential output for the in-phase summing amplifier. External LPF capacitor must be connected
between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.
CW_IP_AMPINM
8
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SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
CW_QP_AMPINM
J2
Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor must be
connected between CW_QP_AMPINM and CW_QP_OUTP. This pin provides the current output for the
CW mixer. This pin becomes CH8 PGA negative output when PGA test mode is enabled. Can be floated
if not used.
CW_QP_AMPINP
J1
Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor must be
connected between CW_QP_AMPINP and CW_QP_OUTM. This pin provides the current output for the
CW mixer. This pin becomes CH8 PGA positive output when PGA test mode is enabled. Can be floated if
not used.
CW_QP_OUTM
H1
Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor must be
connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.
CW_QP_OUTP
H2
Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor must be
connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.
N8
D1M to D8M
P9 to P7
P3 to P1
ADC CH1 to CH8 LVDS negative outputs
N2
N9
D1P to D8P
R9 to R7
R3 to R1
ADC CH1 to 8 LVDS positive outputs
N1
DCLKM
P6
LVDS bit clock (7x) negative output
DCLKP
R6
LVDS bit clock (7x) positive output
DVDD
N3
N7
ADC digital and I/O power supply, 1.8 V
N5
DVSS
P5
ADC digital ground
R5
N4
DVDD_LDO1,
DVDD_LDO2
N6
When LDO_EN L4 = 1.8 V, demodulator digital power supply generated internally. These two pins should
be separated on the PCB and decoupled respectively with 0.1-µF capacitors. When LDO_EN L4=DVSS,
the internal LDOs are disabled. External higher performance 1.4-V supply can be applied to N4 and N6
for minimizing digital noise emission.
FCLKM
P4
LVDS frame clock (1×) negative output
FCLKP
R4
LVDS frame clock (1×) positive output
INM1 to INM8
C9 to C2
CH1 to CH8 complementary analog inputs. Bypass to ground with ≥0.015-µF capacitors. The HPF
response of the LNA depends on the capacitors.
INP1 to INP8
A9 to A2
CH1 to CH8 analog inputs. AC couple to inputs with ≥0.1-µF capacitors.
LDO_EN
L6
Enable/Disable AFE's internal LDO regulators. When it is tied to 1.8-V DVDD or Logic "1", AFE's internal
LDO is enabled. When it is tied to DVSS or Logic "0", AFE's internal LDO is disabled and external 1.4-V
supply can be applied at N4 and N6 pins, that is, DVDD_LDO1, DVDD_LDO2.
LDO_SETV
M6
Sets the internal LDO votlage. Logic "1" or tie to 1.8-V DVDD sets the LDO output as 1.4V. It can be tied
to DVSS when the internal LDO is disabled.
PDN_ADC
L8
ADC partial (fast) power-down control pin with an internal pulldown resistor of 100 kΩ. Active high. Either
1.8-V or 3.3-V logic level can be used.
PDN_VCA
J8
VCA partial (fast) power-down control pin with an internal pulldown resistor of 20 kΩ. Active high. 3.3-V
logic level should be used.
PDN_GLOBAL
H8
Global (complete) power-down control pin for the entire chip with an internal pulldown resistor of 20 kΩ.
Active high. 3.3-V logic level should be used. When the complete power-down mode is enabled, the
digital demodulator may lose register settings. Therefore, it is required to reconfigure the
demodulator registers, filter coefficient memory, and profile memory after existing the complete
power-down mode.
REFM
L4
0.5-V reference output in the internal reference mode. Must leave floated in the internal reference mode.
TI recommends adding a test point on the PCB for monitoring the reference output
REFP
M4
1.5-V reference output in the internal reference mode. Must leave floated in the internal reference mode.
TI recommends adding a test point on the PCB for monitoring the reference output
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SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
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Pin Functions (continued)
PIN
DESCRIPTION
NAME
NO.
RESET
H9
Hardware reset pin with an internal pulldown resistor of 20 kΩ. Active high. The designer can use 3.3-V
logic level.
SCLK
J9
Serial interface clock input with an internal pulldown resistor of 20 kΩ. This pin is connected to both ADC
and VCA. The designer should use 3.3-V logic.
SDATA
K9
Serial interface data input with an internal pulldown resistor of 20 kΩ. This pin is connected to both ADC
and VCA. The designer should use 3.3-V logic.
SDOUT
M9
Serial interface data readout. High impedance when readout is disabled. This pin is connected to ADC
only. The designer can use 1.8-V logic.
SEN
L9
Serial interface enable with an internal pullup resistor of 20 kΩ. Active low. This pin is connected to both
ADC and VCA. The designer should use 3.3-V logic.
SPI_DIG_EN
M7
Serial interface enable for the digital demodulator memory space. SPI_DIG_EN pin is required to be set
to 0 during SPI transactions to demodulator registers. Each transaction starts by setting SEN as 0 and
terminates by setting it back to 1 (similar to other register transactions). Pull up internally through a 20-kΩ
resistor. This pin is connected to both ADC and VCA. The designer should use 3.3-V logic.
TX_SYNC_IN
L7
System trig signal input. It indicates the start of signal transmission. Either 3.3-V or 1.8-V logic level can
be used. Note: TX_SYNC signal must be synchronized with ADC CLK. Typically, pulse repetition
frequency (PRF) signal can be used for TX_SYNC_IN.
VCNTLM
K4
Negative differential attenuation control pin
VCNTLP
K3
Positive differential attenuation control pin
VHIGH
K5
Bias voltage; bypass to ground with ≥1 µF
VREF_IN
M3
ADC 1.4-V reference input in the external reference mode; bypass to ground with 0.1 µF.
K7
L5
DNC
M5
Do not connect. Must leave floated
M8
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
Supply voltage
MIN
MAX
AVDD
–0.3
3.9
AVDD_ADC
–0.3
2.2
AVDD_5V
–0.3
6
DVDD
–0.3
2.2
DVDD_LDO
–0.3
1.6
UNIT
V
Voltage between AVSS and LVSS
–0.3
0.3
Voltage at analog inputs and digital inputs
–0.3
min [3.6, AVDD + 0.3]
V
260
°C
Peak solder temperature (2)
Maximum junction temperature (TJ), any condition
Operating temperature
Storage temperature, Tstg
(1)
(2)
10
V
105
°C
0
85
°C
–55
150
°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
Device complies with JSTD-020D.
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SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
MAX
3.15
3.6
V
AVDD_ADC
1.7
1.9
V
DVDD
1.7
1.9
V
DVDD_LDO1/2 (internally generated)
1.2
1.4
V
DVDD_LDO1/2 (external supplied)
1.4
1.5
V
4.75
5.5
V
0
85
°C
AVDD
AVDD_5V
Ambient temperature, TA
UNIT
7.4 Thermal Information
AFE5809
THERMAL METRIC (1)
BGA (NFBGA)
UNIT
135 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
34.1
°C/W
5
RθJB
°C/W
Junction-to-board thermal resistance
11.5
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
10.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
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7.5 Electrical Characteristics
AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15 nF at INM, No active termination, VCNTL = 0 V, ƒIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF Filter = 15 MHz, low-noise mode, VOUT = –1 dBFS, Single-ended VCNTL mode, VCNTLM = GND, ADC configured
in internal reference mode, internal 500-Ω CW feedback resistor, CMOS CW clocks, at ambient temperature, TA = 25°C,
Digital demodulator is disabled unless otherwise noted. Min and max values are specified across full-temperature range with
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TGC FULL SIGNAL CHANNEL (LNA + VCAT + LPF + ADC)
en (RTI)
en (RTI)
NF
Input voltage noise over LNA gain (lownoise mode)
Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 24 dB
0.76, 0.83, 1.16
Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 30 dB
0.75, 0.86, 1.12
Input voltage noise over LNA gain (lowpower mode)
Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 24 dB
1.1, 1.2, 1.45
Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 30 dB
1.1, 1.2, 1.45
Input voltage noise over LNA gain
(medium-power mode)
Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 24 dB
1, 1.05, 1.25
Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 30 dB
0.95, 1, 1.2
Input voltage noise at low frequency
ƒ = 100 kHz, INM capacitor = 1 µF, PGA integrator disabled
Input referred current noise
Low-noise mode/medium-power mode/low-power mode
Noise figure
nV/rtHz
nV/rtHz
nV/rtHz
0.9
nV/rtHz
2.7, 2.1, 2
pA/rtHz
Rs = 200 Ω, 200-Ω active termination, PGA = 24 dB, LNA = 12, 18, 24 dB
3.85, 2.4, 1.8
dB
Rs = 100 Ω, 100-Ω active termination, PGA = 24 dB, LNA = 12, 18, 24 dB
5.3, 3.1, 2.3
dB
NF
Noise figure
Rs = 500 Ω, 1 kΩ, no termination, low-NF mode is enabled (Reg53[9] = 1)
0.94, 1.08
dB
NF
Noise figure
Rs = 50 Ω / 200 Ω, no termination, low-noise mode (Reg53[9] = 0)
2.35, 1.05
dB
VMAX
Maximum linear input voltage
LNA gain = 24, 18, 12 dB
250, 500, 1000
VCLAMP
Clamp voltage
Reg52[10:9] = 0, LNA = 24, 18, 12 dB
350, 600, 1150
mVpp
Low-noise mode
24, 30
PGA gain
dB
Medium-power/low-power mode
24, 28.5
LNA = 24 dB, PGA = 30 dB, low-noise mode
Total gain
Ch-CH noise correlation factor without
signal (1)
54
LNA = 24 dB, PGA = 30 dB, medium-power mode
52.5
LNA = 24 dB, PGA = 30 dB, low-power mode
52.5
Summing of 8 channels
0
Full band (VCNTL = 0, 0.8)
Ch-CH noise correlation factor with
signal (1)
0.15, 0.17
1-MHz band over carrier (VCNTL= 0, 0.8)
0.18, 0.75
VCNTL= 0.6 V (22-dB total channel gain)
Signal-to-noise ratio (SNR)
dB
VCNTL= 0, LNA = 18 dB, PGA = 24 dB
68
70
59.3
63
VCNTL= 0, LNA = 24 dB, PGA = 24 dB
dBFS
58
Narrow-band SNR
SNR over 2-MHz band around carrier at VCNTL = 0.6 V (22-dB total gain)
Input common-mode voltage
At INP and INM pins
75
77
dBFS
2.4
V
8
kΩ
Input resistance
Preset active termination enabled
Input capacitance
Input control voltage
VCNTLP – VCNTLM
Common-mode voltage
VCNTLP and VCNTLM
pF
1.5
V
0.75
V
–40
dB
Gain slope
VCNTL= 0.1 to 1.1 V
35
dB/V
Input resistance
Between VCNTLP and VCNTLM
200
kΩ
Input capacitance
Between VCNTLP and VCNTLM
1
pF
TGC response time
VCNTL= 0- to 1.5-V step function
Third-order LPF
1.5
10, 15, 20, 30
Settling time for change in LNA gain
Settling time for change in active
termination setting
µs
MHz
14
µs
1
µs
Noise correlation factor is defined as Nc / (Nu + Nc), where Nc is the correlated noise power in single channel; and Nu is the
uncorrelated noise power in single channel. Its measurement follows the below equation, in which the SNR of single-channel signal and
the SNR of summed eight-channel signal are measured.
NC
=
10
8CH_SNR
10
10
Nu + NC
12
Ω
20
0
Gain range
(1)
50,100,200,400
1CH_SNR
1
x
1
-
56
7
10
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Electrical Characteristics (continued)
AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15 nF at INM, No active termination, VCNTL = 0 V, ƒIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF Filter = 15 MHz, low-noise mode, VOUT = –1 dBFS, Single-ended VCNTL mode, VCNTLM = GND, ADC configured
in internal reference mode, internal 500-Ω CW feedback resistor, CMOS CW clocks, at ambient temperature, TA = 25°C,
Digital demodulator is disabled unless otherwise noted. Min and max values are specified across full-temperature range with
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC ACCURACY
LPF bandwidth tolerance
±5%
CH-CH group delay variation
2 to 15 MHz
CH-CH phase variation
15-MHz signal
0 V < VCNTL< 0.1 V (Dev-to-Dev)
Gain matching
0.1 V < VCNTL< 1.1 V(Dev-to-Dev), TA = 25°C
0.1 V < VCNTL< 1.1 V (Dev-to-Dev), TA = 0°C and 85°C
Channel-to-channel
Output offset
VCNTL= 0, PGA = 30 dB, LNA = 24 dB
ns
°
±0.5
–1
±0.5
1
dB
1.1 V < VCNTL< 1.5 V (Dev-to-Dev)
Gain matching
2
11
±0.5
–1.1
1.1
±0.25
–75
dB
75
LSB
AC PERFORMANCE
HD2
HD3
THD
Second-harmonic distortion
Third-harmonic distortion
Total harmonic distortion
FIN = 2 MHz; VOUT = –1 dBFS
–60
FIN = 5 MHz; VOUT = –1 dBFS
–60
FIN = 5 MHz; VIN= 500 mVPP,
VOUT = –1 dBFS, LNA = 18 dB, VCNTL= 0.88 V
–55
FIN = 5 MHz; VIN = 250 mVPP,
VOUT = –1 dBFS, LNA = 24 dB, VCNTL= 0.88 V
–55
FIN = 2 MHz; VOUT = –1 dBFS
–55
FIN = 5 MHz; VOUT = –1 dBFS
–55
FIN = 5 MHz; VIN = 500 mVPP,
VOUT = –1 dBFS, LNA = 18 dB, VCNTL = 0.88 V
–55
FIN = 5 MHz; VIN = 250 mVPP,
VOUT = –1dBFS, LNA = 2 4dB, VCNTL= 0.88 V
–55
FIN = 2 MHz; VOUT = –1 dBFS
–55
FIN = 5 MHz; VOUT = – 1dBFS
–55
–60
IMD3
Intermodulation distortion
ƒ1 = 5 MHz at –1 dBFS,
ƒ2 = 5.01 MHz at –27 dBFS
XTALK
Cross-talk
FIN = 5 MHz; VOUT= –1 dBFS
Phase noise
kHz off 5 MHz (VCNTL= 0 V)
Input referred voltage noise
Rs = 0 Ω, ƒ = 2 MHz, Rin = High Z, Gain = 24, 18, 12 dB
dBc
dBc
dBc
dBc
–65
dB
–132
dBc/Hz
0.63, 0.70, 0.9
nV/rtHz
50, 100, 150,
200
kHz
4
Vpp
LNA
High-pass filter (HPF)
–3 dB cut-off frequency
LNA linear output
VCAT+ PGA
VCAT input noise
0-dB, –40-dB attenuation
PGA input noise
24 dB, 30 dB
–3 dB HPF cut-off frequency
2, 10.5
nV/rtHz
1.75
nV/rtHz
80
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Electrical Characteristics (continued)
AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15 nF at INM, No active termination, VCNTL = 0 V, ƒIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF Filter = 15 MHz, low-noise mode, VOUT = –1 dBFS, Single-ended VCNTL mode, VCNTLM = GND, ADC configured
in internal reference mode, internal 500-Ω CW feedback resistor, CMOS CW clocks, at ambient temperature, TA = 25°C,
Digital demodulator is disabled unless otherwise noted. Min and max values are specified across full-temperature range with
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CW DOPPLER
en (RTI)
en (RTO)
en (RTI)
en (RTO)
1-channel mixer, LNA = 24 dB, 500-Ω feedback resistor
0.8
8-channel mixer, LNA = 24 dB, 62.5-Ω feedback resistor
0.33
1-channel mixer, LNA = 24 dB, 500-Ω feedback resistor
12
8-channel mixer, LNA = 24 dB, 62.5-Ω feedback resistor
5
1-channel mixer, LNA = 18 dB, 500-Ω feedback resistor
1.1
8-channel mixer, LNA = 18 dB, 62.5-Ω feedback resistor
0.5
1-channel mixer, LNA = 18 dB, 500-Ω feedback resistor
8.1
8-channel mixer, LNA = 18 dB, 62.5-Ω feedback resistor
4
Input voltage noise (CW)
nV/rtHz
Output voltage noise (CW)
nV/rtHz
Input voltage noise (CW)
nV/rtHz
Output voltage noise (CW)
NF
Noise figure
fCW
CW operation range
nV/rtHz
Rs = 100 Ω, RIN = High Z, FIN = 2 MHz (LNA, I/Q mixer and summing
amplifier/filter)
(2)
1.8
CW signal carrier frequency
8
1× CLK (16× mode)
CW clock frequency
dB
MHz
8
16× CLK(16× mode)
128
4× CLK(4× mode)
AC coupled LVDS clock amplitude
0.7
CLKM_16X-CLKP_16X; CLKM_1X-CLKP_1X
Vpp
AC coupled LVPECL clock amplitude
VCMOS
1.6
CLK duty cycle
1× and 16× CLKs
Common-mode voltage
Internal provided
35%
CMOS input clock amplitude
4
CW mixer phase noise
1 kHz off 2-MHz carrier
Input dynamic range
FIN = 2 MHz, LNA = 24/18/12 dB
IMD3
Intermodulation distortion
V
5
4
DR
14
65%
2.5
CW mixer conversion loss
(2)
MHz
32
156
160, 164, 165
V
dB
dBc/Hz
dBFS/Hz
ƒ1 = 5 MHz, ƒ2 = 5.01 MHz, both tones at –8.5-dBm amplitude, 8 channels
summed up in-phase, CW feedback resistor = 87 Ω
–50
dBc
ƒ1 = 5 MHz, ƒ2= 5.01 MHz, both tones at –8.5-dBm amplitude, singlechannel case, CW feedback resistor = 500 Ω
–60
dBc
dB
I/Q channel gain matching
16× mode
±0.04
I/Q channel phase matching
16× mode
±0.1
°
I/Q channel gain matching
4× mode
±0.04
dB
I/Q channel phase matching
4× mode
±0.1
°
Image rejection ratio
FIN = 2.01 MHz, 300-mV input amplitude, CW clock frequency = 2 MHz
–50
dBc
In the 16× operation mode, the CW operation range is limited to 8 MHz due to the 16× CLK. The maximum clock frequency for the 16×
CLK is 128 MHz. In the 8×, 4×, and 1× modes, higher CW signal frequencies up to 15 MHz can be supported with small degradation in
performance, see CW Clock Selection.
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Electrical Characteristics (continued)
AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15 nF at INM, No active termination, VCNTL = 0 V, ƒIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF Filter = 15 MHz, low-noise mode, VOUT = –1 dBFS, Single-ended VCNTL mode, VCNTLM = GND, ADC configured
in internal reference mode, internal 500-Ω CW feedback resistor, CMOS CW clocks, at ambient temperature, TA = 25°C,
Digital demodulator is disabled unless otherwise noted. Min and max values are specified across full-temperature range with
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CW SUMMING AMPLIFIER
VCMO
Common-mode voltage
Summing amplifier inputs and outputs
1.5
Summing amplifier output
100 Hz
V
4
Vpp
2
nV/rtHz
1.2
nV/rtHz
1
nV/rtHz
Input referred current noise
2.5
pA/rtHz
Unit gain bandwidth
200
MHz
20
mApp
Input referred voltage noise
1 kHz
2 kHz to 100 MHz
Max output current
Linear operation range
ADC SPECIFICATIONS
Sample rate
SNR
Signal-to-noise ratio
10
65
MSPS
Idle channel SNR of ADC 14b
77
dBFS
REFP
1.5
V
REFM
0.5
V
VREF_IN voltage
1.4
V
VREF_IN current
50
µA
65 MSPS at 14 bit
910
Internal reference mode
External reference mode
ADC input full-scale range
LVDS rate
2
Vpp
Mbps
POWER DISSIPATION
AVDD voltage
3.15
3.3
3.6
V
1.7
1.8
1.9
V
4.75
5
5.5
V
1.7
1.8
1.9
V
TGC low-noise mode, 65 MSPS
158
190
TGC low-noise mode, 40 MSPS
145
TGC medium-power mode, 40 MSPS
114
AVDD_ADC voltage
AVDD_5V voltage
DVDD voltage
Total power dissipation per channel
mW/CH
TGC low-power mode, 40 MSPS
101.5
TGC low-noise mode, no signal
202
TGC medium-power mode, no signal
126
TGC low-power mode, no signal
240
99
CW-mode, no signal
147
TGC low-noise mode, 500 mVPP Input,1% duty cycle
210
TGC medium-power mode, 500 mVPP Input, 1% duty cycle
133
TGC low power, 500 mVPP Input, 1% duty cycle
105
170
AVDD (3.3-V) current
mA
CW-mode, 500 mVPP Input
375
TGC mode no signal
25.5
CW mode no signal, 16× clock = 32 MHz
32
TGC mode, 500-mVpp Input,1% duty cycle
26
35
AVDD_5V current
mA
CW-mode, 500-mVpp input
42.5
TGC low-noise mode, no signal
99
TGC medium-power mode, no signal
68
TGC low-power mode, no signal
121
55.5
VCA power dissipation
mW/CH
TGC low-noise mode, 500-mVPP input,1% duty cycle
TGC medium-power mode, 500-mVPP Input, 1% duty cycle
TGC low-power mode, 500-mVpp input,1% duty cycle
No signal, ADC shutdown CW mode no signal, 16× clock = 32 MHz
102.5
71
59.5
80
CW power dissipation
mW/CH
500-mVPP input, ADC shutdown , 16× clock = 32 MHz
173
AVDD_ADC (1.8-V) current
65MSPS
187
205
mA
DVDD (1.8-V) current
65 MSPS
77
110
mA
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Electrical Characteristics (continued)
AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15 nF at INM, No active termination, VCNTL = 0 V, ƒIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF Filter = 15 MHz, low-noise mode, VOUT = –1 dBFS, Single-ended VCNTL mode, VCNTLM = GND, ADC configured
in internal reference mode, internal 500-Ω CW feedback resistor, CMOS CW clocks, at ambient temperature, TA = 25°C,
Digital demodulator is disabled unless otherwise noted. Min and max values are specified across full-temperature range with
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V.
PARAMETER
TYP
MAX
65 MSPS
TEST CONDITIONS
MIN
59
69
50 MSPS
51
40 MSPS
46
20 MSPS
35
ADC power dissipation/CH
mW/CH
PDN_VCA = High, PDN_ADC = High
25
Complete power-down PDN_Global = High
0.6
Power dissipation in power-down mode
Power-down response time
Power-up response time
Power supply modulation ratio, AVDD
and AVDD_5V
Power supply rejection ratio
(3)
UNIT
mW/CH
Time taken to enter power down
1
µs
VCA power down
2 µs + 1% of
PDN time
µs
ADC power down
1
Complete power down
2.5
ms
FIN = 5 MHz, at 50 mVPP noise at 1 kHz on supply (3)
–65
dBc
FIN = 5 MHz, at 50 mVpp noise at 50 kHz on supply (3)
–65
ƒ = 10 kHz,VCNTL = 0 V (high gain), AVDD
–40
dBc
ƒ = 10 kHz,VCNTL = 0 V (high gain), AVDD_5 V
–55
dBc
ƒ = 10 kHz,VCNTL = 1 V (low gain), AVDD
–50
dBc
PSMR specification is with respect to carrier signal amplitude.
7.6 Digital Demodulator Electrical Characteristics
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, DVDD_LDO = 1.4 V (internal generated), 14 bit/65
MSPS, 4× decimation factor, at ambient temperature TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Additional power consumption on DVDD (1.8 V)
65 MSPS, 4× decimation factor
90
mW/CH
Additional power consumption on DVDD (1.8 V)
40 MSPS, 4× decimation factor
61
mW/CH
Additional power consumption on DVDD (1.8 V)
65 MSPS, 32× decimation factor, half
LVDS pairs are powered down
77
mW/CH
Additional power consumption on DVDD (1.8 V)
40 MSPS, 32× decimation factor, half
LVDS pairs are powered down
55
mW/CH
VIH
Logic high input voltage, TX_SYNC pin
Support 1.8-V and 3.3-V CMOS logic
1.3
3.3
VIL
Logic low input voltage, TX_SYNC pin
Support 1.8-V and 3.3-V CMOS logic
0
0.3
IIH
Logic high input current, TX_SYNC pin
VHIGH = 1.8 V
IIL
Logic low input current, TX_SYNC pin
VLOW = 0 V
VIH
Logic high input voltage, LDO_EN pin
VIL
Logic low input voltage, LDO_EN pin
IIH
Logic high input current, LDO_EN pin
VHIGH = 1.8 V
IIL
Logic low input current, LDO_EN pin
VLOW = 0 V
16
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11
V
V
µA
< 0.1
µA
1.7
3.3
V
0
0.3
V
11
µA
< 0.1
µA
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7.7 Digital Characteristics
Typical values are at 25°C, AVDD = 3.3 V, AVDD_5 = 5 V and AVDD_ADC = 1.8 V, DVDD = 1.8 V unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = 0°C to TMAX = 85°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT (1)
DIGITAL INPUTS/OUTPUTS
VIH
Logic high input voltage
2
3.3
VIL
Logic low input voltage
0
0.3
V
V
Logic high input current
200
µA
Logic low input current
200
µA
5
pF
VOH
Input capacitance
Logic high output voltage
SDOUT pin
DVDD
V
VOL
Logic low output voltage
SDOUT pin
0
V
LVDS OUTPUTS
Output differential voltage
With 100-Ω external differential
termination
Output offset voltage
Common-mode voltage
FCLKP and FCLKM
1× clock rate
10
65
MHz
DCLKP and DCLKM
7× clock rate
70
455
MHz
6× clock rate
60
390
MHz
400
1100
(2)
tsu
Data setup time
th
Data hold time (2)
mV
mV
350
ps
350
ps
ADC INPUT CLOCK
Clock frequency
10
Clock duty cycle
45%
Sine-wave, AC-coupled
Clock input amplitude,
differential(VCLKP_ADC – VCLKM_ADC)
Common-mode voltage
(2)
MSPS
55%
0.5
Vpp
LVPECL, AC-coupled
1.6
Vpp
LVDS, AC-coupled
0.7
Vpp
Biased internally
Clock input amplitude VCLKP_ADC (singleCMOS clock
ended)
(1)
65
50%
1
1.8
V
Vpp
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1
with 100-Ω external termination.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margins
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7.8 Switching Characteristics
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V. Typical values are at 25°C, Differential clock, CLOAD =
5 pF, RLOAD = 100 Ω, 14 bit, sample rate = 65 MSPS, digital demodulator is disabled, unless otherwise noted. Minimum and
maximum values are across the full temperature range TMIN = 0°C to TMAX = 85°C. (1)
PARAMETER
ta
tj
TEST CONDITIONS
MIN
Aperture delay
The delay in time between the rising edge of the input sampling
clock and the actual time at which the sampling occurs.
Aperture delay
matching
Across channels within the same device
0.7
Aperture jitter
TYP MAX
3
ns
±150
ps
450
Fs rms
11/8
Input
clock
cycles
ADC latency
Default, after reset, or / 0 x 2 [12] = 1, LOW_LATENCY = 1
tdelay
Data and frame clock
delay
Input clock rising edge (zero cross) to frame clock rising edge (zero
cross) minus 3/7 of the input clock period (T)
Δtdelay
Delay variation
At fixed supply and 20°C T difference; device to device
tRISE
Data rise time
Rise time measured from –100 to 100 mV
0.14
tFALL
Data fall time
Fall time measured from 100 to –100 mV 10 MHz < ƒCLKIN < 65
MHz
0.15
tFCLKRISE
Frame clock rise time
Rise time measured from –100 to 100 mV
0.14
Frame clock fall time
Fall time measured from 100 to –100 mV 10 MHz < ƒCLKIN < 65
MHz
0.15
tFCLKFALL
3
5.4
–1
Frame clock duty cycle
Zero crossing of the rising edge to zero crossing of the falling edge
tDCLKRISE
Bit clock rise time
Rise time measured from –100 to 100 mV
0.13
tDCLKFALL
Bit clock fall time
Fall time measured from 100 to –100 mV 10 MHz < ƒCLKIN < 65
MHz
0.12
Bit clock duty cycle
Zero crossing of the rising edge to zero crossing of the falling edge
10 MHz < ƒCLKIN < 65 MHz
(1)
48%
UNIT
50%
46%
7
ns
1
ns
ns
ns
52%
ns
54%
Timing parameters are ensured by design and characterization; not production tested.
7.9 SPI Switching Characteristics
Minimum values across full temperature range TMIN = 0°C to TMAX = 85°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8
V, DVDD = 1.8 V
PARAMETER
MIN
TYP
MAX
UNIT
t1
SCLK period
50
ns
t2
SCLK high time
20
ns
t3
SCLK low time
20
ns
t4
Data setup time
5
ns
t5
Data hold time
5
ns
t6
SEN fall to SCLK rise
8
ns
t7
Time between last SCLK rising edge to SEN rising edge
8
ns
t8
SDOUT delay
18
12
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20
28
ns
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7.10 Output Interface Timing Requirements (14-bit)
ƒCLKIN,
Input Clock
Frequency (
1) (2) (3)
(1)
(2)
(3)
Setup Time (tsu), ns
Hold Time (th), ns
tPROG = (3/7) × T + tdelay, ns
Data Valid to Bit Clock ZeroCrossing
Bit Clock Zero-Crossing to Data
Invalid
Input Clock Zero-Cross (Rising Edge) to
Frame Clock Zero-Cross (Rising Edge)
MHz
MIN
TYP
MIN
TYP
MIN
TYP
MAX
65
0.24
0.37
MAX
0.24
0.38
MAX
11
12
12.5
50
0.41
0.54
0.46
0.57
13
13.9
14.4
40
0.55
0.70
0.61
0.73
15
16
16.7
30
0.87
1.10
0.94
1.1
18.5
19.5
20.1
20
1.30
1.56
1.46
1.6
25.7
26.7
27.3
FCLK timing is the same as for the output data lines. It has the same relation to DCLK as the data pins. Setup and hold are the same
for the data and frame clock.
Data valid is logic high = 100 mV and logic low = –100 mV
Timing parameters are ensured by design and characterization; not production tested.
SPACER
NOTE
The data from Output Interface Timing Requirements (14-bit) can be applied to 12-bit or
16-bit LVDS rates as well. For example, the maximum LVDS output rate at 65 MHz and
14-bit is equal to 910 MSPS, which is approximately equivalent to the rate at 56 MHz and
16 bits.
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tPROG
12-Bit 6x Serialization Mode
Input Signal
Sample N
Sample
N+Cd+1
Sample
N+Cd
ta
ta
Cd clock cycles
latency
Input Clock
CLKIN
Freq = fCLKIN
Frame Clock
FCLK
Freq = fCLKIN
T
tPROG
Bit Clock
DCLK
Freq = 7 x fCLKIN
Output Data
CHnOUT
Data rate = 14 x fCLKIN
D0 D13 D12
D1
(D12) (D13) (D0) (D1)
D11
(D2)
D10 D9
(D3) (D4)
D8
D7
(D5) (D6)
D6
D5
(D7) (D8)
D4
D3
D2
D1
D0
(D9) (D10) (D11) (D12) (D13)
D13 D12
(D0) (D1)
D11 D10
(D2) (D3)
D9
D8
(D4) (D5)
SAMPLE N-Cd
D13
(D0)
D7
D6
(D6) (D7)
D5
D4
D3
D2
D1
D0 D13 D12
(D8) (D9) (D10) (D11) (D12) (D13) (D0) (D1)
SAMPLE N-1
D11 D10
(D2) (D3)
D9
D8
(D4) (D5)
D7
D6
(D6) (D7)
D1
D0 D11
D5
D4
D3
D2
(D8) (D9) (D10) (D11) (D12) (D13) (D0)
D10
(D1)
SAMPLE N
Data bit in MSB First mode
14-Bit 7x Serialization Mode
Data bit in LSB First mode
DCLKP
Bit Clock
DCLKM
tsu
th
th
tsu
Output Data Pair
CHi out
Dn
Dn + 1
T0434-01
LVDS Setup and Hold Timing
Figure 1. LVDS Timing Diagrams
20
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7.11 Typical Characteristics
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
45
45
Low noise
Medium power
Low power
40
35
35
30
Gain (dB)
25
20
25
20
15
15
10
10
5
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Vcntl (V)
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Figure 3. Gain Variation vs Temperature, LNA = 18 dB and
PGA = 24 dB
9000
8000
8000
7000
7000
3000
Gain (dB)
Gain (dB)
G004
G005
Figure 4. Gain Matching Histogram, VCNTL = 0.3 V (34951
Channels)
Figure 5. Gain Matching Histogram, VCNTL = 0.6 V (34951
Channels)
8000
Number of Occurrences
7000
Number of Occurrences
6000
5000
4000
3000
2000
1000
120
110
100
90
80
70
60
50
40
30
20
10
0
−72
−68
−64
−60
−56
−52
−48
−44
−40
−36
−32
−28
−24
−20
−16
−12
−8
−4
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
0
−0.7
0.6
0.5
0.4
0.3
−0.7
0.5
0.4
0.3
0.2
0
0.1
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
0
−0.8
0
−0.9
1000
0.2
2000
1000
0.1
2000
4000
0
3000
5000
−0.1
4000
−0.2
5000
6000
−0.3
6000
−0.4
Number of Occurrences
9000
−0.5
Figure 2. Gain vs VCNTL, LNA = 18 dB and PGA = 24 dB
−0.6
Gain (dB)
30
Number of Occurrences
−40 deg C
25 deg C
85 deg C
40
Gain (dB)
ADC Output
G005
Figure 6. Gain Matching Histogram, VCNTL = 0.9 V (34951
Channels)
G058
Figure 7. Output Offset Histogram, VCNTL = 0 V (1247
Channels)
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Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
10
Open
12000
−10
Phase (Degrees)
10000
Impedance (Ω)
Open
0
8000
6000
4000
−20
−30
−40
−50
−60
−70
2000
−80
500k
4.5M
8.5M
12.5M
16.5M
−90
500k
20.5M
4.5M
Frequency (Hz)
500
350
300
250
200
150
0
−10
−20
−30
−40
−50
−60
100
−70
50
−80
12.5M
16.5M
50 Ω
100 Ω
200 Ω
400 Ω
−90
500k
20.5M
Frequency (Hz)
8.5M
12.5M
16.5M
3
10MHz
15MHz
20MHz
30MHz
0
0
−3
−6
Amplitude (dB)
−5
−10
−15
−9
−12
−15
−18
−20
−21
−25
−24
01
00
11
10
−27
0
10
20
30
40
50
60
−30
10
100
Frequency (MHz)
Figure 12. LPF Response
22
20.5M
Figure 11. Input Impedance With Active Termination (Phase)
5
Amplitude (dB)
4.5M
Frequency (Hz)
Figure 10. Input Impedance With Active Termination
(Magnitude)
−30
20.5M
10
Phase (Degrees)
Impedance (Ω)
400
8.5M
16.5M
Figure 9. Input Impedance Without Active Termination
(Phase)
50 Ω
100 Ω
200 Ω
400 Ω
450
4.5M
12.5M
Frequency (Hz)
Figure 8. Input Impedance Without Active Termination
(Magnitude)
0
500k
8.5M
500
Frequency (kHz)
Figure 13. LNA HPF Response vs Reg59[3:2]
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Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
5
−146
−150
Phase Noise (dBc/Hz)
−5
−10
Amplitude (dB)
16X Clock Mode
8X Clock Mode
4X Clock Mode
−148
0
−15
−20
−25
−152
−154
−156
−158
−160
−162
−164
−30
−166
−35
−40
−168
10
100
−170
100
500
1000
−146
−146
PN 1 Ch
PN 8 Ch
−148
−150
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
16X Clock Mode
8X Clock Mode
4X Clock Mode
−148
−150
−152
−154
−156
−158
−160
−162
−164
−152
−154
−156
−158
−160
−162
−164
−166
−166
−168
−168
−170
100
1000
10000
−170
100
50000
1000
Frequency Offset (Hz)
3.5
Hz)
LNA 12 dB
LNA 18 dB
LNA 24 dB
Input reffered noise (nV
Hz)
50000
Figure 17. CW Phase Noise vs Clock Modes, FIN= 2 MHz
60
Input reffered noise (nV
10000
Offset Frequency (Hz)
Figure 16. CW Phase Noise, FIN = 2 MHz, 1 Channel vs 8
Channel
40
50000
Figure 15. CW Phase Noise, FIN = 2 MHz
Figure 14. Full Channel HPF Response at Default Register
Setting
50
10000
Offset Frequency (Hz)
Frequency (kHz)
30
20
10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Figure 18. IRN, PGA = 24 dB and Low Noise Mode
3.0
LNA 12 dB
LNA 18 dB
LNA 24 dB
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.1
0.2
Vcntl (V)
0.3
0.4
Figure 19. IRN, PGA = 24 dB and Low Noise Mode
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Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
Hz)
60
4.0
LNA 12 dB
LNA 18 dB
LNA 24 dB
50
Input reffered noise (nV
Input reffered noise (nV
Hz)
70
40
30
20
10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Hz)
Input reffered noise (nV
Hz)
Input reffered noise (nV
50
40
30
20
10
1.5
1.0
0.1
0.2
Vcntl (V)
0.3
0.4
LNA 12 dB
LNA 18 dB
LNA 24 dB
Output reffered noise (nV
170
150
130
110
90
70
50
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Figure 24. ORN, PGA = 24 dB and Low Noise Mode
LNA 12 dB
LNA 18 dB
LNA 24 dB
3.0
2.5
2.0
1.5
1.0
0.1
0.2
Vcntl (V)
0.3
0.4
Figure 23. IRN, PGA = 24 dB and Low-Power Mode
Hz)
190
3.5
0.5
0.0
Figure 22. IRN, PGA = 24 dB and Low-Power Mode
220
210
Hz)
2.0
4.0
LNA 12 dB
LNA 18 dB
LNA 24 dB
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Output reffered noise (nV
2.5
Figure 21. IRN, PGA = 24 dB and Medium-Power Mode
70
24
LNA 12 dB
LNA 18 dB
LNA 24 dB
3.0
0.5
0.0
Figure 20. IRN, PGA = 24 dB and Medium-Power Mode
60
3.5
300
280
260
240
220
200
180
160
140
120
100
80
60
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vcntl (V)
LNA 12 dB
LNA 18 dB
LNA 24 dB
1.0 1.1 1.2
Figure 25. ORN, PGA = 24 dB and Medium-Power Mode
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SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
Typical Characteristics (continued)
Output reffered noise (nV
Hz)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
LNA 12 dB
LNA 18 dB
LNA 24 dB
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vcntl (V)
1
1.1 1.2
Figure 26. ORN, PGA = 24 dB and Low-Power Mode
Figure 27. IRN, PGA = 24 dB and Low Noise Mode
75
180.0
120.0
70
SNR (dBFS)
Hz)
140.0
Amplitude (nV
160.0
100.0
80.0
65
60
60.0
40.0
1.0
24 dB PGA gain
30 dB PGA gain
3.0
5.0
7.0
Frequency (MHz)
9.0
55
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
11.0 12.0
Figure 28. ORN, PGA = 24 dB and Low Noise Mode
Figure 29. SNR, LNA = 18 dB and Low Noise Mode
75
73
Low noise
Low power
71
69
SNR (dBFS)
SNR (dBFS)
70
65
60
67
65
63
61
24 dB PGA gain
30 dB PGA gain
55
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
59
57
0
Figure 30. SNR, LNA = 18 dB and Low-Power Mode
3
6
9
12 15 18 21 24 27 30 33 36 39 42
Gain (dB)
Figure 31. SNR vs Different Power Modes
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Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
9
10
100 ohm act term
200 ohm act term
400 ohm act term
Without Termination
8
8
Noise Figure (dB)
Noise Figure (dB)
7
6
5
4
3
7
6
5
4
3
2
2
1
1
0
50
100
150
200
50 ohm act term
100 ohm act term
200 ohm act term
400 ohm act term
Without Termination
9
250
300
350
0
400
50
100
150
Source Impedence (Ω)
200
250
300
350
400
Source Impedence (Ω)
Figure 32. Noise Figure, LNA = 12 dB and Low Noise Mode
Figure 33. Noise Figure, LNA = 18 dB and Low Noise Mode
8
50 ohm act term
100 ohm act term
200 ohm act term
400 ohm act term
No Termination
7
Noise Figure (dB)
6
5
4
3
2
1
0
50
100
150
200
250
300
350
400
Source Impedence (Ω)
Figure 34. Noise Figure, LNA = 24 dB and Low Noise Mode
Figure 35. Noise Figure vs Power Modes With 400-Ω
Termination
−50.0
Low noise
Low power
Medium power
−55.0
HD2 (dB)
−60.0
−65.0
−70.0
−75.0
−80.0
Figure 36. Noise Figure vs Power Modes Without
Termination
26
1
2
3
4
5
6
7
Frequency (MHz)
8
9
10
Figure 37. HD2 vs Frequency, VIN = 500 mVpp and
VOUT = –1 dBFS
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SLOS738E – SEPTEMBER 2012 – REVISED AUGUST 2015
Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
−45
−40
Low noise
Low power
Medium power
−50
−50
−55
HD2 (dBc)
−55
HD3 (dBc)
Low noise
Low power
Medium power
−45
−60
−65
−60
−65
−70
−75
−80
−70
−85
−75
1
2
3
4
5
6
7
Frequency (MHz)
8
9
−90
10
18
24
30
36
Figure 39. HD2 vs Gain, LNA = 12 dB and PGA = 24 dB and
VOUT = –1 dBFS
−40
−40
Low noise
Low power
Medium power
−60
−70
Low noise
Low power
Medium power
−50
HD2 (dBc)
−50
HD3 (dBc)
12
Gain (dB)
Figure 38. HD3 vs Frequency, VIN = 500 mVpp and
VOUT = –1 dBFS
−80
−90
6
−60
−70
−80
6
12
18
24
30
−90
36
12
18
24
Gain (dB)
30
36
42
Gain (dB)
Figure 40. HD3 vs Gain, LNA = 12 dB and PGA = 24 dB and
VOUT = –1 dBFS
Figure 41. HD2 vs Gain, LNA = 18 dB and PGA = 24 dB and
VOUT = –1 dBFS
−40
−40
Low noise
Low power
Medium power
−50
Low noise
Low power
Medium power
−45
−50
HD2 (dBc)
HD3 (dBc)
−55
−60
−70
−60
−65
−70
−75
−80
−80
−85
−90
12
18
24
30
36
42
−90
18
Gain (dB)
24
30
36
42
48
Gain (dB)
Figure 42. HD3 vs Gain, LNA = 18 dB and PGA = 24 dB and
VOUT = –1 dBFS
Figure 43. HD2 vs Gain, LNA = 24 dB and PGA = 24 dB and
VOUT = –1 dBFS
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Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
−50
−40
Fin1=2MHz, Fin2=2.01MHz
Fin1=5MHz, Fin2=5.01MHz
Low noise
Low power
Medium power
−54
IMD3 (dBFS)
−50
HD3 (dB)
−60
−70
−62
−66
−80
−90
−58
−70
18
21
24
27
30
33
36
Gain (dB)
39
42
45
48
14
18
22
26
30
Gain (dB)
34
42
G001
Figure 45. IMD3, Fout1 = –7 dBFS and Fout2 = –21 dBFS
Figure 44. HD3 vs Gain, LNA = 24 dB and PGA = 24 dB and
VOUT = –1 dBFS
−50
−60
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
Fin1=2MHz, Fin2=2.01MHz
Fin1=5MHz, Fin2=5.01MHz
PSMR (dBc)
−54
IMD3 (dBFS)
38
−58
−62
−65
−70
−66
−70
14
18
22
26
30
Gain (dB)
34
38
−75
42
10
100
1000 2000
Supply Frequency (kHz)
Figure 46. IMD3, Fout1 = –7 dBFS and Fout2 = –7 dBFS
Figure 47. AVDD Power Supply Modulation Ratio, 100 mVpp
Supply Noise With Different Frequencies
−20
−55
−65
−70
−75
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−30
PSRR wrt supply tone (dB)
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−60
PSMR (dBc)
5
G001
−40
−50
−60
−70
−80
−80
5
10
100
1000 2000
−90
5
100
1000 2000
Supply Frequency (kHz)
Supply Frequency (kHz)
Figure 48. AVDD_5V Power Supply Modulation Ratio,
100 mVpp Supply Noise With Different Frequencies
28
10
Figure 49. AVDD Power Supply Rejection Ratio, 100 mVpp
Supply Noise With Different Frequencies
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Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
20000.0
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−30
16000.0
14000.0
Output Code
−40
Output Code
Vcntl
18000.0
−50
−60
12000.0
10000.0
8000.0
6000.0
−70
4000.0
2000.0
−80
−90
0.0
0.0
5
10
100
0.5
1.0
1.5
Time (µs)
1000 2000
2.0
2.5
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
3.0
Vcntl (V)
PSRR With Respect to Supply Tone (dB)
−20
Supply Frequency (kHz)
Figure 50. AVDD_5V Power Supply Rejection Ratio,
100 mVpp Supply Noise With Different Frequencies
Output Code
Vcntl
16000.0
Output Code
14000.0
12000.0
10000.0
8000.0
6000.0
4000.0
2000.0
0.0
0.0
0.2
0.5
0.8
1.0 1.2 1.5
Time (µs)
1.8
2.0
2.2
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
2.5
1.2
1.0
0.8
0.6
0.4
Input (V)
18000.0
Vcntl (V)
20000.0
Figure 51. VCNTL Response Time, LNA = 18 dB and
PGA = 24 dB
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−1.2
0.0
Figure 52. VCNTL Response Time, LNA = 18 dB and
PGA = 24 dB
2.0
4.0
6.0
8.0 10.0 12.0 14.0 16.0 18.0 20.0
Time (µs)
Figure 53. Pulse Inversion Asymmetrical Positive Input
1.2
10000.0
1.0
8000.0
0.8
Positive overload
Negative overload
Average
6000.0
0.6
4000.0
Output Code
Input (V)
0.4
0.2
0.0
−0.2
−0.4
2000.0
0.0
−2000.0
−4000.0
−0.6
−6000.0
−0.8
−8000.0
−1.0
−1.2
0.0
2.0
4.0
6.0
8.0 10.0 12.0 14.0 16.0 18.0 20.0
Time (µs)
Figure 54. Pulse Inversion Asymmetrical Negative Input
−10000.0
0.0
1.0
2.0
3.0
Time (µs)
4.0
5.0
6.0
Figure 55. Pulse Inversion, VIN = 2 Vpp, PRF = 1 kHz,
Gain = 21 dB
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Typical Characteristics (continued)
AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF
capacitors at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65
MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended VCNTL mode, VCNTLM = GND, ADC is configured in internal
reference mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient
temperature TA = 25°C, unless otherwise noted.
10000
2000
47nF
15nF
6000
1200
4000
800
2000
0
−2000
400
0
−400
−4000
−800
−6000
−1200
−8000
−1600
−10000
0
0.5
1
1.5
2
2.5
3
Time (µs)
3.5
4
4.5
47nF
15nF
1600
Output Code
Output Code
8000
−2000
5
Figure 56. Overload Recovery Response vs INM Capacitor,
VIN = 50 mVpp/100 µVpp, Max Gain
1
1.5
2
2.5
3
3.5
Time (µs)
4
4.5
5
Figure 57. Overload Recovery Response vs INM Capacitor
(Zoomed), VIN = 50 mVpp/100 µVpp, Max Gain
10
5
0
Gain (dB)
−5
k=2
k=3
k=4
k=5
k=6
k=7
k=8
k=9
k=10
−10
−15
−20
−25
−30
−35
−40
0
0.2
0.4
0.6
0.8
1
1.2 1.4
Frequency (MHz)
1.6
2
G000
Figure 58. Digital HPF Response
30
1.8
Figure 59. Signal Chain Low Frequency Response With INM
Capacitor = 1 µF
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8 Detailed Description
8.1 Overview
The AFE5809 device is a highly-integrated AFE solution specifically designed for ultrasound systems in which
high performance and small size are required. The AFE5809 device integrates a complete TGC imaging path
and a CWD path. It also enables users to select one of various power/noise combinations to optimize system
performance. The AFE5809 device contains eight channels; each channel includes a LNA, VCAT, PGA, LPF, 14bit ADC, digital I/Q demodulator, and CW mixer.
Multiple features in the AFE5809 device are suitable for ultrasound applications, such as active termination,
individual channel control, fast power-up and power-down response, programmable clamp voltage control, and
fast and consistent overload recovery. Therefore, the AFE5809 device brings premium image quality to
ultraportable, handheld systems all the way up to high-end ultrasound systems.
In addition, the signal chain of the AFE5809 device can handle signal frequency as low as 50 kHz and as high as
30 MHz. This enables the AFE5809 device to be used in both sonar and medical applications.
Figure 60 shows a simplified functional block diagram.
8.2 Functional Block Diagram
SPI
IN
16X CLKP
16X CLKN
AFE5809 with Demodulator
1 of 8 Channels
SPI Logic
VCAT
LNA
0 to -40 dB
16 Phases
Generator
1X CLK
CW Mixer
PGA
24, 30dB
3rd LP Filter
10, 15, 20, 30
MHz
14 Bit
ADC
Digital
DeMod &
LP Filter
Summing
Amplifier/ Filter
Reference
Reference
Logic
Control
CW I/Q Vout
Differential
TGC Vcntl
EXT/INT
REFM/P
DeMod
Control
LVDS
LVDS
Serializer OUT
Figure 60. Simplified Functional Block Diagram
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Functional Block Diagram (continued)
Channels 1, 2
-SIN
COS
C0
I
ADC 1
DC
Removal
14bit
40MHz
Down
Conversion
I
Q
Q
Samples
RAM
-SIN
I
DC
Removal
ADC 2
14bit
40MHz
ADC 3
Cn
I
Decimation
Filter
Q
LVDS 1
COS
14bit 40MHz
...
Down
Conversion
Q
C0
...
I
Q
Serializer
Cn
I
Decimation
Filter
640Mbps
Q
Channels 3, 4
LVDS 2
ADC 4
640Mbps
14bit 40MHz
ADC 5
14bit 40MHz
Channels 5, 6
LVDS 3
ADC 6
640Mbps
14bit 40MHz
ADC 7
14bit 40MHz
Channels 7, 8
LVDS 4
ADC 8
640Mbps
14bit 40MHz
COS
-SIN
C0
COS & -SIN
Table
...
Cn
Coefficient
Memory
Freq
Regsiters
Control
Control
Figure 61. Digital Demodulator Block Diagram
8.3 Feature Description
8.3.1 LNA
In many high-gain systems, a LNA is critical to achieve overall performance. Using a new proprietary
architecture, the LNA in the AFE5809 device delivers exceptional low-noise performance, while operating on a
low-quiescent current compared to CMOS-based architectures with similar noise performance. The LNA
performs single-ended input to differential output voltage conversion. It is configurable for a programmable gain
of 24, 18, or 12 dB and its input-referred noise is only 0.63, 0.7, or 0.9 nV/√Hz, respectively. Programmable gain
settings result in a flexible linear input range up to 1 Vpp, realizing high-signal handling capability demanded by
new transducer technologies. A larger input signal can be accepted by the LNA; however, the signal can be
distorted because it exceeds the LNA’s linear operation region. Combining the low noise and high-input range,
the device consequently achieves a wide-input dynamic range for supporting the high demands from various
ultrasound imaging modes.
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Feature Description (continued)
The LNA input is internally biased at approximately 2.4 V; the signal source should be AC-coupled to the LNA
input by an adequately-sized capacitor, for example ≥0.1 µF. To achieve low DC offset drift, the AFE5809 device
incorporates a DC offset correction circuit for each amplifier stage. To improve the overload recovery, an
integrator circuit is used to extract the DC component of the LNA output and then fed back to the LNA’s
complementary input for DC offset correction. This DC offset correction circuit has a high-pass response and can
be treated as a HPF. The effective corner frequency is determined by the capacitor CBYPASS connected at INM.
With larger capacitors, the corner frequency is lower. For stable operation at the highest HP filter cut-off
frequency, a ≥15-nF capacitor can be selected. This corner frequency scales almost linearly with the value of the
CBYPASS. For example, 15 nF gives a corner frequency of approximately 100 kHz, while 47 nF can give an
effective corner frequency of 33 kHz. The DC offset correction circuit can also be disabled or enabled through
register 52[12]. A large capacitor like 1 µF can be used for setting low corner frequency (–2 dBFS. For example, for a –2-dBFS
output level, the HD3 degrades by approximately 3 dB. To maximize the output dynamic range, the maximum
PGA output level can be above 2 Vpp even with the clamp circuit enabled; the ADC in the AFE5809 device has
excellent overload recovery performance to detect small signals right after the overload.
NOTE
In the low-power and medium-power modes, PGA_CLAMP is disabled for saving power if
51[7] = 0.
The AFE5809 device integrates an anti-aliasing filter in the form of a programmable LPF in the transimpedance
amplifier. The LPF is designed as a differential, active, third-order filter with Butterworth characteristics and a
typical 18 dB per octave roll-off. Programmable through the serial interface, the –1-dB frequency corner can be
set to one of 10, 15, 20, and 30 MHz. The filter bandwidth is set for all channels simultaneously.
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A selectable DC offset correction circuit is implemented in the PGA as well. This correction circuit is similar to the
one used in the LNA. It extracts the DC component of the PGA outputs and feeds back to the PGA
complementary inputs for DC offset correction. This DC offset correction circuit also has a high-pass response
with a cut-off frequency of 80 kHz.
8.3.4 ADC
The ADC of the AFE5809 device employs a pipelined converter architecture that consists of a combination of
multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring
excellent differential linearity and no missing codes at the 14-bit level. The 14 bits given out by each channel are
serialized and sent out on a single pair of pins in LVDS format. All eight channels of the AFE5809 device operate
from a common input clock (CLKP/M). The sampling clocks for each of the eight channels are generated from
the input clock using a carefully matched clock buffer tree. The 14× clock required for the serializer is generated
internally from the CLKP/M pins. A 7× and 1× clock are also given out in LVDS format, along with the data, to
enable easy data capture. The AFE5809 device operates from internally-generated reference voltages that are
trimmed to improve the gain matching across devices. The nominal values of REFP and REFM are 1.5 and 0.5
V, respectively. Alternatively, the device also supports an external reference mode that can be enabled using the
serial interface.
Using serialized LVDS transmission has multiple advantages, such as a reduced number of output pins (saving
routing space on the board), reduced power consumption, and reduced effects of digital-noise coupling to the
analog circuit inside the AFE5809 device.
8.3.5 Continuous-Wave (CW) Beamformer
CWD is a key function in mid-end to high-end ultrasound systems. Compared to the TGC mode, the CW path
needs to handle high dynamic range along with strict phase-noise performance. CW beamforming is often
implemented in analog domain due to the strict requirements. Multiple beamforming methods are implemented in
ultrasound systems, including passive delay line, active mixer, and passive mixer. Among all of them, the passive
mixer approach achieves optimized power and noise. It satisfies the CW processing requirements, such as wide
dynamic range, low phase noise, accurate gain and phase matching.
Figure 66 and Figure 67 show a simplified CW path block diagram and an in-phase or quadrature (I/Q) channel
block diagram, respectively. Each CW channel includes a LNA, a voltage-to-current converter, a switch-based
mixer, a shared summing amplifier with a LPF, and clocking circuits.
NOTE
The local oscillator inputs of the passive mixer are cos(ωt) for I-CH and sin(ωt) for Q-CH
respectively. Depending on the users' CW Doppler complex FFT processing, swapping I/Q
channels in FPGA or DSP may be needed to get correct blood flow directions.
All blocks include well-matched in-phase and quadrature channels to achieve good image frequency rejection as
well as beamforming accuracy. As a result, the image rejection ratio from an I/Q channel is better than –46 dBc,
which is desired in ultrasound systems.
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I-CLK
LNA1
Voltage to
Current
Converter
I-CH
Q-CH
Q-CLK
Sum Amp
with LPF
1×fcw CLK
I-CH
Clock
Distribution
Circuits
Q-CH
N×fcw CLK
Sum Amp
with LPF
I-CLK
LNA8
Voltage to
Current
Converter
I-CH
Q-CH
Q-CLK
Figure 66. Simplified Block Diagram of CW Path
ACT1
500Ω
IN1
INPUT1
INM1
Mixer Clock 1
LNA1
Cext
500Ω
ACT2
500Ω
IN2
INPUT2
INM2
Mixer Clock 2
CW_AMPINM
10Ω
10Ω
LNA2
500Ω
CW _AMPINP
Rint/Rext
CW_OUTP
I/V Sum
Amp
Rint/Rext
CW_OUTM
Cext
CW I or Q CHANNEL
Structure
ACT8
500Ω
IN8
INPUT8
INM8
Mixer Clock 8
LNA8
500Ω
Note: The approximately 10- to 15-Ω resistors at CW_AMPINM/P are due to internal IC routing and can create slight
attenuation.
Figure 67. Complete In-Phase or Quadrature-Phase Channel
The CW mixer in the AFE5809 device is passive and switch based; a passive mixer adds less noise than an
active mixer. It achieves good performance at low power. Figure 68 and the equations describe the principles of
mixer operation, where Vi(t), Vo(t), and LO(t) are input, output, and local oscillator (LO) signals for a mixer
respectively. The LO(t) is square-wave based and includes odd harmonic components, as shown in Equation 1.
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Vi(t)
Vo(t)
LO(t)
Figure 68. Block Diagram of Mixer Operation
Vi(t) = sin (w0 t + wd t + j ) + f (w0 t )
4é
1
1
ù
sin (w0 t ) + sin (3w0 t ) + sin (5w0 t )...ú
ê
3
5
pë
û
2
Vo(t) = éëcos (wd t + f ) - cos (2w0 t - wd t + f )...ùû
p
LO(t) =
(1)
From Equation 1, the third-order and fifth-order harmonics from the LO can interface with the third-order and fifthorder harmonic signals in the Vi(t), or the noise around the third-order and fifth-order harmonics in the Vi(t).
Therefore, the mixer’s performance is degraded. To eliminate this side effect due to the square-wave
demodulation, a proprietary harmonic-suppression circuit is implemented in the AFE5809 device. The third- and
fifth-harmonic components from the LO can be suppressed by over 12 dB. Thus, the LNA output noise around
the third-order and fifth-order harmonic bands is not down-converted to base band. Hence, the device achieves
better noise figure. The conversion loss of the mixer is about –4 dB, which is derived from
20log10
2
p.
The mixed current outputs of the eight channels are summed together internally. An internal low-noise
operational amplifier is used to convert the summed current to a voltage output. The internal summing amplifier is
designed to accomplish low-power consumption, low noise, and ease of use. CW outputs from multiple AFE5809
devices can be further combined on system board to implement a CW beamformer with more than eight
channels. See Typical Application for more detailed information.
Multiple clock options are supported in the AFE5809 CW path. Two CW clock inputs are required: N × ƒcw clock
and 1 × ƒcw clock, where ƒcw is the CW transmitting frequency and N could be 16, 8, 4, or 1. Users have the
flexibility to select the most convenient system clock solution for the AFE5809 device. In the 16 × ƒcw and 8 × ƒcw
modes, the third- and fifth-harmonic suppression feature can be supported. Thus, the 16 × ƒcw and 8 × ƒcw
modes achieve better performance than the 4 × ƒcw and 1 × ƒcw modes.
8.3.5.1 16 × ƒcw Mode
The 16 × ƒcw mode achieves the best phase accuracy compared to other modes. It is the default mode for CW
operation. In this mode, 16 × ƒcw and 1 × ƒcw clocks are required. 16 × ƒcw generates LO signals with 16
accurate phases. Multiple AFE5809 devices can be synchronized by the 1 × ƒcw , that is LO signals in multiple
AFEs can have the same starting phase. The phase noise specification is critical only for 16× clock. The 1× clock
is for synchronization only and does not require low phase noise. See the phase noise requirement in Typical
Application.
Figure 69 shows the top-level clock distribution diagram. Each mixer's clock is distributed through a 16 × 8 crosspoint switch. The inputs of the cross-point switch are 16 different phases of the 1× clock. TI recommends aligning
the rising edges of the 1 × ƒcw and 16 × ƒcw clocks.
The cross-point switch distributes the clocks with appropriate phase delay to each mixer. For example, Vi(t) is a
1
received signal with a delay of 16
1
T
T
, a delayed LO(t) should be applied to the mixer to compensate for the 16
2p
delay. Thus a 22.5⁰ delayed clock, that is 16 , is selected for this channel. The mathematic calculation is
expressed in the following equations:
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é æ
ù
1 ö
Vi(t) = sin êw0 ç t +
÷ + wd t ú = sin [w0 t + 22.5° + wd t ]
êë è 16 f0 ø
úû
LO(t) =
é æ
4
1 öù 4
sin êw0 ç t +
÷ ú = sin [w0 t + 22.5°]
p
ëê è 16 f0 ø ûú p
Vo(t) =
2
cos (wd t ) + f (wn t )
p
(2)
Vo(t) represents the demodulated Doppler signal of each channel. When the Doppler signals from N channels
are summed, the signal-to-noise ratio improves.
Fin 16X Clock
INV
D Q
Fin 1X Clock
Fin 1X Clock
16 Phase Generator
1X Clock
Phase 0º
1X Clock
Phase 22.5º
SPI
1X Clock
Phase 292.5º
1X Clock
Phase 315º
1X Clock
Phase 337.5º
16-to-8 Cross Point Switch
Mixer 1
1X Clock
Mixer 2
1X Clock
Mixer 3
1X Clock
Mixer 6
1X Clock
Mixer 7
1X Clock
Mixer 8
1X Clock
Figure 69.
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Figure 70. 1× and 16× CW Clock Timing
8.3.5.2 8 × ƒcw and 4 × ƒcw Modes
8 × ƒcw and 4 × ƒcw modes are alternative modes when a higher frequency clock solution (that is 16 × ƒcw clock)
is not available in system. Figure 71 shows a block diagram of these two modes.
Good phase accuracy and matching are also maintained. Quadrature clock generator is used to create in-phase
and quadrature clocks with exactly 90° phase difference. The only difference between 8 × ƒcw and 4 × ƒcw modes
is the accessibility of the third- and fifth-harmonic suppression filter. In the 8 × ƒcw mode, the suppression filter
1
can be supported. In both modes, 16
T
phase delay resolution is achieved by weighting the in-phase and
1
T
quadrature paths correspondingly. For example, if a delay of 16 or 22.5° is targeted, the weighting coefficients
should follow Equation 3, assuming Iin and Qin are sin(ω0t) and cos(ω0t) respectively.
æ
1 ö
æ 2p ö
æ 2p ö
Idelayed (t) = Iin cos ç ÷ + Qin sin ç ÷ = Iin ç t +
÷
è 16 ø
è 16 ø
è 16 f0 ø
æ
1 ö
æ 2p ö
æ 2p ö
Qdelayed (t) = Qin cos ç ÷ - Iin sin ç ÷ = Qin ç t +
÷
è 16 ø
è 16 ø
è 16 f0 ø
(3)
Therefore, after I/Q mixers, phase delay in the received signals is compensated. The mixers’ outputs from all
channels are aligned and added linearly to improve the signal-to-noise ratio. It is preferred to have the 4 × ƒcw or
8 × ƒcw and 1 × ƒcw clocks both aligned at the rising edge.
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INV
4X/8X Clock
I/Q CLK
Generator
D Q
1X Clock
LNA2~8
In-phase
CLK
Summed
In-Phase
Quadrature
CLK
I/V
Weight
Weight
LNA1
I/V
Weight
Summed
Quadrature
Weight
Figure 71. 8 × ƒcw and 4 × ƒcw Block Diagram
Figure 72. 8 × ƒcw and 4 × ƒcw Timing Diagram
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8.3.5.3 1 × ƒcw Mode
1
T
The 1 × ƒcw mode requires in-phase and quadrature clocks with low phase noise specifications. The 16 phase
delay resolution is also achieved by weighting the in-phase and quadrature signals as described in the 8 × ƒcw
and 4 × ƒcw modes.
Syncronized I/Q
CLOCKs
LNA2~8
In-phase
CLK
Summed
In-Phase
Quadrature
CLK
I/V
Weight
Weight
LNA1
I/V
Weight
Summed
Quadrature
Weight
Figure 73. Block Diagram of 1 x ƒcw mode
8.3.6 Digital I/Q Demodulator
The AFE5809 device also includes a digital in-phase and quadrature (I/Q) demodulator and a low-pass
decimation filter. The main purpose of the demodulation block is to reduce the LVDS data rate and improve
overall system power efficiency. The I/Q demodulator accepts ADC output with up to 65-MSPS sampling rate
and 14-bit resolution. For example, after digital demodulation and 4× decimation filtering, the data rate for either
in-phase or quadrature output is reduced to 16.25 MSPS, and the data resolution is improved to 16 bits
consequently. Hence, the overall LVDS trace reduction can be a factor of 2. This demodulator can be bypassed
and powered down completely if it is not needed.
The digital demodulator block given in the AFE5809 device is designed to do down-conversion followed by
decimation. The top-level block is divided into two exactly similar blocks: (1) subchip0 and (2) subchip1. Both
subchips share four channels each, that is, subchip0 (ADC.1, ADC.2, ADC.3, and ADC.4) and subchip1 (ADC.5,
ADC.6, ADC.7, and ADC.8).
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ADC.1
ADC.2
ADC.3
ADC.4
ADC.5
ADC.6
ADC.7
ADC.8
LVDS.1
CH.A
LVDS.2
CH.B
CH.C
Sub-Chip 0
LVDS.3
LVDS.4
CH.D
LVDS.5
CH.A
LVDS.6
CH.B
Sub-Chip 1
CH.C
CH.D
LVDS.7
LVDS.8
Figure 74. Subchip
The following four functioning blocks are given in each demodulator. Every block can be bypassed.
• DC removal block
• Down conversion
• Decimator
• Channel multiplexing
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Down Conversion
(I Phase)
Decimator
M
A.I
To Channel
Multiplexing
Cos ωt
DC Removal Block
Down
Sampler
Decimation
Filter
DC Offset
Channel A
Down Conversion
(Q Phase)
Decimator
-Sin ωt
M
A.Q
To Channel
Multiplexing
Down
Sampler
Decimation
Filter
Figure 75. Digital Demodulator Block
1. DC removal block is used to remove DC offset. An offset value can be given to a specific register.
2. Down conversion or demodulation of signal is done by multiplying signal by cos(ω0t) and by –sin(ω0t) to give
out I phase and Q phase, respectively. cos(ωt) and –sin(ωt) are 14-bit wide plus a sign bit. ω = 2πƒ, ƒ can
be set with resolution Fs / 216, where Fs is the ADC sampling frequency.
NOTE
The digital demodulator is based on a conventional down converter, that is, –sin(ω0t) is
used for Q phase.
3. The decimator block has two functions: decimation filter and down sampler. Decimation filter is a variable
coefficient symmetric FIR filter and its coefficients can be given using coefficient RAM. Number of taps of FIR
filter is 16× decimation factor (M). For decimation factor of M, 8M coefficients must be stored in the
coefficient bank. Each coefficient is 14-bit wide. Down-sampler gives out 1 sample followed by M – 1
samples zeros.
4. In Figure 76, channel multiplexing is implemented for flexible data routing:
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ADC.1
A.I
ADC.1
Channel A
14bits
16bits
Single Channel
Demodulator Blocks
A.Q
16bits
LVDS.1
C
H
Serializer
DEMOD.1
A
N
N
ADC.2
E
B.I
ADC.2
Channel B
14bits
LVDS.2
L
16bits
Single Channel
Demodulator Blocks
Serializer
DEMOD.2
B.Q
16bits
M
U
ADC.3
L
C.I
ADC.3
Channel C
14bits
16bits
Single Channel
Demodulator Blocks
C.Q
16bits
LVDS.3
Serializer
T
I
DEMOD.3
P
L
E
ADC.4
X
D.I
ADC.4
Channel D
14bits
16bits
Single Channel
Demodulator Blocks
I
N
LVDS.4
Serializer
DEMOD.4
G
D.Q
16bits
Figure 76. Channel Multiplexing
8.3.7 Equivalent Circuits
CM
CM
(a) INP
(b) INM
(c) ACT
S0492-01
Figure 77. Equivalent Circuits of LNA Inputs
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S0493-01
Figure 78. Equivalent Circuits of VCNTLP/M
VCM
5 kΩ
5 kΩ
CLKP
CLKM
(a) CW 1X and 16X Clocks
(b) ADC Input Clocks
S0494-01
Figure 79. Equivalent Circuits of Clock Inputs
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(a) CW_OUTP/M
(b) CW_AMPINP/M
S0495-01
Figure 80. Equivalent Circuits of CW Summing Amplifier Inputs and Outputs
+
–
Low
+Vdiff
High
AFE5809
OUTP
+
–
–Vdiff
+
–
High
Vcommon
Low
External
100-W Load
Rout
OUTM
Switch impedance is
nominally 50 W (±10%)
Figure 81. Equivalent Circuits of LVDS Outputs
8.3.8 LVDS Output Interface Description
The AFE5809 device has a LVDS output interface, which supports multiple output formats. The ADC resolutions
can be configured as 12 bit or 14 bit as shown in the LVDS timing diagrams (Figure 1). The ADCs in the
AFE5809 device are running at 14 bits; 2 LSBs are removed when 12-bit output is selected; and two zeros are
added at LSBs when 16-bit output is selected. Appropriate ADC resolutions can be selected for optimizing
system-performance cost effectiveness. When the devices run at 16-bit mode, higher-end FPGAs are required to
process the higher rate of LVDS data. Corresponding register settings are listed in Table 4.
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8.4 Device Functional Modes
The AFE5809 device is a highly-integrated AFE solution. The AFE5809 device has two functional modes:
pulsed-wave imaging mode and continous-wave Doppler imaging mode. When the AFE5809 device operates in
the pulsed-wave imaging mode, LNA, VCAT, PGA, LPF, 14-bit ADC, and digital I/Q demodulator are active. In
the CWD imaging mode, only LNA and CW mixer are enabled. Either mode can be enabled or programmed by
the registers described below.
8.5 Programming
8.5.1 Serial Peripheral Interface (SPI) Operation
The AFE5809 device has two SPIs. The demodulator SPI interface is independent from the ADC/VCA SPI as
shown in Figure 82. SPI_DIG_EN is used to select ADC/VCA SPI (SPI_DIG_EN='1') or demod SPI
(SPI_DIG_EN='0').
Figure 82. SPI Interface in the AFE5809 Device
8.5.1.1 ADC/VCA Serial Register Write Description
Programming of different modes can be done through the serial interface formed by pins SEN (serial interface
enable), SCLK (serial interface clock), SDATA (serial interface data), and RESET. All these pins have a pulldown
resistor to GND of 20 kΩ. Serial shift of bits into the device is enabled when SEN is low. Serial data, SDATA, is
latched at every rising edge of SCLK when SEN is active (low). The serial data is loaded into the register at
every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits
are ignored. Data can be loaded in multiple of 24-bit words within a single active SEN pulse (an internal counter
counts groups of 24 clocks after the falling edge of SEN). The interface can work with the SCLK frequency from
20 MHz to low speeds (of a few Hertz) and even with non-50% duty cycle SCLK. The data is divided into two
main portions: a register address (8 bits) and the data itself (16 bits), to load on the addressed register. When
writing to a register with unused bits, set these to 0. Figure 83 shows this process.
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Programming (continued)
Start Sequence
End Sequence
SEN
t6
t7
t1
t2
Data Latched On Rising Edge of SCLK
SCLK
t3
SDATA
A7
A5
A6
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t4
t5
Start Sequence
End Sequence
RESET
T0384-01
Figure 83. SPI Timing
NOTE
TI recommends synchronizing SCLK to ADC CLK. Typically, SCLK can be generated by
dividing ADC CLK by an integer factor of N. In a system with multiple AFEs, SCLKs may
not reach all AFEs simultaneously due to routing. To compensate routing differences and
ensure AFEs’ outputs are aligned, SCLK can be adjusted to toggle on either the falling
edge of ADCLK or the rising edge of ADC CLK (ensuring new register settings are loaded
before next ADC sampling clock).
8.5.1.2 ADC/VCA Serial Register Readout Description
The device includes an option where the contents of the internal registers can be read back. This may be useful
as a diagnostic test to verify the serial interface communication between the external controller and the AFE.
First, the bit (Reg0[1]) needs to be set to 1. Then, the user should initiate a
serial interface cycle specifying the address of the register (A7 through A0) whose content must be read. The
data bits are don’t care. The device outputs the contents (D15 through D0) of the selected register on the
SDOUT pin. SDOUT has a typical delay, t8, of 20 ns from the falling edge of the SCLK. For lower speed SCLK,
SDOUT can be latched on the rising edge of SCLK. For higher speed SCLK, for example, if the SCLK period is
less than 60 ns, it is better to latch the SDOUT at the next falling edge of SCLK. Figure 84 shows this operation
(the timing specifications follow the same information provided). In the readout mode, users still can access the
through SDATA/SCLK/SEN. To enable serial register writes, set the
bit back to 0.
The AFE5809 SDOUT buffer is tri-stated and gets enabled only when 0[1] (REGISTER READOUT ENABLE) is
enabled. SDOUT pins from multiple AFE5809 devices can be tied together without any pullup resistors. Level
shifter SN74AUP1T04 can be used to convert 1.8-V logic to 2.5-V/3.3-V logics if needed.
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Programming (continued)
Start Sequence
End Sequence
SEN
t6
t7
t1
t2
SCLK
t3
A7
SDATA
A6
A5
A4
A3
t4
A2
A1
A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D6
D5
D4
D3
D2
D1
D0
t8
t5
D15 D14 D13 D12 D11 D10 D9
SDOUT
D8
D7
Figure 84. Serial Interface Register Read
8.5.1.3 Digital Demodulator SPI Description
Demodulator is enabled after a software or hardware reset. It can be disabled by setting the LSB of register 0x16
as 1. This is done using the ADC SPI interface, that is, SPI_DIG_EN = 1.
To access the specific demodulator registers:
1. SPI_DIG_EN pin is required to be set as 0 during SPI transactions to demodulator registers. Meanwhile,
ADC SEN needs to be set as 0 during demodulator SPI programming.
2. The SPI register address is 8 bits and is made of 2 subchip select bits and 6 register address bits. SPI
register data is 16 bits.
Table 2. Register Address Bit Description
Bit7
Bit6
Bit 5:0
SCID1_SEL
SCID0_SEL
Register address
3. SCID0_SEL enables configuration of channels 1 through 4. SCID1_SEL enables configuration of channels 5
through 8. When performing demodulator SPI write transactions, these SCID bits can be individually or
mutually used with a specific register address.
4. Register configuration is normally shared by both subchips (both SCID bits should be set as 1). An exception
to this rule would be the DC OFFSET registers (0x14 through 0x17) for which specific channel access is
expected.
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ADC.1
ADC.2
ADC.3
ADC.4
ADC.5
ADC.6
ADC.7
ADC.8
LVDS.1
CH.A
LVDS.2
CH.B
CH.C
Sub-Chip 0
LVDS.3
LVDS.4
CH.D
LVDS.5
CH.A
LVDS.6
CH.B
Sub-Chip 1
CH.C
CH.D
A.
Each of two subchips supports four channels.
B.
Each of two demodulators has four channels named as A, B, C, and D.
LVDS.7
LVDS.8
Figure 85. Demod Subchip 0 and Subchip 1
5. Demodulator register readout follows these procedures:
– Write 1 to register 0x0[1]; pin SPI_DIG_EN should be 0 while writing. This is the readout enable register
for demodulator.
– Write 1 to register 0x0[1]; pin SPI_DIG_EN should be 1 while writing. This is the readout enable register
for ADC and VCA.
– Set SPI_DIG_EN as 0 and write anything to the register whose stored data needs to be known. Device
finds the address of the register and sends its stored data at the SDOUT pin serially.
NOTE
After enabling the register 0x0[1] REGISTER_READOUT_ENABLE, data cannot be
written to the register (whose data needs to be known), but stored data would come
serially at the SDOUT pin.
– To disable the register readout, first write 0 to register 0x0[1] while SPI_DIG_EN is 1; then write 0 to
register 0x0[1] while SPI_DIG_EN is 0.
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8.6 Register Maps
8.6.1 ADC and VCA Register Description
A reset process is required at the AFE5809 device's initialization stage. Initialization can be done in one of two
ways:
• Through a hardware reset, by applying a positive pulse in the RESET pin.
• Through a software reset, using the serial interface, by setting the SOFTWARE RESET bit to high. Setting
this bit initializes the internal registers to the respective default values (all zeros), and then self-resets the
SOFTWARE RESET bit to low. In this case, the RESET pin can stay low (inactive).
After reset, all ADC and VCA registers are set to 0, that is default setting. During register programming, all
unlisted register bits must be set as 0.
Some demodulator registers are set as 1 after reset. During register programming, all unlisted register bits must
be set as 0. In addition, the demodulator registers can be reset when 0x16[0] is set as 0. Thus, it is required to
reconfigure the demodulator registers after toggling the 0x16[0] from 1 to 0.
8.6.1.1 ADC Register Map
Address
(DEC)
0[0]
0[1]
Address
(HEX)
0x0[0]
0x0[1]
Default
Value
0
0
Function
Description
SOFTWARE_RESET
0: Normal operation
1: Resets the device and self-clears the bit to 0. Note: Register 0 is a write
only register.
REGISTER_READOUT_ENABLE
0:Disables readout
1: Enables readout of register at SDOUT pin. Note: When this bit is set to 0,
the device always operates in write mode and when it is set to 1, device will be
in read mode. Multiple reading or writing events can be performed when this
bit is set to 1 or 0 correspondingly. Register 0 is a write-only register.
1[0]
0x1[0]
0
ADC_COMPLETE_PDN
0: Normal
1: Complete power down. Note: When the complete power-down mode is
enabled, the digital demodulator may lose register settings. Therefore, it is
required to reconfigure the demodulator registers, filter coefficient memory,
and profile memory after exiting the complete power-down mode.
1[1]
0x1[1]
0
LVDS_OUTPUT_DISABLE
0: Output enabled
1: Output disabled
1[9:2]
0x1[9:2]
0
ADC_PDN_CH
0: Normal operation
1: Power down. Power down individual ADC channels.
1[9] → CH8…1[2] → CH1
1[10]
0x1[10]
0
PARTIAL_PDN
0: Normal operation
1: Partial power down ADC
1[11]
0x1[11]
0
LOW_FREQUENCY_
NOISE_SUPPRESSION
0: No suppression
1: Suppression enabled
1[13]
0x1[13]
0
EXT_REF
0: Internal reference
1: External reference. VREF_IN is used. Both 3[15] and 1[13] should be set as
1 in the external reference mode
1[14]
0x1[14]
0
LVDS_OUTPUT_RATE_2X
0: 1× rate
1: 2× rate. Combines data from 2 channels on 1 LVDS pair. When ADC clock
rate is low, this feature can be used.
1[15]
0x1[15]
0
SINGLE-ENDED_CLK_MODE
0: Differential clock input
1: Single-ended clock input
2[2:0]
0x2[2:0]
0
RESERVED
Set to 0
2[10:3]
0x2[10:3]
0
POWER-DOWN_LVDS
0: Normal operation
1: PDN individual LVDS outputs. 2[10] → CH8…2[3] → CH1
2[11]
0x2[11]
0
AVERAGING_ENABLE
0: No averaging
1: Average two channels to increase SNR
2[12]
0x2[12]
0
LOW_LATENCY
0: Default latency with digital features supported
1: Low latency with digital features bypassed
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Register Maps (continued)
Address
(DEC)
2[15:13]
Address
(HEX)
0x2[15:13]
Default
Value
0
Function
Description
TEST_PATTERN_MODES
000: Normal operation
001: Sync
010: De-skew
011: Custom
100:All 1's
101: Toggle
110: All 0's
111: Ramp
3[7:0]
0x3[7:0]
0
INVERT_CHANNELS
0: No inverting
1: Invert channel digital output. 3[7] → CH8;3[0] → CH1. Note: Suppose that
the device is giving digital output of 11001100001111. After enabling this bit,
output of device becomes 00110011110000. Note: This function is not
applicable for ADC test patterns and in demod mode.
3[8]
0x3[8]
0
CHANNEL_OFFSET_
SUBSTRACTION_ENABLE
0: No offset subtraction
1: Offset value subtract enabled
3[9:11]
0x3[9:11]
0
RESERVED
Set to 0
3[12]
0x3[12]
0
DIGITAL_GAIN_ENABLE
0: No digital gain
1: Digital gain enabled
3[14:13]
0x3[14:13]
0
SERIALIZED_DATA_RATE
Serialization factor
00: 14×
01: 16×
10: Reserved
11: 12×
When 4[1] = 1, in the 16× serialization rate, two zeros are filled at two LSBs
(see Table 4). Note: Make sure the settings aligning with the demod register
0x3[14:13]. Be aware that the same setting, for example, 00, in these two
registers can represent different LVDS data rates respectively.
3[15]
0x3[15]
0
ENABLE_EXTERNAL_
REFERENCE_MODE
0: Internal reference mode
1: Set to external reference mode
Note: Both 3[15] and 1[13] should be set as 1 when configuring the device in
the external reference mode.
4[1]
0x4[1]
0
ADC_RESOLUTION_SELECT
0: 14 bit
1: 12 bit
4[3]
0x4[3]
0
ADC_OUTPUT_FORMAT
0: 2's complement
1: Offset binary
Note: When the demodulation feature is enabled, only 2's complement
format can be selected.
4[4]
0x4[4]
0
LSB_MSB_FIRST
0: LSB first
1: MSB first
5[13:0]
0x5[13:0]
0
CUSTOM_PATTERN
Custom pattern data for LVDS output (2[15:13] = 011)
10[8]
0xA[8]
0
SYNC_PATTERN
0: Test pattern outputs of 8 channels are not synchronized.
1: Test pattern outputs of 8 channels are synchronized.
13[9:0]
0xD[9:0]
0
OFFSET_CH1
Value to be subtracted from channel 1 code
13[15:11]
0xD[15:11]
0
DIGITAL_GAIN_CH1
0 to 6 dB in 0.2-dB steps
15[9:0]
0xF[9:0]
0
OFFSET_CH2
Value to be subtracted from channel 2 code
15[15:11]
0xF[15:11]
0
DIGITAL_GAIN_CH2
0 to 6 dB in 0.2-dB steps
17[9:0]
0x11[9:0]
0
OFFSET_CH3
Value to be subtracted from channel 3 code
17[15:11]
0x11[15:11]
0
DIGITAL_GAIN_CH3
0 to 6 dB in 0.2-dB steps
19[9:0]
0x13[9:0]
0
OFFSET_CH4
Value to be subtracted from channel 4 code
19[15:11]
0x13[15:11]
0
DIGITAL_GAIN_CH4
0 to 6 dB in 0.2-dB steps
21[0]
0x15[0]
0
DIGITAL_HPF_FILTER_ENABLE
_ CH1-4
0: Disable the digital HPF filter;
1: Enable for 1 to 4 channels
Note: This HPF feature is only available when the demodulation block is
disabled.
21[4:1]
0x15[4:1]
0
DIGITAL_HPF_FILTER_K_CH1-4
Set K for the HPF (k from 2 to 10, that is 0010B to 1010B).
This group of four registers controls the characteristics of a digital high-pass
transfer function applied to the output data, following the formula:
y(n) = 2k/(2k + 1) [x(n) – x(n – 1) + y(n – 1)] (see Table 3)
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Register Maps (continued)
Address
(DEC)
Address
(HEX)
Default
Value
Function
Description
22[0]
0x16[0]
0
EN_DEMOD
0: Digital demodulator is enabled
1: Digital demodulator is disabled
Note: The demodulator registers can be reset when 0x16[0] is set as 0. Thus,
it is required to reconfigure the demodulator registers after toggling the
0x16[0].
25[9:0]
0x19[9:0]
0
OFFSET_CH8
Value to be subtracted from channel 8 code
25[15:11]
0x19[15:11]
0
DIGITAL_GAIN_CH8
0 to 6-dB in 0.2-dB steps
27[9:0]
0x1B[9:0]
0
OFFSET_CH7
Value to be subtracted from channel 7 code
27[15:11]
0x1B[15:11]
0
DIGITAL_GAIN_CH7
0 to 6-dB in 0.2-dB steps
29[9:0]
0x1D[9:0]
0
OFFSET_CH6
Value to be subtracted from channel 6 code
29[15:11]
0x1D[15:11]
0
DIGITAL_GAIN_CH6
0 to 6-dB in 0.2-dB steps
31[9:0]
0x1F[9:0]
0
OFFSET_CH5
Value to be subtracted from channel 5 code
31[15:11]
0x1F[15:11]
0
DIGITAL_GAIN_CH5
0 to 6-dB in 0.2-dB steps
33[0]
0x21[0]
0
DIGITAL_HPF_FILTER_ENABLE
_ CH5-8
0: Disable the digital HPF filter
1: Enable for 5 to 8 channels
Note: This HPF feature is only available when the demodulation block is
disabled.
DIGITAL_HPF_FILTER_K_CH5-8
Set K for the HPF (k from 2 to 10, 0010B to 1010B)
This group of four registers controls the characteristics of a digital high-pass
transfer function applied to the output data, following the formula:
y(n) = 2k / (2k + 1) [x(n) – x(n – 1) + y(n – 1)] (see Table 3)
33[4:1]
0x21[4:1]
0
8.6.1.2 AFE5809 ADC Register/Digital Processing Description
The ADC in the AFE5809 device has extensive digital processing functionality, which can be used to enhance
ultrasound system performance. The digital processing blocks are arranged as in Figure 86.
ADC
Output
12/14b
Channel
Average
Default=No
Digital
Gain
Default=0
Digital HPF
Default = No
12/14b
Final
Digital
Output
Digital Offset
Default=No
Figure 86. ADC Digital Block Diagram
NOTE
These digital processing features are only available when the demodulation block is
disabled. ADC output data directly enter the digital demodulator when the demod is
enabled.
8.6.1.2.1 AVERAGING_ENABLE: Address: 2[11]
When set to 1, two samples, corresponding to two consecutive channels, are averaged (channel 1 with 2, 3 with
4, 5 with 6, and 7 with 8). If both channels receive the same input, the net effect is an improvement in SNR. The
averaging is performed as:
• Channel 1 + channel 2 comes out on channel 3
• Channel 3 + channel 4 comes out on channel 4
• Channel 5 + channel 6 comes out on channel 5
• Channel 7 + channel 8 comes out on channel 6
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8.6.1.2.2 ADC_OUTPUT_FORMAT: Address: 4[3]
The ADC output, by default, is in 2’s-complement mode. Programming the ADC_OUTPUT_FORMAT bit to 1
inverts the MSB, and the output becomes straight-offset binary mode.
NOTE
When the demodulation feature is enabled, only 2's complement format can be selected.
8.6.1.2.3 ADC Reference Mode: Address 1[13] and 3[15]
The following shows the register settings for the ADC internal reference mode and external reference mode.
• 0x1[13] 0x3[15] = 00: ADC internal reference mode, VREF_IN floating (pin M3)
• 0x1[13] 0x3[15] = 01: N/A
• 0x1[13] 0x3[15] = 10: N/A
• 0x1[13] 0x3[15] = 11: ADC external reference mode, VREF_IN = 1.4 V (pin M3)
8.6.1.2.4 DIGITAL_GAIN_ENABLE: Address: 3[12]
Setting this bit to 1 applies to each channel i the corresponding gain given by DIGTAL_GAIN_CHi . The
gain is given as 0 dB + 0.2 dB × DIGTAL_GAIN_CHi. For instance, if DIGTAL_GAIN_CH5 = 3,
channel 5 is increased by 0.6-dB gain. DIGTAL_GAIN_CHi = 31 produces the same effect as
DIGTAL_GAIN_CHi = 30, setting the gain of channel i to 6 dB.
8.6.1.2.5 DIGITAL_HPF_ENABLE
•
•
CH1 to CH4: Address 21[0]
CH5 to CH8: Address 33[0]
8.6.1.2.6 DIGITAL_HPF_FILTER_K_CHX
•
•
CH1 to CH4: Address 21[4:1]
CH5 to CH8: Address 33[4:1]
This group of registers controls the characteristics of a digital high-pass transfer function applied to the output
data, following Equation 4.
y (n ) =
2k
2k + 1
éë x (n ) - x (n - 1) + y (n - 1)ùû
(4)
These digital HPF registers (one for the first four channels and one for the second group of four channels)
describe the setting of K. The digital HPF can be used to suppress low frequency noise, which commonly exists
in ultrasound echo signals. The digital filter can significantly benefit near-field recovery time due to T/R switch
low-frequency response. Table 3 shows the cut-off frequency versus K.
Table 3. Digital HPF –1-dB Corner Frequency versus K and Fs
k
40 MSPS
50 MSPS
65 MSPS
2
2780 kHz
3480 kHz
4520 kHz
3
1490 kHz
1860 kHz
2420 kHz
4
770 kHz
960 kHz
1250 kHz
8.6.1.2.7 LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
The low-frequency noise suppression mode is especially useful in applications where good noise performance is
desired in the frequency band of 0 to 1 MHz (around DC). Setting this mode shifts the low-frequency noise of the
AFE5809 device to approximately Fs / 2, thereby moving the noise floor around DC to a much lower value.
Register bit 1[11] is used for enabling or disabling this feature. When this feature is enabled, power consumption
of the device is increased slightly by approximately 1 mW/CH.
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8.6.1.2.8 LVDS_OUTPUT_RATE_2X: Address: 1[14]
The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges
of the LVDS bit clock, DCLK. The output rate is set by default to 1× (LVDS_OUTPUT_RATE_2X = 0), where
each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one
LVDS stream, in this way lowering the power consumption devoted to the interface. The unused outputs will
output zero. To avoid consumption from those outputs, no termination should be connected to them. The
distribution on the used output pairs is done in the following way:
• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.
• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.
• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.
• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first.
8.6.1.2.9 CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
Setting this bit to 1 enables the subtraction of the value on the corresponding OFFSET_CHx (offset for
channel i) from the ADC output. The number is specified in 2's complement format. For example,
OFFSET_CHx = 11 1000 0000 means subtract –128. For OFFSET_CHx = 00 0111 1111 the effect is
to subtract 127. In effect, both addition and subtraction can be performed. The offset is applied before the digital
gain (see DIGITAL_GAIN_ENABLE). The whole data path is 2's complement throughout internally, with digital
gain being the last step. Only when ADC_OUTPUT_FORMAT = 1 (straight binary output format) is the 2's
complement word translated into offset binary at the end.
8.6.1.2.10 SERIALIZED_DATA_RATE: Address: 3[14:13]
See Table 4 for detailed description.
Table 4. Corresponding Register Settings
LVDS Rate
12 bit (6× DCLK)
14 bit (7× DCLK)
Register 3 [14:13]
11
00
16 bit (8× DCLK)
01
Register 4 [2:0]
010
000
000
Description
2 LSBs removed
N/A
2 zeroes added at LSBs
8.6.1.2.11 TEST_PATTERN_MODES: Address: 2[15:13]
The AFE5809 device can output a variety of test patterns on the LVDS outputs. These test patterns replace the
normal ADC data output. The device may also be made to output 6 preset patterns:
• Ramp: Setting Register 2[15:13] = 111 causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
• Zeros: The device can be programmed to output all 0 s by setting Register 2[15:13] = 110.
• Ones: The device can be programmed to output all 1 s by setting Register 2[15:13] = 100.
• Deskew Patten: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101
word.
• Sync Pattern: When 2[15:13] = 001, the normal ADC output is replaced by a fixed 11111110000000 word.
• Toggle: When 2[15:13] = 101, the normal ADC output is alternating from 1 s to 0 s. The start state of ADC
word can be either 1 s or 0 s.
• Custom Pattern: It can be enabled when 2[15:13] = 011. Users can write the required VALUE into register bits
, which is Register 5[13:0]. Then, the device will output VALUE at its outputs, about 3
to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24 SCLK
clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register
5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be
high. For example, 128 points custom pattern takes approximately 128 × (24 SCLK clock cycles + 4 ADC
clock cycles).
56
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NOTE
Only one of the above patterns can be active at any given instant. Test pattern from the
ADC output stage can NOT be sent to the demodulator; it can only be sent to the LVDS
serializer when the demodulator is off.
8.6.1.2.12 SYNC_PATTERN: Address: 10[8]
By enabling this bit, all channels' test pattern outputs are synchronized. When 10[8] is set as 1, the ramp
patterns of all 8 channels start simultaneously.
8.6.1.3 VCA Register Map
Address
(DEC)
Address
(HEX)
Default
Value
Function
Description
51[0]
0x33[0]
0
RESERVED
0
51[3:1]
0x33[3:1]
0
LPF_PROGRAMMABILITY
000: 15 MHz
010: 20 MHz
011: 30 MHz
100: 10 MHz
Note: 0x3D[14], that is, 5 MHz LPF, should be set
as 0.
51[4]
0x33[4]
0
PGA_INTEGRATOR_DISABLE
(PGA_HPF_DISABLE)
0: Enable
1: Disable offset integrator for PGA. See the
explanation for the PGA integrator function in the
Application Information section
51[7:5]
0x33[7:5]
0
PGA_CLAMP_LEVEL
Low-noise mode: 53[11:10] = 00
000: –2 dBFS
010: 0 dBFS
1XX: Clamp is disabled
Low-power/medium-power mode; 53[11:10] =
01/10
100: –2 dBFS
110: 0 dBFS
0XX: clamp is disabled
Note: The clamp circuit makes sure that PGA
output is in linear range. For example, at 000
setting, PGA output HD3 will worsen by 3 dB at
–2-dBFS ADC input. In normal operation, clamp
function can be set as 000 in the low-noise mode.
The maximum PGA output level can exceed 2Vpp
with the clamp circuit enabled.
Note: In the low-power and medium-power
modes, PGA_CLAMP is disabled for saving power
if 51[7] = 0. .
Note: Register 61[15] should be set as 0;
otherwise, PGA_CLAMP_LEVEL is affected by
Register 61[15].
51[13]
0x33[13]
0
PGA_GAIN_CONTROL
0:24 dB
1:30 dB
52[4:0]
0x34[4:0]
0
ACTIVE_TERMINATION_
INDIVIDUAL_RESISTOR_CNTL
See Table 6. Register 52[5] should be set as 1 to
access these bits
52[5]
0x34[5]
0
ACTIVE_TERMINATION_
INDIVIDUAL_RESISTOR_ENABLE
0: Disable
1: Enable internal active termination individual
resistor control
52[7:6]
0x34[7:6]
0
PRESET_ACTIVE_ TERMINATIONS
00: 50 Ω
01: 100 Ω
10: 200 Ω
11: 400 Ω
Note: The device adjusts resistor mapping
(52[4:0]) automatically. 50-Ω active termination is
not supported in 12-dB LNA setting. Instead, 00
represents high-impedance mode when LNA gain
is 12 dB.
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Address
(DEC)
Address
(HEX)
Default
Value
Function
Description
52[8]
0x34[8]
0
ACTIVE TERMINATION ENABLE
0: Disable
1: Enable active termination
52[10:9]
0x34[10:9]
0
LNA_INPUT_CLAMP_SETTING
00: Auto setting
01: 1.5 Vpp
10: 1.15 Vpp
11: 0.6 Vpp
52[11]
0x34[11]
0
RESERVED
Set to 0
52[12]
0x34[12]
0
LNA_INTEGRATOR_DISABLE
(LNA_HPF_DISABLE)
0: Enable
1: Disable offset integrator for LNA. See the
explanation for this function in the following
section
52[14:13]
0x34[14:13]
0
LNA_GAIN
00: 18 dB
01: 24 dB
10: 12 dB
11: Reserved
52[15]
0x34[15]
0
LNA_INDIVIDUAL_CH_CNTL
0: Disable
1: Enable LNA individual channel control. See
Register 57 for details
53[7:0]
0x35[7:0]
0
PDN_CH
0: Normal operation
1: Powers down corresponding channels. Bit7 →
CH8, Bit6 → CH7…Bit0 → CH1. PDN_CH shuts
down whichever blocks are active depending on
TGC mode or CW mode.
53[8]
0x35[8]
0
RESERVED
Set to 0
53[9]
0x35[9]
0
LOW_NF
0: Normal operation
1: Enable low-noise figure mode for highimpedance probes
53[11:10]
0x35[11:10]
0
POWER_MODES
00: Low noise mode
01: Set to low-power mode. At 30-dB PGA, total
chain gain may slightly change. See Typical
Characteristics.
10: Set to medium-power mode. At 30-dB PGA,
total chain gain may slightly change. See Typical
Characteristics.
11: Reserved
53[12]
0x35[12]
0
PDN_VCAT_PGA
0: Normal operation
1: Powers down VCAT and PGA
53[13]
0x35[13]
0
PDN_LNA
0: Normal operation
1: Powers down LNA only
53[14]
0x35[14]
0
VCA_PARTIAL_PDN
0: Normal operation
1: Powers down LNA, VCAT, and PGA partially
(fast-wake response)
53[15]
0x35[15]
0
VCA_COMPLETE_PDN
0: Normal operation
1: Power down LNA, VCAT, and PGA completely
(slow-wake response). This bit can overwrite
53[14].
54[4:0]
0x36[4:0]
0
CW_SUM_AMP_GAIN_CNTL
Select feedback resistor for the CW amplifier as
per Table 6
54[5]
0x36[5]
0
CW_16X_CLK_SEL
0: Accept differential clock
1: Accept CMOS clock
54[6]
0x36[6]
0
CW_1X_CLK_SEL
0: Accept CMOS clock
1: Accept differential clock
54[7]
0x36[7]
0
RESERVED
Set to 0
54[8]
0x36[8]
0
CW_TGC_SEL
0: TGC mode
1 : CW mode
Note : VCAT and PGA are still working in CW
mode. They should be powered down separately
through 53[12].
58
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Address
(DEC)
Address
(HEX)
Default
Value
Function
Description
54[9]
0x36[9]
0
CW_SUM_AMP_ENABLE
0: Enable CW summing amplifier
1: Disable CW summing amplifier
Note: 54[9] is only effective in CW mode.
54[11:10]
0x36[11:10]
0
CW_CLK_MODE_SEL
00: 16× mode
01: 8× mode
10: 4× mode
11: 1× mode
55[3:0]
0x37[3:0]
0
CH1_CW_MIXER_PHASE
55[7:4]
0x37[7:4]
0
CH2_CW_MIXER_PHASE
55[11:8]
0x37[11:8]
0
CH3_CW_MIXER_PHASE
55[15:12]
0x37[15:12]
0
CH4_CW_MIXER_PHASE
56[3:0]
0x38[3:0]
0
CH5_CW_MIXER_PHASE
56[7:4]
0x38[7:4]
0
CH6_CW_MIXER_PHASE
56[11:8]
0x38[11:8]
0
CH7_CW_MIXER_PHASE
56[15:12]
0x38[15:12]
0
CH8_CW_MIXER_PHASE
57[1:0]
0x39[1:0]
0
CH1_LNA_GAIN_CNTL
57[3:2]
0x39[3:2]
0
CH2_LNA_GAIN_CNTL
0000 → 1111, 16 different phase delays, see
Table 10
00: 18 dB
01: 24 dB
10: 12 dB
11: Reserved
REG52[15] should be set as 1.
57[5:4]
0x39[5:4]
0
CH3_LNA_GAIN_CNTL
57[7:6]
0x39[7:6]
0
CH4_LNA_GAIN_CNTL
00: 18 dB
01: 24 dB
10: 12 dB
11: Reserved
REG52[15] should be set as 1.
57[9:8]
0x39[9:8]
0
CH5_LNA_GAIN_CNTL
57[11:10]
0x39[11:10]
0
CH6_LNA_GAIN_CNTL
57[13:12]
0x39[13:12]
0
CH7_LNA_GAIN_CNTL
57[15:14]
0x39[15:14]
0
CH8_LNA_GAIN_CNTL
59[3:2]
0x3B[3:2]
0
HPF_LNA
00: 100 kHz
01: 50 kHz
10: 200 kHz
11: 150 kHz with 0.015 µF on INMx
59[6:4]
0x3B[6:4]
0
DIG_TGC_ATT_GAIN
000: 0-dB attenuation
001: 6-dB attenuation
N: About N × 6 dB attenuation when 59[7] = 1
59[7]
0x3B[7]
0
DIG_TGC_ATT
0: Disable digital TGC attenuator
1: Enable digital TGC attenuator
59[8]
0x3B[8]
0
CW_SUM_AMP_PDN
0: Power down
1: Normal operation
Note: 59[8] is only effective in TGC test mode.
59[9]
0x3B[9]
0
PGA_TEST_MODE
0: Normal CW operation
1: PGA outputs appear at CW outputs.
61[13]
0x3D[13]
0
V2I_CLAMP
0: Clamp disabled
1: Clamp enabled at the V2I input. An additional
voltage clamp at the V2I input. This limits the
amount of overload signal the PGA sees.
Note: This bit is supported by AFE5809 with date
code later than 2014, that is, date code >41XXXX.
61[14]
0x3D[14]
0
5MHz_LPF
0: 5-MHz LPF disabled
1: 5-MHz LPF enabled. Suppress signals >5 MHz
or high-order harmonics. The LPF Register
51[3:1] needs to be set as 100, that is, 10 MHz.
Note: This bit is supported by AFE5809 with date
code later than 2014, that is date code >41XXXX.
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Address
(DEC)
Address
(HEX)
Default
Value
Function
Description
61[15]
0x3D[15]
0
PGA_CLAMP_-6dBFS
0: Disable the –6-dBFS clamp. PGA_CLAMP is
set by Reg51[7:5].
1: Enable the –6-dBFS clamp. PGA_CLAMP
Reg51[7:5] should be set as 000 in the lownoise mode or 100 in the low-power/mediumpower mode. In this setting, PGA output HD3 will
be worsen by 3 dB at –6-dBFS ADC input. The
actual PGA output is reduced to approximately 1.5
Vpp, about 2.5 dB below the ADC full-scale input
2 Vpp . As a result, AFE5809’s LPF is not
saturated, and it can suppress harmonic signals
better at PGA output. Due to PGA output
reduction, the ADC output dynamic range is
impacted.
Note: This bit is supported by AFE5809 with
date code later than 2014, that is date code
>41XXXX.
Note: This bit is ONLY valid when PGA=24dB.
8.6.1.4 VCA Register Description
8.6.1.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
Different LNA input impedances can be configured through the register 52[4:0]. By enabling and disabling the
feedback resistors between LNA outputs and ACTx pins, LNA input impedance is adjustable accordingly. Table 5
describes the relationship between LNA gain and 52[4:0] settings. The input impedance settings are the same for
both TGC and CW paths.
The AFE5809 device also has four preset active termination impedances as described in 52[7:6]. An internal
decoder is used to select appropriate resistors corresponding to different LNA gain.
Table 5. Register 52[4:0] Description
52[4:0]/0x34[4:0]
FUNCTION
00000
No feedback resistor enabled
00001
Enables 450-Ω feedback resistor
00010
Enables 900-Ω feedback resistor
00100
Enables 1800-Ω feedback resistor
01000
Enables 3600-Ω feedback resistor
10000
Enables 4500-Ω feedback resistor
The input impedance of AFE can be programmed through Register 52[8:0]. Each bit of Register 52[4:0] controls
one active termination resistor. The following tables indicate the nominal impedance values when individual
active termination resistors are selected. See Active Termination for more details. Table 6 shows the
corresponding impedances under different Register 52[4:0] values, while Table 7 shows the Register 52[4:0]
settings under different impedances.
NOTE
Table 6 and Table 7 show nominal input impedance values. Due to silicon process
variation, the actual values can vary.
Table 6. Register 52[4:0] versus LNA Input Impedances
52[4:0]/0x34[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
LNA:12dB
High Z
150 Ω
300 Ω
100 Ω
600 Ω
120 Ω
200 Ω
86 Ω
LNA:18dB
High Z
90 Ω
180 Ω
60 Ω
360 Ω
72 Ω
120 Ω
51 Ω
LNA:24dB
High Z
50 Ω
100 Ω
33 Ω
200 Ω
40 Ω
66.67 Ω
29 Ω
52[4:0]/0x34[4:0]
01000
01001
01010
01011
01100
01101
01110
01111
LNA:12dB
1200 Ω
133 Ω
240 Ω
92 Ω
400 Ω
109 Ω
171 Ω
80 Ω
60
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Table 6. Register 52[4:0] versus LNA Input Impedances (continued)
52[4:0]/0x34[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
LNA:18dB
720 Ω
80 Ω
144 Ω
55 Ω
240 Ω
65 Ω
103 Ω
48 Ω
LNA:24dB
400 Ω
44 Ω
80 Ω
31 Ω
133 Ω
36 Ω
57 Ω
27 Ω
52[4:0]/0x34[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
LNA:12dB
1500 Ω
136 Ω
250 Ω
94 Ω
429 Ω
111 Ω
176 Ω
81 Ω
LNA:18dB
900 Ω
82 Ω
150 Ω
56 Ω
257 Ω
67 Ω
106 Ω
49 Ω
LNA:24dB
500 Ω
45 Ω
83 Ω
31 Ω
143 Ω
37 Ω
59 Ω
27 Ω
52[4:0]/0x34[4:0]
11000
11001
11010
11011
11100
11101
11110
11111
LNA:12dB
667 Ω
122 Ω
207 Ω
87 Ω
316 Ω
102 Ω
154 Ω
76 Ω
LNA:18dB
400 Ω
73 Ω
124 Ω
52 Ω
189 Ω
61 Ω
92 Ω
46 Ω
LNA:24dB
222 Ω
41 Ω
69 Ω
29 Ω
105 Ω
34 Ω
51 Ω
25 Ω
Table 7. LNA Input Impedances versus Register 52[4:0]
Z (Ω) LNA:12dB
LNA:18dB
LNA:24dB
Z (Ω) LNA:12dB
LNA:18dB
LNA:24dB
10101
Z (Ω) LNA:12dB
25
11111
67
27
10111/011
11
69
29
00111/110
11
72
00101
150
00001
31
01011/100
11
73
11001
154
11110
33
00011
76
11111
171
01110
34
11101
80
01111
176
10110
36
01101
81
10111
37
10101
82
40
00101
83
41
11001
86
00111
44
01001
87
11011
45
10001
90
11010
11111
92
01011
01111
94
10011
49
10111
100
00011
50
00001
102
11101
51
00111/111
10
103
11011
105
01011
106
56
10011
57
59
01010
11100
200
00110
207
11010
11000
240
01010
11110
250
10010
257
300
00010
316
11100
00100
400
01100
429
10100
109
01101
500
01110
111
10101
600
00100
10110
667
11000
00101
122
11001
61
11101
124
65
01101
133
01001
136
10001
00110
00110
11010
01100
01100
10100
360
11100
120
00100
222
10110
00011
10010
00010
00001
01110
60
66.7
144
189
00010
LNA:24dB
10100
180
10010
48
55
01010
10001
46
52
01001
LNA:18dB
143
11000
01000
10000
720
01000
900
10000
1200 01000
1500 10000
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8.6.1.4.2 Programmable Gain for CW Summing Amplifier
Different gain can be configured for the CW summing amplifier through the register 54[4:0]. By enabling and
disabling the feedback resistors between the summing amplifier inputs and outputs, the gain is adjustable
accordingly to maximize the dynamic range of CW path. Table 8 describes the relationship between the summing
amplifier gain and 54[4:0] settings.
Table 8. Register 54[4:0] Description
54[4:0]/0x36[4:0]
FUNCTION
00000
No feedback resistor
00001
Enables 250-Ω feedback resistor
00010
Enables 250-Ω feedback resistor
00100
Enables 500-Ω feedback resistor
01000
Enables 1000-Ω feedback resistor
10000
Enables 2000-Ω feedback resistor
Table 9. Register 54[4:0] vs Summing Amplifier Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
00000
00001
00010
00011
00100
00101
00110
N/A
0.5
0.5
0.25
1
0.33
0.33
00111
0.20
01000
01001
01010
01011
01100
01101
01110
01111
2
0.4
0.4
0.22
0.67
0.29
0.29
0.18
10000
10001
10010
10011
10100
10101
10110
10111
4
0.44
0.44
0.24
0.80
0.31
0.31
0.19
11000
11001
11010
11011
11100
11101
11110
11111
1.33
0.36
0.36
0.21
0.57
0.27
0.27
0.17
8.6.1.4.3 Programmable Phase Delay for CW Mixer
Accurate CW beamforming is achieved through adjusting the phase delay of each channel. In the AFE5809
device, 16 different phase delays can be applied to each LNA output. It meets the standard requirement of
1
λ
typical ultrasound beamformer, that is, 16 beamformer resolution. Table 8 describes the relationship between
the phase delays and the register 55 and 56 settings.
Table 10. CW Mixer Phase Delay vs Register Settings
CH1: 55[3:0], CH2: 55[7:4], CH3: 55[11:8], CH4: 55[15:12],
CH5: 56[3:0], CH6: 56[7:4], CH7: 56[11:8], CH8: 56[15:12]
Phase Delay
CHX_CW_MIXER_PHASE
PHASE SHIFT
Register Settings
0000
0001
0010
0011
0100
0101
0110
0111
0
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
CHX_CW_MIXER_PHASE
1000
1001
1010
1011
1100
1101
1110
1111
PHASE SHIFT
180°
202.5°
225°
247.5°
270°
292.5°
315°
337.5°
62
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8.6.2 Digital Demodulator Register Description
Table 11. Digital Demodulator Register Map (1) (2) (3)
Address
(HEX)
BIT [5:0]
Address
(DEC)
BIT [5:0]
00[2]
00[2]
0
1: Generate internal TX_TRIG (self clear, write only). This is an
alternative for TX_SYNC hardware pulse.
REGISTER_READOUT_EN
00[1]
ABLE
00[1]
0
1: Enables readout of register at SDOUT pin (write only)
CHIP_ID
01[4:0]
0
Unique chip ID
0
000 = Normal operation
011 = Custom pattern (set by register 05)
Note: LSB always comes out first regardless of whether 0x04[4] = 0 or
1.
111 = chipID + ramp test pattern. ChipID (5 bit) and subchip
information (3 bit) are the 8 LSBs and the ramp pattern is in the rest
MSBs. (0x0A[9] = 1)
11
Serialization factor (output rate)
00 = 10x
01 = 12x
10 = 14x
11 = 16x
Note: This register is different from the ADC
SERIALIZED_DATA_RATE. The demod and ADC serialization factors
must be matched. See .
0
Output resolution of the demodulator. It refers to the ADC resolution
when the demodulator is bypassed.
100 = 16 bit (demod only)
000 = 14 bit
001 = 13 bit
010 = 12 bit
0
0 = LSB first
1 = MSB first
This bit does not affect the test mode: customer pattern, that is,
02[15:13] = 011B.
Note: in the CUSTOM_PATTERN mode, the output is always set as
LSB first regardless of this bit setting.
Register Name
MANUAL_TX_TRIG
OUTPUT_MODE
SERZ_FACTOR
OUTPUT_RESOLUTION
01[4:0]
02[15:13]
03[14:13]
03[11:9]
02[15:13]
03[14:13]
03[11:9]
Default
Description
MSB_FIRST
04[4]
04[4]
CUSTOM_PATTERN
05[15:0]
05[15:0]
0000
COEFF_MEM_ADDR_WR
06[7:0]
06[7:0]
0
Write address offset to coefficient memory (auto increment)
COEFF_BANK
07[111:0]
07[111:0]
—
Writes chunks of 112 bits to the coefficient memory. This RAM does
not have default values, so it is necessary to write required values to
the RAM. TI recommends to configure the RAM before other registers.
PROFILE_MEM_ADDR_W
R
08[4:0]
08[4:0]
0
Write address offset to profile memory (auto increment)
Custom data pattern for LVDS (0x02[15:13] = 011)
PROFILE_BANK
09 [63:0]
09 [63:0]
—
Writes chunks of 64 bits to the profile memory (effective 62 bits
because two LSBs are ignored). This RAM does not have default
values, so it is necessary to write required values to the RAM. TI
recommends to configure the RAM before other registers.
RESERVED
0A[15]
10[15]
0
Must set to 0
MODULATE_BYPASS
0A[14]
10[14]
0
Arrange the demodulator output format for I/Q data. See Table 10.
DEC_SHIFT_SCALE
0A[13]
10[13]
0
0 = No additional shift applied to the decimation filter output.
1 = Shift the decimation filter output by 2 bits additionally, that is apply
12-dB additional digital gain.
DHPF
0A[12]
10[12]
1
0 = Enable first-order digital HPF. –3 dB cut off frequency is at 0.0225
× Fs / 2. Its transfer function equation is h(n) = a / b, where a = [1 –
7569 / 213] and b = [1 –1];
1 = Disable first-order digital HPF.
(1)
(2)
(3)
When programming the SPI, 8-bit address is required. This table and the following sections only list the Add_Bit5 to Add_Bit0. The
Add_Bit7 = SCID1_SEL and Add_Bit6 = SCID0_SEL must be appended as 11, 10, or 01, which determines if SubChip1 or SubChip0 is
being programmed. If SCID1_SEL,SCID0_SEL = 11, then both subchips get written with the same register value. See Table 2.
Reserved register bits must be programmed based on their descriptions.
Unlisted register bits must be programmed as zeros.
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Table 11. Digital Demodulator Register Map(1)(2)(3) (continued)
Address
(HEX)
BIT [5:0]
Address
(DEC)
BIT [5:0]
OUTPUT_CHANNEL_SEL
0A[11]
10[11]
0
Swap channel pairs. It is used in 4 LVDS bypass configuration to
select which of the two possible data streams to pass on. See
Table 10.
SIN_COS_RESET_ON_TX
_TRIG
0A[10]
10[10]
1
0 = Continuous phase
1 = Reset down conversion phase on TX_TRIG
Register Name
Default
Description
FULL_LVDS_MODE
0A[9]
10[9]
0
0 = Use 4 LVDS lines (1, 3, 5, 7)
1 = Use 8 LVDS lines (1 through 8)
Note: 4 LVDS mode valid only for decimation factors ≥4. See
Table 13.
RESERVED
0A[8:5]
10[8:5]
0
Must set to 0
RESERVED
0A[4]
10[4]
0
Must set to 1
DEC_BYPASS
0A[3]
10[3]
0
0 = Enable decimation filter
1 = Bypass decimation filter
DWN_CNV_BYPASS
0A[2]
10[2]
0
0 = Enable down conversion block
1 = Bypass down conversion block. Note: the decimation filter can still
be used when the down conversion block is bypassed.
RESERVED
0A[1]
10[1]
1
Must be set as 1
DC_REMOVAL_BYPASS
0A[0]
10[0]
0
0 = Enable DC removal block
1 = Bypass DC removal block
SYNC_WORD
0B[15:0]
11[15:0]
0x2772
PROFILE_INDX
0E[15:11]
14[15:11]
0
Profile word selector.
The Profile Index register is a special 5-bit data register. Read value
still uses 16-bit convention, which means data will be available on LSB
0e[4:0])
0
54[13:0] → DC offset for channel 1, SCID1_SEL,SCID0_SEL = 01
94[13:0] → DC offset for channel 5, SCID1_SEL,SCID0_SEL = 10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
0
55[13:0] → DC offset for channel 2, SCID1_SEL,SCID0_SEL = 01
95[13:0] → DC offset for channel 6, SCID1_SEL,SCID0_SEL = 10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
0
56[13:0] → DC offset for channel 3, SCID1_SEL,SCID0_SEL=01
96[13:0] → DC offset for channel 7, SCID1_SEL,SCID0_SEL=10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
DC_REMOVAL_1_5
DC_REMOVAL_2_6
DC_REMOVAL_3_7
14[13:0]
15[13:0]
16[13:0]
20[13:0]
21[13:0]
22[13:0]
LVDS sync word. When MODULATE_BYPASS = 1, there is no sync
word output.
DC_REMOVAL_4_8
17[13:0]
23[13:0]
0
57[13:0] → DC offset for channel 4, SCID1_SEL,SCID0_SEL = 01
97[13:0] → DC offset for channel 8, SCID1_SEL,SCID0_SEL = 10
Note: Considering the CH-to-CH DC offset variation, the offset value
must be set individually. Therefore, SCID1_SEL,SCID0_SEL should
not be set as 11.
Note: DC_REMOVAL_X_X registers are write-only.
DEC_SHIFT_FORCE_EN
1D[7]
29[7]
0
0 = Profile vector specifies the number of bit to shift for the decimation
filter output.
1 = Register 1D[6:4] specifies the number of bit to shift for the
decimation filter output.
DEC_SHIFT_FORCE
1D[6:4]
29[6:4]
0
Specify that the decimation filter output is right-shifted by (20 – N) bit,
N = 0x1D[6:4]. N = 0, minimal digital gain; N = 7 maximal digital gain;
additional 12-dB digital gain can be applied by setting
DEC_SHIFT_SCALE = 1, that is, 0x0A[13] = 1
TM_COEFF_EN
1D[3]
29[3]
0
1 = Set coefficient output test mode
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Table 11. Digital Demodulator Register Map(1)(2)(3) (continued)
Address
(HEX)
BIT [5:0]
Address
(DEC)
BIT [5:0]
TM_SINE_EN
1D[2]
29[2]
0
1 = Set sine output mode; the sine waveform specifications can be
configured through register 0x1E.
RESERVED
1D[1]
29[1]
0
Must set to 0
RESERVED
1D[0]
29[0]
0
Must set to 0
TM_SINE_DC
1E[15:9]
30[15:9]
0
7-bit signed value for sine wave DC offset control.
TM_SINE_AMP
1E[8:5]
30[8:5]
0
4-bit unsigned value, controlling the sine wave amplitude (powers of
two), from unity to the full scale of 14 bit, including saturation.
0 = No sine (only DC)
TM_SINE_STEP
1E[4:0]
30[4:0]
0
5-bit unsigned value, controlling the sine wave frequency with
resolution of Fs / 26, which is 0.625 MHz for 40-MHz ADC clock.
MANUAL_COEFF_START_
1F[15]
EN
31[15]
0
0 = The starting address of the coefficient RAM is set by the profile
vector, that is, the starting address is set manually.
1 = The starting address of the coefficient RAM is set by the register
0x1F[14:7].
MANUAL_COEFF_START_
1F[14:7]
ADDR
31[14:7]
0
When 0x1F[15] is set, the starting address of coefficient RAM is set by
these 8 bits.
MANUAL_DEC_FACTOR_
EN
1F[6]
31[6]
0
0 = The decimation factor is set by profile vector.
1 = The decimation factor is set by the register 0x1F[5:0].
MANUAL_DEC_FACTOR
1F[5:0]
31[5:0]
0
When 0x1F[6] is set, the decimation factor is set by these 6 bits.
Note: It is from 1 to 32.
MANUAL_FREQ_EN
20[0]
32[0]
0
0 = The down convert frequency is set by profile vector.
1 = The down convert frequency is set by the register 0x21[15:0].
MANUAL_FREQ
21[15:0]
33[15:0]
0
When 0x20[0] is set, the value of manual down convert frequency is
calculated as N × Fs / 216
Register Name
Default
Description
NOTE
RF mode allows for the streaming of ADC data through the demodulator to the LVDS
serializer. RF mode without sync word can be set by the following:
1. Write 0x0041 to register 0xDF; that is MANUAL_DEC_FACTOR_EN = 1 and
MANUAL_DEC_FACTOR = 1.
2. Write 0x121F to register 0xCA, that is, MODULATE_BYPASS = 0, FULL_LVDS_MODE = 1,
DC_REMOVAL_BYPASS = 1, DWN_CNV_BYPASS = 1. DEC_BYPASS = 1,
SYN_COS_RESET_ON_TX_TRIG = 0.
3. Write 0x6800 to register 0xC3, that is, SERZ_FACTOR = 16x, OUTPUT_RESOLUTION = 16x,
4. Write 0x0010 to register 0xC4, that is, MSB_FIRST = 1
5. Provide TX_TRIG pulse or set Register 0xC0[2] MANUAL_TX_TRIG
Table 12. Configuring Data Output
Register Name
SPI Address
SERZ_FACTOR
0x03[14:13]
OUTPUT_RESOLUTION
0x03[11:9]
MSB_FIRST
0x04[4]
OUT_MODE
0x02[15:13]
CUSTOM_PATTERN
0x05[15:0]
OUTPUT_CHANNEL_SEL
0x0A[11]
MODULATE_BYPASS
0x0A[14]
FULL_LVDS_MODE
0x0A[9]
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spacer
1. LVDS Serializer configuration:
– Serialization Factor 0x03[14:13]: It can be set using demodulator register SERZ_FACTOR. Default
serialization factor for the demodulator is 16×. However, the actual LVDS clock speed can be set by the
serialization factor in the ADC SPI interface as well; the ADC serialization factor is adjusted to 14× by
default. Therefore, it is necessary to sync these two settings when the demodulator is enabled, that is, set
the ADC register 0x03[14:13] = 01. For RF mode (passing 14 bits only), demodulator serialization factor
can be changed to 14× by setting demodulator register 0xC3[14:13] to 10.
– Output Resolution 0x03[11:9]: In the default setting, it is 14 bits. The demodulator output resolution
depends on the decimation factor. 16-bit resolution can be used when higher decimation factor is
selected.
2. Channel selection:
– Using register MODULATE_BYPASS 0x0A[14], channel output mode can be selected as IQ modulated or
single-channel I or Q output.
– Channel output is also selected using registers OUTPUT_CHANNEL_SEL 0x0A[11] and
FULL_LVDS_MODE 0x0A[9] and decimation factor.
– Each of the two demodulator subchips in a device has four channels named A, B, C, and D.
NOTE
After decimation, the LVDS FCLK rate keeps the same as the ADC sampling rate.
Considering the reduced data amount, zeros are appended after I and Q data and ensure
the LVDS data rate matches the LVDS clock rate. For detailed information about channel
multiplexing, see Table 13. In the table, A.I refers to CHA in-phase output, and A.Q refers
to CHA quadrature output. For example, M = 3, the valid data output rate is Fs / 3 for both
I and Q channels, that is 2 × Fs / 3 bandwidth is occupied. The left Fs / 3 bandwidth is
then filled by M-2 zeros. As a result, the demod LVDS output data are A.I, A.Q, 0, A.I A.Q
0 after SYNC_WORD, FCLK = Fs and DCLK = Fs × 8. When two ADC CHs' data are
transferred by one LVDS lane, M-4 zeros are filled after A.I, A.Q, B.I, and B.Q. See more
details in Table 13 and Figure 87.
66
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Table 13. Channel Selection (1)
Decimation
Factor (M)
Modulate
Bypass
Output
Full LVDS Decimation
Channel Select
Mode
Factor M
LVDS Output Description
LVDS1: A.I, A.Q, (zeros)
M1μF
RVCNTL
200Ω
10μF
3.3VA
AVDD_ADC
0.1μF
AVSS
AVDD_5V
10μF
5VA
AFE5809
CLOCK
INPUTS
SOUT
SDATA
SCLK
D7P
SEN
AFE5809
D7M
AFE5809
RESET
D8P
PDN_VCA
D8M
ANALOG INPUTS
ANALOG OUTPUTS
REF/BIAS DECOUPLING
LVDS OUTPUTS
PDN_ADC
DCLKP
PDN_GLOBAL
DCLKM
FCLKP
OTHER
AFE5809
OUTPUT
FCLKM
OTHER
AFE5809
OUTPUT
CVCNTL
470pF
VCNTLP
VCNTLM
CVCNTL
470pF
VREF_IN
DIGITAL
INPUTS
OTHER
AFE5809
OUTPUT
CW_QP_AMPINP
CW_QP_OUTM
CCW
CW_QP_AMPINM
REXT (optional)
CW_QP_OUTP
CCW
REFM
CAC R
SUM
CAC RSUM
CAC R
SUM
TO
SUMMING
AMP
CAC RSUM
CAC R
SUM
CAC RSUM
CAC R
SUM
REXT (optional)
TO
SUMMING
AMP
DNCs
REFP
AVSS
DVSS
OTHER
AFE5809
OUTPUT
CAC RSUM
Figure 98. Application Circuit With Digital Demodulator
82
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Typical Application (continued)
9.2.1 Design Requirements
The AFE5809 device is a highly integrated analog front-end solution. To maximize its performance, users must
carefully optimize its surrounding circuits, such as T/R switch, Vcntl circuits, audio ADCs for CW path, clock
distribution network, synchronized power supplies and digital processors. Typical requirements for a traditional
medical ultrasound imaging system are shown in Table 26.
Table 26. Design Parameters
PARAMETER
EXAMPLE VALUES
Signal center frequency (f0)
1~20 MHz
Signal Bandwidth (BW)
10~100% of f0
Overloaded signals due to T/R
switch leakage
~2 Vpp
Maximum input signal amplitude
100 mVpp to 1 Vpp
Transducer noise level
1 nV/rtHz
Dynamic range
151 dBc/Hz
Time gain compensation range
40 dB
Total harmonic distortion
40 dBc at 5MHz
9.2.2 Detailed Design Procedure
Medical ultrasound imaging is a widely-used diagnostic technique that enables visualization of internal organs,
their size, structure, and blood flow estimation. An ultrasound system uses a focal imaging technique that
involves time shifting, scaling, and intelligently summing the echo energy using an array of transducers to
achieve high imaging performance. The concept of focal imaging provides the ability to focus on a single point in
the scan region. By subsequently focusing at different points, an image is assembled.
When initiating an imaging, a pulse is generated and transmitted from each of the 64 transducer elements. The
pulse, now in the form of mechanical energy, propagates through the body as sound waves, typically in the
frequency range of 1MHz to 15 MHz. The sound waves are attenuated as they travel through the objects being
imaged, and the attenuation coefficients ɑ are about 0.54 dB/(MHz×cm) in soft tissue and 6~10 dB/(MHz×cm) in
bone as shown in many published papers. Most medical ultrasound systems use the reflection imaging mode
and the total signal attenuation is calculated by 2×depth×ɑ×f0. As the signal travels, portions of the wave front
energy are reflected. Signals that are reflected immediately after transmission are very strong because they are
from reflections close to the surface; reflections that occur long after the transmit pulse are very weak because
they are reflecting from deep in the body. As a result of the limitations on the amount of energy that can be put
into the imaging object, the industry developed extremely sensitive receive electronics with wide dynamic range.
Receive echoes from focal points close to the surface require little, if any, amplification. This region is referred to
as the near field. However, receive echoes from focal points deep in the body are extremely weak and must be
amplified by a factor of 100 or more. This region is referred to as the far field. In the high-gain (far field) mode,
the limit of performance is the sum of all noise sources in the receive chain. In high-gain (far field) mode, system
performance is defined by its overall noise level, which is limited by the noise level of the transducer assembly
and the receive low-noise amplifier (LNA). However in the low-gain (near field) mode, system performance is
defined by the maximum amplitude of the input signal that the system can handle. The ratio between noise levels
in high-gain mode and the signal amplitude level in low-gain mode is defined as the dynamic range of the
system. The high integration and high dynamic range of the device make it ideally suited for ultrasound imaging
applications.
The device includes an integrated LNA and VCAT (which use the gain that can be changed with enough time to
handle both near- and far-field systems), a low-pass anti-aliasing filter to limit the noise bandwidth, an ADC with
high SNR performance, and a CW mixer.
Use the following steps to design medical ultrasound imaging systems:
1. Use the signal center frequency and signal bandwidth to select an appropriate ADC sampling frequency.
2. Use the time gain compensation range to select the range of the VCNTL signal.
3. Use the transducer noise level and maximum input signal amplitude to select the appropriate LNA gain. The
device input-referred noise level reduces with higher LNA gain. However, higher LNA gain leads to lower
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input signal swing support.
4. Select different passive components for different device pins.
5. Select the appropriate input termination configuration.
6. Select the clock configuration for the ADC and CW clocks
9.2.2.1 LNA Configuration
9.2.2.1.1 LNA Input Coupling and Decoupling
The LNA closed-loop architecture is internally compensated for maximum stability without the need of external
compensation components. The LNA inputs are biased at 2.4 V and AC coupling is required. Figure 99 shows a
typical input configuration. CIN is the input AC coupling capacitor. CACT is a part of the active termination
feedback path. Even if the active termination is not used, the CACT is required for the clamp functionality. The
recommended values for CACT is ≥1 µF and CIN is ≥0.1 µF. A pair of clamping diodes is commonly placed
between the T/R switch and the LNA input. Schottky diodes with suitable forward drop voltage (for example: the
BAT754/54 series, the BAS40 series, the MMBD7000 series, or similar) can be considered depending on the
transducer echo amplitude.
AFE
CLAMP
CACT
ACTx
CIN
INPx
CBYPASS
INMx
Input
LNAx
Optional
Diodes
DC Offset
Correction
S0498-01
Figure 99. LNA Input Configurations
This architecture minimizes any loading of the signal source that may lead to a frequency-dependent voltage
divider. The closed-loop design yields low offsets and offset drift. CBYPASS (≥0.015 µF) is used to set the HPF cutoff frequency and decouple the complementary input. Its cut-off frequency is inversely proportional to the CBYPASS
value. The HPF cut-off frequency can be adjusted through the register 59[3:2] Table 27 lists. Low-frequency
signals at T/R switch output, such as signals with slow ringing, can be filtered out. In addition, the HPF can
minimize system noise from DC-DC converters, pulse repetition frequency (PRF) trigger, and frame clock. Most
ultrasound systems’ signal-processing unit includes digital HPFs or band-pass filters (BPFs) in FPGAs or ASICs.
Further noise suppression can be achieved in these blocks. In addition, a digital HPF is available in the AFE5809
ADC. If low-frequency signal detection is desired in some applications, the LNA HPF can be disabled.
Table 27. LNA HPF Settings (CBYPASS = 15 nF)
84
Reg59[3:2] (0x3B[3:2])
FREQUENCY (kHz)
00
100
01
50
10
200
11
150
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CM_BYP and VHIGH pins, which generate internal reference voltages, must be decoupled with ≥1-µF capacitors.
Bigger bypassing capacitors (>2.2 µF) may be beneficial if low-frequency noise exists in the system.
9.2.2.1.2 LNA Noise Contribution
The noise specification is critical for LNA and it determines the dynamic range of the entire system. The LNA of
the AFE5809 device achieves low power and an exceptionally low-noise voltage of 0.63 nV/√Hz, and a low
current noise of 2.7 pA/√Hz.
Typical ultrasonic transducer’s impedance, RS, varies from tens of Ω to several hundreds of Ω. Voltage noise is
the dominant noise in most cases; however, the LNA current noise flowing through the source impedance (RS)
generates additional voltage noise.
2
2
LNA _ Noise total = VLNAnoise
+ R2s ´ ILNAnoise
(12)
The AFE5809 device achieves low-noise figure (NF) over a wide range of source resistances as shown in
Figure 32, Figure 33, and Figure 34.
9.2.2.1.3 Active Termination
In ultrasound applications, signal reflection exists due to long cables between the transducer and system. The
reflection results in extra ringing added to echo signals in PW mode. Because the axial resolution depends on
echo signal length, such ringing effect can degrade the axial resolution. Therefore, either passive termination or
active termination is preferred if good axial resolution is desired. Figure 100 shows three termination
configurations.
Rs
LNA
(a) No Termination
Rf
Rs
LNA
(b) Active Termination
Rs
Rt
LNA
(c) Passive Termination
S0499-01
Figure 100. Termination Configurations
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Under the no termination configuration, the input impedance of the AFE5809 is about 6 kΩ (8 K//20 pF) at 1
MHz. Passive termination requires external termination resistor Rt, which contributes to additional thermal noise.
The LNA supports active termination with programmable values, as shown in Figure 101 .
450Ω
900Ω
1800Ω
ACTx
3600Ω
4500Ω
INPx
Input
INMx
LNAx
AFE
S0500-01
Figure 101. Active Termination Implementation
The AFE5809 device has four pre-settings 50, 100, 200, and 400 Ω, which are configurable through the
registers. Other termination values can be realized by setting the termination switches shown in Figure 101.
Register [52] is used to enable these switches. The input impedance of the LNA under the active termination
configuration approximately follows:
ZIN =
Rf
AnLNA
1+
2
(13)
Table 5 lists the LNA RINs under different LNA gains. System designers can achieve fine tuning for different
probes.
The equivalent input impedance is given by Equation 14 where RIN (8 kΩ) and CIN (20 pF) are the input
resistance and capacitance of the LNA.
ZIN =
Rf
/ /CIN / /RIN
AnLNA
1+
2
(14)
Therefore, the ZIN is frequency dependent, and it decreases as frequency increases as shown in Figure 10.
Because 2 to 10 MHz is the most commonly used frequency range in medical ultrasound, this rolling-off effect
does not impact system performance greatly. Active termination can be applied to both CW and TGC modes.
Because each ultrasound system includes multiple transducers with different impedances, the flexibility of
impedance configuration is a great plus.
Figure 32, Figure 33, and Figure 34 show the NF under different termination configurations. It indicates that no
termination achieves the best noise figure; active termination adds less noise than passive termination. Thus,
termination topology should be carefully selected based on each use scenario in ultrasound.
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9.2.2.1.4 LNA Gain Switch Response
The LNA gain is programmable through SPI. The gain switching time depends on the SPI speed as well as the
LNA gain response time. During the switching, glitches might occur and they can appear as artifacts in images.
In addition, the signal chain needs about 14 µs to settle after the LNA gain change. Thus, LNA gain switching
may not be preferred when switching time or settling time for the signal chain is limited.
9.2.2.2 Voltage-Controlled Attenuator
The attenuator in the AFE5809 device is controlled by a pair of differential control inputs, the VCNTLM,P pins. The
differential control voltage spans from 0 to 1.5 V. This control voltage varies the attenuation of the attenuator
based on its linear-in-dB characteristic. Its maximum attenuation (minimum channel gain) appears at VCNTLP –
VCNTLM = 1.5 V and minimum attenuation (maximum channel gain) occurs at VCNTLP – VCNTLM = 0. The typical
gain range is 40 dB and remains constant, independent of the PGA setting.
When only single-ended VCNTL signal is available, this 1.5-Vpp signal can be applied on the VCNTLP pin with the
VCNTLM pin connected to ground; As Figure 102 show, the TGC gain curve is inversely proportional to the
VCNTLP – VCNTLM.
1.5V
VCNTLP
VCNTLM = 0V
X+40dB
TGC Gain
XdB
(a) Single-Ended Input at VCNTLP
1.5V
VCNTLP
0.75V
VCNTLM
0V
X+40dB
TGC Gain
XdB
(b) Differential Inputs at VCNTLP and VCNTLM
W0004-01
Figure 102. VCNTLP and VCNTLM Configurations
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As discussed in the theory of operation, the attenuator architecture uses seven attenuator segments that are
equally spaced to approximate the linear-in-dB gain-control slope. This approximation results in a monotonic
slope; the gain ripple is typically less than ±0.5 dB.
The control voltage input (VCNTLM,P pins) represents a high-impedance input. The VCNTLM,P pins of multiple
AFE5809 devices can be connected in parallel with no significant loading effects. When the voltage level
(VCNTLP – VCNTLM) is above 1.5 V or below 0 V, the attenuator continues to operate at its maximum attenuation
level or minimum attenuation level, respectively. TI recommends lmiting the voltage from –0.3 to 2 V.
When the AFE5809 device operates in CW mode, the attenuator stage remains connected to the LNA outputs.
Therefore, TI recommends powering down the VCA using the PDN_VCA register bit. In this case, VCNTLP –
VCNTLM voltage does not matter.
The AFE5809 gain-control input has a –3-dB bandwidth of approximately 800 kHz. This wide bandwidth,
although useful in many applications (for example, fast VCNTL response), can also allow high-frequency noise to
modulate the gain control input and finally affect the Doppler performance. In practice, this modulation can be
avoided by additional external filtering (RVCNTL and CVCNTL) at VCNTLM,P pins as Figure 81 shows. However, the
external filter's cutoff frequency cannot be kept too low as this results in low gain response time. Without external
filtering, the gain control response time is typically less than 1 μs to settle within 10% of the final signal level of
1VPP (–6-dBFS) output as indicated in Figure 51 and Figure 52.
Typical VCNTLM,P signals are generated by an 8- to 12-bit 10-MSPS digital-to-analog converter (DAC) and a
differential operation amplifier. TI’s DACs, such as TLV5626 and DAC7821/11 (10 MSPS/12 bit), could be used
to generate TGC control waveforms. Differential amplifiers with output common mode voltage control (that is,
THS4130 and OPA1632) can connect the DAC to the VCNTLM/P pins. The buffer amplifier can also be configured
as an active filter to suppress low-frequency noise. The VCNTLM/P circuit achieves low noise to prevent the
VCNTLM/P noise being modulated to RF signals. TI recommends that VCNTLM/P noise is below 25 nV/rtHz at 1 kHz
and 5 nV/rtHz at 50 kHz. In high-channel count premium systems, the VCNTLM/P noise requirement is higher. See
Figure 103
10
16 Channels
32 Channels
64 Channels
128 Channels
192 Channels
9
Noise (nV/—Hz)
8
7
6
5
4
3
2
1
0
1
2 3 4 5 7 10
20 30 50 100 200
Frequency (kHz)
500 1000
5000
D063
Figure 103. Allowed Noise on the VCNTL Signal Across Frequency and Different Channels
More information can be found in SLOS318 and SBAA150. See Figure 2 for the VCNTL vs Gain curves. Table 28
also shows the absolute gain vs VCNTL, which may help program DAC correspondingly.
In PW Doppler and color Doppler modes, VCNTL noise should be minimized to achieve the best close-in phase
noise and SNR. Digital VCNTL feature is implemented to address this need in the AFE5809. In the digital VCNTL
mode, no external VCNTL is needed.
88
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Table 28. VCNTLP – VCNTLM vs Gain Under Different LNA and PGA Gain Settings (Low-Noise Mode)
VCNTLP – VCNTLM
(V)
Gain (dB)
LNA = 12 dB
PGA = 24 dB
Gain (dB)
LNA = 18 dB
PGA = 24 dB
Gain (dB)
LNA = 24 dB
PGA = 24 dB
Gain (dB)
LNA = 12 dB
PGA = 30 dB
Gain (dB)
LNA = 18 dB
PGA = 30 dB
Gain (dB)
LNA = 24 dB
PGA = 30 dB
0
36.45
42.45
48.45
42.25
48.25
54.25
0.1
33.91
39.91
45.91
39.71
45.71
51.71
0.2
30.78
36.78
42.78
36.58
42.58
48.58
0.3
27.39
33.39
39.39
33.19
39.19
45.19
0.4
23.74
29.74
35.74
29.54
35.54
41.54
0.5
20.69
26.69
32.69
26.49
32.49
38.49
0.6
17.11
23.11
29.11
22.91
28.91
34.91
0.7
13.54
19.54
25.54
19.34
25.34
31.34
0.8
10.27
16.27
22.27
16.07
22.07
28.07
0.9
6.48
12.48
18.48
12.28
18.28
24.28
1
3.16
9.16
15.16
8.96
14.96
20.96
1.1
–0.35
5.65
11.65
5.45
11.45
17.45
1.2
–2.48
3.52
9.52
3.32
9.32
15.32
1.3
–3.58
2.42
8.42
2.22
8.22
14.22
1.4
–4.01
1.99
7.99
1.79
7.79
13.79
1.5
–4
2
8
1.8
7.8
13.8
9.2.2.3 CW Operation
9.2.2.3.1 CW Summing Amplifier
To simplify CW system design, a summing amplifier is implemented in the AFE5809 to sum and convert 8channel mixer current outputs to a differential voltage output. Low noise and low power are achieved in the
summing amplifier while maintaining the full dynamic range required in CW operation.
This summing amplifier has five internal gain adjustment resistors which can provide 32 different gain settings
(register 54[4:0], Figure 101 and Table 8). System designers can easily adjust the CW path gain depending on
signal strength and transducer sensitivity. For any other gain values, an external resistor option is supported. The
gain of the summation amplifier is determined by the ratio between the 500-Ω resistors after LNA and the internal
or external resistor network REXT/INT. Thus, the matching between these resistors plays a more important role
than absolute resistor values. Better than 1% matching is achieved on chip. Due to process variation, the
absolute resistor tolerance could be higher. If external resistors are used, the gain error between I/Q channels or
among multiple AFEs may increase. TI recommends using internal resistors to set the gain to achieve better gain
matching (across channels and multiple AFEs). With the external capacitor CEXT , this summing amplifier has
first-order LPF response to remove high-frequency components from the mixers, such as 2f0±fd. Its cut-off
frequency is determined by:
fHP =
1
2pRINT/EXT CEXT
(15)
When different gain is configured through Register 54[4:0], the LPF response varies as well.
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CEXT
REXT
250Ω
250Ω
RINT
500Ω
1000Ω
2000Ω
CW_AMPINP
CW_AMPINM
CW_OUTM
I/V Sum
Amp
CW_OUTP
250Ω
250Ω
500Ω
RINT
1000Ω
2000Ω
REXT
CEXT
S0501-01
Figure 104. CW Summing Amplifier Block Diagram
Multiple AFE5809 devices are usually used in parallel to expand CW beamformer channel count. The AFE5809
CW's voltage outputs can be summed and filtered externally further to achieve desired gain and filter response.
AC-coupling capacitors CAC are required to block the DC component of the CW carrier signal. CAC can vary from
1 to 10 μF depending on the desired low-frequency Doppler signal from slow blood flow. Multiple AFE5809s’ I/Q
outputs can be summed together with a low-noise differential amplifiers before 16, 18-bit differential audio ADCs.
The TI ultralow noise differential precision amplifier OPA1632 and THS4130 are suitable devices.
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Figure 106 shows an alternative current summing circuit. However, this circuit only achieves good performance
when a lower-noise operational amplifier is available compared to the AFE5809's internal summing differential
amplifier.
AFE No.4
AFE No.3
AFE No.2
ACT1
500 Ω
INP1
INPUT1
INM1
AFE No.1
Mixer 1
Clock
LNA1
500 Ω
ACT2
500 Ω
INP2
INPUT2
INM2
Ext Sum
Amp
Cext
Mixer 2
Clock
Rint/Rext
CW_AMPINP
CW_AMPINM
LNA2
I/V Sum
Amp
CW_OUTM
CW_OUTP
Rint/Rext
500 Ω
CAC
RSUM
Cext
CW I or Q CHANNEL
Structure
ACT8
500 Ω
INP8
INPUT8
INM8
Mixer 8
Clock
LNA8
500 Ω
S0502-01
Figure 105. CW Circuit With Multiple AFE5809s (Voltage Output Mode)
Figure 106. CW Circuit With Multiple AFE5809s (Current Output Mode, CM_BYP=1.5 V)
The CW I/Q channels are well matched internally to suppress image frequency components in the Doppler
spectrum. Low-tolerance components and precise operational amplifiers should be used for achieving good
matching in the external circuits as well.
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NOTE
The local oscillator inputs of the passive mixer are cos(ωt) for I-CH and sin(ωt) for Q-CH,
respectively. Depending on the users' CW Doppler complex FFT processing, swapping I/Q
channels in FPGA or DSP may be needed to get correct blood flow directions.
9.2.2.3.2 CW Clock Selection
The AFE5809 device can accept differential LVDS, LVPECL, and other differential clock inputs as well as singleended CMOS clock. An internally generated VCM of 2.5 V is applied to CW clock inputs, that is, CLKP_16X/
CLKM_16X and CLKP_1X/ CLKM_1X. Because this 2.5-V VCM is different from the one used in standard LVDS
or LVPECL clocks, AC coupling is required between clock drivers and the AFE5809 CW clock inputs. When the
CMOS clock is used, CLKM_1X and CLKM_16X should be tied to ground. Figure 107 shows common clock
configurations. TI recommends appropriate termination to achieve good signal integrity.
3.3 V
130 Ω
83 Ω
CDCM7005
CDCE7010
3.3 V 0.1 μF
AFE
CLOCKs
0.1 μF
130 Ω
LVPECL
(a) LVPECL Configuration
100 Ω
CDCE72010
0.1 μF
0.1 μF
AFE
CLOCKs
LVDS
(b) LVDS Configuration
0.1μF
0.1μF
CLOCK
SOURCE
0.1μF
AFE
CLOCKs
50 Ω
0.1μF
(c) Transformer Based Configuration
CMOS CLK
Driver
AFE
CMOS CLK
CMOS
(d) CMOS Configuration
S0503-01
Figure 107. Clock Configurations
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The combination of the clock noise and the CW path noise can degrade the CW performance. The internal
clocking circuit is designed for achieving excellent phase noise required by CW operation. The phase noise of
the AFE5809 CW path is better than 155 dBc/Hz at 1-kHz offset. Consequently, the phase noise of the mixer
clock inputs needs to be better than 155 dBc/Hz.
In the 16/8/4 × ƒcw operations modes, low phase noise clock is required for 16, 8, 4 × ƒcw clocks (that is,
CLKP_16X/ CLKM_16X pins) to maintain good CW phase noise performance. The 1 × ƒcw clock (that is,
CLKP_1X/ CLKM_1X pins) is only used to synchronize the multiple AFE5809 chips and is not used for
demodulation. Thus, 1 × ƒcw clock’s phase noise is not a concern. However, in the 1 × ƒcw operation mode, lowphase noise clocks are required for both CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X pins because both of
them are used for mixer demodulation. In general, a higher slew rate clock has lower phase noise; thus, clocks
with high amplitude and fast slew rate are preferred in CW operation. In the CMOS clock mode, a 5-V CMOS
clock can achieve the highest slew rate.
Clock phase noise can be improved by a divider as long as the divider’s phase noise is lower than the target
phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20logN dB where
N is the dividing factor of 16, 8, or 4. If the target phase noise of mixer LO clock 1 × ƒcw is 160 dBc/Hz at 1 kHz
off carrier, the 16 × ƒcw clock phase noise should be better than 160 – 20log16 = 136 dBc/Hz. TI’s jitter cleaners
LMK048X/CDCM7005/CDCE72010 exceed this requirement and can be selected for the AFE5809. In the 4×/1×
modes, higher-quality input clocks are expected to achieve the same performance because N is smaller. Thus,
the 16× mode is a preferred mode because it reduces the phase noise requirement for system clock design. In
addition, the phase delay accuracy is specified by the internal clock divider and distribution circuit. Note in the
16× operation mode, the CW operation range is limited to 8 MHz due to the 16× CLK. The maximum clock
frequency for the 16× CLK is 128 MHz. In the 8×, 4×, and 1× modes, higher CW signal frequencies up to 15 MHz
can be supported with small degradation in performance, for example, the phase noise is degraded by 9 dB at 15
MHz, compared to 2 MHz.
As the channel number in a system increases, clock distribution becomes more complex. It is not preferred to
use one clock driver output to drive multiple AFEs because the clock buffer’s load capacitance increases by a
factor of N. As a result, the falling and rising time of a clock signal is degraded. A typical clock arrangement for
multiple AFE5809 devices is shown in Figure 108. Each clock buffer output drives one AFE5809 device to
achieve the best signal integrity and fastest slew rate, that is, better phase noise performance. When clock phase
noise is not a concern, for example, the 1 × ƒcw clock in the 16, 8, 4 × ƒcw operation modes, one clock driver
output may excite more than one AFE5809 device. Nevertheless, special considerations should be applied in
such a clock distribution network design. In typical ultrasound systems, it is preferred that all clocks are
generated from a same clock source, such as 16 × ƒcw , 1 × ƒcw clocks, audio ADC clocks, RF ADC clock, pulse
repetition frequency signal, frame clock, and so on. By doing this, interference due to clock asynchronization can
be minimized.
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FPGA Clock/
Noisy Clock
n×16×CW Freq
LMK048X
CDCE72010
CDCM7005
16X CW
CLK
1X CW
CLK
CDCLVP1208
LMK0030X
LMK01000
CDCLVP1208
LMK0030X
LMK01000
AFE
AFE
AFE
AFE
8 Synchronized
1X CW CLKs
AFE
AFE
AFE
AFE
8 Synchronized
16 X CW CLKs
B0436-01
Figure 108. CW Clock Distribution
9.2.2.3.3 CW Supporting Circuits
As a general practice in CW circuit design, in-phase and quadrature channels should be strictly symmetrical by
using well-matched layout and high-accuracy components.
In systems, additional high-pass wall filters (20 to 500 Hz) and low-pass audio filters (10 to 100 kHz) with multiple
poles are usually needed. Because the CW Doppler signal ranges from 20 Hz to 20 kHz, noise under this range
is critical. Consequently, low-noise audio operational amplifiers are suitable to build these active filters for CW
post-processing, that is, OPA1632 or OPA2211. To find more filter design techniques, see www.ti.com. For the
TI active filter design tool, see www.ti.com/filterdesigner.
The filtered audio CW I/Q signals are sampled by audio ADCs and processed by DSP or PC. Although CW
signal frequency is from 20 Hz to 20 kHz, higher sampling rate ADCs are still preferred for further decimation and
SNR enhancement. Due to the large dynamic range of CW signals, high resolution ADCs (≥16 bit) are required,
such as ADS8413 (2 MSPS, 16-bit, 92-dBFS SNR) and ADS8472 (1 MSPS, 16-bit, 95-dBFS SNR). ADCs for inphase and quadrature-phase channels must be strictly matched, not only amplitude matching but also phase
matching, to achieve the best I/Q matching. In addition, the in-phase and quadrature ADC channels must be
sampled simultaneously.
9.2.2.4 Low Frequency Support
In addition, the signal chain of the AFE5809 can handle signal frequency lower than 100 kHz, which enables the
AFE5809 to be used in both sonar and medical applications. The PGA integrator must be turned off to enable the
low frequency support. Meanwhile, a large capacitor like 1 µF can be used for setting low corner frequency of the
LNA DC offset correction circuit as shown in Figure 62. See Figure 59 to find AFE5809's low frequency
response.
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9.2.2.5 ADC Operation
9.2.2.5.1 ADC Clock Configurations
To ensure that the aperture delay and jitter are the same for all channels, the AFE5809 uses a clock tree
network to generate individual sampling clocks for each channel. The clock, for all the channels, are matched
from the source point to the sampling circuit of each of the eight internal ADCs. The variation on this delay is
described in the aperture delay parameter of the output interface timing. Its variation is given by the aperture jitter
number of the same table.
FPGA Clock/
Noisy Clock
n × (20 to 65)MHz
TI Jitter Cleaner
LMK048X
CDCE72010
CDCM7005
20 to 65 MHz
ADC CLK
CDCLVP1208
LMK0030X
LMK01000
CDCE72010 has 10
outputs thus the buffer
may not be needed for
64CH systems
AFE
AFE
AFE
AFE
AFE
AFE
AFE
AFE
8 Synchronized
ADC CLKs
B0437-01
Figure 109. ADC Clock Distribution Network
The AFE5809 ADC clock input can be driven by differential clocks (sine wave, LVPECL, or LVDS) or singled
clocks (LVCMOS) similar to CW clocks as shown in Figure 107. In the single-end case, TI recommends that the
use of low jitter square signals (LVCMOS levels, 1.8-V amplitude). See TI document SLYT075 for further details
on the theory.
The jitter cleaner CDCM7005 or CDCE72010 is suitable to generate the AFE5809’s ADC clock and ensure the
performance for the14-bit ADC with 77-dBFS SNR. Figure 109 shows a clock distribution network.
9.2.2.5.2 ADC Reference Circuit
The ADC’s voltage reference can be generated internally or provided externally. When the internal reference
mode is selected, the REFP/M become output pins and should be floated. When 3[15] = 1 and 1[13] = 1, the
device is configured to operate in the external reference mode in which the VREF_IN pin should be driven with a
1.4-V reference voltage and REFP/M must be left open. Because the input impedance of the VREF_IN is high,
no special drive capability is required for the 1.4-V voltage reference
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The digital beam-forming algorithm in an ultrasound system relies on gain matching across all receiver channels.
A typical system would have about 12 octal AFEs on the board. In such a case, it is critical to ensure that the
gain is matched, essentially requiring the reference voltages seen by all the AFEs to be the same. Matching
references within the eight channels of a chip is done by using a single internal reference voltage buffer.
Trimming the reference voltages on each chip during production ensures that the reference voltages are wellmatched across different chips. When the external reference mode is used, a solid reference plane on a PCB
can ensure minimal voltage variation across devices. More information on voltage reference design can be found
in the document SLYT339.
The dominant gain variation in the AFE5809 comes from the VCA gain variation. The gain variation contributed
by the ADC reference circuit is much smaller than the VCA gain variation. Hence, in most systems, using the
ADC internal reference mode is sufficient to maintain good gain matching among multiple AFE5809s. In addition,
the internal reference circuit without any external components achieves satisfactory thermal noise and phase
noise performance.
9.2.3 Application Curves
Figure 110 show the output SNR of one AFE channel from VCNTL = 0 V and VCNTL = 1.2 V, respectively, with
an input signal at 5 MHz captured at a sample rate of 65 MHz. VCNTL = 0 V represents far field while VCNTL =
1.2 V represents near field.Figure 111 shows the CW phase noise or dyanmic range of a singe AFE channel.
75
−146
16X Clock Mode
8X Clock Mode
4X Clock Mode
−148
Phase Noise (dBc/Hz)
−150
SNR (dBFS)
70
65
60
−152
−154
−156
−158
−160
−162
−164
−166
24 dB PGA gain
30 dB PGA gain
55
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Figure 110. SNR vs. Vcntl at 18 dB LNA
−168
−170
100
1000
10000
50000
Offset Frequency (Hz)
Figure 111. CW Phase Noise at Fin = 2 MHz
9.3 System Example
In a complex system design, system debug features of a device are very important. The AFE5809 includes
multiple test modes to accelerate system development.
9.3.1 ADC Debug
The ADC test modes are discussed in the ADC register description section. The AFE5809 device can output a
variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. The
device may also be made to output 6 preset patterns:
• Ramp: Setting Register 2[15:13] = 111 causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
• Zeros: The device can be programmed to output all 0 s by setting Register 2[15:13] = 110.
• Ones: The device can be programmed to output all 1 s by setting Register 2[15:13] = 100.
• Deskew Patten: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101
word.
• Sync Pattern: When 2[15:13] = 001, the normal ADC output is replaced by a fixed 11111110000000 word.
• Toggle: When 2[15:13] = 101, the normal ADC output is alternating from 1 s to 0 s. The start state of ADC
word can be either 1 s or 0 s.
• Custom Pattern: It can be enabled when 2[15:13] = 011. Users can write the required VALUE into register bits
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System Example (continued)
, which is Register 5[13:0]. Then, the device will output VALUE at its outputs, about 3
to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24 SCLK
clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register
5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be
high. For example, 128 points custom pattern takes approximately 128 × (24 SCLK clock cycles + 4 ADC
clock cycles).
NOTE
Only one of the above patterns can be active at any given instant. Test pattern from the
ADC output stage can NOT be sent to the demodulator; it can only be sent to the LVDS
serializer when the demodulator is off.
NOTE
After the demodulator is enabled, digital demodulator register 02[15:13] can be configured
to send out test patterns for demod block, please seeDigital Demodulator Register
Description.
9.3.2 VCA Debug
The VCA has a test mode in which the CH7 and CH8 PGA outputs can be brought to the CW pins. By monitoring
these PGA outputs, the functionality of VCA operation can be verified. The PGA outputs are connected to the
virtual ground pins of the summing amplifier (CW_IP_AMPINM/P, CW_QP_AMPINM/P) through 5-kΩ resistors.
The PGA outputs can be monitored at the summing amplifier outputs when the LPF capacitors CEXT are
removed. The signals at the summing amplifier outputs are attenuated due to the 5-kΩ resistors. The attenuation
coefficient is RINT/EXT / 5 kΩ.
If users would like to check the PGA outputs without removing CEXT, an alternative way is to measure the PGA
outputs directly at the CW_IP_AMPINM/P and CW_QP_AMPINM/P when the CW summing amplifier is powered
down.
Some registers are related to this test mode, PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down
Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0]. Based on the buffer amplifier configuration, the registers
can be set in different ways:
•
•
Configuration 1
– In this configuration, the test outputs can be monitored at CW_AMPINP/M.
– Reg59[9] = 1; test mode enabled
– Reg59[8] = 0; buffer amplifier powered-down
Configuration 2
– In this configuration, the test outputs can be monitored at CW_OUTP/M.
– Reg59[9] = 1; test mode enabled
– Reg59[8] = 1; buffer amplifier powered on
– Reg54[4:0] = 10H; internal feedback 2-kΩ resistor enabled. Different values can be used as well.
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System Example (continued)
PGA_P
Cext
5K
ACT
500 Ω
INP
INPUT
INM
Mixer
Clock
Rint/Rext
CW_AMPINP
CW_AMPINM
LNA
500 Ω
CW_OUTM
I/V Sum
Amp
Rint/Rext
CW_OUTP
5K
Cext
PGA_M
S0504-01
Figure 112. AFE5809 PGA Test Mode
9.4 Do's and Don'ts
9.4.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
For device reliability, an input must not go more than 300 mV below the ground pins or 300 mV above the supply
pins as suggested in the table. Exceeding these limits, even on a transient basis, can cause faulty or erratic
operation and can impair device reliability.
9.4.2 Driving the Device Signal Input With an Excessively High Level Signal
The device offers consistent and fast overload recovery with a 6-dB overloaded signal. For very large overload
signals (> 6 dB of the linear input signal range), TI recommends back-to-back Schottky clamping diodes at the
input to limit the amplitude of the input signal. Refer to the section for more details.
9.4.3 Driving the VCNTL Signal With an Excessive Noise Source
Noise on the VCNTL signal gets directly modulated with the input signal and causes higher output noise and
reduction in SNR performance. Maintain a noise level for the VCNTL signal as discussed in the section.
9.4.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or
Having Other Signals Coupled to the ADC or CW Clock Signal Trace
These situations cause the sampling interval to vary, causing an excessive output noise and a reduction in SNR
performance. For a system with multiple devices, the clock tree scheme must be used to apply an ADC or CW
clock. Refer to the section for clock mismatch between devices, which can lead to latency mismatch and
reduction in SNR performance. Clocks generated by FPGA may include excessive jitter and must be evaluated
carefully before driving ADC or CW circuits.
9.4.5 LVDS Routing Length Mismatch
The routing length of all LVDS lines routing to the FPGA must be matched to avoid any timing related issue. For
systems with multiple devices, the LVDS serialized data clock (DCLKP, DCLKM) and the frame clock (FCLKP,
FCLKM) of each individual device must be used to deserialize the corresponding LVDS serialized data
(DnP,DnM).
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Do's and Don'ts (continued)
9.4.6 Failure to Provide Adequate Heat Removal
Use the appropriate thermal parameter listed in the table and an ambient, board, or case temperature to
calculate device junction temperature. A suitable heat removal technique must be used to keep the device
junction temperature below the maximum limit of 105°C.
10 Power Supply Recommendations
Figure 113 shows the suggested power-up sequencing and reset timing for the device.
t1
AVDD
AVDD_5V
AVDD_ADC
t2
DVDD
t3
t4
t7
t5
RESET
t6
Device Ready for
Serial Register Write
SEN
Start of Clock
Device Ready for
Data Conversion
CLKP_ADC
t8
A.
10 μs < t1 < 50 ms, 10 μs < t2 < 50 ms, –10 ms < t3 < 10 ms, t4 > 10 ms, t5 > 100 ns, t6 > 100 ns, t7 > 10 ms, and t8 >
100 μs. When the demodulator power DVDD_LDO1 and DVDD_LDO2 are supplied externally, it should be powered
up 1ms after DVDD. LDOs for external DVDD_LDO1 and DVDD_LDO2 can be powered down if the demodualtor is
not used.
B.
The AVDDx and DVDD power-on sequence does not matter as long as –10 ms < t3 < 10 ms. Similar considerations
apply while shutting down the device.
Figure 113. Recommended Power-Up Sequencing and Reset Timing with Internally Generated 1.4V
Demod Supply
10.1 Power/Performance Optimization
The AFE5809 device has options to adjust power consumption and meet different noise performances. This
feature would be useful for portable systems operated by batteries when low power is more desired. Refer to
characteristics information listed in the Electrical Characteristics as well as the Typical Characteristics.
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10.2 Power Management Priority
Power management plays a critical role to extend battery life and ensure long operation time. The AFE5809
device has fast and flexible power-down and power-up control which can maximize battery life. The AFE5809
can be powered down or up through external pins or internal registers. Table 29 indicates the affected circuit
blocks and priorities when the power management is invoked. The higher priority controls can overwrite the lower
priority controls.
In the device, all the power-down controls are logically ORed to generate final power down for different blocks.
The higher priority controls can cover the lower priority controls.
Table 29. Power Management Priority
Name
Blocks
Priority
Pin
PDN_GLOBAL
All
High
Pin
PDN_VCA
LNA + VCAT+ PGA
Medium
Register
VCA_PARTIAL_PDN
LNA + VCAT+ PGA
Low
Register
VCA_COMPLETE_PDN
LNA + VCAT+ PGA
Medium
Pin
PDN_ADC
ADC
Medium
Register
ADC_PARTIAL_PDN
ADC
Low
Register
ADC_COMPLETE_PDN
ADC
Medium
Register
PDN_VCAT_PGA
VCAT + PGA
Lowest
Register
PDN_LNA
LNA
Lowest
10.3 Partial Power-Up and Power-Down Mode
The partial power-up and power-down mode is also called fast power-up and power-down mode. In this mode,
most amplifiers in the signal path are powered down, while the internal reference circuits remain active as well as
the LVDS clock circuit, that is, the LVDS circuit still generates its frame and bit clocks.
The partial power-down function allows the AFE5809 device to wake up from a low-power state quickly. This
configuration ensures that the external capacitors are discharged slowly; thus, a minimum wake-up time is
needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2
μs or 1% of the power-down duration, whichever is larger. The longest wake-up time depends on the capacitors
connected at INP and INM, because the wake-up time is the time required to recharge the capacitors to the
desired operating voltages. 0.1 μF at INP and 15 nF at INM can give a wake-up time of 2.5 ms. For larger
capacitors, this time will be longer. The ADC wake-up time is about 1 μs. Thus, the AFE5809 wake-up time is
more dependent on the VCA wake-up time. This also assumes that the ADC clock has been running for at least
50 µs before normal operating mode resumes. The power-down time is instantaneous, less than 1 µs.
This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical.
The pulse repetition frequency of an ultrasound system could vary from 50 kHz to 500 Hz, while the imaging
depth (that is, the active period for a receive path) varies from 10 μs to hundreds of µs. The power saving can be
significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC
keeps running normally to ensure minimal impact to FPGAs.
In the partial power-down mode, the AFE5809 device typically dissipates only 26 mW/ch, representing an 80%
power reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA
and PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN).
10.4 Complete Power-Down Mode
To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5809 device can be placed into a complete
power-down mode. This mode is controlled through the registers ADC_COMPLETE_PDN,
VCA_COMPLETE_PDN, or PDN_GLOBAL pin. In the complete power-down mode, all circuits including
reference circuits within the AFE5809 device are powered down, and the capacitors connected to the AFE5809
device are discharged. The wake-up time depends on the time needed to recharge these capacitors. The wakeup time depends on the time that the AFE5809 device spends in shutdown mode. 0.1 μF at INP and 15 nF at
INM can give a wake-up time close to 2.5 ms.
100
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Complete Power-Down Mode (continued)
NOTE
When the complete power-down mode is enabled, the digital demodulator may lose
register settings. Therefore, it is required to reconfigure the demodulator registers, filter
coefficient memory, and profile memory after exiting the complete power-down mode.
10.5 Power Saving in CW Mode
Usually, only half the number of channels in a system are active in the CW mode. Thus, the individual channel
control through ADC_PDN_CH and VCA_PDN_CH can power down unused channels and save
power consumption greatly. Under the default register setting in CW mode, the voltage controlled attenuator,
PGA, and ADC are still active. During the debug phase, both the PW and CW paths can run simultaneously. In
real operation, these blocks must be powered down manually.
11 Layout
11.1 Layout Guidelines
Proper grounding and bypassing, short lead length, and the use of ground and power-supply planes are
particularly important for high-frequency designs. Achieving optimum performance with a high-performance
device such as the AFE5809 requires careful attention to the PCB layout to minimize the effects of board
parasitics and optimize component placement. A multilayer PCB usually ensures best results and allows
convenient component placement. To maintain proper LVDS timing, all LVDS traces should follow a controlled
impedance design. In addition, all LVDS trace lengths should be equal and symmetrical; TI recommends to keep
trace length variations less than 150 mil (0.150 inch or 3.81 mm).
NOTE
To avoid noise coupling through supply pins, TI recommends keeping sensitive input net
classes, such as INM, INP, ACT pins, away from AVDD 3.3 V, AVDD_5V, DVDD,
AVDD_ADC, DVDD_LDO1/2 nets or planes. For example, vias connected to these pins
should NOT be routed across any supply plane. That is to avoid power planes under INM,
INP, and ACT pins.
In addition, appropriate delay matching should be considered for the CW clock path, especially in systems with
high channel count. For example, if clock delay is half of the 16× clock period, a phase error of 22.5°C could
exist. Thus, the timing delay difference among channels contributes to the beamformer accuracy.
Additional details on BGA PCB layout techniques can be found in the TI application report MicroStar BGA
Packaging Reference Guide (SSYZ015), which can be downloaded from www.ti.com.
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11.2 Layout Example
Caps to INP, INM, ACT pins
CW I/Os
Vcntl
Decoupling caps close to
power pins
Figure 114. Layout Example
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Layout Example (continued)
No Power Plane below
INP, INM, and ACT pins
Power Planes for AVDD_5V
and AVDD_ADC
SPI pins
Figure 115. Layout Example
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Layout Example (continued)
No Power Plane below
INP, INM, and ACT pins
Power Plane
AVDD
Power Plane
AVDD_ADC
Power Plane
DVDD
Figure 116. Layout Example
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Layout Example (continued)
CW CLKs
CW I/Os
GND Fanout
CW CLKs
ADC CLK
LVDS Outputs
Figure 117. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For the Power Stage Designer see www.ti.com/filterdesigner
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• MicroStar BGA Packaging Reference Guide, SSYZ015
• Clocking High-Speed Data Converters, SLYT075
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AFE5809ZCF
ACTIVE
NFBGA
ZCF
135
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 85
AFE5809
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of