AM26LV32E
AM26LV32E
SLLS849D – APRIL 2008 – REVISED DECEMBER
2020
SLLS849D – APRIL 2008 – REVISED DECEMBER 2020
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AM26LV32E Low-Voltage High-Speed Quadruple Differential Line Receiver
With ±15-KV IEC ESD Protection
1 Features
3 Description
•
The AM26LV32E device consists of quadruple
differential line receivers with 3-state outputs. This
device is designed to meet TIA/EIA-422-B and ITU
recommendation V.11 drivers with reduced supply
voltage. The device is optimized for balanced bus
transmission at switching rates up to 32 MHz. The 3state outputs permit connection directly to a busorganized system. The AM26LV32E has an internal
fail-safe circuitry that prevents the device from putting
an unknown voltage signal at the receiver outputs. In
the open fail-safe, a high state is produced at the
respective output. This device is supported for partialpower-down applications using Ioff. Ioff circuitry
disables the outputs, preventing damaging current
back-flow through the device when it is powered
down.
•
•
•
•
•
•
•
•
•
•
Meets or Exceeds Standard TIA/EIA-422-B and
ITU Recommendation V.11
Operates From a Single 3.3-V Power Supply
Switching Rates up to 32 MHz
ESD Protection for RS422 Bus Pins
(See ESD Ratings)
Low Power Dissipation: 27 mW Typ
Open Circuit Fail-Safe
±7-V Common-Mode Input Voltage Range With
±200-mV Sensitivity
Accepts 5-V Logic Inputs With 3.3-V Supply
(Enable Inputs)
Input Hysteresis: 35 mV Typ
Pin-to-Pin Compatible With AM26C32, AM26LS32
Ioff Supports Partial-Power-Down Mode Operation
Device Information
2 Applications
•
•
•
•
•
PART NUMBER
High-Reliability Automotive Applications
Configuration Control/Print Support
ATM and Cash Counters
Smart Grid
AC and Servo Motor Drives
AM26LV32E
(1)
PACKAGE(1)
BODY SIZE (NOM)
SO (16)
10.20 mm x 5.30 mm
SOIC (16)
9.90 mm x 3.90 mm
VQFN (16)
4.00 mm x 3.50 mm
TSSOP (16)
5.00 mm x 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
G 4
12
G
1A 2
1B 1
2A 6
2B 7
3A 10
3B 9
4A 14
4B 15
3 1Y
5 2Y
11 3Y
13 4Y
Logic Diagram (Positive Logic)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
9 Application Information Disclaimer............................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Receiving Notification of Documentation Updates..13
12.2 Support Resources................................................. 13
12.3 Trademarks............................................................. 13
12.4 Electrostatic Discharge Caution..............................13
12.5 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2018) to Revision D (December 2020)
Page
• Changed feature From: Open Circuit, Short Circuit, and Terminated Fail-Safe To: Open Circuit Fail-Safe ...... 1
• Deleted text from the Description: shorted fail-safe, and terminated fail-safe To: Open Circuit Fail-Safe ......... 1
• Deleted text from the last paragraph in Input Fail-Safe Circuitry: terminated or short .......................................8
• Deleted text from Table 8-1: shorted, or terminated .......................................................................................... 9
Changes from Revision B (July 2015) to Revision C (July 2018)
Page
• Changed the pinout image appearance .............................................................................................................3
• Changed the A and B Input signals on the waveform of Figure 7-1 .................................................................. 7
Changes from Revision A (May 2008) to Revision B (July 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
2
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1A
2
15
4B
1Y
3
14
4A
G
4
13
4Y
2Y
5
12
G
6
11
3Y
2B
7
10
3A
GND
8
9
3B
1A
2
15
4B
1Y
3
14
4A
G
4
13
4Y
Thermal
Pad
2Y
5
12
G
2A
6
11
3Y
2B
7
10
3A
8
2A
VCC
VCC
16
16
9
1
1B
1B
1
5 Pin Configuration and Functions
GND
Figure 5-1. D, NS, or PW Package, 16-Pin SOIC,
SO, or TSSOP Top View
3B
Not to scale
Not to scale
Figure 5-2. RGY Package 16-Pin VQFN Top View
Table 5-1. Pin Functions
PIN
NAME
NO,
1A
2
1B
1Y
I/O
DESCRIPTION
I
RS422/RS485 differential input (noninverting)
1
I
RS422/RS485 differential input (inverting)
3
O
Logic level output
2A
6
I
RS422/RS485 differential input (noninverting)
2B
7
I
RS422/RS485 differential input (inverting)
2Y
5
O
Logic level output
3A
10
I
RS422/RS485 differential input (noninverting)
3B
9
I
RS422/RS485 differential input (inverting)
3Y
11
O
Logic level output
4A
14
I
RS422/RS485 differential input (noninverting)
4B
15
I
RS422/RS485 differential input (inverting)
4Y
13
O
Logic level output
G
4
I
Active-high select
G
12
I
GND
8
—
Ground
VCC
16
—
Power Supply
Active-low select
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (3)
MIN
VCC
Supply
VI
voltage(2)
Input voltage
MAX
UNIT
V
-0.5
6
A or B inputs
–14
14
G or G inputs
–0.5
6
V
VID
Differential input voltage(4)
–14
14
V
VO
Output voltage
–0.5
6
V
IO
Output current
±20
mA
IIK
Input clamp current
VI < 0
-20
mA
IOK
Output clamp current
VO < 0
-20
mA
TJ
Operating virtual junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
–65
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values except differential input voltage are with respect to the network GND.
This device is designed to meet TIA/EIA-422-B and ITU.
Differential input voltage is measured at the non-inverting input with respect to the corresponding inverting input.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
(1)
Electrostatic discharge
UNIT
±15000
IEC61000-4-2, Contact Gap Discharge
±8000
IEC61000-4-2, Air Gap Discharge
±15000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±15000 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
V
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
VIC
Common-mode input voltage
–7
7
V
VID
Differential input voltage
–7
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
–40
UNIT
7
V
–5
mA
5
mA
85
°C
6.4 Thermal Information
AM26LV32E
THERMAL
RθJA
METRIC(1)
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
(1)
4
D (SOIC)
PW (TSSOP)
NS (SOP)
RGY (VQFN)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
73.1
109
69
92
°C/W
38.4
34
34
40
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended ranges of common-mode input, supply voltage, and operating free-air temperature (unless otherwise
noted)
PARAMETER
VIT+
Positive-going input threshold voltage,
differential input
VIT–
Negative-going input threshold voltage,
differential input
Vhys
Input hysteresis (VIT+ – VIT–)
VIK
Input clamp voltage, G and G
TEST CONDITIONS
MIN
High-level output voltage
VOL
Low-level output voltage
IOZ
Ioff
MAX
0.2
–0.2
II = –18 mA
VID = 200 mV, IOH = –100 μA
V
3.2
V
VCC –
0.1
VID = –200 mV, IOL = 5 mA
V
mV
–1.5
2.4
UNIT
V
35
VID = 200 mV, IOH = –5 mA
VOH
TYP
0.17
0.5
V
VID = –200 mV, IOL = 100 μA
0.1
High-impedance state output current
VO = VCC or GND
±50
μA
Output current with power off
VCC = 0 V, VO = 0 or 5.5 V
±100
μA
II
Line input current
Other input at 0 V
II
Enable input current, G and G
VI = VCC or GND
VI = 10 V
1.5
VI = –10 V
–2.5
ri
Input resistance
VIC = –7 V to 7 V, Other input at 0 V
ICC
Supply current (total package)
G, G = VCC or GND, No load, Line inputs open
Cpd
Power dissipation capacitance
One channel
4
±1
μA
17
mA
17
8
mA
kΩ
150
pF
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
See Figure 7-1
MIN
TYP(1)
MAX
UNIT
8
16
26
ns
8
16
26
ns
tt
Transition time
See Figure 7-1
5
tPZH
Output-enable time to high-level
See Figure 7-2
17
40
ns
tPZL
Output-enable time to low-level
See Figure 7-2
10
40
ns
tPHZ
Output-disable time from high-level
See Figure 7-2
20
40
ns
tPLZ
Output-disable time from low-level
See Figure 7-2
16
40
ns
tsk(p)
Pulse skew
See Figure 7-1 Figure 7-2
4
6
ns
tsk(o)
Pulse skew
See Figure 7-1 Figure 7-2
4
6
ns
tsk(pp)
Pulse skew (device to device)
See Figure 7-1 Figure 7-2
6
9
ns
f(max)
Maximum operating frequency
See Figure 7-1
(1)
32
ns
MHz
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.7 Typical Characteristics
6
Output Voltage - V
5
4
3
2
1
0
HIGH
LOW
±1
0
10
20
30
Logic Input Current - mA
40
50
C001
Figure 6-1. Output Voltage vs Input Current
6
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7 Parameter Measurement Information
A
Generator
(see Note B)
Y
VO
B
50Ÿ
CL = 15 pF
(see Note A)
50Ÿ
B
2V
A
1V
Input
tPLH
VCC
Output
G
G
(see Note C)
tPHL
90%
50%
10%
90%
VOH
50%
10% V
OL
tr
tf
A. CL includes probe and jig capacitance.
Figure 7-1. Switching Test Circuit and Voltage Waveforms
VID = 1 V
A
Y
VO
B
CL = 15 pF
(see Note A)
RL = 2 kΩ
G
Generator
(see Note B)
50 Ω
G
VCC
(see Note C)
VCC
Input
50%
50%
0V
tPZH
Output
tPHZ
VOH
VOH - 0.3 V
Voff ≈ 0
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle ≤ 50%, tr = tf = 6 ns.
Figure 7-2. Enable/Disable Time Test Circuit and Output Voltage Waveforms
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8 Detailed Description
8.1 Overview
The AM26LV32E is a low-voltage, quadruple-differential line receiver that meets the necessary requirements for
NSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11. This device allows a low power or
low voltage MCU to interface with heavy machinery, subsystems and other devices through long wires of up to
1000 m, giving any design a reliable and easy to use connection. As with any RS422 interface, the AM26LV32E
works in a differential voltage range, which enables very good signal integrity.
8.2 Functional Block Diagram
EQUIVALENT OF EACH INPUT (A, B)
VCC
EQUIVALENT OF EACH
ENABLE INPUT (G, G)
VCC
TYPICAL OF EACH RECEIVER OUTPUT
VCC
2.4 kΩ
5 kΩ
7 kΩ
Enable
G, G
1.5 kΩ
A, B
200 kΩ
Output
1.5 kΩ
VCC(A)
or
GND(B)
2.4 kΩ
GND
GND
GND
8.3 Feature Description
8.3.1 ±7-V Common-Mode Range With ±200-mV Sensitivity
For a common-mode voltage varying from –7 V to 7 V, the input voltage is acceptable in low ranges greater than
200 mV as a standard.
8.3.2 Input Fail-Safe Circuitry
RS-485 specifies that the receiver output state should be logic high for differential input voltages of VAB ≥ +200
mV and logic low for VAB ≤ –200 mV. For input voltages in between these limits, a receiver’s output state is not
defined and can randomly assume high or low. Removing the uncertainty of random output states, modern
transceiver designs include internal biasing circuits that put the receiver output into a defined state (typically
high) in the absence of a valid input signal. A loss of input signal can be caused by:
• an open circuit caused by a wire break or the unintentional disconnection of a transceiver from the bus
• a short circuit due to an insulation fault, connecting both conductors of a differential pair to one another
• an idle bus when none of the bus transceivers are active.
An open circuit caused by a wire break or the unintentional disconnection of a transceiver from the bus. The
AM26LV32E has an internal circuit that ensures functionality during an open failure.
8.3.3 Active-High and Active-Low
The device can be configure using the G and G logic inputs to select receiver output. The high voltage or logic 1
on the G pin, allows the device to operate on an active-high and having a low voltage or logic 0 on the G enables
active low operation. These are simply a way to configure the logic to match that of the receiving or transmitting
controller or microprocessor.
8
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8.4 Device Functional Modes
8.4.1 Enable and Disable
The receivers implemented in these RS422 devices can be configured using the G and G pins to be enabled or
disabled. This allows users to ignore or filter out transmissions as desired.
Table 8-1. Function Table (Each Driver)
DIFFERENTIAL
INPUT
VID ≥ 0.2 V
–0.2 V < VID < 0.2 V
VID ≤ –0.2 V
Open
X
(1)
ENABLES(1)
OUTPUT
G
G
H
X
H
X
L
H
H
X
?
X
L
?
H
X
L
X
L
L
H
X
H
X
L
H
L
H
Z
H = high-level, L = low-level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
When designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,
proper cable termination is essential for highly reliable applications with reduced reflections in the transmission
line. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end of the
cable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors to
consider when determining the type of termination usually are performance requirements of the application and
the ever-present factor, cost. The different types of termination techniques discussed are unterminated lines,
parallel termination, ac termination, and multipoint termination. Laboratory waveforms for each termination
technique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and, indirectly, RS485). Similar results can be obtained if 485-compliant devices and termination techniques are used. For
laboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver and
receiver, TI AM26LV31E and AM26LV32E, respectively, were tested at room temperature with a 3.3-V supply
voltage. Two plots per termination technique are shown. In each plot, the top waveform is the driver input and
the bottom waveform is the receiver output. To show voltage waveforms related to transmission-line reflections,
the first plot shows output waveforms from the driver at the start of the cable; the second plot shows input
waveforms to the receiver at the far end of the cable.
9.2 Typical Application
AM26LV31E
(One Driver)
DIN
D
AM26LV32E
(One Receiver)
RT
ROUT
D
Figure 9-1. Differential Terminated Configuration
9.2.1 Design Requirements
Resistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary from
system to system. For example, the termination resistor, RT, must be within 20% of the characteristic
impedance, ROUT , of the cable and can vary from about 80 Ω to 120 Ω.
9.2.2 Detailed Design Procedure
Figure 9-1 shows a configuration with RT as termination. Although reflections are present at the receiver inputs
at a data signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the input
differential voltage and produces a clean signal at the output.
10
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9.2.3 Application Curve
5
4
Voltage (V)
3
2
1
0
±1
±2
±3
Y
A/B
±4
0
0.1
0.2
0.3
Time ( s)
0.4
0.5
C001
Figure 9-2. Differential 120-Ω Terminated Output Waveforms (CAT 5E Cable)
10 Power Supply Recommendations
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
VDD
VCC
1B 1
16
1A 2
15 4B
1Y
3
14 4A
Reduce logic signal trace G
when possible
4
2Y
5
12 G
2A 6
11 3Y
2B 7
10 3A
Termination Resistor
GND
0.1µF
13 4Y
AM26LV32E
8
9 3B
Figure 11-1. Trace Layout on PCB and Recommendations
12
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AM26LV32EIDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26LV32EI
AM26LV32EIDRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26LV32EI
AM26LV32EINSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
26LV32EI
AM26LV32EIPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SB32
AM26LV32EIPWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SB32
AM26LV32EIRGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SB32
AM26LV32EIRGYRG4
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SB32
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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