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AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25
SBAS734B – MARCH 2017 – REVISED JUNE 2018
AMC1306x Small, High-Precision,
Reinforced Isolated Delta-Sigma Modulators With High CMTI
1 Features
3 Description
•
The AMC1306 is a precision, delta-sigma (ΔΣ)
modulator with the output separated from the input
circuitry by a capacitive double isolation barrier that is
highly resistant to magnetic interference. This barrier
is certified to provide reinforced isolation of up to
7000 VPEAK according to the DIN V VDE V 0884-11
and UL1577 standards. Used in conjunction with
isolated power supplies, this isolated modulator
separates parts of the system that operate on
different common-mode voltage levels and protects
lower-voltage parts from damage.
1
•
•
•
•
•
Pin-Compatible Family Optimized for ShuntResistor-Based Current Measurements:
– ±50-mV or ±250-mV Input Voltage Ranges
– Manchester Coded or Uncoded Bitstream
Options
Excellent DC Performance:
– Offset Error: ±50 µV or ±100 µV (max)
– Offset Drift: 1 µV/°C (max)
– Gain Error: ±0.2% (max)
– Gain Drift: ±40 ppm/°C (max)
Transient Immunity: 100 kV/µs (typ)
System-Level Diagnostic Features
Safety-Related Certifications:
– 7000-VPEAK Reinforced Isolation per DIN V
VDE V 0884-11 (VDE V 0884-11): 2017-01
– 5000-VRMS Isolation for 1 Minute per UL1577
– CAN/CSA No. 5A-Component Acceptance
Service Notice, IEC 60950-1, and IEC 60065
End Equipment Standards
Fully Specified Over the Extended Industrial
Temperature Range: –40°C to +125°C
The input of the AMC1306 is optimized for direct
connection to shunt resistors or other low voltagelevel signal sources. The unique low input voltage
range of the ±50-mV device allows significant
reduction of the power dissipation through the shunt
and supports excellent ac and dc performance. The
output bitstream of the AMC1306 is Manchester
coded (AMC1306Ex) or uncoded (AMC1306Mx),
depending on the derivate. By using an integrated
digital filter (such as those in the TMS320F2807x or
TMS320F2837x microcontroller families) to decimate
the bitstream, the device can achieve 16 bits of
resolution with a dynamic range of 85 dB at a data
rate of 78 kSPS.
The bitstream output of the Manchester coded
AMC1306Ex versions support single-wire data and
clock transfer without having to consider the setup
and hold time requirements of the receiving device.
2 Applications
•
Shunt-Resistor-Based Current Sensing and
Isolated Voltage Measurements in:
– Industrial Motor Drives
– Photovoltaic Inverters
– Uninterruptible Power Supplies
Device Information(1)
PART NUMBER
AMC1306x
PACKAGE
SOIC (8)
BODY SIZE (NOM)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Floating
Power Supply
HV+
AMC1306Mx
AGND
RSHUNT
Optional
AINN
To Load
Optional
DVDD
AVDD
Optional
AINP
Reinforced Isolation
3.3 V or 5.0 V
DGND
3.0 V, 3.3 V, or 5.0 V
TMS320F28x7x
DOUT
SD-Dx
CLKIN
SD-Cx
PWMx
HV-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25
SBAS734B – MARCH 2017 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Power Ratings........................................................... 4
Insulation Specifications............................................ 5
Safety-Related Certifications..................................... 6
Safety Limiting Values .............................................. 6
Electrical Characteristics: AMC1306x05 ................... 7
Electrical Characteristics: AMC1306x25 ................. 9
Switching Characteristics ...................................... 11
Insulation Characteristics Curves ......................... 12
Typical Characteristics .......................................... 13
Detailed Description ............................................ 20
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
21
25
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Applications ................................................ 27
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
35
35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
Changes from Revision A (July 2017) to Revision B
•
Page
Changed Reinforced Isolation Capacitor Lifetime Projection figure .................................................................................... 12
Changes from Original (March 2017) to Revision A
Page
•
Released AMC1306E05 and AMC1306M05 to production .................................................................................................... 1
•
Added ±50 µV to first DC Performance sub-bullet to reflect the AMC1306x05 devices ........................................................ 1
•
Changed standard deviation from 0884-10 to 0884-11 in first Safety-Related Certifications sub-bullet................................ 1
•
Changed VPEAK from 8000 to 7000 and standard deviation from 0884-10 to 0884-11 in first paragraph of Description
section ................................................................................................................................................................................... 1
•
Deleted Status column from Device Comparison Table......................................................................................................... 3
•
Changed standard deviation from 0884-10 to 0884-11 in DIN V VDE V 0884-11 section of Insulation Specifications table 5
•
Changed standard deviation from 0884-10 to 0884-11 in Safety-Related Certifications table .............................................. 6
•
Changed prevent to minimize in condition statement of Safety Limiting Values table........................................................... 6
•
Added Electrical Characteristics: AMC1306x05 table ........................................................................................................... 7
•
Changed test conditions of Analog Inputs test conditions from (AINP – AINN) / 2 to AGND to (AINP + AINN) / 2 to
AGND to include all possible conditions................................................................................................................................. 9
•
Changed IIB test condition from Inputs shorted to AGND to AINP = AINN = AGND, IIB = IIBP + IIBN ...................................... 9
•
Added AINP = AINN = AGND to EO parameter test conditions ............................................................................................ 9
•
Changed minus sign to plus or minus sign in typical specification of EG parameter ............................................................. 9
•
Changed 10% to 90% to 90% to 10% in test conditions of tf parameter ............................................................................ 11
•
Added AMC1306x05 devices to Typical Characteristics section ........................................................................................ 13
2
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SBAS734B – MARCH 2017 – REVISED JUNE 2018
5 Device Comparison Table
PART NUMBER
INPUT VOLTAGE RANGE
DIFFERENTIAL INPUT
RESISTANCE
DIGITAL OUTPUT INTERFACE
AMC1306E05
±50 mV
4.9 kΩ
Manchester coded CMOS
AMC1306E25
±250 mV
22 kΩ
Manchester coded CMOS
AMC1306M05
±50 mV
4.9 kΩ
Uncoded CMOS
AMC1306M25
±250 mV
22 kΩ
Uncoded CMOS
6 Pin Configuration and Functions
DWV Package
8-Pin SOIC
Top View
AVDD
1
8
DVDD
AINP
2
7
CLKIN
AINN
3
6
DOUT
AGND
4
5
DGND
Not to scale
Pin Functions
PIN
NO.
1
NAME
I/O
DESCRIPTION
Analog (high-side) power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
AVDD
—
2
AINP
I
Noninverting analog input
3
AINN
I
Inverting analog input
4
AGND
—
Analog (high-side) ground reference
5
DGND
—
Digital (controller-side) ground reference
6
DOUT
O
Modulator data output. This pin is a Manchester coded output for AMC1306Ex derivates.
7
CLKIN
I
Modulator clock input: 5 MHz to 21 MHz (5-V operation) with internal pulldown resistor (typical value: 1.5 MΩ)
8
DVDD
—
Digital (controller-side) power supply, 2.7 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
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SBAS734B – MARCH 2017 – REVISED JUNE 2018
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Supply voltage
MIN
MAX
UNIT
–0.3
6.5
V
AGND – 6
AVDD + 0.5
V
DGND – 0.5
DVDD + 0.5
V
AVDD to AGND or DVDD to DGND
Analog input voltage at AINP, AINN
Digital input or output voltage at CLKIN or DOUT
Input current to any pin except supply pins
–10
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
10
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
AVDD
Analog (high-side) supply voltage (AVDD to AGND)
3.0
5.0
5.5
UNIT
V
DVDD
Digital (controller-side) supply voltage (DVDD to DGND)
2.7
3.3
5.5
V
TA
Operating ambient temperature
–40
125
°C
7.4 Thermal Information
AMC1306x
THERMAL METRIC
(1)
DWV (SOIC)
UNIT
8 PINS
RθJA
112.2
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
47.6
°C/W
RθJB
Junction-to-board thermal resistance
60.0
°C/W
ψJT
Junction-to-top characterization parameter
23.1
°C/W
ψJB
Junction-to-board characterization parameter
60.0
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
PD
Maximum power dissipation
(both sides)
PD1
Maximum power dissipation
(high-side supply)
PD2
Maximum power dissipation
(low-side supply)
4
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TEST CONDITIONS
MIN
TYP
MAX
AMC1306Ex, AVDD = DVDD = 5.5 V
91.85
AMC1306Mx, AVDD = DVDD = 5.5 V
86.90
AVDD = 5.5 V
53.90
AMC1306Ex, DVDD = 5.5 V
37.95
AMC1306Mx, DVDD = 5.5 V
33.00
UNIT
mW
mW
mW
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SBAS734B – MARCH 2017 – REVISED JUNE 2018
7.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest pin-to-pin distance through air
≥9
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
≥9
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double insulation
(2 × 0.0105 mm)
≥ 0.021
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category per IEC 60664-1
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
Maximum-rated isolation working
voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage (3)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Insulation resistance, input to output (5)
RIO
At ac voltage (bipolar)
2121
VPK
At ac voltage (sine wave)
1500
VRMS
At dc voltage
2121
VDC
VTEST = VIOTM, t = 60 s (qualification test)
7000
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
8400
Test method per IEC 60065, 1.2/50-μs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s
≤5
Method b1, at routine test (100% production) and preconditioning
(type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~1
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
VPK
VPK
pC
pF
Ω
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
UL
Certified according to DIN V VDE V 0884-11 (VDE V 0884-11):
2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08,
and DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
File number: DIN 40040142
File number: E181974
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output (I/O) circuitry.
A failure of the I/O may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
θJA = 112.2°C/W, AVDD = DVDD = 5.5 V,
TJ = 150°C, TA = 25°C
202.5
θJA = 112.2°C/W, AVDD = DVDD = 3.6 V,
TJ = 150°C, TA = 25°C
309.4
mA
1114 (1)
θJA = 112.2°C/W, TJ = 150°C, TA = 25°C
UNIT
150
mW
°C
Input, output, or the sum of input and output power must not exceed this value.
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
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SBAS734B – MARCH 2017 – REVISED JUNE 2018
7.9 Electrical Characteristics: AMC1306x05
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are
at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VClipping
Differential input voltage before clipping output
VIN = AINP – AINN
FSR
Specified linear differential full-scale
VIN = AINP – AINN
Absolute common-mode input voltage (1)
VCM
±64
mV
–50
50
(AINP + AINN) / 2 to AGND
–2
AVDD
V
Operating common-mode input voltage
(AINP + AINN) / 2 to AGND
–0.032
AVDD – 2.1
V
VCMov
Common-mode overvoltage detection level (2)
(AINP + AINN) / 2 to AGND
AVDD - 2
CIN
Single-ended input capacitance
AINN = AGND
CIND
Differential input capacitance
IIB
Input bias current
AINP = AINN = AGND, IIB = IIBP + IIBN
RIN
Single-ended input resistance
AINN = AGND
4.75
kΩ
RIND
Differential input resistance
4.9
kΩ
IIO
Input offset current
±10
nA
CMTI
Common-mode transient immunity
100
kV/μs
CMRR
V
4
pF
2
Common-mode rejection ratio
–97
50
–72
AINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–99
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–98
pF
–57
μA
dB
Input bandwidth (3)
BW
mV
800
kHz
DC ACCURACY
DNL
Differential nonlinearity
Resolution: 16 bits
INL
Integral nonlinearity (4)
EO
Offset error
TCEO
Offset error thermal drift (5)
EG
Gain error
TCEG
Gain error thermal drift (6)
PSRR
0.99
LSB
–4
±1
4
Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V
–5
±1.5
5
–50
±2.5
50
µV
–1
±0.25
1
μV/°C
–0.2%
±0.005%
0.2%
–40
±20
40
Initial, at 25°C, AINP = AINN = AGND
Initial, at 25°C
Power-supply rejection ratio
–0.99
Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V, at dc
–108
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V,
10 kHz, 100-mV ripple
–107
LSB
ppm/°C
dB
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
78
82.5
dB
SINAD
Signal-to-noise + distortion
fIN = 1 kHz
77.5
82.3
dB
THD
Total harmonic distortion
SFDR
(1)
(2)
(3)
(4)
(5)
Spurious-free dynamic range
–98
–84
3.0 V ≤ AVDD ≤ 3.6 V,
5 MHz ≤ fCLKIN ≤ 20 MHz, fIN = 1 kHz
–93
–83
fIN = 1 kHz
dB
83
100
dB
Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
This is the –3-dB, second-order roll-off frequency of the integrated differential input amplifier to consider for the antialiasing filter design.
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).
Offset error drift is calculated using the box method, as described by the following equation:
TCE O
(6)
4.5 V ≤ AVDD ≤ 5.5 V,
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz
value MAX value MIN
TempRange
Gain error drift is calculated using the box method, as described by the following equation:
TCE G ( ppm )
§ value MAX value MIN
¨¨
© value u TempRange
·
¸¸ u 10 6
¹
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Electrical Characteristics: AMC1306x05 (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are
at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
CMOS Logic With Schmitt-Trigger
DGND ≤ VIN ≤ DVDD
IIN
Input current
CIN
Input capacitance
0
7
VIH
High-level input voltage
0.7 × DVDD
DVDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 × DVDD
CLOAD
Output load capacitance
VOH
High-level output voltage
VOL
Low-level output voltage
4
pF
30
IOH = –20 µA
DVDD – 0.1
IOH = –4 mA
DVDD – 0.4
µA
V
V
pF
V
IOL = 20 µA
0.1
IOL = 4 mA
0.4
V
POWER SUPPLY
AVDD
High-side supply voltage
IAVDD
High-side supply current
DVDD
Controller-side supply voltage
IDVDD
8
Controller-side supply current
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5.0
5.5
3.0 V ≤ AVDD ≤ 3.6 V
3.0
6.3
8.5
4.5 V ≤ AVDD ≤ 5.5 V
7.2
9.8
3.3
5.5
AMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
2.7
4.1
5.5
AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
3.3
4.8
AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
5.0
6.9
AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
3.9
6.0
V
mA
V
mA
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SBAS734B – MARCH 2017 – REVISED JUNE 2018
7.10 Electrical Characteristics: AMC1306x25
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –250 mV to 250 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications
are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VClipping
Differential input voltage before clipping output
AINP – AINN
FSR
Specified linear differential full-scale
AINP – AINN
Absolute common-mode input voltage (1)
VCM
±320
mV
–250
250
(AINP + AINN) / 2 to AGND
–2
AVDD
V
Operating common-mode input voltage
(AINP + AINN) / 2 to AGND
–0.16
AVDD – 2.1
V
VCMov
Common-mode overvoltage detection level (2)
(AINP + AINN) / 2 to AGND
AVDD – 2
CIN
Single-ended input capacitance
AINN = AGND
CIND
Differential input capacitance
IIB
Input bias current
AINP = AINN = AGND, IIB = IIBP + IIBN
RIN
Single-ended input resistance
AINN = AGND
19
kΩ
RIND
Differential input resistance
22
kΩ
IIO
Input offset current
±5
nA
CMTI
Common-mode transient immunity
100
kV/µs
CMRR
Common-mode rejection ratio
V
2
pF
1
–82
–60
50
AINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–95
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–95
pF
–48
µA
dB
Input bandwidth (3)
BW
mV
900
kHz
DC ACCURACY
DNL
Differential nonlinearity
Resolution: 16 bits
–0.99
0.99
LSB
INL
Integral nonlinearity (4)
Resolution: 16 bits
–4
±1
4
LSB
EO
Offset error
Initial, at 25°C, AINP = AINN = AGND
–100
±4.5
100
(5)
TCEO
Offset error thermal drift
EG
Gain error
TCEG
Gain error thermal drift (6)
Initial, at 25°C
–1
±0.15
1
–0.2%
±0.005%
0.2%
–40
±20
40
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V, at dc
PSRR
Power-supply rejection ratio
µV
µV/°C
ppm/°C
–103
dB
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V,
10 kHz, 100-mV ripple
–92
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
82
86
dB
SINAD
Signal-to-noise + distortion
fIN = 1 kHz
81.9
85.7
dB
THD
Total harmonic distortion
SFDR
(1)
(2)
(3)
(4)
(5)
(6)
Spurious-free dynamic range
4.5 V ≤ AVDD ≤ 5.5 V,
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz
–98
–86
3.0 V ≤ AVDD ≤ 3.6 V,
5 MHz ≤ fCLKIN ≤ 20 MHz, fIN = 1 kHz
–93
–85
fIN = 1 kHz
dB
83
100
dB
Steady-state voltage supported by the device in case of a system failure; see the specified common-mode input voltage VCM for normal
operation. Adhere to the analog input voltage range as specified in the Absolute Maximum Ratings table.
The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter
designs.
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
value MAX value MIN
TempRange
.
§ value MAX value MIN ·
6
TCE G ( ppm ) ¨¨
¸¸ u 10
© value u TempRange ¹
Gain error drift is calculated using the box method, as described by the following equation:
.
Offset error drift is calculated using the box method, as described by the following equation:
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TCE O
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Electrical Characteristics: AMC1306x25 (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –250 mV to 250 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications
are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
CMOS Logic with Schmitt-trigger
DGND ≤ VIN ≤ DVDD
IIN
Input current
CIN
Input capacitance
0
7
VIH
High-level input voltage
0.7 × DVDD
DVDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 × DVDD
CLOAD
Output load capacitance
VOH
High-level output voltage
VOL
Low-level output voltage
4
fCLKIN = 20 MHz
pF
30
IOH = –20 µA
DVDD – 0.1
IOH = –4 mA
DVDD – 0.4
μA
V
V
pF
V
IOL = 20 µA
0.1
IOL = 4 mA
0.4
V
POWER SUPPLY
AVDD
High-side supply voltage
IAVDD
High-side supply current
DVDD
Controller-side supply voltage
IDVDD
10
Controller-side supply current
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5.0
5.5
3.0 V ≤ AVDD ≤ 3.6 V
3.0
6.3
8.5
4.5 V ≤ AVDD ≤ 5.5 V
7.2
9.8
3.3
5.5
AMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
2.7
4.1
5.5
AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
3.3
4.8
AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
5.0
6.9
AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
3.9
6.0
V
mA
V
mA
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SBAS734B – MARCH 2017 – REVISED JUNE 2018
7.11 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.5 V ≤ AVDD ≤ 5.5 V
5
21
3.0 V ≤ AVDD ≤ 5.5 V
5
20
4.5 V ≤ AVDD ≤ 5.5 V
47.6
200
3.0 V ≤ AVDD ≤ 5.5 V
50
200
UNIT
fCLKIN
CLKIN clock frequency
tCLKIN
CLKIN clock period
tHIGH
CLKIN clock high time
20
25
120
ns
tLOW
CLKIN clock low time
20
25
120
ns
tH
DOUT hold time after rising edge AMC1306Mx (1),
of CLKIN
CLOAD = 15 pF
3.5
tD
Rising edge of CLKIN to DOUT
valid delay
tr
DOUT rise time
tf
DOUT fall time
0.8
3.5
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.8
3.9
90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
0.8
3.5
90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.8
3.9
DVDD at 2.7 V (min) to DOUT valid with
AVDD ≥ 3.0 V
tASTART
Analog startup time
AVDD step to 3.0 V with DVDD ≥ 2.7 V,
0.1% settling
(1)
15
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
Interface startup time
ns
ns
AMC1306Mx (1), CLOAD = 15 pF
tISTART
MHz
ns
ns
ns
32
32
CLKIN
cycles
0.5
ms
The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns;
see the Manchester Coding Feature section for additional details.
tCLKIN
tHIGH
CLKIN
tLOW
tH
tr / tf
tD
DOUT
Figure 1. Digital Interface Timing
AVDD
DVDD
tASTART
CLKIN
...
DOUT
Test Pattern
Bitream not valid
(analog settling)
Valid bitstream
tISTART
Figure 2. Device Startup Timing
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7.12 Insulation Characteristics Curves
1200
500
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
1100
1000
400
900
PS (mW)
IS (mA)
800
300
200
700
600
500
400
300
100
200
100
0
0
0
50
100
TA (°C)
150
200
0
50
D001
Figure 3. Thermal Derating Curve for Safety-Limiting
Current per VDE
1.E+11
1.E+10
87.5%
100
TA (°C)
150
200
D002
Figure 4. Thermal Derating Curve for Safety-Limiting
Power per VDE
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (
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