AMC3301
AMC3301
SBAS917B – AUGUST 2019 – REVISED
MAY 2021
SBAS917B – AUGUST 2019 – REVISED MAY 2021
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AMC3301 Precision, ±250-mV Input, Reinforced Isolated Amplifier
With Integrated DC/DC Converter
1 Features
3 Description
•
The AMC3301 is a precision, isolated amplifier
optimized for shunt-based current measurements.
The fully integrated, isolated DC/DC converter allows
single-supply operation from the low-side of the
device, which makes the device a unique solution
for space-constrained applications. The reinforced
capacitive isolation barrier is certified according to
VDE V 0884-11 and UL1577 and supports a working
voltage of up to 1.2 kVRMS.
•
•
•
•
•
•
•
•
3.3-V or 5-V single supply with integrated DC/DC
converter
±250-mV input voltage range optimized for current
measurement using shunt resistors
Fixed gain: 8.2
Low DC errors:
– Offset voltage: ±150 μV (max)
– Offset drift: ±1 µV/°C (max)
– Gain error: ±0.2% (max)
– Gain error drift: ±40 ppm/°C (max)
– Nonlinearity: ±0.04% (max)
High CMTI: 85 kV/µs (min)
System-level diagnostic features
Meets CISPR-11 and CISPR-25 EMI standards
Safety-related certifications:
– 6000-VPK reinforced isolation per DIN VDE V
0884-11
– 4250-VRMS isolation for 1 minute per UL1577
Fully specified over the extended industrial
temperature range: –40°C to +125°C
2 Applications
•
The isolation barrier separates parts of the system
that operate on different common-mode voltage levels
and protects the low-voltage side from hazardous
voltages and damage.
The input of the AMC3301 is optimized for direct
connection to a low-impedance shunt resistor or other,
low-impedance voltage source with low signal levels.
The excellent DC accuracy and low temperature drift
supports accurate current measurements over the
extended industrial temperature range from –40°C to
+125°C.
The integrated DC/DC converter fault-detection and
diagnostic output pin of the AMC3301 simplify
system-level design and diagnostics.
Isolated shunt-based current sensing in:
– Protection relays
– Motor drives
– Power supplies
– Photovoltaic inverters
Device Information(1)
PART NUMBER
AMC3301
(1)
PACKAGE
SOIC (16)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Low-side supply
(3.3 V or 5 V)
DCDC_OUT
DCDC_IN
HLDO_IN
I
NC
RSHUNT
HLDO_OUT
+250 mV
0V
± 250 mV
INP
DCDC_GND
Isolated
Power
Reinforced Isolation
DCDC_HGND
Isolated
Power
INN
DIAG
VDD
OUTP
OUTN
HGND
To MCU (optional)
LDO_OUT
VCMout
±2.05 V
ADC
GND
AMC3301
Typical Application
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Power Ratings ............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics ............................................8
6.10 Switching Characteristics .......................................10
6.11 Timing Diagram....................................................... 10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................ 12
7 Detailed Description......................................................18
7.1 Overview................................................................... 18
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................21
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Device Support........................................................28
11.2 Documentation Support.......................................... 28
11.3 Receiving Notification of Documentation Updates.. 28
11.4 Support Resources................................................. 28
11.5 Trademarks............................................................. 28
11.6 Electrostatic Discharge Caution.............................. 28
11.7 Glossary.................................................................. 28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2020) to Revision B (May 2021)
Page
• Changed Features section: changed Offset voltage and Offset drift sub-bullets in Low DC errors bullet,
rearranged bullets, added last bullet...................................................................................................................1
• Changed target application from Isolated voltage sensing to Isolated shunt-based current sensing in
Applications section............................................................................................................................................ 1
• Changed Pin Configuration and Functions section.............................................................................................3
• Changed Absolute Maximum Ratings: changed max for DIAG pin from 5.5 V to 6.5 V..................................... 4
• Changed overvoltage category for rated mains voltage ≤ 600 V from I-IV to I-III and for rated mains voltage
≤1000 V from I-III to I-II ......................................................................................................................................6
• Changed output bandwidth (BW) (min) from 250 kHz to 290 kHz......................................................................8
• Changed Typical Characteristics section. Removed histograms, editorial changes.........................................12
• Changed Functional Block Diagram figure....................................................................................................... 18
• Changed Data Isolation Channel Signal Transmission section........................................................................ 19
• Changed Analog Output section.......................................................................................................................20
• Changed Diagnostic Output section: added DIAG Output Under Different Operating Conditions figure......... 21
• Changed Typical Application section................................................................................................................ 22
• Changed Input Filter Design section: changed Differential Input Filter figure...................................................23
• Added Differential to Single-Ended Output Conversion section....................................................................... 24
• Changed Step Response of the AMC3301 figure.............................................................................................24
• Changed Power Supply Recommendations section: changed nominal value in the first sentence from 3.3 V
(or 5 V) ± 10 V to 3.3 V or 5 V, changed primary-side to low-side, secondary-side to high-side, and
Decoupling the AMC3301 figure.......................................................................................................................26
• Changed Recommended Layout of the AMC3301 figure................................................................................. 27
Changes from Revision * (August 2019) to Revision A (July 2020)
Page
• Changed document status from advance information to production data ......................................................... 1
2
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5 Pin Configuration and Functions
DCDC_OUT
1
16
DCDC_IN
DCDC_HGND
2
15
DCDC_GND
HLDO_IN
3
14
DIAG
NC
4
13
LDO_OUT
HLDO_OUT
5
12
VDD
INP
6
11
OUTP
INN
7
10
OUTN
HGND
8
9
GND
Not to scale
Figure 5-1. DWE Package, 16-Pin SOIC, Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
High-side output of the isolated DC/DC converter; connect this pin to the HLDO_IN pin.(1)
1
DCDC_OUT
Power
2
DCDC_HGND
High-side power ground
3
HLDO_IN
Power
High-side ground reference for the isolated DC/DC converter; connect this pin to the
HGND pin.
Input of the high-side LDO; connect this pin to the DCDC_OUT pin.(1)
4
NC
—
5
HLDO_OUT
Power
No internal connection; connect this pin to HGND or leave this pin unconnected.
6
INP
Analog input
Noninverting analog input. Either INP or INN must have a DC current path to HGND to
define the common-mode input voltage.(2)
7
INN
Analog input
Inverting analog input. Either INP or INN must have a DC current path to HGND to define
the common-mode input voltage.(2)
Output of the high-side LDO.(1)
8
HGND
High-side signal ground
High-side analog ground; connect this pin to the DCDC_HGND pin.
9
GND
Low-side signal ground
Low-side analog ground; connect this pin to the DCDC_GND pin.
10
OUTN
Analog output
Inverting analog output.
11
OUTP
Analog output
Noninverting analog output.
12
VDD
Low-side power
13
LDO_OUT
Power
14
DIAG
Digital output
15
DCDC_GND
Low-side power ground
Low-side ground reference for the isolated DC/DC converter; connect this pin to the GND
pin.
16
DCDC_IN
Power
Low-side input of the isolated DC/DC converter; connect this pin to the LDO_OUT pin.(1)
(1)
(2)
Low-side power supply.(1)
Output of the low-side LDO; connect this pin to the DCDC_IN pin. The output of the LDO
must not be loaded by external circuitry.(1)
Active-low, open-drain status indicator output; connect this pin to the pullup supply (for
example, VDD) using a resistor or leave this pin floating if not used.
See the Power Supply Recommendations section for power-supply decoupling recommendations.
See the Layout section for details.
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
MAX
UNIT
Power-supply voltage
VDD to GND
–0.3
6.5
V
Analog input voltage
INP, INN
HGND – 6
VHLDO_OUT + 0.5
V
Analog output voltage
OUTP, OUTN
GND – 0.5
VDD + 0.5
V
Digital output voltage
DIAG
GND – 0.5
6.5
V
10
mA
Input current
Temperature
(1)
Continuous, any pin except power-supply pins
–10
Junction, TJ
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
3
3.3
5.5
V
–250
250
mV
POWER SUPPLY
VDD
Low-side power supply
VDD to GND
ANALOG INPUT
VClipping
Differential input voltage before clipping output
VIN = VINP – VINN
VFSR
Specified linear differential full-scale voltage
VIN = VINP – VINN
Absolute common-mode input voltage (1)
(VINP + VINN) / 2 to HGND
–2
VHLDO_OUT
V
Operating common-mode input voltage
(VINP + VINN) / 2 to HGND
–0.16
1
V
–40
125
°C
VCM
±320
mV
TEMPERATURE RANGE
TA
(1)
4
Specified ambient temperature
Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
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6.4 Thermal Information
AMC3301
THERMAL
METRIC(1)
UNIT
DWE (SOIC)
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
44
°C/W
ψJT
Junction-to-top characterization parameter
16.7
°C/W
ψJB
Junction-to-board characterization parameter
42.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
73.5
°C/W
31
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation
TEST CONDITIONS
MIN
TYP
MAX
VDD = 5.5 V
231
VDD = 3.6 V
151
UNIT
mW
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest pin-to-pin distance through air
≥8
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
≥8
mm
Minimum internal gap (internal clearance - capacitive signal isolation)
≥ 21
Minimum internal gap (internal clearance - transformer power isolation)
≥ 120
≥ 600
DTI
Distance through the insulation
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-III
Rated mains voltage ≤ 1000 VRMS
I-II
DIN VDE V 0884-11 (VDE V 0884-11):
µm
V
I
2017-01(2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
Maximum-rated isolation
working voltage
At AC voltage (bipolar)
1700
VPK
At AC voltage (sine wave); time-dependent dielectric breakdown (TDDB)
test
1200
VRMS
At DC voltage
1700
VDC
VTEST = VIOTM, t = 60 s (qualification test)
6000
VPK
VIOTM
Maximum transient
isolation voltage
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
7200
VPK
VIOSM
Maximum surge
isolation voltage(3)
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
6250
VPK
Apparent charge(4)
qpd
CIO
Barrier capacitance,
input to output(5)
RIO
Insulation resistance,
input to output(5)
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1, at routine test (100% production) and preconditioning (type
test),
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~3.5
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL1577
VISO
(1)
Withstand isolation voltage
VTEST = VISO = 4250 VRMS or 6000 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO, t = 1 s (100% production test)
4250
VRMS
(2)
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings must be ensured
(3)
(4)
(5)
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
6
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
6.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
ofthe I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 73.5°C/W, VDD = 5.5 V,
TJ = 150°C, TA = 25°C
309
RθJA = 73.5°C/W, VDD = 3.6 V,
TJ = 150°C, TA = 25°C
472
RθJA = 73.5°C/W,
TJ = 150°C, TA = 25°C
UNIT
mA
1700
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum low-side voltage.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –250 mV to +250 mV,
INN = HGND = 0 V, and the external components listed in the Typical Application section; typical specifications are at TA =
25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
Single-ended input resistance
INN = HGND
19
RIND
Differential input resistance
IIB
Input bias current
TCIIB
Input bias current drift
IIO
Input offset current
IIO = |IIBP – IIBN|
CIN
Single-ended input capacitance
INN = HGND, fIN = 275 kHz
2
CIND
Differential input capacitance
fIN = 275 kHz
1
kΩ
22
INP = INN = HGND; IIB = (IIBP +
IIBN) / 2
–41
–30
–24
µA
0.8
nA/°C
1.4
nA
pF
ANALOG OUTPUT
Nominal gain
8.2
Common-mode output voltage
VCLIPout
Clipping differential output voltage
VOUT = (VOUTP – VOUTN);
|VIN| = |VINP – VINN| > VClipping
±2.49
VFailsafe
Failsafe differential output voltage
VOUT = (VOUTP – VOUTN);
VDCDC_OUT ≤ VDCDCUV, or
VHLDO_OUT ≤ VHLDOUV
–2.57
BW
Output bandwidth
334
kHz
ROUT
Output resistance
On OUTP or OUTN
0.2
Ω
Output short-circuit current
On OUTP or OUTN, sourcing or
sinking, INP = INN = HGND, outputs
shorted to either GND or VDD
14
mA
Common-mode transient immunity
|HGND – GND| = 2 kV
135
kV/µs
VOS
Input offset voltage(1) (2)
TA = 25°C, INP = INN = HGND
TCVOS
Input offset drift(1) (2) (4)
EG
Gain error(1)
TCEG
Gain error drift(1) (5)
CMTI
1.39
290
85
1.44
V/V
VCMout
1.49
V
V
-2.5
V
ACCURACY
TA = 25°C
Nonlinearity(1)
–0.15
±0.02
0.15
–1
±0.15
1
–0.2%
±0.04%
0.2%
–40
±6
40
–0.04%
±0.002%
0.04%
Nonlinearity drift(1)
SNR
Signal-to-noise ratio
THD
CMRR
PSRR
8
0.9
VIN = 0.5 VPP, fIN = 1 kHz, BW = 10
kHz, 10 kHz filter
80
85
VIN = 0.5 VPP, fIN = 10 kHz,
BW = 100 kHz, 1 MHz filter
67
71
mV
uV/°C
ppm/°C
ppm/°C
dB
Total harmonic distortion(3)
VIN = 0.5 Vpp, fIN = 10 kHz,
BW = 100 kHz
–85
dB
Output noise
INP = INN = HGND, fIN = 0 Hz,
BW = 100 kHz
300
µVRMS
fIN = 0 Hz, VCM min ≤ VCM ≤VCM max
–97
fIN = 10 kHz, VCM min ≤ VCM ≤VCM max
–98
VDD from 3.0 V to 5.5 V, at dc, input
referred
–109
Common-mode rejection ratio
Power-supply rejection ratio
INP = INN = HGND, VDD from 3.0
V to 5.5 V, 10 kHz / 100 mV ripple,
input referred
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dB
dB
–98
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –250 mV to +250 mV,
INN = HGND = 0 V, and the external components listed in the Typical Application section; typical specifications are at TA =
25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
no external load on HLDO
27.5
40
1 mA external load on HLDO
29.5
42
3.1
3.5
4.65
2.1
2.25
3
3.2
2.4
2.6
UNIT
POWER SUPPLY
IDD
Low-side supply current
VDCDC_OUT DCDC output voltage
DCDC_OUT to HGND
VDCDCUV
DCDC output undervoltage detection
DCDC output falling
threshold voltage
VHLDO_OUT
High-side LDO output voltage
HLDO to HGND, up to 1 mA external
load
VHLDOUV
High-side LDO output undervoltage
detection threshold voltage
HLDO output falling
IH
High-side supply current for auxiliary Load connected from HLDO_OUT to
circuitry
HGND, non-switching
tAS
Analog settling time
VDD step to 3.0 V, to OUTP and
OUTN valid, 0.1% settling
0.9
(1)
The typical value includes one standard deviation ("sigma") at nominal operating conditions.
(2)
(3)
(4)
This parameter is input referred.
THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
(5)
mA
V
V
3.4
V
V
1
mA
1.4
ms
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
tr
tf
TEST CONDITIONS
MIN
Output signal rise time
TYP
MAX
1.3
Output signal fall time
UNIT
µs
1.3
µs
VINx to VOUTx signal delay (50% – 10%)
Unfiltered output
1
1.5
µs
VINx to VOUTx signal delay (50% – 50%)
Unfiltered output
1.6
2.1
µs
VINx to VOUTx signal delay (50% – 90%)
Unfiltered output
2.5
3
µs
6.11 Timing Diagram
250 mV
INP - INN
0
± 250 mV
tf
tr
OUTN
VCMout
OUTP
50% - 10%
50% - 50%
50% - 90 %
Figure 6-1. Rise, Fall, and Delay Time Waveforms
10
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6.12 Insulation Characteristics Curves
500
1800
VDD = 3.6 V
VDD = 5.5 V
1600
400
1400
PS (mW)
IS (mA)
1200
300
200
1000
800
600
400
100
200
0
0
0
25
50
75
TA (°C)
100
125
0
150
25
50
75
TA (°C)
D069
Figure 6-2. Thermal Derating Curve for Safety-Limiting Current
per VDE
100
125
150
D070
Figure 6-3. Thermal Derating Curve for Safety-Limiting Power
per VDE
1.E+11
87.5%
1.E+10
143 Yrs
76 Yrs
1.E+09
Time to Fail (sec)
1.E+08
1.E+07
TDDB Line (< 1 ppm Fail Rate)
1.E+06
Operating Zone
1.E+05
1.E+04
VDE Safety Margin Zone
1.E+03
20 %
1.E+02
1.E+01
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
6500
Applied Voltage (VRMS)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1200 VRMS, operating lifetime = 76 years
Figure 6-4. Reinforced Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
-10
-23
-25
-15
-27
IIB (PA)
IIB (PA)
-29
-20
-25
-31
-33
-35
-30
-37
-35
-0.5
-41
-39
-0.25
0
0.25
0.5
VCM (V)
0.75
1
1.25
3
-23
5
-25
4.5
5.5
D004
VOUTN
VOUTP
4
VOUT (V)
IIB (PA)
5
3.5
-29
-31
-33
-35
3
2.5
2
1.5
-37
1
-39
0.5
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
0
-350
110 125
-250
D005
Figure 6-7. Input Bias Current vs Temperature
-150
-50
50
150
Differential Input Voltage (mV)
250
350
D022
Figure 6-8. Output Voltage vs Input Voltage
1.49
1.49
1.48
1.48
1.47
1.47
1.46
1.46
1.45
1.45
VCMout (V)
VCMout (V)
4.5
Figure 6-6. Input Bias Current vs Supply Voltage
-27
1.44
1.43
1.44
1.43
1.42
1.42
1.41
1.41
1.4
1.4
1.39
3
3.5
4
4.5
VDD (V)
5
5.5
1.39
-40
-25
D009
Figure 6-9. Output Common-Mode Voltage vs Supply Voltage
12
4
VDD (V)
Figure 6-5. Input Bias Current vs Common-Mode Input Voltage
-41
-40
3.5
D003
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D010
Figure 6-10. Output Common-Mode Voltage vs Temperature
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
5
0°
0
-45°
-90°
-10
Output Phase
Normalized Gain (dB)
-5
-15
-20
-25
-135°
-180°
-225°
-270°
-30
-315°
-35
-40
-360°
1
10
100
1000
fIN (kHz)
1
1000
D008
Figure 6-12. Output Phase vs Input Frequency
350
350
340
340
330
330
BW (kHz)
BW (kHz)
100
fIN (kHz)
Figure 6-11. Normalized Gain vs Input Frequency
320
320
310
310
300
3
3.5
4
4.5
5
5.5
VDD (V)
300
-40
75
75
50
50
25
25
VOS (PV)
100
0
-25
-50
-50
-75
-75
-100
4
5
4.5
VDD (V)
5
5.5
-100
-40
D027
Figure 6-15. Input Offset Voltage vs Supply Voltage
20 35 50 65
Temperature (°C)
80
95
110 125
D012
Device 1
Device 2
Device 3
0
-25
3.5
-10
Figure 6-14. Output Bandwidth vs Temperature
100
3
-25
D011
Figure 6-13. Output Bandwidth vs Supply Voltage
VOS (PV)
10
D007
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D026
Figure 6-16. Input Offset Voltage vs Temperature
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6.13 Typical Characteristics (continued)
0.3
0.3
0.2
0.2
0.1
0.1
EG (%)
EG (%)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
0
0
-0.1
-0.1
-0.2
-0.2
-0.3
3
3.5
4
4.5
5
-0.3
-40
5.5
VDD (V)
Device 1
Device 2
Device 3
Figure 6-17. Gain Error vs Supply Voltage
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D021
Figure 6-18. Gain Error vs Temperature
0.03
0.03
0.02
0.02
0.01
0.01
Nonlinearity (%)
Nonlinearity (%)
-25
D020
0
-0.01
0
-0.01
-0.02
-0.02
-0.03
-250 -200 -150 -100 -50
0
50 100 150
Differential Input Voltage (mV)
-0.03
200
250
3
3.5
4
4.5
5
VDD (V)
D029
D001
D024
Figure 6-19. Nonlinearity vs Input Voltage
5.5
D028
Figure 6-20. Nonlinearity vs Supply Voltage
80
0.03
Device 1
Device 2
Device 3
0.02
75
SNR (dB)
Nonlinearity (%)
70
0.01
0
-0.01
65
60
55
50
-0.02
45
-0.03
-40
40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
0
D030
50
100
150
200
|VINP - VINN| (mV)
250
300
D032
VIN = 0.5 Vpp, fIN = 10 kHz
Figure 6-21. Nonlinearity vs Temperature
14
Figure 6-22. Signal-to-Noise Ratio vs Input Voltage
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6.13 Typical Characteristics (continued)
80
80
77.5
77.5
75
75
72.5
72.5
SNR (dB)
SNR (dB)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
70
67.5
70
67.5
65
65
62.5
62.5
60
3
3.5
4
4.5
5
60
-40
5.5
VDD (V)
Device 1
Device 2
Device 3
-25
VIN = 0.5 Vpp, fIN = 10 kHz
-75
-75
-80
-80
THD (dB)
THD (dB)
-70
-85
-90
-95
-95
-100
-40
-100
4.5
80
95
110 125
D035
-85
-90
4
20 35 50 65
Temperature (°C)
Figure 6-24. Signal-to-Noise Ratio vs Temperature
-70
3.5
5
VIN = 0.5 Vpp, fIN = 10 kHz
Figure 6-23. Signal-to-Noise Ratio vs Supply Voltage
3
-10
D034
5
5.5
VDD (V)
Device 1
Device 2
Device 3
-25
-10
D056
Figure 6-25. Total Harmonic Distortion vs Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
D059
Figure 6-26. Total Harmonic Distortion vs Temperature
0
10000
-40
1000
CMRR (dB)
Noise Density (nV/—Hz)
-20
-60
-80
100
-100
10
0.01
0.1
1
10
Frequency (kHz)
100
1000
-120
0.001
D017
Figure 6-27. Input-Referred Noise Density vs Frequency
0.01
0.1
1
fIN (kHz)
10
100
1000
D038
Figure 6-28. Common-Mode Rejection Ratio vs Input Frequency
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
-70
0
-75
-20
-40
-85
PSRR (dB)
CMRR (dB)
-80
-90
-95
-60
-80
-100
-100
-105
-110
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-120
0.01
110 125
32.5
32.5
30
30
27.5
100
1000
D041
27.5
25
25
22.5
-40
22.5
3
3.5
4
4.5
5
5.5
VDD (V)
-25
-10
D043
5
20 35 50 65
Temperature (°C)
80
95
110 125
D044
Figure 6-32. Supply Current vs Temperature
Figure 6-31. Supply Current vs Supply Voltage
3.4
4
3.35
3.5
3.3
3
3.25
2.5
tr / tf (Ps)
VHLDO_OUT (V)
1
10
Ripple Frequency (kHz)
Figure 6-30. Power-Supply Rejection Ratio vs Ripple Frequency
IDD (mA)
IDD (mA)
Figure 6-29. Common-Mode Rejection Ratio vs Temperature
3.2
3.15
2
1.5
3.1
1
3.05
0.5
3
3
3.5
4
4.5
5
5.5
VDD (V)
0
3
3.5
4
4.5
VDD (V)
D046
Figure 6-33. High-Side LDO Line Regulation
16
0.1
D039
5
5.5
D065
Figure 6-34. Output Rise and Fall time vs Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
4
3.8
3.5
3.4
3
Signal Delay (Ps)
3
tr/tf (Ps)
2.5
2
1.5
1
2.6
2.2
1.8
1.4
1
0.5
0
-40
50% - 90%
50% - 50%
50% - 10%
0.6
0.2
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
3
3.5
4
Figure 6-35. Output Rise and Fall Time vs Temperature
4.5
VDD (V)
D066
5
5.5
D067
Figure 6-36. VIN to VOUT Signal Delay vs Supply Voltage
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
Signal Delay (Ps)
3
2.6
2.2
1.8
1.4
1
0.6
0.2
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D068
Figure 6-37. VIN to VOUT Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC3301 is a fully differential, precision, isolated amplifier with a fully integrated DC/DC converter that
can supply the device from a single 3.3-V or 5-V voltage supply on the low-side. The input stage of the device
consists of a fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator
uses an internal voltage reference and clock generator to convert the analog input signal to a digital bitstream.
The drivers (termed TX in the Functional Block Diagram) transfer the output of the modulator across the isolation
barrier that separates the high-side and low-side voltage domains. As shown in the Functional Block Diagram,
the received bitstream and clock are synchronized and processed by a fourth-order analog filter on the low-side
and presented as a differential output of the device
The signal path is isolated by a double capacitive silicon dioxide (SiO2) insuation barrier, whereas power
isolation uses an on-chip transformer separated by a thin-film polymer as the insulating material.
7.2 Functional Block Diagram
DCDC_OUT
DCDC_IN
Resonator
And
Driver
Rectifier
DCDC_HGND
HLDO_IN
AMC3301
Isolation Barrier
NC
Diagnostics
LDO
DIAG
LDO_OUT
LDO
HLDO_OUT
VDD
Analog Filter
HGND
TX / RX
û Modulator
RX / TX
INP
INN
DCDC_GND
OUTP
OUTN
GND
7.3 Feature Description
7.3.1 Analog Input
The differential amplifier input stage of the AMC3301 feeds a second-order, switched-capacitor, feed-forward
ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential input
impedance of RIND. The modulator converts the analog signal into a bitstream that is transferred across the
isolation barrier, as described in the Data Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signals (INP and INN). First, if the input voltages VINP or VINN
exceed the range specified in the Absolute Maximum Ratings table, the input current must be limited to the
absolute maximum value, because the device input electrostatic discharge (ESD) diodes turns on. In addition,
the linearity and parametric performance of the device are ensured only when the analog input voltage remains
within linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the
Recommended Operating Conditions table.
18
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7.3.2 Data Isolation Channel Signal Transmission
The AMC3301 uses an on-off keying (OOK) modulation scheme, as shown in Figure 7-1, to transmit the
modulator output bitstream across the capacitive SiO2-based isolation barrier. The transmit driver (TX) shown
in the Functional Block Diagram transmits an internally generated, high-frequency carrier across the isolation
barrier to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of
the carrier used inside the AMC3301 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and produces
the output. The AMC3301 transmission channel is optimized to achieve the highest level of common-mode
transient immunity (CMTI) and lowest level of radiated emissions caused by the high-frequency carrier and
RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
Figure 7-1. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC3301 offers a differential analog output comprised of the OUTP and OUTN pins. For differential input
voltages (VINP – VINN) in the range from –250 mV to +250 mV, the device provides a linear response with a
nominal gain of 8.2. For example, for a differential input voltage of 250 mV, the differential output voltage (VOUTP
– VOUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output voltage
VCMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater than
250 mV but less than 320 mV, the differential output voltage continues to increase in magnitude but with reduced
linearity performance. The outputs saturate at a differential output voltage of VCLIPout as shown in Figure 7-2 if
the differential input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping)
Linear input range (VFSR)
VOUTN
VFAILSAFE
VCLIPout
VCMout
VOUTP
± 320 mV
± 250 mV
0
320 mV
250 mV
Differential Input Voltage (VINP ± VINN)
Figure 7-2. Output Behavior of the AMC3301
The AMC3301 provides a fail-safe output that simplifies diagnostics on system level. Figure 7-2 shows the
fail-safe mode, in which the AMC3301 outputs a negative differential output voltage that does not occur under
normal operating conditions. The fail-safe output is active in two cases:
• The low-side does not receive data from the high-side (for example, because of a loss of power on the high
side).
• The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop
below their respective undervoltage detection thresholds (brown-out).
Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for the
fail-safe detection on the system level.
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7.3.4 Isolated DC/DC Converter
The AMC3301 offers a fully integrated isolated DC/DC converter that includes the following components as
illustrated in the Functional Block Diagram:
• Low-dropout regulator (LDO) on the low-side to stabilize the supply voltage VDD that drives the low-side of
the converter. This circuit does not output a constant voltage and is not intended for driving any external load.
• Low-side full-bridge inverter and drivers
• Laminate-based, air-core transformer for high-immunity to magnetic fields
• High-side full-bridge rectifier
• High-side LDO to stabilize the output voltage of the DC/DC converter for high analog performance of the
signal path. The high-side LDO outputs a constant voltage and can provide a limited amount of current to
power external circuitry.
The DC/DC converter uses a spread-spectrum clock generation technique to reduce the spectral density of
the electromagnetic radiation. The resonator frequency is synchronized to the operation of the ΔΣ modulator to
minimize the interference with data transmission and support the high analog performance of the device.
The architecture of the DC/DC converter is optimized to drive the high-side circuitry of the AMC3301 and can
source up to IH of additional DC current for an optional auxiliary circuit such as an active filter, preamplifier, or
comparator. IH is specified in the Electrical Characteristics table as a DC, non-switching current.
7.3.5 Diagnostic Output
The open-drain DIAG pin can be monitored to confirm the device is operational and the output voltage is valid.
As shown in Figure 7-3, during power-up, the DIAG pin is actively held low until the high-side supply is in
regulation and the device operates properly. During normal operation, the DIAG pin is in high-impedance (Hi-Z)
state and is pulled high through an external pullup resistor. The DIAG pin is actively pulled low if:
•
•
The low-side does not receive data from the high-side (for example, because of a loss of power on the high
side). In this case, the amplifier outputs are driven to the VFAILSAFE value that is shown in Figure 7-2.
The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop
below their respective undervoltage detection thresholds (brown-out). In this case, the low-side may still
receive data from the high-side but the data may not be valid. The amplifier outputs are driven to the
VFAILSAFE value that is shown in Figure 7-2.
DIAG
Power-up
Normal
Operation
High-side supply undervoltage
Normal
Operation
Figure 7-3. DIAG Output Under Different Operating Conditions
During normal operation, the DIAG pin is in a high-impedance state. Connect the DIAG pin to a pullup resistor or
leave open if not used.
7.4 Device Functional Modes
The AMC3301 is operational when the power supply VDD is applied, as specified in the Recommended
Operating Conditions table.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The low input voltage range, low nonlinearity, and low temperature drift make the AMC3301 a high-performance
solution for industrial applications where shunt-based current sensing with high common-mode voltage levels is
required.
8.2 Typical Application
The AMC3301 is ideally suited for shunt-based current sensing applications where accurate current monitoring is
required in the presence of high common-mode voltages. The AMC3301 integrates an isolated power supply for
the high-voltage side and therefore makes the device particularly easy to use in applications that do not have a
high-side supply readily available or where a high-side supply is referenced to a different ground potential than
the signal to be measured.
Figure 8-1 shows a simplified schematic of the AMC3301 in a solar inverter where the phase current is
measured on the grid-side of an LCL filter. Although the system offers a supply for the high-side gate driver,
there is a large common-mode voltage between the gate driver supply ground reference and the shunt resistor
on the other side of the LCL filter. Therefore, the gate driver supply is not suitable for powering the high-side
of an isolated amplifier that measures the voltage across the shunt. The integrated isolated power supply of the
AMC3301 solves that problem and enables current sensing at locations that is optimal for the system.
The diagram also shows the AMC3330 being used for sensing the AC output voltage.
DC+
SW
N
HS Gate
Driver
Supply
PGND
SW
IPHASE
to grid (L1)
RSHUNT
PGND
RL11
LS Gate
Driver
Supply
RL1SNS
DC-
PGND
RL12
AMC3301
1 µF 1 nF
100 nF
DCDC_OUT
N
DCDC_IN
DCDC_HGND
DCDC_GND
HLDO_IN
47 NŸ
DIAG
to uC (optional)
100 nF
NC
LDO_OUT
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
10 Ÿ
VDD
3.3 V / 5 V supply
10 nF
INP
OUTP
ADS8363
INN
OUTN
16-Bit ADC
to MCU
10 Ÿ
HGND
GND
GND
AMC3330
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
DCDC_IN
DCDC_GND
47 NŸ
DIAG
to uC (optional)
100 nF
NC
LDO_OUT
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
VDD
3.3 V / 5 V supply
INP
OUTP
ADS8363
INN
OUTN
16-Bit ADC
HGND
to MCU
GND
GND
Figure 8-1. The AMC3301 in a Solar Inverter Application
22
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8.2.1 Design Requirements
Table 8-1 lists the parameters for this typical application.
Table 8-1. Design Requirements
PARAMETER
VALUE
Supply voltage
3.3 V or 5 V
Voltage drop across the shunt for a linear response (VSHUNT)
±250 mV (maximum)
8.2.2 Detailed Design Procedure
The AMC3301 requires a single 3.3-V or 5-V supply on its low-side. The high-side supply is internally generated
by an integrated DC/DC converter as explained in the Isolated DC/DC Converter section.
The ground reference (HGND) is derived from the terminal of the shunt resistor that is connected to the negative
input of the AMC3301 (INN). If a four-pin shunt is used, the inputs of the AMC3301 are connected to the inner
leads and HGND is connected to one of the outer shunt leads. To minimize offset and improve accuracy, set the
ground connection to a separate trace that connects directly to the shunt resistor rather than shorting HGND to
INN directly at the input to the device. See the Layout section for more details.
8.2.2.1 Shunt Resistor Sizing
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT .
Consider the following two restrictions to choose the proper value of the shunt resistor, RSHUNT:
•
•
The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range: |VSHUNT| ≤ |VFSR|
The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤ |VClipping|
8.2.2.2 Input Filter Design
TI recommends placing an RC filter in front of the isolated amplifier to improve signal-to-noise performance of
the signal path. Design the input filter such that:
•
•
•
The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency
(20 MHz) of the ΔΣ modulator
The input bias current does not generate significant voltage drop across the DC impedance of the input filter
The impedances measured from the analog inputs are equal
For most applications, the structure shown in Figure 8-2 achieves excellent performance.
AMC3301
DCDC_OUT
DCDC_HGND
DCDC_IN
DCDC_GND
HLDO_IN
NC
DIAG
LDO_OUT
RSHUNT
HLDO_OUT
10 Ÿ
VDD
10 nF
INP
OUTP
INN
OUTN
10 Ÿ
HGND
GND
Figure 8-2. Differential Input Filter
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8.2.2.3 Differential to Single-Ended Output Conversion
Figure 8-3 shows an example of a TLV6001 based signal conversion and filter circuit for systems using singleended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage
equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ and C1 = C2 = 330 pF yields good performance.
AMC3301
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
C1
LDO_OUT
HLDO_OUT
INP
R2
VDD
R1
OUTP
±
R3
INN
OUTN
HGND
C2
GND
ADC
+
To MCU
TLV6001
GND
R4
GND
VREF
GND
Figure 8-3. Connecting the AMC3301 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of successiveapproximation-register (SAR) ADCs, see the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest
Distortion and Noise reference guide and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power
reference guide, available for download at www.ti.com.
8.2.3 Application Curve
In frequency inverter applications, the power switches must be protected in case of an overcurrent condition.
To allow for fast powering off of the system, a low delay caused by the isolated amplifier is required. Figure
8-4 shows the typical full-scale step response of the AMC3301. Consider the delay of the required window
comparator and the MCU to calculate the overall response time of the system.
VOUTN
VOUTP
VIN
Figure 8-4. Step Response of the AMC3301
24
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8.2.4 What To Do and What Not To Do
Do not leave the analog inputs INP and INN of the AMC3301 unconnected (floating) when the device is powered
up. If the device inputs are left floating, the input bias current may drive the inputs to a positive value that
exceeds the operating common-mode input voltage and the output of the device is undetermined.
Connect the negative input (INN) to the high-side ground (HGND), either by a hard short or through a resistive
path. A DC current path between INN and HGND is required to define the input common-mode voltage. Take
care not to exceed the input common-mode range as specified in the Recommended Operating Conditions table.
For best accuracy, route the ground connection as a separate trace that connects directly to the shunt resistor
rather than shorting AGND to INN directly at the input to the device. See the Layout section for more details.
The high-side LDO can source a limited amount of current (IH) to power external circuitry. Take care not to
overload the high-side LDO.
The low-side LDO does not output a constant voltage and is not intended for powering any external circuitry. Do
not connect any external load to the HLDO_OUT pin.
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9 Power Supply Recommendations
The AMC3301 is powered from the low-side power supply (VDD) with a nominal value of 3.3 V or 5 V. TI
recommends a low-ESR decoupling capacitor of 1 nF (C8 in Figure 9-1) placed as close as possible to the VDD
pin, followed by a 1-µF capacitor (C9) to filter this power-supply path.
The low-side of the DC/DC converter is decoupled with a low-ESR 100-nF capacitor (C4) positioned close to
the device between the DCDC_IN and DCDC_GND pins. Use a 1-µF capacitor (C2) to decouple the high side
in addition to a low-ESR, 1-nF capacitor (C3) placed as close as possible to the device and connected to the
DCDC_OUT and DCDC_HGND pins.
For the high-side LDO, use low-ESR capacitors of 1-nF (C6), placed as close as possible to the AMC3301,
followed by a 100-nF decoupling capacitor (C5).
The ground reference for the high-side (HGND) is derived from the terminal of the shunt resistor which is
connected to the negative input (INN) of the device. For best DC accuracy, use a separate trace to make this
connection instead of shorting HGND to INN directly at the device input. The high-side DC/DC ground terminal
(DCDC_HGND) is shorted to HGND directly at the device pins.
AMC3301
C2 C3
1 µF 1 nF
DCDC_OUT
DCDC_HGND
C4
100 nF
DCDC_IN
DCDC_GND
R1
47 NŸ
C1 100 nF
HLDO_IN
I
RSHUNT
C5
C6
100 nF 1 nF
R2
10 Ÿ
C10
10 nF
NC
HLDO_OUT
DIAG
LDO_OUT
to uC (optional)
C8 C9
1 nF 1 µF
VDD
3.3 V / 5 V supply
INP
OUTP
to RC filter / ADC
INN
OUTN
to RC filter / ADC
R4 10 Ÿ
HGND
GND
Figure 9-1. Decoupling the AMC3301
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
Table 9-1 lists components suitable for use with the AMC3301. This list is not exhaustive. Other components
may exist that are equally suitable (or better), however these listed components have been validated during the
development of the AMC3301.
26
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Table 9-1. Recommended External Components
DESCRIPTION
PART NUMBER
MANUFACTURER
SIZE (EIA, L x W)
VDD
C8
1 nF ± 10%, X7R, 50 V
12065C102KAT2A
AVX
1206, 3.2 mm x 1.6 mm
C9
1 µF ± 10%, X7R, 25 V
12063C105KAT2A
AVX
1206, 3.2 mm x 1.6 mm
C0603C104K5RACAUTO
Kemet
0603, 1.6 mm x 0.8 mm
DC/DC CONVERTER
C4
100 nF ± 10%, X7R, 50 V
C3
1 nF ± 10%, X7R, 50 V
C0603C102K5RACTU
Kemet
0603, 1.6 mm x 0.8 mm
C2
1 µF ± 10%, X7R, 25 V
CGA3E1X7R1E105K080AC
TDK
0603, 1.6 mm x 0.8 mm
C1
100 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
Kemet
0603, 1.6 mm x 0.8 mm
C5
100 nF ± 5%, NP0, 50 V
C3216NP01H104J160AA
TDK
1206, 3.2 mm x 1.6 mm
C6
1 nF ± 10%, X7R, 50 V
12065C102KAT2A
AVX
1206, 3.2 mm x 1.6 mm
HLDO
10 Layout
10.1 Layout Guidelines
Figure 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors. The same
component reference designators are used as in the Power Supply Recommendations section. Decoupling
capacitors are placed as close as possible to the AMC3301 supply pins. For best performance, place the shunt
resistor close to the INP and INN inputs of the AMC3301 and keep the layout of both connections symmetrical.
To avoid causing errors in the measurement by the input bias currents of the AMC3301, connect the high-side
ground pin (HGND) to the INN-side of the shunt resistor. Use a separate trace in the layout to make this
connection to maintain equal currents in the INN and INP traces.
10.2 Layout Example
C4
C3
DIAG
To MCU I/O (optional)
R1
C1
C2
Clearance area, to be
kept free of any
conductive materials.
C9
C8
C6
INN
R4
C5
VDD
R2
C10
RSHUNT
AMC3301
INP
OUTP
OUTN
3.3-V or 5-V supply
To analog filter / ADC / MCU
To analog filter / ADC / MCU
GND
HGND
Top Metal
Inner or Bottom Layer Metal
Via
Figure 10-1. Recommended Layout of the AMC3301
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Texas Instruments, Isolation Glossary
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, AMC3330 Precision, ±1-V Input, Reinforced Isolated Amplifier data sheet
Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive
Systems data sheet
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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21-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AMC3301DWE
ACTIVE
SOIC
DWE
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC3301
AMC3301DWER
ACTIVE
SOIC
DWE
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC3301
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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