Freescale Semiconductor
Data Sheet: Product Preview
Document Number: SC33690DS
Rev. 5, 02/2007
MC33690
SOIC-20
MC33690 Standalone Tag
Reader Circuit
The standalone tag reader circuit (STARC) is an integrated
circuit dedicated to the automotive immobilizer applications.
It combines the antenna drivers and demodulator necessary to
interface with a transponder.
A low dropout voltage regulator and a physical interface fully
compatible with the ISO 9141 norm are also available.
The STARC is fabricated with the SMARTMOSTM3.5
technology. This process is a double layer metal 1.4µm
45V technology, combining CMOS and bipolar devices.
• Contactless 125 kHz tag reader module:
– Self synchronous sample and hold demodulator
– Amplitude or phase modulation detection
– High sensitivity
– Fast read after write demodulator settling time
– Low resistance and high current antenna drivers, 2W @
150mA (typ.)
– Bidirectionnal data transmission
– Multi-tag, multi-scheme operation
• Low dropout voltage regulator:
– Wide input supply voltage range from 5.5V up to 40V
– Output current capability up to 150mA DC with an
external power transistor
– 5V output voltage with a ±5% accuracy
– Low voltage reset function
– Low current consumption in standby mode:
– 300µA (typ.)
• ISO 9141 transmitter and receiver module:
– Input voltage thresholds ratiometric to the supply
voltage
– Current limitation
– Output slew rate control
– No external protection device required
Pin Connections
VSUP
1
20
Tx
SOURCE
2
19
Rx
GATE
3
18
K
TD1
4
17
AM
VSS
5
16
XTAL1
VDD
6
15
XTAL2
TD2
7
14
LVR
MODE1
8
13
DOUT
MODE2
9
12
CEXT
RD
10
11
AGND
ORDERING INFORMATION
Device
MC33690DW
MC33690DWE
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Operating
Junction
Temperature
Range
TJ = −40°C to
125°C
TJ = −40°C to
125°C
Package
SOIC 20
SOIC 20
(ROHS)
Table of Contents
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Tag Reader Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Read Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
ISO 9141 Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Communication Modes Description . . . . . . . . . . . . . . . . . . . . .9
Standalone Configuration with One-Wire Bus . . . . . . . . . . . .10
7.1 Timing Definitions for a 8 MHz Crystal . . . . . . . . . . . . .11
Standalone Configuration with Two-Wire Bus. . . . . . . . . . . . .12
Direct Connection to a Microcontroller Configuration . . . . . . .13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Tag Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ISO 9141 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . .19
Application Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
List of Figures
Figure 1. Standalone Tag Reader Circuit . . . . . . . . . . . . . . . . . . . 3
Figure 2. Tag Reader Block Diagram . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current Flow When Buffers are Switched Off . . . . . . . . 7
Figure 4. Voltage Regulator Block Diagram . . . . . . . . . . . . . . . . . 8
Figure 5. ISO 9141 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Mode Access Description in
One-Wire Bus Configuration . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Configuration A State Diagram . . . . . . . . . . . . . . . . . . 11
Figure 8. Modes Access Description in
Two-wire Bus Configuration . . . . . . . . . . . . . . . . . . . . .
Figure 9. Configuration B State Diagram . . . . . . . . . . . . . . . . . .
Figure 10.Configuration C State Diagram . . . . . . . . . . . . . . . . .
Figure 11.Low Voltage Reset Waveform . . . . . . . . . . . . . . . . . .
Figure 12.Demodulator Parameters Definition . . . . . . . . . . . . . .
Figure 13.VSUP, VDD, and Source Internal Circuits . . . . . . . . .
Figure 14.GATE Internal Circuits . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15.TD1, TD2, DOUT, and RX Internal Circuits . . . . . . . .
Figure 16.AGND Internal Circuits. . . . . . . . . . . . . . . . . . . . . . . .
Figure 17.CEXT Internal Circuits . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18.RD Internal Circuits . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19.MODE1, MODE2, and TX Internal Circuits . . . . . . . .
Figure 20.LVR Internal Circuits . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21.XTAL2 and XTAL1 Internal Circuits . . . . . . . . . . . . . .
Figure 22.AM Internal Circuits . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23.K Internal Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24.Standalone Configuration with One-Wire Bus . . . . . .
Figure 25.Standalone Configuration with Two-Wires Bus . . . . .
Figure 26.Direct Connection to a Microcontroller. . . . . . . . . . . .
12
12
13
15
17
19
19
19
20
20
20
20
21
21
22
22
23
24
25
List of Tables
Table 1. Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Communication Modes Description. . . . . . . . . . . . . . . 10
Table 5. Supply Current Specifications . . . . . . . . . . . . . . . . . . . 14
Table 6. Voltage Regulator Specifications . . . . . . . . . . . . . . . . . 14
Table 7. Low-Voltage Reset Specifications . . . . . . . . . . . . . . . . 15
Table 8. Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Tag Reader Specifications. . . . . . . . . . . . . . . . . . . . . . 16
Table 10.ISO 9141 Interface Specifications . . . . . . . . . . . . . . . . 17
Table 11.Digital I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . 18
MC33690 Standalone Tag Reader Circuit, Rev. 5
2
Freescale Semiconductor
Optional: External N channel MOS required for sourced current > 50mA.
A recommended reference is MMFT 3055VL from Freescale.
VBAT
VSUP
C1
GATE
SOURCE
VDD
Voltage Regulator
LVR
VDD
10mF
VSS
8 MHz
RA
TD1
XTAL1
LA
XTAL2
R1
RD
R2
CA
MODE1
Tag Reader
DOUT
TD2
CEXT
MODE2
AM
CEXT
VBAT
10nF
AGND
510W
Tx
ISO 9141 Interface
K
Rx
Figure 1. Standalone Tag Reader Circuit
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
3
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VSUP
VSS −0.3 to +40
V
Supply voltage without using the voltage regulator
(VSUP = VDD)
VDD
VSS −0.3 to +7
V
Voltage on SOURCE
—
VSS −0.3 to +40
V
Current into/from GATE
—
0
mA
Voltage on GATE
—
VSS −0.3
V
Voltage on pins:
MODE1/2, CEXT, DOUT, LVR, XTAL1/2, Rx, Tx
—
VSS −0.3 to VDD +0.3
V
Voltage on RD
—
±10
V
Voltage on K and AM
—
VSS −3 to 40
V
Current on TD1 and TD2
(Drivers on and off)
—
±300
mA
Voltage on AGND
—
VSS ±0.3
V
ESD voltage capability1
—
±2000
V
1
—
±200
V
Solder heat resistance test (10s)
—
260
°C
Junction temperature
TJ
170
°C
Storage temperature
Ts
−65 to +150
°C
ESD voltage capability
1
Human Body Model, AEC-Q100-002 Rev. C; Machine Model, AEC-Q100-003 Rev. E.
Table 2. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Rth
80
°C/W
Junction to ambient thermal resistance (SOIC20)
Table 3. Pin Function Descriptions
Pin
Function
1
VSUP
2
SOURCE
3
GATE
4
TD1
Antenna driver 1 output
5
VSS
Power and digital ground
6
VDD
Voltage regulator output
7
TD2
Antenna driver 2 output
8
MODE1
Mode selection input 1
9
MODE2
Mode selection input 2
10
RD
Description
Power supply
External N channel transistor source
External N channel transistor gate
Demodulator input
MC33690 Standalone Tag Reader Circuit, Rev. 5
4
Freescale Semiconductor
Description
Table 3. Pin Function Descriptions (continued)
11
AGND
Demodulator ground
12
CEXT
Comparator reference input
13
DOUT
Demodulator output (5V)
14
LVR
15
XTAL2
Oscillator output
16
XTAL1
Oscillator input
17
AM
18
K
ISO 9141 transmitter output and receiver input
19
Rx
ISO 9141 receiver monitor output
20
Tx
ISO 9141 transmitter input
1
Description
1.1
Tag Reader Module
Low Voltage Reset input/output
Amplitude modulation input
The tag reader module is dedicated for automotive or industrial applications where information has to be transmitted
contactless.The tag reader module is a write/read (challenge/response) controller for applications that a demand high security
level.
The tag reader module is connected to a serial-tuned LC circuit that generates a magnetic field power supplying the tag. The
use of a synchronous sample and hold technique allows communication with all available tags using admittance switching
producing absorption of the RF field.
Load amplitude or phase shift modulation can be detected at high bit rates up to 8 kHz. The typical operational carrier frequency
of the tag reader module with an 8 MHz clock is 125 kHz.
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
5
Read Function
AM Data
RA
TD1
1/32 counter
LA
4 MHz
125 kHz
Clock 8 MHz
1/2
8 MHz
Shutdown
125 kHz
Self synchronous
CA
Setup and Preload
sample and hold
LVR
TD2
Interface
11.25°, 22.5°, 33.75°, 45°, 56.25°, 67.5°, 78.75°, 90°
+0°, -11.25°, -22.5°, -33.75°, -45°, -56.25°, -67.5°, -78.75°
-
R1
+
VDD
500ns
Buffer
Comparator
+
+
RD
S/H
100KW
Buffer
D
-
Q
Data out
C
VDD
R2
500mA
AGND
CEXT
CEXT
10nF
Figure 2. Tag Reader Block Diagram
2
Read Function
When answering to the base station, a transponder generates an absorption modulation of the magnetic field. It results in an
amplitude/phase modulation of the current across the antenna. This information is picked up at the antenna tap point between
the coil and the capacitor. An external resistive ladder down scales this voltage to a level compatible with the demodulator input
voltage range (see Section 15, “Tag Reader”).
The demodulator (see Figure 2) consists of:
•
•
•
•
an input stage (emitter follower)
a sample and hold circuit
a voltage follower
a low offset voltage comparator
The sampling time is automatically set to take into account a phase shift due to the tolerances of the antenna components (L and
C) and of the oscillator. The allowed phase shift measured at the input RD ranges from −45° to +45°. Assuming that the phase
MC33690 Standalone Tag Reader Circuit, Rev. 5
6
Freescale Semiconductor
Write Function
reference is the falling edge of the driving signal TD1, this leads to a sampling time phase ranging from −78.75° to 90° with
discrete steps of 11.25°. After reset condition, the sampling time phase is +11.25°.
The antenna phase shift evaluation is only done after each wake-up command or after reset. This is necessary to obtain the best
demodulator performances.
To ensure a fast demodulator settling time after wake-up, reset, or a write sequence, the external capacitor CEXT is preloaded
at its working voltage. This preset occurs 256µs after switching the antenna drivers on and its duration is 128µs. After wake-up
or reset, the preset has the same duration, but begins 518µs after clock settling. After power on reset, VSUP must meet the
minimum specified value, enabling the nominal operation of VDD, before the start of the preset. Otherwise, the preset must be
done through a standby/wake-up sequence.
3
Write Function
Whatever the selected configuration (see Section 6, “Communication Modes Description”), the write function is achieved by
switching on/off the output drivers TD1/2. After the drivers have been set in high impedance, the load current flows alternatively
through the internal diodes to VSS and to VDD (see Figure 3).
VDD
RA
TD1
ILOAD
LA
R1
VDD
CA
TD2
Figure 3. Current Flow When Buffers are Switched Off
4
Voltage Regulator
The low dropout voltage regulator provides a regulated 5V supply for the internal circuitry. It can also supply external
peripherals or sensors. The input supply voltage ranges from 5.5V to over 40V.
This voltage regulator uses a series combination of high voltage LDMOS and low voltage PMOS transistors to provide
regulation. An external low ESR capacitor is required for the regulator stability.
The maximum average current is limited by the power dissipation capability of the SO 20 package. This limitation can be
overcome by connecting an external N channel MOS parallel with the internal LDMOS. The threshold voltage of this transistor
must be lower than the one of the internal LDMOS (1.95V typ.) to prevent the current from flowing into the LDMOS. Its
breakdown voltage must be higher than the maximum supply voltage.
A low-voltage reset function monitors the VDD output. An internal 10µA pull-up current source allows, when an external
capacitor is connected between LVR and GND, to generate delays at power up (5ms typ. with CReset=22nF). The LVR pin is
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
7
ISO 9141 Physical Interface
also the input generating the internal reset signal. Applying a logic low level on this pin resets the circuit, all the internal flip
flops are reset, and drivers TD1/2 are switched on.
VBAT
VSUP
GATE
C1
Charge pump
1 MHz oscillator
N channel
LDMOS
SOURCE
Voltage reference
-
and biasing
+
generator
VDD
P channel
MOS
VDD
10mA
LVR
VDD
VDD
C2
C3
10mF 100nF
reset
CReset
Comparator
+
Figure 4. Voltage Regulator Block Diagram
5
ISO 9141 Physical Interface
This interface module is fully compatible with the ISO 9141 norm describing the diagnosis line. It includes one transmitter
(pin K) and two receivers (pins K and AM).
The input stages consist of high-voltage CMOS triggers. The thresholds are ratiometric to VSUP. A ground referenced current
source (2.5µA typ.) pulls down the input when unconnected.
When a negative voltage is applied on the K or AM lines, the input current is internally limited by a 2kΩ resistor (typ.) in series
with a diode.
A current limitation allows the transmitter to drive any capacitive load and protects against short circuit to the battery voltage.
An overtemperature protection shuts the driver down when the junction temperature exceeds 150°C (typ). After shutdown by
the overtemperature protection, the driver can be switched on again if the junction temperature has decreased below the
threshold and by applying an off/on command, coming from the demodulator in configurations A and B, or directly applied on
the input Tx in configuration C (see Table 4).
The electromagnetic emission is reduced because of the voltage slew rate control (5V/µs typ.).
MC33690 Standalone Tag Reader Circuit, Rev. 5
8
Freescale Semiconductor
Communication Modes Description
VDD
L line
2kW
AM data
AM
VSUP
GND
From configuration controller
2.5mA
GND
VSUP
VDD
2kW
Rx
2.5mA
GND
GND
From configuration controller
VBAT
Over temperature
detector
K line
Tag reader module output
K
VDD
Command
Tx
Current limitation
Figure 5. ISO 9141 Interface
6
Communication Modes Description
The STARC offers three different communication modes. Therefore, it can be used as a standalone circuit connected to an
electronic control unit (ECU) through a bus line or it can be directly connected to a microcontroller in case of a single board
architecture.
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
9
Standalone Configuration with One-Wire Bus
Table 4. Communication Modes Description
Configuration
Configuration Pins
Pin Status Function Description
7
Type
Bus Type
Name
Mode1
Mode2
Standalone
1 wire (VBAT)
A
0
0
K output/input:
• demodulator output
• amplitude modulation input
• shutdown/wake-up
AM must be connected to VSUP
DOUT forces a low level
2 wires (VBAT)
B
0
1
K output:
• demodulator output
AM input:
• amplitude modulation input
• shutdown/wake-up
DOUT forces a low level
2 wires (VDD)
Direct
Connection to
a MCU
C
1
x
DOUT output:
• demodulator output
AM input:
• amplitude modulation input
MODE2 input:
• shutdown/wake-up
1
K output/input (standalone ISO 9141 interface):
• driven by Tx and monitored by Rx
0
K input (standalone ISO 9141 interface):
• monitored by Rx
• Tx disabled
Standalone Configuration with One-Wire Bus
When a low level is applied on pins MODE1 and MODE2, the circuit is in configuration A (see Figure 24). After power on, the
circuit is set into read mode. The demodulator output is directly routed to the ISO 9141 interface output K.
The circuit can be set into write mode at anytime by violation of all possible patterns on the single wire bus during more than
1ms. Then, the K line achieves the amplitude modulation by switching on/off both antenna drivers.
After 1ms of inactivity at the end of the challenge phase (bus in idle recessive one state), the circuit is set back into read mode.
The circuit can be put into standby mode by forcing the K line at zero during more than 2 ms after entering the write mode.
After the K line is released, the circuit sends an acknowledge pulse before entering into standby mode. In standby mode, the
oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader, ISO 9141 driver) are
inactive except the voltage regulator and the ISO 9141 receiver on pin K. The driver output TD1 forces a low level and TD2
forces a high level. A rising edge on K wakes up the circuit. After completion of the wake-up sequence, the circuit is
automatically set in read mode.
In configuration A, DOUT and Rx outputs always force a low level and Tx is disabled.
MC33690 Standalone Tag Reader Circuit, Rev. 5
10
Freescale Semiconductor
Standalone Configuration with One-Wire Bus
Read to write mode:
T0 £ t < T 0 ’+T 1 ’
K line
1
1
1
0
read mode
0
0
write mode
Write to read mode:
K line
t ŠT0
read mode
write mode
Write to standby mode:
T2
T2
t Š T1
K line
standby mode
acknowledge
write mode
Standby mode to read mode:
K line
wake-up sequence
standby mode
read mode
Figure 6. Mode Access Description in One-Wire Bus Configuration
T 0 £ K line low
Write
Reset
Read
TD1/2 off
K line high < T 0 ’
K line low
T 0 £ K line high
write
TD1/2
switching
T 1 £ K line low
Wake-up
K
Standby
Figure 7. Configuration A State Diagram
7.1
Timing Definitions for a 8 MHz Crystal
The timing definitions for a 8 MHz crystal are:
•
•
•
•
•
•
Tref is crystal oscillator period (125 ns typ.)
T0=8064.Tref = 1.008ms typ.
T0’=7932.Tref = 0.992ms typ.
T1=16256.Tref = 2.032ms typ.
T1’=16128.Tref = 2.016ms typ.
T2=4096.Tref, = 512µs typ.
T0 is the minimum time required to guarantee the device toggles from read to write (or from write to read). However, the STARC
may toggle from read to write (or from write to read) between T0 and T0’.
T1 is the minimum time required to guarantee the device toggles from write to standby. However, the STARC may toggle in
standby between T1 and T1’.
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
11
Standalone Configuration with Two-Wire Bus
8
Standalone Configuration with Two-Wire Bus
When a low level is applied on MODE1 and a high level on MODE2, the circuit is in configuration B (see Figure 25). The K
pin is set as an output sending the demodulated data.
The AM pin is set as a VSUP referenced input pin receiving the amplitude modulation and the shutdown/wake-up commands.
Forcing high and low levels on AM achieves the amplitude modulation by switching on/off both antenna drivers. This amplitude
modulation can be monitored on the K output and allows antenna short and open circuit diagnosis. The circuit can be put into
standby mode by forcing the AM line at zero during more than 2 ms. The circuit sends an acknowledge pulse before entering
into standby mode.
In standby mode, the oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader
and ISO 9141 driver) are inactive except for the voltage regulator and the ISO 9141 receiver on pin AM. The driver output TD1
forces a low level and TD2 a high level. A rising edge on AM wakes up the circuit. After completion of the wake-up sequence,
the circuit is automatically set in read mode.
In configuration B, DOUT and Rx outputs always force a low level and Tx is disabled.
Read and write sequences:
drivers on
data write modulation
drivers off
AM line
1
1
1
1
1
0
data write
data read
K line
0
0
0
0
AM line monitoring
Entering into standby mode:
AM line
1
0
t Š T1
standby mode
acknowledge
T1
K line
T2
T2
Coming out of standby mode:
AM line
standby mode
wake-up sequence
data read
K line
Figure 8. Modes Access Description in Two-wire Bus Configuration
Reset
TD1/2
switching
AM line low
AM line high
AM line high
TD1/2 off
Wake-up
AM line low
T1 £ AM line low
AM
Standby
Figure 9. Configuration B State Diagram
MC33690 Standalone Tag Reader Circuit, Rev. 5
12
Freescale Semiconductor
Direct Connection to a Microcontroller Configuration
9
Direct Connection to a Microcontroller Configuration
When a high level is applied on MODE1, the circuit is in configuration C (see Figure 26). The demodulated data are sent
through DOUT.
The AM pin is set as a VDD referenced input pin receiving the AM command. Forcing high and low levels on AM achieves the
amplitude modulation by switching on/off both antenna drivers. Meanwhile, this amplitude modulation can be monitored on
DOUT. This allows antenna short and open circuit diagnosis.
The circuit can be put into standby mode by applying a low level on the MODE2 pin. In standby mode, the oscillator and most
of the internal biasing currents are switched off. Therefore, the functions (tag reader and ISO 9141 interface) are inactive except
for the voltage regulator. The driver outputs TD1 and TD2 are frozen in their state (high or low level) before entering into
standby mode. DOUT forces a low level.
The ISO 9141 interface K is standalone and can be directly controlled by the input pin Tx and monitored by the output Rx.
Applying a logic high level on Tx switches the output driver K on (dominant zero state when an external pull-up resistor is
connected between K and VBAT). Applying a logic low level turns the driver off (one recessive state).
Rx monitors the voltage at the K pin. When the voltage is below the low threshold voltage, Rx forces a logic low level. When
the voltage is above the high threshold voltage, Rx forces a logic high level.
In standby mode, Tx is disabled and Rx output monitors the voltage at the K pin.
Reset
TD1/2
switching
AM low
AM high
AM high
TD1/2 off
Wake-up
AM low
mode2 low
mode2 low
mode2 high
Standby
Figure 10. Configuration C State Diagram
10
Electrical Characteristics
Typical values reflect average measurements at VSUP=12V and TJ=25°C.
11
Supply Current
Typical values reflect average measurements at 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted.
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
13
Voltage Regulator
Table 5. Supply Current Specifications
Parameter
Symbol
Test Conditions
and Comments
Min
Typ
Max
Unit
Type
Pin VSUP
9.1
Standby mode current
ISUP1
—
—
300
500
μA
—
9.2
Operating mode current
ISUP2
Circuit in configuration C
No current sunk from VDD
Drivers TD1/2 switched off
Tx forced to low
—
1.5
2.5
mA
—
12
Voltage Regulator
Typical values reflect average measurements at 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted
Table 6. Voltage Regulator Specifications
Parameter
Symbol
Test Conditions
and Comments
Min
Typ
Max
Unit
Type
Without external MOS
transistor, IOUT ≤ 50mA
4.75
5.0
5.25
V
—
—
—
50
mA
—
VLoadReg1
Without external MOS
transistor, 1 to 50mA IOUT
change
—
20
60
mV
—
1.9 Output Voltage (5.5V ≤ VSUP ≤ 40V)
VVDD2
4.7
5.0
5.3
V
—
1.11 Total Output Current
IVDD2
With external MOS transistor,
IOUT ≤ 150mA
—
—
150
mA
—
—
65
150
mV
—
—
—
—
mV
—
Pins VSUP and VDD
1.1 Output Voltage (5.5V ≤ VSUP ≤ 40V)
VVDD1
1.3 Total Output Current
IVDD1
1.5 Load Regulation
The stability is ensured with a
decoupling capacitor between
VDD and VSS: COUT ≥ 10μF
with ESR ≤ 3Ω.
The current capability can be
increased up to 150mA by
using an external N channel
MOS transistor (see Figure 1).
The main characteristics for
choosing this component are
VT < 1.8V and BVDSS > 40V
1.6 Load Regulation
VLoadReg2 With external MOS transistor,1
to 150mA IOUT change
1.4 Line Regulation (6V ≤ VSUP ≤ 16V)
13
VLineReg
IOUT = 1mA
Low-Voltage Reset
Typical values reflect average measurements at 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted
MC33690 Standalone Tag Reader Circuit, Rev. 5
14
Freescale Semiconductor
Oscillator
Table 7. Low-Voltage Reset Specifications
Parameter
Symbol
Test Conditions
and Comments
Min
Typ
Max
Unit
Type
Because the voltage regulator
and the low-voltage reset are
using the same internal voltage
reference, the low-voltage reset
occurs only when the voltage
regulator is out of regulation.
See Figure 11
4.1
4.35
4.6
V
—
50
100
150
mV
—
Pin LVR
1.6 Low Voltage Reset Low Threshold
VLVRON
1.7 Low Voltage Reset Hysteresis
VLVRH
1.12 Pull-up Current
ILVRUP
VLVR = 2.5V
5
10
15
μA
—
RLVR
VLVR = 2.5V
200
370
500
Ω
—
1.14 Input Low Voltage
VILLVR
—
0
—
0.3 x
VDD
V
—
1.15 Input High Voltage
VIHLVR
—
0.7 x
VDD
—
VDD
V
—
1.13 Output Resistance in reset condition
VDD
VLVRON + VLVRH
VLVRON
LVR
Figure 11. Low Voltage Reset Waveform
14
Oscillator
Typical values reflect average measurements at 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted
Table 8. Oscillator Specifications
Characteristic
Symbol
Test Condition
and Comments
Min
Typ
Max
Unit
Type
Pins XTAL1, XTAL2
8.0 Input Capacitance
8.1 Voltage gain VXTAL2 / VXTAL1
8.3 Clock input level
CXTAL1
VXTAL1 = 2.5V
—
5
—
pF
—
AOSC
VXTAL1 = 2.5V
—
25
—
—
—
VXTAL1
This level ensures the circuit
operation with an 8 MHz clock.
It is applied through a
capacitive coupling. A 1MΩ
resistor connected between
XTAL1 and XTAL2 biases the
oscillator input.
1.5
—
VDD
Vpp
—
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
15
Tag Reader
15
Tag Reader
Typical values reflect average measurements at 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted
Table 9. Tag Reader Specifications
Parameter
Symbol
Test Conditions
and Comments
Min
Typ
Max
Unit
Type
Demodulator (pin RD)
2.0
Input Voltage Range
VINRD
—
3
4
5
V
—
2.2
Input Modulation Frequency
FMOD
—
0.5
4
8
kHz
—
2.3
Demodulator Sensitivity
VSENSE1
6.5V ≤ VSUP ≤ 16V
Sensitivity is measured in the
following application
conditions: IANTENNA = 50mA
peak, VRD = 4V peak,
CEXT = 10nF, and square wave
modulation FMOD = FTD1/32.
See Figure 12
—
5
15
mV
—
2.31 Demodulator Sensitivity
VSENSE2
6V ≤ VSUP < 6.5V
The sensitivity is measured in
the following application
conditions:
IANTENNA = 50mA peak,
VRD = 4V peak, CEXT = 10nF,
and square wave modulation
FMOD = FTD1/32
See Figure 12
—
7
30
mV
—
2.4
Demodulation Delay
tDemod
Configuration C
Not including the delay due to
the slew rate of the K output for
configurations A and B
See figure 12
—
7.5
10
μs
—
2.5
After Write Pulse Settling Time
tSettling1
—
—
394
400
μs
—
2.6
Recovery Time after wake-up or
reset from clock stable to
demodulator valid output
tSettling2
Clock stable condition implies
VXTAL1 meets the specification
(see page 15).
—
646
700
μs
—
—
—
64
—
—
—
Drivers (pins TD1, TD2)
3.5
Output Carrier Frequency to Crystal
Frequency Ratio
RFTD/FXT
AL
3.0 Turn on/off Delay
ton/off
—
—
—
250
ns
—
3.1 Driver1/2 Low Side Out. Resistance
RTDL
ILOAD = 150mA DC
—
2.4
4
Ω
—
3.2 Driver1/2 High Side Out. Resistance
RTDH
ILOAD = -150mA DC
—
2.1
4
Ω
—
MC33690 Standalone Tag Reader Circuit, Rev. 5
16
Freescale Semiconductor
ISO 9141 Interface
VRD
VSENSE
Demodulator
output (K or DOUT)
tDemod
Figure 12. Demodulator Parameters Definition
16
ISO 9141 Interface
Typical values reflect average measurements at 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted
Table 10. ISO 9141 Interface Specifications
Parameter
Symbol
Test Conditions
and Comments
Min
Typ
Max
Unit
Type
Receiver (pins K and AM)
4.0 Input Low Voltage
VIL
—
—
—
0.3 x
VSUP
V
—
4.1 Input High Voltage
VIH
—
0.65 x
VSUP
—
40
V
—
VHY1
—
0.4
0.65
1.3
V
—
IB
0V ≤ VIN ≤ 16V
1
3
5
μA
—
4.31 Input Current
IBM
-3 ≤ VIN < 0
−2
−1
—
mA
—
4.4 K to Rx delay
tdkrx
—
2
10
μs
—
3.5
5
6.5
V/μs
—
3.5
5
6.5
V/μs
—
−1
0
1
V/μs
—
4.2 Input Hysteresis Voltage
4.3 Biasing Current
Driver (pin K)
5.0
Output Falling Edge Slew Rate
SRF
5.1
Output Rising Edge Slew Rate
SRR
Rise Fall Slew Rates Symmetry
SRSYMET
5.2
RPull-up = 510Ω,
Calculated from 20% to 80% of
the output swing.
RY
VOLK
ILOAD = 25mA
—
1.1
1.4
V
—
Input Current
(driver switched on or off)
IIK
−3V ≤ VIN ≤ 0V
−2
—
0
mA
—
5.5
Current Limitation Threshold
IL
0V ≤ VIN ≤ 40V
35
50
65
mA
—
5.6
Thermal Shutdown Threshold
THSDWN
—
130
150
170
°C
—
5.3
Output Low Voltage
5.4
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
17
Digital I/O
17
Digital I/O
Typical values reflect average measurements at 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted
Table 11. Digital I/O Specifications
Characteristic
Symbol
Test Condition
and Comments
Min
Typ
Max
Unit
Type
Input (pins MODE1, MODE2, AM, TX)
6.0 Input Low Voltage
VILD
—
0
—
0.3 x
VDD
V
—
6.1 Input High Voltage
VIHD
—
0.7 x
VDD
—
VDD
V
—
6.2 Input Hysteresis Voltage
VHD
—
.24
.7
1
V
—
Output (pins DOUT,RX)
7.0 Output Low Voltage
VOL
ILOAD = 500uA
0
0.5
0.2 x
VDD
V
—
7.1 Output High Voltage
VOH
ILOAD = -500uA
0.8 x
VDD
4.6
VDD
V
—
7.2 Fall/Rise Time
tF/R
CLOAD=10pF,
Calculated from 10% to 90% of
the output swing
—
—
150
ns
—
MC33690 Standalone Tag Reader Circuit, Rev. 5
18
Freescale Semiconductor
Pin Definition and Function
18
Pin Definition and Function
The internal circuits connected to the pins of the device are shown in Figures 13 – 23, including the diodes used for ESD
protection.
1
VSUP
40V
6V
VDD
6
VDD
16V
2
SOURCE
16V
Figure 13. VSUP, VDD, and Source Internal Circuits
2k
30k
GATE
9V
16V
Figure 14. GATE Internal Circuits
VDD
4
TD1
16V
7
TD2
idem
13
DOUT
19
RX
Figure 15. TD1, TD2, DOUT, and RX Internal Circuits
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
19
Pin Definition and Function
VSS
8
AGND
Figure 16. AGND Internal Circuits
500µA
9
CEXT
16V
Figure 17. CEXT Internal Circuits
VDD
2k
10
RD
16V
10V
200µA
16V
10V
Figure 18. RD Internal Circuits
VDD
2k
12
MODE1
16V
13
MODE2
11V
idem
20
TX
Figure 19. MODE1, MODE2, and TX Internal Circuits
MC33690 Standalone Tag Reader Circuit, Rev. 5
20
Freescale Semiconductor
Pin Definition and Function
VDD
2k
14
LVR
16V
11V
VDD
10µA
200
Figure 20. LVR Internal Circuits
15
VDD
XTAL2
2k
16
XTAL1
200
16V
11V
Figure 21. XTAL2 and XTAL1 Internal Circuits
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
21
Pin Definition and Function
VSUP
VSUP
22V
22V
2k
VDD
17
AM
40V
40V
2µA
16V
22V
Figure 22. AM Internal Circuits
VSUP
2k
18
K
40V
40V
16V
22V
2µA
1k
Figure 23. K Internal Circuits
MC33690 Standalone Tag Reader Circuit, Rev. 5
22
Freescale Semiconductor
Application Schemes
19
Application Schemes
VBAT
VSUP
C1
NC
GATE
NC
SOURCE
C2
VSS
NC
C3
LVR
VSS
XTAL1
TD1
XTAL2 1MW
8.2pF
10mF 100nF
RA
LA
VDD
R1
RD
R2
CA
TD2
STARC
8 MHz
8.2pF
MODE1
MODE2
NC
CEXT
CEXT
10nF
AGND
Tx
DOUT VSUP
AM
VBAT
510W
K
NC
Rx
Note: If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and
SOURCE must be left unconnected. In this configuration, the outputs Rx and DOUT force a low level. C1 is not
required for the STARC functionality and only acts as a reservoir of energy. To preserve the demodulator sensitivity,
CEXT and R2 should be connected to AGND and VSS connected to AGND using a low resistance path.
Figure 24. Standalone Configuration with One-Wire Bus
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
23
Application Schemes
VBAT
VSUP
C1
NC
GATE
NC
SOURCE
C2
VSS
C3
CA
LVR
VSS
XTAL1
TD1
XTAL2
8.2pF
10mF 100nF
RA
LA
NC
VDD
R1
RD
R2
TD2
STARC
8 MHz
1MW
MODE1
MODE2
8.2pF
VDD
VBAT
NC
CEXT
CEXT
10nF
AGND
Tx
NC
DOUT
510W
K
AM
Rx
Note: If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and
SOURCE must be left unconnected. C1 is not required for the STARC functionality and only acts as a reservoir of
energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND and VSS connected
to AGND using a low resistance path.
Figure 25. Standalone Configuration with Two-Wires Bus
MC33690 Standalone Tag Reader Circuit, Rev. 5
24
Freescale Semiconductor
Application Schemes
VBAT
VSUP
C1
NC
GATE
NC
SOURCE
To microcontroller
power supply pin
C2
VSS
LA
C3
VDD
To microcontroller
port/reset pin
8.2pF
LVR
10uF 100nF
R1
R2
CA
VSS
RA
XTAL1
TD1
XTAL2
RD
TD2
CEXT
CEXT
10nF
AGND
To microcontroller
port
Tx
STARC
8 MHz
1MW
VDD
8.2pF
MODE1
MODE2
DOUT
AM
To microcontroller
port
VBAT
510W
K
Rx
Note: If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and
SOURCE must be left unconnected. C1 is not required for the STARC functionality and only acts as a reservoir of
energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND and VSS connected
to AGND using a low resistance path.
Figure 26. Direct Connection to a Microcontroller
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor
25
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Document Number: SC33690DS
Rev. 5
02/2007
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