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BQ24156YFFR

BQ24156YFFR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    20-UFBGA,DSBGA

  • 描述:

    IC LI-ION CHARGE MGMT 20DSBGA

  • 数据手册
  • 价格&库存
BQ24156YFFR 数据手册
bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support Check for Samples: bq24153, bq24156, bq24158 FEATURES 1 • • 2 • • • • • • • • • • • • • Charge Faster than Linear Chargers High-Accuracy Voltage and Current Regulation – Input Current Regulation Accuracy: ±5% (100 mA and 500 mA) – Charge Voltage Regulation Accuracy: ±0.5% (25°C), ±1% (0°C to 125°C) – Charge Current Regulation Accuracy: ±5% Input Voltage Based Dynamic Power Management (VIN DPM) Bad adaptor detection and rejection Safety limit register for maximum charge voltage and current limiting High-Efficiency Mini-USB/AC Battery Charger for Single-Cell Li-Ion and Li-Polymer Battery Packs 20-V Absolute Maximum Input Voltage Rating 9.0-V Maximum Operating Input Voltage-bq24156 6-V Maximum Operating Input Voltage-bq24153/8 Built-In Input Current Sensing and Limiting Integrated Power FETs for Up To 1.5-A Charge Rate-bq24156, 1.25A-bq24153/8 Programmable Charge Parameters through I2C™ Compatible Interface (up to 3.4 Mbps): – Input Current Limit – VIN DPM Threshold – Fast-Charge/Termination Current – Charge Regulation Voltage (3.5 V to 4.44 V) – Low Charge Current Mode Enable/Disable – Safety Timer with Reset Control – Termination Enable/Disable Synchronous Fixed-Frequency PWM Controller Operating at 3 MHz With 0% to 99.5% Duty Cycle Automatic High Impedance Mode for Low Power Consumption Robust Protection • • • • • • – Reverse Leakage Protection Prevents Battery Drainage – Thermal Regulation and Protection – Input/Output Overvoltage Protection Status Output for Charging and Faults USB Friendly Boot-Up Sequence Automatic Charging Power Up System without Battery bq24158 Boost Mode Operation for USB OTG: (bq24153/8 only) – Input Voltage Range (from Battery): 2.5 V to 4.5 V – Output for VBUS: 5.05 V/ 200 mA 2.1 mm x 2 mm 20-Pin WCSP Package APPLICATIONS • • • Mobile and Smart Phones MP3 Players Handheld Devices Typical Application Circuit VBUS VBUS 1 µF CIN VAUX PMID 4.7 µF HOST LO 1 µH 10 kΩ CD SCL SDA STAT OTG CD 10 kΩ VSNS CO2 10 µF 10 µF 10 nF BOOT PGND VBAT CO1 CBOOT CSIN 0.1 µF CSIN 10 kΩ 10 kΩ SCL SDA STAT OTG 10 kΩ SW U1 bq24153/8 CIN CSOUT VREF PACK+ + PACK– CVREF CSOUT 0.1 µF 1 µF DESCRIPTION The bq24153/6/8 is a compact, flexible, high-efficiency, USB-friendly switch-mode charge management device for single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The charge parameters can be programmed through an I2C interface. The IC integrates a synchronous PWM controller, power MOSFETs, input current sensing, high-accuracy current and voltage regulation, and charge termination, into a small WCSP package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips Electronics. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com The IC charges the battery in three phases: conditioning, constant current and constant voltage. The input current is automatically limited to the value set by the host. Charge is terminated based on battery voltage and user-selectable minimum current level. A safety timer with reset control provides a safety backup for I2C interface. During normal operation, The IC automatically restarts the charge cycle if the battery voltage falls below an internal threshold and automatically enters sleep mode or high impedance mode when the input supply is removed. The charge status can be reported to the host using the I2C interface. During the charging process, the IC monitors its junction temperature (TJ) and reduces the charge current once TJ increases to about 125°C. To support USB OTG device, bq24153/8 can provide VBUS (5.05V) by boosting the battery voltage. The IC is available in 20-pin WCSP package. DEVICE SPINS AND COMPARISONS PART NUMBER bq24153 bq24156 bq24158 6.5 9.8 6.5 D4 Pin Definition OTG SLRST OTG Maximum Charge Current (A) 1.25 1.55 1.25 Boost Function Yes No Yes Input Current Limit in 15Min Mode 100mA (OTG=LOW); 500mA (OTG=High) 500mA 100mA (OTG=LOW); 500mA (OTG=High) Battery Detection at Power Up Yes Yes No I2C Address 6BH 6AH 6AH PN1 (bit4 of 03H) 1 0 1 PN0 (bit3 of 03H) 0 0 0 VOVP (V) PIN LAYOUT (20-Bump YFF Package) bq24153/8 (Top View) bq24156 (Top View) A1 A2 A3 A4 A1 A2 A3 A4 VBUS VBUS BOOT SCL VBUS VBUS BOOT SCL B3 B4 B1 B3 B4 PMID B1 PMID B2 PMID SDA PMID PMID B2 PMID SDA C1 C2 C3 C4 C1 C2 C3 C4 SW SW SW STAT SW SW SW STAT D1 D2 D3 D4 D1 D2 D3 D4 PGND PGND PGND OTG PGND PGND PGND SLRST E1 E2 E3 E4 E1 E2 E3 E4 CD VREF CSOUT CSIN CD VREF CSOUT CSIN PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. CSOUT E4 I VBUS A1, A2 I/O Charger input voltage. Bypass it with a 1-mF ceramic capacitor from VBUS to PGND. It also provides power to the load during boost mode (bq24153/8 only) . PMID B1, B2, B3 I/O Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-mF capacitor from PMID to PGND. SW C1, C2, C3 O Internal switch to output inductor connection. BOOT A3 I/O Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor (voltage rating ≥ 10 V) from BOOT pin to SW pin. PGND D1, D2, D3 CSIN E1 I Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-mF ceramic capacitor to PGND is required. SCL A4 I I2C interface clock. Connect a 10-kΩ pullup resistor to 1.8V rail (VAUX=VCC_HOST) SDA B4 I/O I2C interface data. Connect a 10-kΩ pullup resistor to 1.8V rail (VAUX=VCC_HOST) 2 Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 mF) to PGND if there are long inductive leads to battery. Power ground Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 PIN FUNCTIONS (continued) PIN I/O DESCRIPTION C4 O Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-ms pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or communicate with a host processor. VREF E3 O Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on VREF is not recommended. CD E2 I Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high impedance to GND. In 15min mode, Setting CD=1 resets the 15min timer; while in 32s mode,Setting CD=1 will NOT reset the 32-second timer. NAME NO. STAT OTG (bq24153/8 only) D4 I Boost mode enable control or input current limiting selection pin. When OTG is in active status, bq24153/8 is forced to operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR, the OTG pin is default to be used as the input current limiting selection pin. When OTG=High, IIN_LIMIT=500mA and when OTG=Low, IIN_LIMIT=100mA, refer to Control Register for detail. SLRST (bq24156 only) D4 I Safety limit register reset control. When SLRST=0, bq24156 resets all the safety limits (06H) to default values, regardless of the write actions to safety limits registers (06H). When SLRST=1, bq24156 can program the safety limit register until any write action to other registers locks the programmed safety limits. ORDERING INFORMATION (1) (1) PART NUMBER MARKING MEDIUM QUANTITY bq24153YFFR bq24153 Tape and Reel 3000 bq24153YFFT bq24153 Tape and Reel 250 bq24156YFFR bq24156 Tape and Reel 3000 bq24156YFFT bq24156 Tape and Reel 250 bq24158YFFR bq24158 Tape and Reel 3000 bq24158YFFT bq24158 Tape and Reel 250 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PACKAGE DISSIPATION RATINGS (1) PACKAGE WSCP-20 (1) (2) (1) RqJA RqJC TA ≤ 25°C POWER RATING DERATING FACTOR TA > 25°C 76°C/W (2) 1.57°C/W 1.32 W 0.0132 W/°C Maximum power dissipation is a function of TJ(max), RqJA and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max)–TA] / RqJA. Using JEDEC 4-layer High-K board. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 3 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com vertical spacer vertical spacer ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) Supply voltage range (with respect to PGND (3)) (3) Input voltage range (with respect to PGND ) Output voltage range (with respect to PGND (3)) bq24153/6/8 UNIT VBUS; VPMID ≥ VBUS –0.3 V –2 to 20 V SCL, SDA, OTG, SLRST, CSIN, CSOUT, CD –0.3 to 7 V PMID, STAT –0.3 to 20 V 7 V –0.7 to 20 V VREF SW, BOOT Voltage difference between CSIN and CSOUT inputs (V(CSIN) – V(CSOUT) ) ±7 V Voltage difference between BOOT and SW inputs (V(BOOT) – V(SW) ) -0.3 to 7 V Voltage difference between VBUS and PMID inputs (V(VBUS) – V(PMID) ) -7 to 0.7 V Voltage difference between PMID and SW inputs (V(PMID) – V(SW) ) -0.7 to 20 V 10 mA Output sink STAT Output Current (average) SW 1.55 (2) A TA Operating free-air temperature range –30 to 85 °C TJ Junction temperature –40 to 125 °C Tstg Storage temperature –45 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Duty cycle for output current should be less than 50% for 10- year life time when output current is above 1.25A. All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal, if not specified. Consult Packaging Section of the data sheet for thermal limitations and considerations of packages. vertical spacer vertical spacer RECOMMENDED OPERATING CONDITIONS MIN VBUS Supply voltage, bq24153/8 NOM MAX 6 (1) (1) V °C VBUS Supply voltage, bq24156 4.0 9 TJ Operating junction temperature range –40 +125 (1) 4 UNIT 4.0 V The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW pins. A tight layout minimizes switching noise. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 ELECTRICAL CHARACTERISTICS Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENTS VBUS > VBUS(min), PWM switching I(VBUS) VBUS supply current control 10 VBUS > VBUS(min), PWM NOT switching 0°C < TJ < 85°C, CD=1 or HZ_MODE=1 I(vbus_leak) mA 5 23 mA 0°C < TJ < 85°C, V(CSOUT) = 4.2 V, High Impedance mode, VBUS=0 V 5 mA 0°C < TJ < 85°C, V(CSOUT) = 4.2 V, High Impedance Battery discharge current in High mode, V(BUS) = 0 V, SCL, SDA, OTG = 0 V Impedance mode, (CSIN, CSOUT, SW pins) or 1.8 V 23 mA 3.5 4.44 V –0.5% 0.5% –1% 1% Leakage current from battery to VBUS pin 15 VOLTAGE REGULATION V(OREG) Output regulation voltage progrmmable range Operating in voltage regulation, programmable TA = 25°C Voltage regulation accuracy CURRENT REGULATION (FAST CHARGE) Output charge current programmable range IO(CHARGE) bq24153, V(LOWV) ≤ V(CSOUT) < V(OREG), VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG=0, Programmable 550 bq24156, V(LOWV) ≤ V(CSOUT) < V(OREG), VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG=0, Programmable 550 VLOWV ≤ VCSOUT < VOREG, VBUS>VSLP, RSNS=68 mΩ, LOW_CHG=1 Low charge current Regulation accuracy of the voltage across R(SNS) (for charge current regulation) V(IREG) = IO(CHARGE) × R(SNS) 37.4 mV ≤ V(IREG)< 44.2mV 44.2 mV ≤ V(IREG) 325 1250 mA 1550 mA 350 mA –3.5% 3.5% -3% 3% 3.4 3.7 WEAK BATTERY DETECTION V(LOWV) Adjustable using I2C control Weak battery voltage threshold programmable range Weak battery voltage accuracy –5% Hysteresis for V(LOWV) Battery voltage falling Deglitch time for weak battery threshold Rising voltage, 2-mV over drive, tRISE = 100 ns V 5% 100 mV 30 ms CD, OTG and SLRST PIN LOGIC LEVEL VIL Input low threshold level VIH Input high threshold level I(bias) Input bias current 0.4 V 1.0 µA 1.3 V Voltage on control pin is 5 V CHARGE TERMINATION DETECTION I(TERM) Termination charge current programmable range V(CSOUT) > V(OREG) – V(RCH), VBUS > V(SLP), R(SNS) = 68 mΩ, Programmable Deglitch time for charge termination Both rising and falling, 2-mV overdrive, tRISE, tFALL = 100 ns Regulation accuracy for termination current across R(SNS) V(IREG_TERM) = IO(TERM) × R(SNS) 50 400 30 ms 3.4 mV ≤ V(IREG_TERM) ≤ 6.8 mV –15% 15% 6.8 mV < V(IREG_TERM) ≤ 17 mV –10% 10% 17 mV < V(IREG_TERM) ≤ 27.2 mV –5.5% 5.5% Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 mA 5 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3.6 3.8 4.0 UNIT BAD ADAPTOR DETECTION VIN(min) Input voltage lower limit BAD ADAPTOR DETECTION Deglitch time for VBUS rising above VIN(min) Rising voltage, 2-mV overdrive, tRISE = 100 ns Hysteresis for VIN(min) Input voltage rising ISHORT Current source to GND During bad adaptor detection tINT Detection Interval Input power source detection 30 100 20 30 V ms 200 mV 40 mA 2 S INPUT BASED DYNAMIC POWER MANAGEMENT Input Voltage DPM threshold programmable range VIN_DPM VIN DPM threshold accuracy 4.2 4.76 –3% 1% V INPUT CURRENT LIMITING IIN = 100 mA IIN_LIMIT Input current limiting threshold IIN = 500 mA TJ = 0°C – 125°C 88 93 98 TJ = –40°C –125°C 86 93 98 TJ = 0°C – 125°C 450 475 500 TJ = –40°C –125°C 440 475 500 mA mA VREF BIAS REGULATOR VREF VBUS >VIN(min) or V(CSOUT) > V(BATMIN), I(VREF) = 1 mA, C(VREF) = 1 mF Internal bias regulator voltage 2 VREF output short current limit 6.5 30 V mA BATTERY RECHARGE THRESHOLD V(RCH) Recharge threshold voltage Below V(OREG) Deglitch time V(SCOUT) decreasing below threshold, tFALL = 100 ns, 10-mV overdrive Low-level output saturation voltage, STAT pin IO = 10 mA, sink current High-level leakage current for STAT Voltage on STAT pin is 5 V 100 120 150 130 mV ms STAT OUTPUTS VOL(STAT) 0.55 V 1 mA I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS VOL Output low threshold level IO = 10 mA, sink current 0.4 V VIL Input low threshold level V(pull-up) = 1.8 V, SDA and SCL 0.4 V VIH Input high threshold level V(pull-up) = 1.8 V, SDA and SCL I(BIAS) Input bias current V(pull-up) = 1.8 V, SDA and SCL 1 mA f(SCL) SCL clock frequency 1.2 V 3.4 MHz BATTERY DETECTION I(DETECT) Battery detection current before charge done (sink current) (1) tDETECT Battery detection time Begins after termination detected, VCSOUT ≤ V(OREG) –0.5 mA 262 ms SLEEP COMPARATOR V(SLP) Sleep-mode entry threshold, VBUS – VCSOUT 2.3 V ≤ V(CSOUT) ≤ V(OREG), VBUS falling V(SLP_EXIT) Sleep-mode exit hysteresis 2.3 V ≤ V(CSOUT) ≤ V(OREG) Deglitch time for VBUS rising above V(SLP) + V(SLP_EXIT) Rising voltage, 2-mV overdrive, tRISE = 100 ns 0 40 100 mV 140 200 260 mV 30 ms UNDERVOLTAGE LOCKOUT (UVLO) VUVLO IC active threshold voltage VBUS rising - Exits UVLO 3.05 3.3 VUVLO(HYS) IC active hysteresis VBUS falling below VUVLO - Enters UVLO 120 150 (1) 6 3.55 V mV Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM f(OSC) Voltage from BOOT pin to SW pin During charge or boost operation Internal top reverse blocking MOSFET on-resistance 6.5 IIN(LIMIT) = 500 mA, Measured from VBUS to PMID 180 250 Internal top N-channel Switching MOSFET on-resistance Measured from PMID to SW, VBOOT – VSW= 4V 120 250 Internal bottom N-channel MOSFET on-resistance Measured from SW to PGND 110 210 Oscillator frequency Maximum duty cycle D(MIN) Minimum duty cycle mΩ 3.0 Frequency accuracy D(MAX) V –10% MHz 10% 99.5% 0 Synchronous mode to non-synchronous mode transition current threshold (2) Low-side MOSFET cycle-by-cycle current sensing 100 mA CHARGE MODE PROTECTION VOVP_IN_USB VOVP-IN_DYN VOVP ILIMIT VSHORT ISHORT Input VBUS OVP threshold voltage (bq24153/8) VBUS threshold to turn off converter during charge V(OVP_IN_USB) hysteresis (bq24153/8) VBUS falling from above V(OVP_IN_USB) Input VBUS OVP threshold voltage (bq24156) Threshold over VBUS to turn off converter during charge V(OVP_IN_DYN) hysteresis (bq24156) VBUS falling from above V(OVP_IN_DYN) Output OVP threshold voltage V(CSOUT) threshold over V(OREG) to turn off charger during charge V(OVP) hysteresis Lower limit for V(CSOUT) falling from above V(OVP) Cycle-by-cycle current limit for charge Charge mode operation 1.8 2.4 3.0 Trickle to fast charge threshold V(CSOUT) rising 2.0 2.1 2.2 VSHORT hysteresis VCSOUT falling below VSHORT Trickle charge charging current VCSOUT ≤ VSHORT) 6.3 6.5 6.7 V 170 9.57 9.8 mV 10 140 110 117 121 %VOREG 11 100 20 30 A V mV 40 mA BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0, bq24153/8 only) VBUS_B Boost output voltage (to VBUS pin) 2.5V < VCSOUT < 4.5 V Boost output voltage accuracy Including line and load regulation IBO Maximum output current for boost VBUS_B = 5.05 V, 2.5 V < VCSOUT < 4.5 V IBLIMIT Cycle by cycle current limit for boost VBUS_B = 5.05 V, 2.5 V < VCSOUT < 4.5 V VBUSOVP Overvoltage protection threshold for boost (VBUS pin) Threshold over VBUS to turn off converter during boost VBUSOVP hysteresis VBUS falling from above VBUSOVP Maximum battery voltage for boost (CSOUT pin) VCSOUT rising edge during boost VBATMAX hysteresis VCSOUT falling from above VBATMAX 200 Minimum battery voltage for boost (CSOUT pin) During boosting 2.5 Before boost starts 2.9 VBATMAX VBATMIN Boost output resistance at high-impedance mode (From VBUS to PGND) CD = 1 or HZ_MODE = 1 5.05 –3% V 3% 200 mA 1.0 5.8 6.0 A 6.2 162 4.75 4.9 V mV 5.05 V mV V 3.05 217 V kΩ PROTECTION TSHTDWN) Thermal trip 165 Thermal hysteresis 10 TCF Thermal regulation threshold Charge current begins to reduce T32S 32 second timer 32 Second mode 15 T15M 15 minute timer 15 Minute mode 12 (2) °C 120 32 s 15 m Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 7 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com TYPICAL APPLICATION CIRCUITS VBUS = 5 V, ICHARGE = 1250 mA, VBAT = 3.5 V to 4.44 V (Adjustable). LO 1.0 mH VBUS VBUS CIN 10 mF 10 nF C IN 4.7 mF VBAT CO1 CBOOT U1 bq24153/8 1 mF RSNS SW CO2 10 mF BOOT PMID VAUX PACK+ CCSIN PGND + 0.1 mF CSIN 10 kW I 10 kW 10 kW 10 kW 2C BUS PACK– CSOUT SCL SCL SDA STAT SDA STAT OTG 10 kW CCSOUT VREF OTG CD CD 0.1 mF CVREF 1 mF 10 kW HOST Figure 1. I2C Controlled 1-Cell USB Charger Application Circuit with USB OTG Support. vertical spacer vertical spacer vertical spacer VBUS = 5 V, ICHARGE = 1550 mA, Vbat = 3.5 V to 4.44V (adjustable). LO 1.0 mH VBUS VBUS CIN SW 10 mF 10 nF C IN 4.7 mF PMID CO2 10 mF BOOT PACK+ + CCSIN PGND VAUX VBAT CO1 CBOOT U1 bq24156 1 mF RSNS 0.1 mF CSIN 10 kW 10 kW 10 kW 10 kW 2 I C BUS SCL SCL SDA STAT SLRST 10 kW SDA STAT SLRST CD 10 kW CD PACK– CSOUT CCSOUT VREF CVREF 0.1 mF 1 mF HOST Figure 2. I2C Controlled 1-Cell Charger Application Circuit with External Safety Limit Register Control. 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 TYPICAL PERFORMANCE CHARACTERISTICS Using circuit shown in Figure 1, TA = 25°C, unless otherwise specified. ADAPTER INSERTION CYCLE BY CYCLE CURRENT LIMITING IN CHARGE MODE VBUS 2 V/div VSW 2 V/div IL 0.5 A/div VSW 5 V/div IBAT 0.5 A/div 10 ms/div 2 ms/div Figure 3. VBUS = 0-5V, Iin_limit = 500mA, Voreg = 4.2V VBAT = 3.5V, Ichg = 550mA, 32S mode Figure 4. VBUS = 5V, VBAT = 3.5V Charge Mode Overload Operation BATTERY INSERTION/REMOVAL PWM CHARGING WAVEFORMS VBAT 2 V/div VSW 2 V/div VSW 5 V/div IL 0.5 A/div IBAT 0.5 A/div Battery Inserted Battery Removed 100 nS/div 1 S/div Figure 5. VBUS = 5 V, VBAT = 3.4V, Iin_limit = 500 mA (32s Mode) Figure 6. VBUS = 5 V, VBAT = 2.6 V, Voreg = 4.2 V, Ichg = 1550 mA BATTERY DETECTION AT POWER UP (bq24153/6) BATTERY DETECTION AT POWER UP (bq24158) VBUS 5 V/div VBUS 4 V/div VBAT 2 V/div VBAT 2 V/div VSW 5 V/div IBUS 50 mA/div IBUS 100 mA/div 100 mS/div 100 mS/div Figure 7. VBUS=5V, No battery connected Figure 8. VBUS=5V, No battery connected Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 9 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) POOR SOURCE DETECTION CHARGE CURRENT RAMP UP VSW 5 V/div VBUS 2 V/div VSW 2 V/div IBUS 20 mA/div IBAT 200 mA/div 10 mS/div 500 mS/div Figure 9. VBUS = 5 V @ 8 mA, VBAT = 3.2V, Iin_limit = 100 mA, Ichg = 550 mA Figure 10. Vin = 5 V, Vbat = 3. 2V, No input current limit, ICHG=1550mA INPUT CURRENT CONTROL (bq24153/8) VIN BASED DPM VBUS 1 V/div OTG 2 V/div 15 Minute Mode 32 S Mode IBUS 0.2 A/div IBAT 0.1 A/div Write Command 0.5 mS/div 1 S/div Figure 11. VBUS = 5 V, VBAT = 3.1V, Iin_limit = 100/500 mA, (OTG control, 15 minute mode), Iin_limit = 100 mA (I2C control, 32 second Mode) Figure 12. VBUS = 5 V @ 500 mA, VBAT = 3.5V, ICHG = 1550 mA, VIN_DPM = 4.52 V CHARGER EFFICIENCY BOOST WAVEFORM (PWM MODE) 94 93 Vbat = 4.2 V 92 Vbat = 3.6 V 91 Efficiency - % 90 VBUS 10 mV/div, 5.05 V Offset VBAT 10 mV/div, 3.5 V Offset 89 VSW 2V/div 88 87 86 85 Vbat = 3 V 84 IL 100 mA/div 83 82 81 80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Charge Current - A Figure 13. 10 100 nS/div 1.1 1.2 1.3 1.4 1.5 Figure 14. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 217 mA Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 TYPICAL PERFORMANCE CHARACTERISTICS (continued) BOOST WAVEFORM (PFM MODE) VBUS OVERLOAD WAVEFORMS (BOOST MODE) VBUS 100 mV/div, 5.05 V Offset VBUS 2 V/div VBAT 100 mV/div, 3.5 V Offset VPMID 200 mV/div, 5.02 V Offset VSW 2 V/div VSW 5 V/div IL 0.2 A/div IBUS 0.2 A/div 5 mS/div 5 mS/div Figure 15. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 42 mA Figure 16. VBUS = 5.05 V, VBAT = 3.5V, RLOAD (at VBUS)= 1KΩ to 0.5Ω LOAD STEP UP RESPONSE (BOOST MODE) LOAD STEP DOWN RESPONSE (BOOST MODE) VBUS 100 mV/div, 5.05 V Offset VBUS 100 mV/div, 5.05 V Offset VBAT 0.2 V/div, 3.5 V Offset VBAT 0.2 V/div, 3.5 V Offset VSW 5 V/div VSW 5 V/div IBAT 0.1 A/div IBAT 0.1 A/div 100 mS/div Figure 17. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 0-217 mA 100 mS/div Figure 18. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 217 mA BOOST TO CHARGE MODE TRANSITION (OTG CONTROL) BOOST EFFICIENCY 95 VBUS 0.5 V/div, 4.5 V Offset VBAT = 2.7 V VBAT = 3.6 V VBAT = 4.2 V 90 Efficiency - % OTG 2 V/div VSW 5 V/div 85 80 75 IL 0.5 A/div 70 0 10 mS/div 50 Figure 19. VBUS = 4.5 V (Charge Mode) / 5.1 V (Boost Mode), VBAT = 3.5V, IIN_LIM = 500 mA, (32S mode) 100 150 Load Current at VBUS - mA Figure 20. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 200 11 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) LINE REGULATION FOR BOOST LOAD REGULATION FOR BOOST 5.09 5.08 IBUS = 200 mA VBAT = 2.7 V VBAT = 3.6 V 5.08 5.07 5.07 5.06 5.05 5.04 VBUS VBUS - V 5.06 IBUS = 50 mA 5.05 VBAT = 4.2 V 5.04 IBUS = 100 mA 5.03 5.03 5.02 5.02 5.01 2.6 5.01 5 2.8 3 3.2 3.4 3.6 3.8 4 4.2 0 50 100 150 Load Current at VBUS - mA 200 VBAT - V Figure 21. 12 Figure 22. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 FUNCTIONAL BLOCK DIAGRAM (Charge Mode) PMID b q 24153 /6 /8 PMID V PMID PMID NMOS VBUS NMOS SW V BUS VBUS Q2 Q1 VREF 1 OSC Charge Pump - PWM Controller CBC Current Limiting Q3 I LIMIT NMOS - - + V IN _ DPM - T CF + TJ - V BUS + V UVLO - V BUS + V IN ( MIN ) - V BUS - TJ + T SHTDWN - V OUT + V OVP - V CSIN + CSOUT V OREG - CSIN IOCHARGE VREF I SHORT PWM _ CHG VBUS UVLO LINEAR Poor Input Source + V OVP_IN V OUT + + I IN _ LIMIT SW SW VREF REFERNCES & BIAS VBUS OVP Thermal Shutdown * _CHG CHARGE CONTROL TIMER and DISPLAY LOGIC , VREF BOOT VREF 1 V PMID Battery OVP VOUT STAT V BAT + - V BUS V OREG - V RCH V OUT PGND V OUT V CSIN PGND I TERM * Sleep CD + - + - * Recharge * ( I2 C Control ) Decoder DAC PGND V BAT + V SHORT - OTG (bq 24153 /8) SLRST(bq24156) Termination SCL SDA Charge * PWMMode * Signal Deglitched Figure 23. Function Block Diagram of bq2415x in Charge Mode Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 13 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM (Boost Mode) PMID bq24153/ 8 PMID V PMID PMID NMOS VBUS NMOS SW SW SW V BUS VBUS Q2 Q1 VREF 1 Charge Pump OSC PWM Controller CBC Current Limiting Q3 PFM Mode V BUS _ B - I BO NMOS - 75 mA + + + I BLIMIT - VREF REFERNCES & BIAS PWM _ BOOST V BUS + VBUS OVP TJ V PMID + V OUT + V BATMAX - CSIN Thermal Shutdown - T SHTDWN BOOT VREF 1 - V BUSOVP VREF * Battery OVP V OUT CHARGE CONTROL, TIMER and DISPLAY LOGIC CSOUT STAT CD PGND PGND V BAT + V BATMIN - * * Low Battery Signal Deglitched PGND OTG ( I2 C Control) Decoder DAC SCL SDA Figure 24. Function Block Diagram of bq2415x in Boost Mode 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 OPERATIONAL FLOW CHART Power Up V BUS > V UVLO V POR Load I 2 C Registers with Default Value CSOUT < V LOWV High Impedance Mode or Host No Controlled Operation Mode Yes Reset and Start 15-M inute T imer Disable Charge /CE = LOW /CE = HIGH Charge Configure Mode Any Charge State Disable Charge Wait Mode Delay TINT Indicate Power not Good Yes No Enable I SHORT V CSOPUT V OREG -V RCH ? Indicate DONE No Yes Charge Complete V CSOUT < V OREG VRCH ? High Impedance Mode Yes Figure 25. Operational Flow Chart of bq2415x in Charge Mode DETAILED FUNCTIONAL DESCRIPTION For a current restricted power source, such as a USB host or hub, a high efficiency converter is critical to fully use the input power capacity for quickly charging the battery. Due to the high efficiency for a wide range of input voltages and battery voltages, the switch mode charger is a good choice for high speed charging with less power loss and better thermal management than a linear charger. The bq24153/6/8 are highly integrated synchronous switch-mode chargers, featuring integrated FETs and small external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or Li-polymer battery pack. Furthermore, bq24153/8 also has bi-directional operation to achieve boost function for USB OTG support. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 15 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com The bq24153/8 have three operation modes: charge mode, boost mode, and high impedance mode, while bq24156 only has charge mode and high impedance mode. In charge mode, the IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost mode, the IC boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode, the IC stops charging or boosting and operates in a mode with very low current from VBUS or battery, to effectively reduce the power consumption when the portable device is in standby mode. Through the proper control, the IC achieves the smooth transition among the different operation modes. CHARGE MODE OPERATION Charge Profile In charge mode, the IC has five control loops to regulate input voltage, input current, charge current, charge voltage and device junction temperature. During the charging process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. Figure 26 (a) indicates a typical charge profile without input current regulation loop. It is the traditional CC/CV charge curve, while Figure 26(b) shows a typical charge profile when input current limiting loop is dominant during the constant current mode. In this case, the charge current is higher than the input current so the charge process is faster than the linear chargers. For bq24153/6/8, the input voltage threshold for DPM loop, input current limits, the charge current, termination current, and charge voltage are all programmable using I2C interface. 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 Precharge Phase Current Regulation Phase Voltage Regulation Phase Regulation Voltage Regulation Current Charge Voltage V SHORT Charge Current Termination I SHORT Precharge (Linear Charge) Precharge Phase Fast Charge (PWM Charge) (a) Current Regulation Phase Voltage Regulation Phase Regulation voltage Charge Voltage VSHORT Charge Current Termination I SHORT Precharge (Linear Charge) Fast Charge (PWM Charge) (b) Figure 26. Typical Charging Profile of bq24153/6/8 for (a) without Input Current Limit, and (b) with Input Current Limit Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 17 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com PWM Controller in Charge Mode The IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate charge current or voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation network used for both continuous and discontinuous current conduction operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with very low ESR. The device operates between 0% to 99.5% duty cycles. The IC has back to back common-drain N-channel FETs at the high side and one N-channel FET at low side.The input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET (Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2. Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4-A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used when the current of the low-side FET is greater than 100mA to minimize power losses. Battery Charging Process At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit current, I(SHORT), to the battery. When the battery voltage is above VSHORT and below VOREG, the charge current ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT. The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input current limit, IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. Once the battery voltage reaches the regulation voltage, VOREG, the charge current is tapered down as shown in Figure 26. The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. The regulation voltage is adjustable (3.5V to 4.44V) and is programmed through I2C interface. The IC monitors the charging current during the voltage regulation phase. When the termination is enabled, once the termination threshold, ITERM, is detected and the battery voltage is above the recharge threshold, the IC terminates charge. The termination current level is programmable. To disable the charge current termination, the host can set the charge termination bit (I_Term) of charge control register to 0, refer to I2C section for detail. A • • • new charge cycle is initiated when one of the following conditions is detected: The battery voltage falls below the V(OREG) – V(RCH) threshold. VBUS Power-on reset (POR), if battery voltage is below the V(LOWV) threshold. CE bit toggle or RESET bit is set (Host controlled) Safety Timer in Charge Mode At the beginning of charging process, the IC starts a 15-minute timer (T15min) that can be disable by any write-action performed by host through I2C interface. Once the 15-minute timer is disabled, a 32-second timer (T32sec) is automatically started. The 32-second timer can be reset by host using I2C interface. Writing “1” to reset bit of TMR_RST in control register will reset the 32-second timer and TMR_RST is automatically set to “0” after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge parameters are reset to default values. Then the 15-minute timer starts and the charge resumes. During normal charging process, the IC is usually in 32-second mode with host control and 15-minute mode without host control using I2C interface. The above process repeats until the battery is fully charged. If the 15-minute timer expires, the IC turns off the charge, enunciates FAULT on the STATx bits of status register, and sends the 128ms interrupt pulse. This function prevents battery over charge if the host fails to reset the safety timer. The 15-minute charge, with default parameters, allows time for a discharged battery to charge sufficiently to be able to power the host and start communication. The safety timer flow chart is shown in Figure 27. Fault condition is cleared by POR and fault status bits can only be updated after the status bits are read by the host. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 Charge Start Start T15 min Timer Reset Charge Parameters Yes No T 32 sec Expired ? Start T32 sec Stop T15 min No Yes Charge 2 T 15 min Active ? Yes Any I C Write Action ? No T 15 min Expired ? No Host Should Reset T 32 sec Timer Yes Timer Fault Figure 27. Timer Flow Chart for bq24153/6/8 USB Friendly Boot-Up Sequence Prior to power up if the host continus to write the TMR_RST bit to 1, to stay in 32 second mode, on power up the charger enters normal charge mode (using the desired control bits). If not in 32 second mode at power up, the charge will operate with default bit values, in 15 minute mode, until the host updates the control registers. If the battery voltage is above the VLOWV threshold while in 15 minute mode, the charger will be in the high impedance state. The default control bits set the charging current and regulation voltage low as a safety feature to avoid violating USB spec and over-charging any of the Li-Ion chemistries, while the host has lost communication. The input current limiting is described below. Input Current Limiting The input current sensing circuit and control loop are integrated into the IC. When operating in 15 minute mode, for bq24153/8, the OTG pin sets the input current limit to 100mA for a logic low and 500mA for a logic high, whereas the bq24156 defaults to 500mA. In 32 second mode, the input current limit is set by the programmed control bits in register 01H. Thermal Regulation and Protection To prevent overheat of the chip during the charging process, the IC monitors the junction temperature, TJ, of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TCF. The charge current is reduced to zero when the junction temperature increases approximately 10°C above TCF. In any state, if TJ exceeds TSHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and all timers are frozen. Charging resumes when TJ falls below TSHTDWN by approximately 10°C. Input Voltage Protection in Charge Mode Sleep Mode The IC enters the low-power sleep mode if the voltage on VBUS pin falls below sleep-mode entry threshold, VCSOUT+VSLP, and VBUS is higher than the bad adaptor detection threshold, VIN(MIN). This feature prevents draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch Q1 and PWM are turned off. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 19 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com Bad Adaptor Detection/Rejection At the POR of VBUS, the IC performs the bad adaptor detection by applying a current sink to VBUS. If the VBUS is higher than VIN(MIN) for 30ms, the adaptor is good and the charge process begins. Otherwise, if the VBUS drops below VIN(MIN), the bad adaptor is detected. Then, the IC disables the current sink, sends a send fault pulse in FAULT pin and sets the bad adaptor flag (B2-B0=011 for Register 00H). After a delay of TINT, the IC repeats the adaptor detection process, as shown in Figure 28 and Figure 29. Adpator V BUS VBUS ISHORT (30 mA) Adaptor Detection Control VIN_GOOD Deglitch 30ms PGND GND START VIN VIN(MIN) VIN_POOR Delay TINT Figure 28. Bad Adaptor Detection Circuit 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 Charge Command (Host Control or VBUS Ramps Up) Delay 10mS Enable Adaptor Detection Start 30ms Timer Enable Input Current Sink (30mA, to GND) No VBUS>VIN(MIN)? Yes 30ms Timer Expired? No Yes Bad Adaptor Detected Good Adaptor Detected Pulsing STAT Pin Set Bad Adaptor Flag Disable Adaptor Detection Charge Start Enable VIN Based DPM Delay TINT (2 Seconds) Figure 29. Bad Adaptor Detection Scheme FLow Chart Input Voltage Based DPM (Special charger identifiction) During the charging process, if the input power source is not able to support the programmed or default charging current, VBUS voltage will decease. Once the VBUS drops to VIN_DPM (default 4.52V), the charge current begins to taper down to prevent the further drop of VBUS. When the IC enters this mode, the charge current is lower than the set value and the special charger bit is set (B4 in Register 05H). This feature will make the IC compatible with adapters with different current capabilities. Input Over-Voltage Protection The IC provides a built-in input over-voltage protection to protect the device and other components against damage if the input voltage (Voltage from VBUS to PGND) goes too high. When an input over-voltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once VBUS drops below the input over-voltage exit threshold, the fault is cleared and charge process resumes. Battery Protection in Charge Mode Output Over-Voltage Protection The IC provides a built-in over-voltage protection to protect the device and other components against damage if the battery voltage goes too high, as when the battery is suddenly removed. When an over-voltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once VCSOUT drops to the battery over-voltage exit threshold, the fault is cleared and charge process resumes. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 21 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com Battery Detection During Normal Charging For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably detect insertion or removal of battery packs. During normal charging process with host control, once the voltage at the CSOUT pin is above the battery recharge threshold, VOREG- VRCH, and the termination charge current is detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT, then checks the battery voltage. If the battery voltage is still above recharge threshold, the battery is present and the charge done is detected. On the other hand, if the battery voltage is below battery recharge threshold, the battery is absent. Under this condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes after a delay of TINT. This function ensures that the charge parameters are reset whenever the battery is replaced. Battery Detection at Power Up bq24153/6 also has a unique battery detection scheme during the start up of the charger. At VBUS power up, if the timer is in 15-minute mode, bq24153/6 will start a 32ms timer when exiting from short circuit mode to PWM charge mode. If the battery voltage is charged to recharge threshold (VOREG-VRCH) and the 32ms timer is not expired yet, or battery voltage is above output OVP threshold during short-circuit mode, bq2153/6 will considered that the battery is not present; then stop charging and go to high impedance mode immediately. However, if the 32ms timer is expired before the recharge threshold is reached, the charging process will continue as normal battery charging process. For bq24158, the 32ms timer for battery detection at power up is disabled. Therefore, bq24158 can power up the system without a battery. Battery Short Protection During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the charger operates in short circuit mode with a lower charge rate of ISHORT. Charge Status Output, STAT Pin The STAT pin is used to indicate operation conditions for bq24153/6/8. STAT is pulled low during charging when EN_STAT bit in control register (00H) is set to “1”. Under other conditions, STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128-µs pulse will be sent out to notify the host. The status of STAT pin at different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED or communicate to the host processor. Table 1. STAT Pin Summary CHARGE STATE STAT Charge in progress and EN_STAT=1 Low Other normal conditions Open-drain Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source, VBUS UVLO, no battery, thermal shutdown 128-ms pulse, then open-drain Boost mode faults (bq24153/8 only): Timer fault, over load, VBUS or battery overvoltage, low battery voltage, thermal shutdown 128-ms pulse, then open-drain Control Bits in Charge Mode CE Bit (Charge Mode) The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge. RESET Bit The RESET bit in the control register is used to reset all the charge parameters. Write ‘1” to RESET bit will reset all the charge parameters to default values except safety limit register, and RESET bit is automatically cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge starts and it is not recommended to set RESET bit when charging or boosting in progress. 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 OPA_Mode Bit OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in boost mode. Table 2. Operation Mode Summary OPA_MODE HZ_MODE OPERATION MODE 0 0 Charge (no fault) Charge configure (fault, Vbus > VUVLO) High impedance (Vbus < VUVLO) 1(bq24153/8 only) 0 Boost (no faults) Any fault go to charge configure mode X 1 High impedance Control Pins in Charge Mode CD Pin (Charge Disable) The CD pin is used to disabled the charging process. When CD=0, charge is enabled. When CD=1, charge is disabled and VBUS pin is high impedance to GND. In 15-minute mode, setting CD=1 resets the 15-minute timer; while in 32s mode, setting CD=1does NOT reset the 32-second timer. SLRST Pin (Safety Limit Register 06H Reset, bq24156 only) When SLRST=0, bq24156 will reset all the safety limits to default values, regardless of the write actions to safety limits registers (06H). When SLRST=1, bq24156 can program the safety limit register until any write action to other registers locks the programmed safety limits. Boost Mode Operation (bq24153/8 only) In 32 second mode, when OTG pin is in active status or the bit of operation mode (OPA_MODE) at control register is set to 1, bq24153/8 operates in boost mode and delivers the power to VBUS from the battery. In normal boost mode, bq24153/8 converts the battery voltage to VBUS-B (about 5.05V) and delivers a current as much as IBO (about 200mA) to support other USB OTG devices connected to the USB connector. PWM Controller in Boost Mode Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation with a wide load range and battery voltage range. In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses. Boost Start Up To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up. PFM Mode at Light Load In boost mode, the IC operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the converter efficiency at light load condition. During boosting, the PWM converter is turned off once the inductor current is less than 75mA; and the PWM is turned back on only when the voltage at PMID pin drops to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM and PFM mode. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 23 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com Safety Timer in Boost Mode At the beginning of boost operation, the IC starts a 32-second timer that is reset by the host using the I2C interface. Writing “1” to reset bit of TMR_RST in control register will reset the 32-second timer and TMR_RST is automatically set to “0” after the 32-second timer is reset. Once the 32-second timer expires, the IC turns off boost converter, enunciates the fault pulse from the STAT pin and sets fault status bits in the status register.The fault condition is cleared by POR or host control. Protection in Boost Mode Output Overvoltage Protection The IC provides a built-in over-voltage protection to protect the device and other components against damage if the VBUS voltage goes too high. When an over-voltage condition is detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. Once VBUS drops to the normal level, the boost starts after host sets OPA_MODE to “1” or OTG pin stays in active status. Output Overload Protection The IC provides a built-in over-load protection to prevent the device and battery from damage when VBUS is over loaded. Once over load condition is detected, Q1 will operate in linear mode to limit the output current while VPMID keeps in voltage regulation. If the over load condition lasts for more than 30ms, the over-load fault is detected. When an over-load condition is detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out fault pulse in STAT pin. The boost will not start until the host clears the fault register. Battery Overvoltage Protection During boosting, when battery voltage is above the battery over voltage threshold, VBATMAX, or below the minimum battery voltage threshold, VBATMIN, the IC will turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out fault pulse in STAT pin. Once the battery voltage goes above VBATMIN, the boost will start after the host sets OPA_MODE to “1” or OTG pin stays in active status. STAT Pin Boost Mode During normal boosting process, the STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128-ms pulse is sent out to notify the host. High Impedance Mode When control bit of HZ-MODE is set to “1” and OTG pin is not in active status, the IC operates in high impedance mode, with the input impedance of the VBUS pin to be higher than 217kΩ. In high impedance mode, a low power 32-second timer will be enabled when the battery voltage is below VLOWV to monitor if the host control is available or not. If the low power 32 second timer expires, the IC operates in 15 minute mode and the low power 32 second timer is disabled. In 15 minute mode, when VBUS is below VUVLO, the IC operates in high impedance mode regardless of the setting of the HZ_MODE bit. SERIAL INTERFACE DESCRIPTION I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The IC works as a slave and is compatible with the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that SDA changes while SCL is LOW. The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-mode. The bq24150/1 device supports 7-bit addressing only. The device 7-bit address is defined as ‘1101011’ (6BH) for bq24153, and ‘1101010’ (6AH) for bq24156/8. F/S Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 30. All I2C-compatible devices should recognize a start condition. DATA CLK S P START Condition STOP Condition Figure 30. START and STOP Condition The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 31). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 31) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 31. Bit Transfer on the Serial Interface The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 33). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not listed in this section will result in FFh being read out. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 25 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 9 8 2 Clock Pulse for Acknowledgement START Condition Figure 32. Acknowledge on the I2C Bus™ Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA Acknowledgement Signal From Slave MSB Sr Address R/W SCL S or Sr ACK ACK Sr or P Clock Line Held Low While Interrupts are Serviced Figure 33. Bus Protocol H/S Mode Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not listed in this section results in FFh being read out. 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 bq24153 bq24156, bq24158 www.ti.com SLUSA27 – MARCH 2010 I2C Update Sequence The IC requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the IC. The IC performs an update on the falling edge of the acknowledge signal that follows the LSB byte. For the first update, the IC requires a start condition, a valid I2C address, a register address byte, a data byte. For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is received, the IC releases the I2C bus, and awaits a new start conditions. S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P Data Transferred (n Bytes + Acknowledge) ‘0’ (Write) From master to IC A A From IC to master S Sr P = Acknowledge (SDA LOW) = Not acknowledge (SDA HIGH) = START condition = Repeated START condition = STOP condition (a) F/S-Mode F/S-Mode S F/S-Mode HS-Mode HS-MASTER CODE A Sr SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A Data Transferred (n Bytes + Acknowledge) ‘0’ (write) P HS-Mode Continues Sr Slave A. (b) HS- Mode Figure 34. Data Transfer Format in F/S Mode and H/S Mode Slave Address Byte MSB X LSB 1 1 0 1 0 1 1 The slave address byte is the first byte received following the START condition from the master device. Register Address Byte MSB 0 LSB 0 0 0 0 D2 D1 D0 Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a bidirectional I2C-bus interface. Among them, four internal registers have read and write access; and one has only read access. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 27 bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com REGISTER DESCRIPTION Table 3. Status/Control Register (Read/Write) Memory Location: 00, Reset State: x1xx 0xxx BIT NAME READ/WRITE FUNCTION B7 (MSB) TMR_RST/OTG Read/Write Write: TMR_RST function, write "1" to reset the safety timer (auto clear) Read: OTG pin status, (for bq24153/8 only) 0-OTG pin at Low level, 1-OTG pin at High level SLRST pin status (for bq2156 only), 0-SLRST pin at LOW level, 1-SLRST pin at HIGH level. B6 EN_STAT Read/Write 0-Disable STAT pin function, 1-Enable STAT pin function (default 1) B5 STAT2 Read Only B4 STAT1 Read Only B3 BOOST Read Only B2 FAULT_3 Read Only B1 FAULT_2 Read Only B0 (LSB) FAULT_1 Read Only 00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault 1-Boost mode, 0-Not in boost mode, for bq24153/8/9 only; NA–for bq24156. Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or VBUS
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