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bq24187
SLUSBM0 – APRIL 2014
bq24187 2A, 30V Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery
Charger with Integrated Sense Element and 1A USB-OTG Support
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
Charge Time Optimizer (Enhanced CC/CV
Transition) for Faster Charging
Integrated FETs for Up to 2A Charge Rate at 5%
Accuracy and 93% Peak Efficiency
Boost Capability to Supply 5V at 1A at IN for USB
OTG Supply
Integrated Current Sense Resistor for Smallest
Size and Cost
30V Input Rating with Over-Voltage Protection
Supports 5V USB2.0/3.0 with 6.5V OVP
Small Solution Size In a 2,4mm x 2,4mm 36-ball
WCSP or 4mm x 4mm QFN-24 Package
Safe and Accurate Battery Management
Functions Programmed Using I2C Interface
– Charge Voltage, Current, Termination
Threshold, Input Current Limit, VIN_DPM
Threshold
– Voltage-based, JEITA Compatible NTC
Monitoring Input
– Thermal Regulation Protection for Input
Current Control
– Thermal Shutdown and Protection
Smartphones and Tablets
Handheld Products
Power Banks and External Battery Packs
Small Power Tools
Portable Media Players and Gaming
3 Description
The bq24187 is a highly integrated single cell Li-Ion
battery charger targeted for space-limited, portable
applications with high capacity batteries. The single
cell charger has a single input that supports operation
from either a USB port or wall adapter supply for a
versatile solution. The integrated sense element
reduces solution size and external component count.
The charge parameters are programmable using the
I2C interface. To Support USB OTG applications, the
bq24187 is configurable to boost the battery voltage
to 5V at the input. In this mode, the bq24187 supplies
up to 1A and operates with battery voltages down to
3.3V. A voltage-based, JEITA compatible battery
pack thermistor monitoring input (TS) is included that
monitors battery temperature for safe charging.
Device Information
ORDER NUMBER (1)
PACKAGE
BODY SIZE
bq24187YFFR
DSBGA (36)
2,4mm × 2,4mm
bq24187RGER (2)
VQFN (24)
4mm × 4mm
(1)
(2)
For ordering information see the addendums at the end of the
data sheet.
PREVIEW
4 Typical Application
IN
SW
VBUS
D+
DGND
BOOT
PGND
CS+
DRV
BAT
USB PHY
PSEL
HOST
GPIO1
System
Load
bq24187
PACK+
TEMP
TS
INT
SDA
SDA
SCL
SCL
VDRV
PACK-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
Not Recommended for New Designs
bq24187
SLUSBM0 – APRIL 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
8.2
8.3
8.4
8.5
8.6
1
1
1
1
2
3
5
9
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
12
14
14
23
26
Applications and Implementation ...................... 31
9.1 Application Information............................................ 31
9.2 Typical Application .................................................. 31
Absolute Maximum Ratings ...................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information ................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
Detailed Description ............................................ 11
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
8.1 Overview ................................................................. 11
5 Revision History
2
DATE
REVISION
NOTES
April 2014
*
Initial release.
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6 Terminal Configuration and Functions
SW
SW
PGND
PGND
AGND
IN
RGE Package
(24-Terminal 4 mm X 4 mm QFN)
Top View
24
23
22
21
20
19
PMID
1
18 IN
BOOT
2
17 SDA
DRV
3
16 SCL
bq24187
11
12
10
8
9
7
AGND
13 STAT
N.C.
CS+ 6
INT
14 PSEL
BAT
TS 5
BAT
15 N.C.
CS+
CD 4
YFF Package
(36-Ball 2,6 mm X 2,6 mm DSBGA)
Top View
1
2
3
4
5
6
A
PGND
PGND
PGND
PGND
PGND
PGND
B
PMID
SW
SW
SW
SW
SW
C
IN
IN
IN
IN
CD
BOOT
D
SDA
SCL
N.C.
PSEL
TS
DRV
E
STAT
INT
CS+
CS+
CS+
CS+
F
AGND
N.C.
BAT
BAT
BAT
BAT
Terminal Functions
TERMINAL
NAME
YFF
AGND
F1
BAT
F3-F6
BOOT
CD
RGE
I/O
12, 20
DESCRIPTION
Analog Ground. Connect to the PGND TERMINALs and the ground plane of the circuit.
8, 9
I/O
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to GND
with a 1μF capacitor.
C6
2
I
High Side MOSFET Gate Driver Supply. Connect a 0.033µF ceramic capacitor (voltage rating > 10V)
from BOOT to SW to supply the gate drive for the high side MOSFETs.
C5
4
I
IC Hardware Disable Input. Drive CD high to place the bq24187 in Hi-Z mode. Drive CD low for
normal operation.
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Terminal Functions (continued)
TERMINAL
NAME
YFF
DRV
D6
IN
C1-C4
I/O
DESCRIPTION
3
O
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV
to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is
active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP).
18, 19
I
DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass
IN to PGND with at least a 4.7μF ceramic capacitor.
10
O
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls
low during charging. INT is high impedance when charging is complete or the charger is disabled.
When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is enabled /disabled
using the EN_STAT bit in the control register. Connect INT to a logic rail through a 100kΩ resistor to
communicate with the host processor.
RGE
INT
E2
N.C.
D3, F2
11, 15
--
Connect to the ground plane of the circuit.
PGND
A1-A6
21, 22
--
Ground terminal. Connect to the the ground plane of the circuit.
PMID
B1
1
I
High Side Bypass Connection. Connect a 1µF capacitor from PMID to PGND as close to the PMID
and PGND TERMINALs as possible.
PSEL
D4
14
I
Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit during
DEFAULT mode. Drive PSEL high to select USB100 mode, drive PSEL low to select 1.5A mode.
SCL
D2
16
I
I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor.
SDA
D1
17
I/O
I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
13
O
Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT
pulls low during charging. STAT is high impedance when charging is complete or the charger is
disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is enabled
/disabled using the EN_STAT bit in the control register. Connect STAT to a logic rail using an LED for
visual indication or through a 10kΩ resistor to communicate with the host processor.
STAT
E1
SW
B2-B6
23, 24
O
Inductor Connection. Connect to the switched side of the external inductor.
CS+
E3-E6
6, 7
I
System Voltage Sense and Charger FET Connection. Connect CS+ to the inductor. Bypass CS+
locally with 20μF.
TS
D5
5
I
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The
NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS
faults are reported by the I2C interface. Pull TS high to VDRV to disable the TS function. See the NTC
Monitor section for more details on operation and selecting the resistor values.
Thermal
PAD
–
–
–
There is an internal electrical connection between the exposed thermal pad and the PGND
TERMINAL of the device. The thermal pad must be connected to the same potential as the PGND
TERMINAL on the printed circuit board. Do not use the thermal pad as the primary ground input for
the device. PGND TERMINAL must be connected to ground at all times.
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
IN
Terminal voltage range (with
respect to PGND)
MIN
MAX
–1.3
30
BOOT
–0.3
30
V
–0.7
20
V
SDA, SCL, CS+, BAT, STAT, DRV, TS, PSEL, INT
–0.3
5
V
–0.3
5
V
SW
4.5
A
CS+, BAT (charging)
3.5
A
Input Current (Continuous)
Output Sink Current
V
SW
BOOT to SW
Output Current (Continuous)
UNIT
2.75
STAT, INT
A
10
mA
Operating free-air temperature range
–40
85
°C
Junction temperature, TJ
–40
125
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
TSTG
Storage temperature range
MIN
MAX
UNIT
–65
150
°C
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
MIN
MAX
UNIT
IN voltage
4.2
28 (1)
V
IN operating voltage
4.2
6.0
IIN
Input current, IN input
ISW
Ouput Current from SW, DC
IBAT
Charge Current
TJ
Operating junction temperature, TJ
(1)
0
2.5
A
2
A
2
A
125
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW terminals. A
tight layout minimizes switching noise.
7.4 Thermal Information
bq24187
THERMAL METRIC
(1)
YFF
RGE
36 TERMINALS
24 TERMINALS
RθJA
Junction-to-ambient thermal resistance
55.8
32.6
RθJCtop
Junction-to-case (top) thermal resistance
0.5
30.5
RθJB
Junction-to-board thermal resistance
10
3.3
ψJT
Junction-to-top characterization parameter
2.6
0.4
ψJB
Junction-to-board characterization parameter
9.9
9.3
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
2.6
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, PWM
switching
IIN
Supply current for control
Battery discharge current in high
impedance mode, (BAT, SW,
CS+)
IBAT_HIZ
15
mA
VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, PWM
NOT switching
6.5
0°C< TJ < 85°C, VIN = 5V, High-Z Mode
250
μA
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 5V, SCL, SDA
= 0V or 1.8V, High-Z Mode
15
μA
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0V, SCL, SDA
= 0V or 1.8V
80
μA
CHARGER PARAMETERS
RSENSE
Internal Sense Element
Resistance
Measured from BAT to
CS+, VBAT = 4.2V, High-Z
mode
YFF
17
25
mΩ
RGE
32
47
mΩ
Charge voltage
Operating in voltage regulation, Programmable
range
TJ = 25°C, RGE Package
VBATREG
Voltage Regulation Accuracy
TJ = 0°C to 85°C, RGE and YFF Package
Fast charge current range
VLOWV ≤ VBAT < VBAT(REG)
TJ = 0°C to 125°C, RGE and YFF Package
ICHARGE
Fast charge current accuracy
500 mA ≤ ICHARGE ≤ 1A
ICHARGE ≥ 1000mA
3.5
4.44
–0.5%
0.5%
–0.75%
0.75%
-1.0%
1.0%
500
2000
–10%
10%
–5%
5%
VBATSHRT
Battery short circuit threshold
VBATSHRT(hys)
Hysteresis for VLOWV
Battery voltage falling
1.9
IBATSHRT
Battery short circuit charge
current
VBAT < VLOWV
33.5
≤ 50mA
–30%
30%
ITERM
Termination charge current
50mA < ITERM < 200mA
–15%
15%
ITERM ≥ 200mA
–15%
ITERM
VRCH
Recharge threshold voltage
VDET(SRC1)
VDET(SRC2)
Battery detection voltage
threshold (TE = 1)
VDET(SNK)
IDETECT
6
Below VOREG
100
50
VRCH
During current source (Turn IBATSHRT on)
VRCH –
200mV
Termination enabled (TE = 1)
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2.1
mA
V
mV
66.5
mA
10%
120
During current source (Turn IBATSHRT off)
During current sink
Battery detection current before
charge done (sink current)
2
100
V
150
mV
V
VBATSHRT
7
mA
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Electrical Characteristics (continued)
Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENT LIMITING
IIN_USB
VIN_DPM
Input current limiting threshold
Input based DPM threshold
range
USB charge mode,
VIN = 5V,
Current pulled from SW
IINLIM = USB100
90
95
100
IINLIM = USB500
450
475
500
IINLIM = USB150
125
140
150
IINLIJM = USB900
800
850
900
IINLIM = 1.5A
1425
1500
1575
IINLIM = 2.0A
1850
2000
2200
Charge mode, programmable via I2C
VIN_DPM threshold Accuracy
4.2
4.76
–3%
3%
mA
V
VDRV BIAS REGULATOR
VDRV
Internal bias regulator voltage
IDRV
DRV Output current
VDO_DRV
DRV Dropout voltage (VIN –
VDRV)
VIN>5V
4.3
4.8
5.3
V
10
mA
IIN = 1A, VIN = 4.2V, IDRV = 10mA
450
mV
0.4
V
1
µA
0
STATUS OUTPUT (STAT, INT)
VOL
Low-level output saturation
voltage
IO = 5 mA, sink current
IIH
High-level leakage current
V/CHG = V/PG = 5V
INPUT TERMINALS (CD, PSEL)
VIL
Input low threshold
VIH
Input high threshold
0.4
RPULLDOWN
CD pull-down resistance
CD only
VUVLO
IC active threshold voltage
VIN rising
VUVLO_HYS
IC active hysteresis
VIN falling from above VUVLO
VSLP
Sleep-mode entry threshold, VINVBAT
2.0 V ≤ VBAT ≤ VBATREG, VIN falling
VSLP_HYS
Sleep-mode exit hysteresis
VOVP
Input supply OVP threshold
voltage
IN rising, 100mV hysteresis
VBOVP
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger
during charge
VBOVP_HYS
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
ICbCLIMIT
Cycle-by-cycle current limit
VCS+ shorted
TSHTDWN
Thermal trip
V
1.4
V
100
kΩ
PROTECTION
3.2
Thermal regulation threshold
3.4
V
mV
0
40
120
mV
40
100
190
mV
6.25
6.5
6.75
V
1.03 ×
VBATREG
1.05 ×
VBATREG
1.07 ×
VBATREG
V
% of
VBATREG
1
4.1
4.5
4.9
150
Thermal hysteresis
TREG
3.3
300
A
°C
10
Charge current begins to cut off
Safety Timer Accuracy
125
–20%
°C
20%
PWM
RDSON_Q1
RDSON_Q2
Internal top MOSFET onresistance
YFF Package: Measured from IN to SW
75
120
mΩ
RGE Package: Measured from IN to SW
80
135
mΩ
Internal bottom N-channel
MOSFET on-resistance
YFF Package: Measured from SW to PGND
75
115
mΩ
RGE Package: Measured from SW to PGND
80
135
mΩ
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Electrical Characteristics (continued)
Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VTS falling, 2% VDRV Hysteresis
27.3
30
32.6
%VDRV
VWARM
Warm temperature threshold
VTS falling, 2% VDRV Hysteresis
36.0
38.3
41.2
%VDRV
VCOOL
Cool temperature threshold
VTS rising, 2% VDRV Hysteresis
54.7
56.4
58.1
%VDRV
VCOLD
Low temperature threshold
VTS rising, 2% VDRV Hysteresis
58.2
60
61.8
%VDRV
TSOFF
TS Disable threshold
VTS rising, 4% VDRV Hysteresis
80
85
%VDRV
1.3
I2C COMPATIBLE INTERFACE
VIH
Input low threshold level
VPULL-UP=1.8V, SDA and SCL
VIL
Input low threshold level
VPULL-UP=1.8V, SDA and SCL
0.4
V
V
VOL
Output low threshold level
IL=5mA, sink current
0.4
V
IBIAS
High-Level leakage current
VPULL-UP=1.8V, SDA and SCL
1
μA
2.7V VOVP or Boost Mode OVP
010- Low Supply connected (VIN TS temp > TCOLD (Charge current reduced by half)
11— TWARM < TS temp < THOT (Charge voltage reduced by 100mV)
Always write to ‘0’
The BOOST_ILIM bit programs the cycle by cycle current limit threshold for boost
operation. The 1A setting sets the low side cycle by cycle current limit to 4A (typ).
This ensures that at least 1A can be supplied from the boost converter over the entire
battery range. The 500mA setting sets the current limit to 2A(typ) to ensure at least
500mA available from the boost converter. See the boost mode over-current section
for more details
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9 Applications and Implementation
9.1 Application Information
The bq24187-625 evaluation module (EVM) is a complete charger module for evaluating the bq24187. The
application curves were taken using the bq24187EVM-625. See Related Documentation.
9.2 Typical Application
1.5uH
PMID
SW
1uF
0.033uF
BOOT
CS+
IN
VBUS
D+
20uF
DGND
4.7uF
DRV
BAT
SYSTEM
VDRV
1uF
1uF
PGND
STAT
PACK+
TS
TEMP
VI/O
(1.8V)
PSEL
USB PHY
PACK-
HOST
bq24187
INT
GPIO1
SDA
SDA
SCL
SCL
CD
Figure 16. bq24187 Typical Application Circuit
9.2.1 Design Requirements
Table 9. Design Requirements
DESIGN PARAMATER
EXAMPLE VALUE
Input Voltage Range
4.75 V to 5.25 V nominal, withstand 28 V
Input Current Limit
1500 mA
Input DPM Threshold
4.25 V
Fast Charge Current
2000 mA
Battery Charge Voltage
4.2 V
Termination Current
150 mA
9.2.2 Detailed Design Procedure
The parameters are configurable using the EVM software.
The typical application circuit shows the minimum capacitance requirements for each terminal. Options for sizing
the inductor outside the 1.5 μH recommended value and additional SYS terminal capacitance are explained in
the next section. The resistors on STAT and INT are sized per each LED's current requirements. The TS resistor
divider for configuring the TS function to work with the battery's specific thermistor can be computed from
Equation 1 and Equation 2. The external battery FET is optional.
9.2.2.1 Output Inductor And Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq24187 is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
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Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use Equation 5 and Equation 6 to calculate the peak current.
V - VBAT
VBAT
%RIPPLE = IN
´
L
VIN ´ ¦ SW
(5)
For the 5V adapter case, a good rule of thumb is to use 3.5V as VBAT. This provides a reasonable worst case
ripple. For higher adapters, the closer to 50% duty cycle, the worse the ripple.
æ %
ö
IPEAK = ICHARGE ´ ç 1 + RIPPPLE ÷
2
è
ø
(6)
The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due to
the high currents possible with the bq24187, a thermal analysis must also be done for the inductor. Many
inductors have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise
above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted
for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at
2.5A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D ´ (IPEAK - ILOAD ) = 1.5A + 0.2 ´ (2.5A - 1.5A) = 1.7A
(7)
The internal loop compensation of the bq24187 is designed to be stable with 10µF to 150µF of local capacitance
but requires at least 20µF total capacitance on CS+. To reduce the output voltage ripple, a ceramic capacitor
with the capacitance between 20µF and 47µF is recommended for local bypass to CS+. If more than 100µF is
placed on CS+, place at least 10µF from BAT to GND.
9.2.3 Application Curves
Figure 17. Boost Startup No Load
32
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Figure 18. Boost Startup 1A Load
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Product Folder Links: bq24187
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bq24187
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SLUSBM0 – APRIL 2014
Figure 19. Boost Transient Response
Figure 20. Input OVP Event With INT
95.00%
Efficiency (%)
90.00%
85.00%
80.00%
VBAT = 4.2 V
VBAT = 3.6 V
75.00%
0.5
1.0
1.5
2.0
ICHG (A)
C002
VIN = 5 V
Figure 21. Boost Burst Mode During Light Load
TA = 25°C
Figure 22. Charger Efficiency vs Battery Voltage
100.00%
95.00%
80.00%
Efficiency (%)
Efficiency (%)
90.00%
85.00%
80.00%
60.00%
40.00%
20.00%
VBAT = 3.6 V
ICHG = 1A
ICHG = 2A
75.00%
2.5
3
3.5
4
4.5
VBAT (V)
VIN = 5 V
VBATREG = 4.44 V
VBAT = 4.2 V
0.00%
0.0
0.2
0.4
0.6
0.8
Load Current (A)
C001
1.0
C003
TA = 25°C
Figure 23. Charger Efficiency vs Charge Current
Figure 24. Boost Efficiency vs Load Current
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10 Layout
10.1 Layout Guidelines
It is important to pay special attention to the PCB layout. Figure 25 provides a sample layout for the high current
paths of the bq24187YFF.
The following provides some guidelines:
• Place 4.7µF input capacitor as close to IN terminal and PGND terminal as possible to make high frequency
current loop area as small as possible.
• Place 1µF input capacitor as close to PMID terminal and PGND terminal as possible to make high frequency
current loop area as small as possible. Connect the GND of the PMID and IN caps as close as possible.
• The local bypass capacitor from CS+ to GND should be connected between the CS+ terminal and PGND of
the IC. The intent is to minimize the current path loop area from the SW terminal through the LC filter and
back to the PGND terminal.
• Place all decoupling capacitor close to their respective IC terminal and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
• The high-current charge paths into IN, BAT, CS+ and from the SW terminals must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND terminals should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
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10.2 Layout Example
PMID and IN
CAP Gnds
PMID
Close together
PGND
IN Cap
SW
Close to
IN Terminal
BOOT
Thermal
CS+ Cap
Vias Connect
Close to
to PGND
CS+ Terminals
BAT Cap
Close to
BAT Terminals
Figure 25. Recommended bq24187 PCB Layout For WCSP Package
PGND
SW
PMID
PMID and IN
Cap Gnds
BOOT
Close together
CS+ Cap
Close to
IN Cap
CS+ Terminals
Close to
IN Terminal
BAT Cap
Close to
Thermal
BAT Terminals
Vias connect
To GND
Figure 26. Recommended bq24187 PCB Layout For QFN Package
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
High-efficiency, Switch-mode Battery Charge Evaluation Module User's Guide, SLUUAI5
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24187YFFR
NRND
DSBGA
YFF
36
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24187
BQ24187YFFT
NRND
DSBGA
YFF
36
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24187
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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