bq24273
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SLUSB08 – JUNE 2012
2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with
Integrated Current Sense
Check for Samples: bq24273
FEATURES
APPLICATIONS
•
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1
•
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High-Efficiency Switch Mode Charger with
Integrated Current Sense Element
Single Input Charger
– 20V input rating, with 10.5V Over-Voltage
Protection (OVP)
– Integrated FETs for Up to 2.5A Charge Rate
Integrated Charge Current Sense Element for
Reduced BOM Count and Board Space
Savings
Safe and accurate Battery Management
Functions
– 0.5% Battery Regulation Accuracy
– 10% Charge Current Accuracy
Voltage-based, NTC Monitoring Input (TS)
– JEITA Compatible
Thermal Regulation Protection for Output
Current Control
BAT Short-Circuit Protection
Soft-Start Feature to Reduce Inrush Current
Thermal Shutdown and Protection
Available in Small 49-ball WCSP or QFN-24
Packages
Handheld Prducts
Portable Media Players
Portable Equipment
Tablets and Portable Internet Devices
APPLICATION SCHEMATIC
IN
SW
PMID
BOOT
CS+
SDA
SCL
CD
HOST
`
BAT
INT
System
Load
BYP
PGND
TS
STAT
TEMP
PACK+
DRV
PACK-
DESCRIPTION
The bq24273 is a highly integrated single cell Li-Ion battery charger with integrated charge current sense
element device targeted for space-limited, portable applications with high capacity batteries. The single cell
charger operates from a dedicated power source such as a wall adapter or wireless power supply for a versatile
solution. The integrated sense element eliminates the need for an external sense resistor reducing the total
solution size and external component count.
The battery is charged in three phases: precharge, fast charge constant current and constant voltage. In all
charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if
the internal temperature threshold is exceeded. Charge is terminated based on user-selectable minimum current
level. A software watchdog provides a safety backup for I2C interface while a safety timer prevents continuously
charging a damaged battery. During normal operation, bq24273 automatically restarts the charge cycle if the
battery voltage falls below an internal threshold and automatically enters sleep mode or high impedance mode
when the input supply is removed. The charge status is reported to the host using the I2C interface. Additionally,
a voltage-based battery pack thermistor monitoring input (TS) is included that monitors battery temperature for
safe charging. The TS function for bq24273 JEITA compatible.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
bq24273
SLUSB08 – JUNE 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
OVP
NTC MONITORING
(TS)
JEITA COMPATIBLE
PACKAGE
bq24273YFFR
10.5 V
Yes
Yes
WCSP
bq24273YFFT
10.5 V
Yes
Yes
WCSP
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
IN
Pin voltage range (with
respect to VSS)
UNIT
–2
20
V
BYP, PMID, BOOT
–0.3
20
V
SW
–0.7
12
V
CS+, BAT, BGATE, DRV, STAT, INT, SDA, SCL, CD,TS
–0.3
7
V
–0.3
7
V
4.5
A
2.75
A
BOOT to SW
Output Current (Continuous)
SW
Input Current (Continuous)
IN
Output Sink Current
STAT, INT
10
mA
Operating free-air temperature range
–40
85
°C
Junction temperature, TJ
–40
125
°C
Storage temperature, TSTG
–65
150
°C
300
°C
Lead temperature (soldering, 10 s)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
THERMAL METRIC (1)
bq24273
49 PINS (YFF)
θJA
Junction-to-ambient thermal resistance
49.8
θJCtop
Junction-to-case (top) thermal resistance
0.2
θJB
Junction-to-board thermal resistance
1.1
ψJT
Junction-to-top characterization parameter
1.1
ψJB
Junction-to-board characterization parameter
6.6
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
UNITS
°C/W
spacer
(1)
2
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
MIN
VIN
4.2
18 (1)
IN operating range
4.2
10
IIN
Input current IN input
IBAT
Charging
TJ
Operating junction temperature range
(1)
MAX UNITS
IN voltage range
2.5
0
V
A
2.5
A
125
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight
layout minimizes switching noise.
ELECTRICAL CHARACTERISTICS
Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP,
PWM switching
TYP
MAX
UNITS
15
mA
IIN
Input quiescent current
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP,
PWM NOT switching
IBATLEAK
Leakage current from BAT to the supply
0°C< TJ < 85°C, VBAT = 4.2V, VIN = 0V
IBAT_HIZ
Battery discharge current in high impedance mode,
(BAT, SW)
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0 V or 5 V, High-Z
mode
5
0°C< TJ < 85°C, High-Z Mode
175
μA
5
μA
55
μA
BATTERY CHARGER
RON(BAT-CS+)
Measured from BAT to CS+,
VBAT = 4.2V
Internal battery charger MOSFET on-resistance
YFF pkg
37
57
RGE pkg
50
70
mΩ
Battery regulation voltage
VBATREG
TA = 25°C
Battery regulation voltage accuracy
Over temperature
3.5
4.44
–0.5%
0.5%
–1%
1%
550
2500
–10%
10%
Charge current programmable range
VBATSHRT < VBAT < VBATREG
Fast charge current accuracy
0°C to 125°C
VBATSHRT
Battery short threshold
VBAT Rising, 100 mV Hysteresis
IBATSHRT
Battery short current
VBAT < VBATSHRT
tDGL(BATSHRT)
Deglitch time for battery short to fast charge transition
ITERM
Termination charge current accuracy
tDGL(TERM)
Deglitch time for charge termination
Both rising and falling, 2-mV over-drive,
tRISE, tFALL = 100 ns
VRCH
Recharge threshold voltage
Below VBATREG
tDGL(RCH)
Deglitch time
VBAT falling below VRCH, tFALL = 100ns
During battery detection source cycle
3.3
During battery detection sink cycle
3.0
ICHARGE
VDETECT
Battery detection voltage threshold
IDETECT
Battery detection current before charge done (sink
current)
tDETECT
Battery detection time
VIH(CD)
CD input high logic level
VIL(CD)
CD input low logic level
2.9
3.0
3.1
50.0
–35%
ICHARGE > 50 mA
–15%
mA
V
mA
32
ICHARGE = 50 mA
V
ms
35%
15%
32
ms
120
mV
32
ms
V
2.5
mA
250
ms
1.3
V
0.4
V
INPUT PROTECTION
IINLIM
VIN_DPM
Input current limit
VIN=5V, DC current pulled from SW
IINLIM = 1.5 A
1.35
1.5
1.65
IINLIM = 2.5 A
2.3
2.5
2.8
A
Input DPM threshold
4.2
4.76
Input DPM accuracy
–2%
2%
VDRV
Internal bias regulator voltage
IDRV
DRV Output current
5
VDO_DRV
DRV Dropout voltage (VIN – VDRV)
IIN = 1A, VIN = 5V, IDRV = 10mA
VUVLO
IC active threshold voltage
VIN rising, 150 mV hysteresis
VSLP
Sleep-mode entry threshold, VIN-VBAT
2.0 V ≤ VBAT ≤ VOREG, VIN falling
VSLP_EXIT
Sleep-mode exit hysteresis
2.0 V ≤ VBAT ≤ VOREG
5.2
5.45
10
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V
mA
450
mV
3.6
3.8
4.0
V
0
40
100
mV
40
100
160
mV
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Deglitch time for supply rising above
VSLP+VSLP_EXIT
Rising voltage, 2-mV over drive, tRISE=100ns
VOVP
Input supply OVP threshold voltage
IN, VIN Rising, 100 mV hysteresis
VBOVP
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger during charge
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
TYP
MAX
30
UNITS
ms
10.3
10.5
10.7
V
1.025 ×
VBATREG
1.05 ×
VBATREG
1.075 ×
VBATREG
V
% of
VBATREG
1
VBATUVLO
Battery UVLO threshold voltage
2.5
V
VBAT_SOURCE
Bad source detection threshold
VIN_DPM –
80mV
V
Bad source detection deglitch
ILIMIT
Cycle by cycle current limit
TSHUTDWN
Thermal shutdown
TREG
Thermal regulation threshold
32
4.1
10°C Hysteresis
4.9
ms
5.6
165
120
Safety timer accuracy
–20%
A
C
C
20%
STAT, INT
IIH
High-level leakage current
V/CHG = V/PG = 5 V
VOL
Low-level output saturation voltage
IO = 10 mA, sink current
1
µA
0.4
V
PWM CONVERTER
Internal top reverse blocking MOSFET on-resistance
IIN_LIMIT = 1.5 A, Measured from VIN to PMIDU
45
80
mΩ
Internal top N-channel Switching MOSFET onresistance
Measured from PMID to SW
65
110
mΩ
Internal bottom N-channel MOSFET on-resistance
Measured from SW to PGND
fOSC
Oscillator frequency
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
1.35
65
115
mΩ
1.50
1.65
MHz
95%
0
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VWARM
VCOOL
Low temperature threshold
VCOLD
VTS falling, 1%VDRV Hysteresis
VTS rising, 1%VDRV Hysteresis
30
30.5
%VDRV
37.9
38.3
39.6
%VDRV
56.0
56.5
56.9
%VDRV
59.5
60
60.4
%VDRV
73
%VDRV
VTSOFF
TS Disable threshold
tDGL(TS)
Deglitch time on TS change
VIH
Input high threshold
VPULLUP = 1.8 V, SDA and SCL
VIL
Input low threshold
VPULLUP = 1.8 V, SDA and SCL
0.4
VOL
Output low threshold
ISDA = 10 mA, sink current
0.4
IIH
Input high leakage current
VPULLUP = 1.8 V, SDA and SCL
tWATCHDOG
Watchdog timer timeout
4
VTS rising, 2%VDRV Hysteresis
29.7
70
50
V
1
30
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ms
1.3
V
V
µA
s
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SLUSB08 – JUNE 2012
BLOCK DIAGRAM
PMID
BYP
5.2V
Reference
DRV
IN
5A
+
BOOT
CbC Current
Limit
IN IINLIM
Q1
IN VINDPM
DC-DC CONVERTER PWM LOGIC,
COMPENSATION AND BATTERY
FET CONTROL
VSYS(REG)
IBAT(REG)
VBAT(REG)
SW
DIE Temp
Regulation
Q2
PGND
CS+
VSUPPLY References
10% of
ICHARGE
+
OVP
Comparator
+
VIN
VINOVP
Termination
Comparator
IBAT
BAT
Recharge Comparator
VIN
VBAT +VSLP
Start Recharge
Cycle
+
Sleep
Comparator
+
VBATREG – 0.12V
VBAT
VSYSREG Comparator
+
VSYS
Enable Linear
Charge
VMINSYS
VBATSC Comparator
SDA
SCL
Enable
I BATSHRT
I2C
Interface
+
VBAT
VBATSHRT
TS
Supplement COMPARATOR
+
VSYS
VBAT
VBSUP
VDRV
VBOVP Comparator
+
VBAT
VBATOVP
CD
+
DISABLE
TS COLD
1C/
0.5 C
+
TS COOL
+
4..2V/4.06 V
STAT
TS WARM
+
DISABLE
INT
CHARGE
CONTROLLER
TS HOT
w/ Timer
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PIN CONFIGURATION
49-Ball WCSP (Top View)
1
2
3
4
6
5
7
A
IN
IN
IN
IN
GND
GND
GND
B
PMIDI
PMIDI
PMIDI
PMIDI
BYP
BYP
BYP
C
SW
SW
SW
SW
SW
SW
SW
D
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E
PGND
N.C.
N.C.
CD
SDA
SCL
BOOT
CS+
CS+
CS+
CS+
N.C.
INT
DRV
BAT
BAT
BAT
BAT
TS
STAT
PGND
F
G
PIN FUNCTIONS
PIN
NAME
bq24273 (YFF)
I/O
DESCRIPTION
IN
A1-A4
I
Input Power Supply. IN is connected to the external DC supply (AC adapter). Bypass IN to PGND
with at least a 1μF ceramic capacitor.
GND
A5-A7
I
Ground. Connect to ground plane.
PMID
B1-B4
O
Reverse Blocking MOSFET and High Side MOSFET Connection Point for the input. Bypass PMID
to GND with at least a 4.7μF ceramic capacitor. Use caution when connecting an external load to
PMID. The PMID output is not current limited. Any short on PMID will result in damage to the IC.
BYP
B5-B7
O
Bypass for internal circuits. Bypass BYP to GND with at least 0.1µF of capacitance. Do not
connect any external load to BYP.
SW
C1-C7
O
Inductor Connection. Connect to the switched side of the external inductor.
PGND
D1-D7, E1, G7
--
Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
N.C.
E2-E3, F5
No Connection. Leave N.C. unconnected.
CD
E4
IC Hardware Disable Input – Drive CD high to place the bq24273 in high-z mode. Drive CD low for
normal operation. Do not leave CD unconnected.
SDA
E5
I2C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor.
SCL
E6
I2C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor.
BOOT
E7
I
High Side MOSFET Gate Driver Supply. Connect a 0.01μF ceramic capacitor (voltage rating >
10V) from BOOT to SW to supply the gate drive for the high side MOSFETs.
CS+
F1-F4
I
Current Sense Input. High side connection to internal current sense element. Bypass CS+ locally
with at least 10µF of ceramic capacitance for stability.
Status Output – INT is an open-drain output that signals charging status and fault interrupts. INT
pulls low during charging. INT is high impedance when charging is complete or the charger is
disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through
a 100kΩ resistor to communicate with the host processor
INT
F6
DRV
F7
O
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. bypass
DRV to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to
10mA. DRV is active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP)
BAT
G1-G4
I/O
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to
GND with a 1μF capacitor.
6
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PIN FUNCTIONS (continued)
PIN
NAME
bq24273 (YFF)
TS
G5
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND.
The NTC is connected from TS to GND. The TS function in the bq24276 provides 2 thresholds for
Hot/ Cold shutoff, while the bq24277 has 2 additional thresholds for JEITA compliance. See the
NTC Monitor section for more details on operation and selecting the resistor values.
G6
Status Output – STAT is an open-drain output that signals charging status and fault interrupts.
STAT pulls low during charging. STAT is high impedance when charging is complete or the
charger is disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host.
STAT is enabled/ disabled using the EN_STAT bit in the control register. Pull STAT up to a logic
rail through an LED for visual indication or through a 10kΩ resistor to communicate with the host
processor.
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of
the device. The thermal pad must be connected to the same potential as the VSS pin on the
printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS
pin must be connected to ground at all times.
STAT
Thermal
Pad
I/O
–
DESCRIPTION
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TYPICAL APPLICATION CIRCUIT
IN
SW
PMID
BOOT
CS+
SDA
`
SCL
CD
HOST
BAT
INT
System
Load
BYP
PGND
TS
STAT
TEMP
PACK+
DRV
PACK-
Figure 1. bq24273 Application Circuit
8
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DETAILED DESCRIPTION
The bq24273 is a highly integrated synchronous switch-mode charger featuring integrated MOSFETs and current
sense element reducing the count of external components. It is targeted at portable applications with higher
capacity batterires powered by 1-cell Li-Ion, LiFePO4 or Li-polymer battery pack. Due to the high efficiency in a
wide range of the input voltage and battery voltage, the switching mode charger is a good choice for high speed
charging with less power loss and better thermal management.
The bq24273 has two operation states: charge state and high impedance state. In the charge state, the bq24273
supports a precision Li-ion, LiFePO4 or Li-polymer charging system for single-cell applications. In the high
impedance state, the bq24273 stops charging and operates in a mode with very low current from IN and battery,
to effectively reduce the power consumption when the portable device is in standby mode.
The bq24273 includes an integrated 35mΩ sense resistor that is used to measure the charge current into the
battery. As resistors are expected to have a temperature coefficient, the bq24273 includes a compensation
mechanism that maintains the accuracy of the charge current as the temperature changes. This allows for a
smaller BOM solution allowing the removal of an external high accuracy sense resistor that are typically needed
for non-power path charger solutions.
Charge Mode Operation
Charge Profile
There are 5 loops that influence the charge current; constant current loop (CC), constant voltage loop (CV),
thermal regulation loop, input current sense loop and input voltage dynamic power management loop (VIN-DPM).
During the charging process, all five loops are enabled and the one that is dominate takes control. The bq24273
supports a precision LiFePO4, Li-Ion or Li-Polymer charging systems for single-cell applications. Figure 2 shows
a typical charge profile.
Regulation
Voltage
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
Voltage
Regulation
Current
Charge Voltage
Charge Voltage
VSHORT
VSHORT
Charge Current
Termination
Termination
ISHORT
Precharge
(Linear Charge)
Charge Current
ISHORT
Fast Charge
(PWM Charge)
Fast Charge
(PWM Charge)
Precharge
(Linear Charge)
(a) Not input current limited
(b) Input current limited
Figure 2. Typical Charging Profile of bq24273
PWM Controller in Charge Mode
The bq24273 provides an integrated, fixed-frequency 1.5MHz voltage-mode controller to supply the charge
current. The voltage loop is internally compensated and provides enough phase margin for stable operation,
allowing the use of small ceramic capacitors with very low ESR.
The input is protected from short circuit by a cycle-by-cycle current limit that is sensed through the high-side
MOSFET. The threshold is set to a nominal 5-A peak current. The input also utilizes an input current limit that
limits the current from the power source.
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Battery Charging Process
When the battery is deeply discharged or shorted (VBAT VCOLD. When VHOT <
VTS < VWARM, the battery regulation voltage is reduced by 140mV from the programmed regulation threshold.
When VCOOL < VTS < VCOLD, the charging current is reduced to half of the programmed charge current.
The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 5. The resistor values are
calculated using the following equations:
é 1
1 ù
VDRV ´ RCOLD ´ RHOT ´ ê
ú
ë VCOLD VHOT û
RLO =
éV
ù
é V
ù
RHOT ´ ê DRV - 1ú - RCOLD ´ ê DRV - 1ú
ë VHOT
û
ë VCOLD
û
12
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VDRV
-1
VCOLD
RHI =
1
1
+
RLO RCOLD
(2)
Where:
VCOLD = 0.60 × VDRV
VHOT = 0.30 × VDRV
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold
temperature.
The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC
resistances for a selected resistor divider are calculated using the following equations:
RLO ´ 0.564 ´ RHI
RCOOL =
RLO - RLO ´ 0.564 - RHI´ 0.564
(3)
RLO ´ 0.383 ´ RHI
RWARM =
RLO - RLO ´ 0.383 - RHI ´ 0.383
(4)
DISABLE
VBAT( REG)
– 140mV
1 x Charge/
0.5 x Charge
TS COLD
TS COOL
TS WARM
VDRV
+
+
+
VDRV
TS HOT
RHI
+
TS
TEMP
PACK+
bq242702
RLW
PACK-
Figure 5. TS Circuit
Thermal Regulation and Protection
During the charging process, to prevent chip overheating, bq24273 monitors the junction temperature, TJ, of the
die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG. The
charge current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the
charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq24273 if the die temperature rises too high. At any state, if
TJ exceeds TSHTDWN, bq24273 suspends charging and disables the buck converter. During thermal shutdown
mode, the PWM is turned off, all timers are suspended, and a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A new charging cycle
begins when TJ falls below TSHTDWN by approximately 10°C.
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Input Voltage Protection in Charge Mode
Sleep Mode
The bq24273 enters the low-power sleep mode if the voltage on VSUPPLY falls below sleep-mode entry threshold,
VBAT+VSLP, and VVBUS is higher than the undervoltage lockout threshold, VUVLO. This feature prevents draining
the battery during the absence of VSUPPLY. When VSUPPLY < VBAT+ VSLP, the bq24273 turns off the PWM
converter and sends a single 128μs pulse on the STAT and INT outputs and updates the STATx and FAULT_x
bits in the status registers. Once VSUPPLY > VBAT+ VSLP, the STATx and FAULT_x bits are cleared and the device
initiates a new charge cycle.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage will decease. Once the supply drops to VIN_DPM (default 4.76V), the input
current limit is reduced down to prevent further supply droop. When the IC enters this mode, the charge current
is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature ensures IC
compatibility with adapters with different current capabilities without a hardware change.
Bad Source Detection
When a source is connected to IN, the bq24273 runs a Bad Source Detection procedure to determine if the
source is strong enough to provide some current to charge the battery. A current sink is turned on (75mA) for
32ms. If the source is valid after the 32ms (VBADSOURCE < VSUPPLY < VOVP), the buck converter starts up and
normal operation continues. If the supply voltage falls below VBAD_SOURCE during the detection, the current sink
shuts off for 2s and then retries, a single 128μs pulse is sent on the STAT and INT outputs and the STATx and
FAULT_x bits of the status registers and the battery/supply status registers are updated in the I2C. The detection
circuits retries continuously until a valid source is detected after the detection time. If during normal operation the
source falls to VBAD_SOURCE, the bq24273 turns off the PWM converter and sends a single 128μs pulse is sent on
the STAT and INT outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status
registers are updated in the I2C. Once a good source is detected, the STATx and FAULT_x bits are cleared and
the device returns to normal operation.
Input Over-Voltage Protection
The bq24273 provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). During normal operation, if VSUPPLY > VOVP, the bq24273 turns off the
PWM converter and sends a single 128μs pulse is sent on the STAT and INT outputs and the STATx and
FAULT_x bits of the status registers and the battery/supply status registers are updated in the I2C. Once the
OVP fault is removed, the STATx and FAULT_x bits are cleared and the device returns to normal operation.
To allow operation with some unregulated adapters, the OVP circuit is not active during Bad Source Detection.
This provides some time for the current sink to pull the unregulated adapter down into an acceptable range. If the
adapter voltage is high at the end of the detection, the startup of the PWM converter does not occur. The OVP
circuit is active during normal operation, so if the system standby current plus the charge current is not enough to
pull down the source, operation is suspended.
Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for bq24273. STAT is pulled low during charging when
EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is high
impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT
during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication or can
be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to
enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be
shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.
Table 1. STAT Pin Summary
Charge State
STAT and INT behavior
Charge in progress and EN_STAT=1
Low
Other normal conditions
High-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault,
watchdog expiration, sleep mode, battery temperature fault (TS), battery fault (OVP or
absent), thermal shutdown
128-µs pulse, then High Impedance
14
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SERIAL INTERFACE DESCRIPTION
The bq24273 uses an I2C compatible interface to program charge parameters. I2C™ is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device.
The bq24273 device works as a slave and supports the following data transfer modes, as defined in the I2C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charging solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as battery voltage remains
above 2.5 V (typical). The I2C circuitry is powered from IN when a supply is connected. If the IN supply is not
connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above 2.5V
with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24273 devices only support 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (6Bh).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 6. All I2C -compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 6. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 7). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 8) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 7. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high ( see Figure 9). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section result in FFh being read out.
Data output
by Transmitter
Not Acknowledge
Data output
by Receiver
Acknowledge
1
SCL From
Master
2
9
8
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 8. Acknowledge on the I2C Bus
Recognize START or
REPRATED START
Condition
Recognize STOP or
REPRATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
1
2
7
8
9
1
2
ACK
3-8
9
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
Figure 9. Bus Protocol
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REGISTER DESCRIPTION
Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 0xxx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
TMR_RST
Read/Write
Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
B6
STAT_2
Read only
B5
STAT_1
Read only
B4
STAT_0
Read only
000001010011100101110111-
B3
NA
Read/Write
0-Set always to 0
B2
FAULT_2
Read only
B1
FAULT_1
Read only
B0(LSB)
FAULT_0
Read only
000-Normal
001- Thermal Shutdown
010- Battery Temperature Fault
011- Watchdog Timer Expired
100- Safety Timer Expired
101- Supply Fault
110- NA
111- Battery Fault
No Valid Source Detected
IN Ready
NA
Charging
NA
Charge Done
NA
Fault
Battery/ Supply Status Register (READ/WRITE)
Memory location: 01, Reset state: xxxx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
INSTAT1
Read Only
B6
INSTAT0
Read Only
00-Normal
01-Supply OVP
10-Weak Source Connected (No Charging)
11- VIN THOT(Charging suspended)
10— TCOOL > TS temp > TCOLD (Charge current reduced by half, bq24273 only)
11— TWARM < TS temp < THOT (Charge voltage reduced by 140mV, bq24273 only)
B0(LSB)
LOW_CHG
Read/Write
0 – Charge current as programmed in Register 0x05
1 – Charge current half programmed value in Register 0x05 (default 0)
LOW_CHG Bit (Low Charge Mode Enable)
The LOW_CHG bit is used to reduce the charge current to half of the programmed value. This feature is used by
systems where battery NTC is monitored by the host and requires a reduced charge current setting or by
systems that need a “preconditioning” current for low battery voltages. Write a “1” to this bit to charge at half of
the programmed charge current. Write a “0” to this bit to charge at the programmed charge current.
20
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APPLICATION INFORMATION
OUTPUT INDUCTOR AND CAPACITOR SELECTION GUIDELINES
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq24273 is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use equation 2 to calculate the peak current.
æ %
ö
IPEAK = ILOAD (MAX ) ´ ç1 + RIPPPLE ÷
2
è
ø
(5)
The inductor selected must have a saturation current rating less than or equal to the calculated IPEAK. Due to the
high currents possible with the bq24273, a thermal analysis must also be done for the inductor. Many inductors
have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise above the
ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty
cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of
the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D ´ I (PEAK -ILOAD ) = 1.5A + 0.2 ´ (2.5A - 1.5A) = 1.7A
(6)
The bq24273 provides internal loop compensation. Using this scheme, the bq24273 is stable with 10µF to 200µF
of local capacitance. The capacitance on the BAT rail can be higher if distributed amongst the rail. To reduce the
output voltage ripple, a ceramic capacitor with the capacitance between 10µF and 47µF is recommended for
local bypass to CS+.
PCB LAYOUT GUIDELINES
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq24273
• Place 4.7µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID_.
• The local bypass capacitor from CS+ to GND should be connected between the CS+ pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
• Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
• The high-current charge paths into IN, BAT, CS+ and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
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Sample Layout
IN
PMID
GND
SW
SW
PGND
BOOT
ILIM
SYS
BAT
ISET
PGND
SW
SYS
(YFF Package)
Figure 10. PCB Layout Example
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ24273YFFR
ACTIVE
DSBGA
YFF
49
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24273
BQ24273YFFT
ACTIVE
DSBGA
YFF
49
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24273
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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