BQ4850YMA-85

bq4850Y RTC Module With 512Kx8 NVSRAM Features General Description ➤ Integrated SRAM, real-time clock, crystal, power-fail control circuit, and battery The bq4850Y RTC Module is a nonvolatile 4,194,304-bit SRAM organized as 524,288 words by 8 bits with an integral accessible real-time clock. ➤ Real-Time Clock counts seconds through years in BCD format ➤ RAM-like clock access ➤ Pin-compatible with industrystandard 512K x 8 SRAMs ➤ Unlimited write cycles ➤ 10-year minimum data retention and clock operation in the absence of power ➤ Automatic power-fail chip deselect and write-protection ➤ Software clock calibration for grea t e r t han ± 1 m inut e pe r month accuracy The device combines an internal lithium battery, quartz crystal, clock and power-fail chip, and a full CMOS SRAM in a plastic 32-pin DIP module. The RTC Module directly replaces industry-standard SRAMs and also fits into many EPROM and EEPROM sockets without any requirement for special write timing or limitations on the number of write cycles. Registers for the real-time clock, alarm and other special functions are located in registers 7FFF8h– 7FFFFh of the memory array. Pin Connections A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 The clock and alarm registers are dual-port read/write SRAM locations that are updated once per second by a clock control circuit from the internal clock counters. The dual-port registers allow clock updates to occur without interrupting normal access to the rest of the SRAM array. The bq4850Y also contains a powerfail-detect circuit. The circuit deselects the device whenever VCC falls below tolerance, providing a high degree of data security. The battery is electrically isolated when shipped from the factory to provide maximum battery capacity. The battery remains disconnected until the first application of VCC. Pin Names 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 32-Pin DIP Module PN485001.eps Aug. 1996 1 A0–A18 Address input CE Chip enable WE Write enable OE Output enable DQ0–DQ7 Data in/data out VCC +5 volts VSS Ground bq4850Y including memory and clock interface, and dataretention modes. Functional Description Figure 1 is a block diagram of the bq4850Y. The following sections describe the bq4850Y functional operation, TimeBase Oscillator Internal Quartz Crystal 7 AD 0-AD 18 . -. 64 4 3 CE OE DQ0 -DQ . -. 8 . -. 64 16 : 1 MUX Control/Status Registers P Bus I/F Clock Alarm and Calendar Bytes Clock/Calendar Update User Buffer (8 Bytes) WE Storage Registers (524,288 Bytes) VCC Internal Battery PowerFail Control WriteProtect BD-961 Figure 1. Block Diagram Truth Table VCC CE OE WE Mode DQ Power < VCC (max.) VIH X X Deselect High Z Standby VIL X VIL Write DIN Active VIL VIL VIH Read DOUT Active VIL VIH VIH Read High Z Active < VPFD (min.) > VSO X X X Deselect High Z CMOS standby ≤ VSO X X X Deselect High Z Battery-backup mode > VCC (min.) Aug. 1996 2 bq4850Y Figure 2 illustrates the address map for the bq4850Y. Table 1 is a map of the bq4850Y registers. Address Map The bq4850Y provides 8 bytes of clock and control status registers and 524,288 bytes of storage RAM. 8 Bytes 32,760 Bytes Clock and 7FFFF Control Status Registers 7FFF8 0 Year 7FFFF 1 Month 7FFFE 7FFF7 2 Date 7FFFD 3 Days 7FFFC 4 Hours 7FFFB 5 Minutes 7FFFA 6 Seconds 7FFF9 7 Control 7FFF8 Storage RAM 0000 MM-961 Figure 2. Address Map Table 1. bq4850Y Clock and Control Register Map Address D7 D6 7FFFF D5 D4 D3 D2 10 Years Range (h) Register Year 00–99 Year Month 01–12 Month Date 01–31 Date 01–07 Days Hours 00–23 Hours X X 7FFFD X X 7FFFC X FTE 7FFFB X X 7FFFA X 10 Minutes Minutes 00–59 Minutes 7FFF9 OSC 10 Seconds Seconds 00–59 Seconds 7FFF8 W 00–31 Control Notes: 10 Month D0 7FFFE R X D1 10 Date X X X Day 10 Hours S Calibration X = Unused bits; can be written and read. Clock/Calendar data in 24-hour BCD format. OSC = 1 stops the clock oscillator. Aug. 1996 3 bq4850Y The internal coin cell maintains data in the bq4850Y after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and Vcc rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write-protection continues for tCER after VCC reaches VPFD to allow for processor stabilization. After tCER, normal RAM operation can resume. Memory Interface Read Mode The bq4850Y is in read mode whenever OE (output enable) is low and CE (chip enable) is low. The device architecture allows ripple-through access of data from eight of 4,194,304 locations in the static storage array. Thus, the unique address specified by the 19 address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data is available at the data I/O pins within tAA (address access time) after the last address input signal is stable, providing that the CE and OE (output enable) access times are also satisfied. If the CE and OE access times are not met, valid data is available after the latter of chip enable access time (tACE) or output enable access time (tOE). Clock Interface Reading the Clock The interface to the clock and control registers of the bq4850Y is the same as that for the general-purpose storage memory. Once every second, the user-accessible clock/calendar locations are updated simultaneously from the internal real time counters. To prevent reading data in transition, updates to the bq4850Y clock registers should be halted. Updating is halted by setting the read bit D6 of the control register to 1. As long as the read bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory locations, the read bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the read bit, reading the clock locations has no effect on clock accuracy. Once the read bit is reset to 0, within one second the internal registers update the user-accessible registers with the correct time. A halt command issued during a clock update allows the update to occur before freezing the data. CE and OE control the state of the eight three-state data I/O signals. If the outputs are activated before tAA, the data lines are driven to an indeterminate state until tAA. If the address inputs are changed while CE and OE remain low, output data remains valid for tOH (output data hold time), but goes indeterminate until the next address access. Write Mode The bq4850Y is in write mode whenever WE and CE are active. The start of a write is referenced from the latter-occurring falling edge of WE or CE. A write is terminated by the earlier rising edge of WE or CE. The addresses must be held valid throughout the cycle. CE or WE must return high for a minimum of tWR2 from CE or tWR1 from WE prior to the initiation of another read or write cycle. Setting the Clock Bit D7 of the control register is the write bit. Like the read bit, the write bit when set to a 1 halts updates to the clock/calendar memory locations. Once frozen, the locations can be written with the desired information in 24-hour BCD format. Resetting the write bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible registers to resume within one second. Use the write bit, D7, only when updating the time registers (7FFFF–7FFF9). Data-in must be valid tDW prior to the end of write and remain valid for tDH1 or tDH2 afterward. OE should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on CE and OE, a low on WE disables the outputs tWZ after WE falls. Data-Retention Mode With valid V CC applied, the bq4850Y operates as a conventional static RAM. Should the supply voltage decay, the RAM automatically power-fail deselects, write-protecting itself tWPT after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as “don’t care.” Stopping and Starting the Clock Oscillator The OSC bit in the seconds register turns the clock on or off. If the bq4850Y is to spend a significant period of time in storage, the clock oscillator can be turned off to preserve battery capacity. OSC set to 1 stops the clock oscillator. When OSC is reset to 0, the clock oscillator is turned on and clock updates to user-accessible memory locations occur within one second. If power-fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within time t WPT, writeprotection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source, which preserves data. The OSC bit is set to 1 when shipped from the Benchmarq factory. Aug. 1996 4 bq4850Y Calibrating the Clock 0 The bq4850Y real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The quartz crystal is contained within the bq4850Y package along with the battery. The clock accuracy of the bq4850Y module is tested to be within 20ppm or about 1 minute per month at 25°C. The oscillation rates of crystals change with temperature as Figure 3 shows. To compensate for the frequency shift, the bq4850Y offers onboard software clock calibration. The user can adjust the calibration based on the typical operating temperature of individual applications. Frequency Error -20 -40 -60 -80 -100 -120 -30 -20 -10 0 10 20 30 40 50 60 70 The software calibration bits are located in the control register. Bits D0–D4 control the magnitude of correction, and bit D5 the direction (positive or negative) of correction. Assuming that the oscillator is running at exactly 32,786 Hz, each calibration step of D0–D4 adjusts the clock rate by +4.068 ppm (+10.7 seconds per month) or -2.034 ppm (-5.35 seconds per month) depending on the value of the sign bit D5. When the sign bit is 1, positive adjustment occurs; a 0 activates negative adjustment. The total range of clock calibration is +5.5 or -2.75 minutes per month. Temperature ( C) GR485001 Figure 3. Frequency Error ister is set to a 1, and the oscillator is running at exactly 32,768 Hz, the LSB of the seconds register toggles at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz indicates a (1E6∗0.01024)/512 or +20 ppm oscillator frequency error, requiring ten steps of negative calibration (10∗-2.034 or -20.34) or 001010 to be loaded into the calibration byte for correction. To read the test frequency, the bq4850Y must be selected and held in an extended read of the seconds register, location 7FFF9, without having the read bit set. The frequency appears on DQ0. The FTE bit must be set using the write bit control. The FTE bit must be reset to 0 for normal clock operation to resume. Two methods can be used to ascertain how much calibration a given bq4850Y may require in a system. The first involves simply setting the clock, letting it run for a month, and then comparing the time to an accurate known reference like WWV radio broadcasts. Based on the variation to the standard, the end user can adjust the clock to match the system’s environment even after the product is packaged in a non-serviceable enclosure. The only requirement is a utility that allows the end user to access the calibration bits in the control register. The second approach uses a bq4850Y test mode. When the frequency test mode enable bit FTE in the days reg- Aug. 1996 5 bq4850Y Absolute Maximum Ratings Symbol Parameter Value Unit VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 to 7.0 V TOPR Operating temperature 0 to +70 °C TSTG Storage temperature (VCC off; oscillator off) -40 to +70 °C TBIAS Temperature under bias -10 to +70 °C TSOLDER Soldering temperature +260 °C Note: Conditions VT ≤ VCC + 0.3 For 10 seconds Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Recommended DC Operating Conditions (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit VCC Supply voltage 4.5 5.0 5.5 V VSS Supply voltage 0 0 0 V VIL Input low voltage -0.3 - 0.8 V VIH Input high voltage 2.2 - VCC + 0.3 V Note: Notes Typical values indicate operation at TA = 25°C. Aug. 1996 6 bq4850Y DC Electrical Characteristics (TA = TOPR, VCCmin Symbol Parameter ≤ VCC ≤ VCCmax) Minimum Typical Maximum Unit Conditions/Notes ILI Input leakage current - - ±1 µA VIN = VSS to VCC ILO Output leakage current - - ±1 µA CE = VIH or OE = VIH or WE = VIL VOH Output high voltage 2.4 - - V IOH = -1.0 mA VOL Output low voltage - - 0.4 V IOL = 2.1 mA ISB1 Standby supply current - 3 5 mA CE = VIH ISB2 Standby supply current - 0.1 1 mA CE ≥ VCC - 0.2V, 0V ≤ VIN ≤ 0.2V, or VIN ≥ VCC - 0.2V ICC Operating supply current - - 90 mA Min. cycle, duty = 100%, CE = VIL, II/O = 0mA VPFD Power-fail-detect voltage 4.30 4.37 4.50 V VSO Supply switch-over voltage - 3 - V Note: Typical values indicate operation at TA = 25°C, VCC = 5V. Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V) Symbol Parameter Minimum Typical Maximum Unit CI/O Input/output capacitance - - 10 pF Output voltage = 0V CIN Input capacitance - - 10 pF Input voltage = 0V Note: These parameters are sampled and not 100% tested. Aug. 1996 7 Conditions bq4850Y AC Test Conditions Parameter Test Conditions Input pulse levels 0V to 3.0V Input rise and fall times 5 ns Input and output timing reference levels 1.5 V (unless otherwise specified) Output load (including scope and jig) See Figures 4 and 5 Figure 4. Output Load A Read Cycle Figure 5. Output Load B (TA = TOPR, VCCmin ≤ VCC ≤ VCCMAX) –85 Symbol Parameter Min. Max. Unit 85 - ns Conditions tRC Read cycle time tAA Address access time - 85 ns Output load A tACE Chip enable access time - 85 ns Output load A tOE Output enable to output valid - 45 ns Output load A tCLZ Chip enable to output in low Z 5 - ns Output load B tOLZ Output enable to output in low Z 0 - ns Output load B tCHZ Chip disable to output in high Z 0 35 ns Output load B tOHZ Output disable to output in high Z 0 25 ns Output load B tOH Output hold from address change 10 - ns Output load A Aug. 1996 8 bq4850Y Read Cycle No. 1 (Address Access) 1,2 Read Cycle No. 2 (CE Access) 1,3,4 Read Cycle No. 3 (OE Access) 1,5 Notes: 1. WE is held high for a read cycle. 2. Device is continuously selected: CE = OE = VIL. 3. Address is valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Device is continuously selected: CE = VIL. Aug. 1996 9 bq4850Y Write Cycle (TA =TOPR , VCCMIN ≤ VCC ≤ VCCMAX) –85 Symbol Parameter Min. Max. Units Conditions/Notes tWC Write cycle time 85 - ns tCW Chip enable to end of write 75 - ns (1) tAW Address valid to end of write 75 - ns (1) tAS Address setup time 0 - ns Measured from address valid to beginning of write. (2) tWP Write pulse width 65 - ns Measured from beginning of write to end of write. (1) tWR1 Write recovery time (write cycle 1) 5 - ns Measured from WE going high to end of write cycle. (3) tWR2 Write recovery time (write cycle 2) 15 - ns Measured from CE going high to end of write cycle. (3) tDW Data valid to end of write 35 - ns Measured to first low-to-high transition of either CE or WE. tDH1 Data hold time (write cycle 1) 0 - ns Measured from WE going high to end of write cycle. (4) tDH2 Data hold time (write cycle 2) 10 - ns Measured from CE going high to end of write cycle. (4) tWZ Write enabled to output in high Z 0 30 ns I/O pins are in output state. (5) tOW Output active from end of write 0 - ns I/O pins are in output state. (5) Notes: 1. A write ends at the earlier transition of CE going high and WE going high. 2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low. 3. Either tWR1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state. Aug. 1996 10 bq4850Y Write Cycle No. 1 (WE-Controlled) 1,2,3 Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5 Notes: 1. CE or WE must be high during address transition. 2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tWR2 must be met. 5. Either tDH1 or tDH2 must be met. Aug. 1996 11 bq4850Y Power-Down/Power-Up Cycle (TA = TOPR) Symbol Minimum Typical Maximum Unit tPF VCC slew, 4.50 to 4.20 V 300 - - µs tFS VCC slew, 4.20 to VSO 10 - - µs tPU VCC slew, VSO to VPFD (max.) 0 - - µs tCER Chip enable recovery time 40 100 200 ms tDR Data-retention time in absence of VCC 10 - - years tWPT Write-protect time 40 100 160 µs Notes: Parameter Conditions Time during which SRAM is write-protected after VCC passes VFPD on power-up. TA = 25°C. (2) Delay after VCC slews down past VPFD before SRAM is write-protected. 1. Typical values indicate operation at TA = 25°C, VCC = 5V. 2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the accumulated time in absence of power beginning when power is first applied to the device. Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down/Power-Up Timing 1 Aug. 1996 12 bq4850Y MA: 32-Pin A-Type Module 32-Pin MA (A-Type Module) Inches Aug. 1996 13 Millimeters Dimension Min. Max. Min. Max. 9.53 A 0.365 0.375 9.27 A1 0.015 - 0.38 - B 0.017 0.023 0.43 0.58 C 0.008 0.013 0.20 0.33 D 1.670 1.700 42.42 43.18 E 0.710 0.740 18.03 18.80 e 0.590 0.630 14.99 16.00 G 0.090 0.110 2.29 2.79 L 0.120 0.150 3.05 3.81 S 0.075 0.110 1.91 2.79 bq4850Y Ordering Information bq4850Y MA Speed Options: 85 = 85 ns Package Option: MA = A-type module Device: bq4850Y 512K x 8 Real-Time Clock Module Aug. 1996 14 Notes 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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