CC2564CRVMT

Product Folder Order Now Technical Documents Tools & Software Support & Community CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 CC2564C Dual-Mode Bluetooth® Controller 1 Device Overview 1.1 Features 1 • TI's Single-Chip Bluetooth® Solution With Bluetooth Basic Rate (BR), Enhanced Data Rate (EDR), and Low Energy (LE) Support • Bluetooth 5.1 Delaration ID D049226 • Highly Optimized for Size-Constrained and LowCost Designs: – Single-Ended 50-Ω RF Interface – VQFNP-MR Package Family, RVM Footprint: 76 Terminals, 0.6-mm Pitch, 8-mm × 8-mm • BR and EDR Features Include: – Up to Seven Active Devices – Scatternet: Up to Three Piconets Simultaneously, One as Master and Two as Slaves – Up to Two Synchronous Connection Oriented (SCO) Links on the Same Piconet – Support for All Voice Air-Coding—Continuously Variable Slope Delta (CVSD), A-Law, µ-Law, Modified Subband Coding (mSBC), and Transparent (Uncoded) – Provide an Assisted Mode for HFP 1.6 Wideband Speech (WBS) Profile or A2DP Profile to Reduce Host Processing and Power – Support of Multiple Bluetooth Profiles With Enhanced QoS • Low Energy Features Include: – Multiple Sniff Instances Tightly Coupled to Achieve Minimum Power Consumption – Independent Buffering for Low Energy Allows Large Numbers of Multiple Connections Without Affecting BR or EDR Performance – Built-In Coexistence and Prioritization Handling for BR, EDR, and Low Energy – Capabilities of Link Layer Topology Scatternet—Can Act Concurrently as Peripheral and Central 1.2 • • • • • • • • • – Network Support for up to 10 Devices – Time Line Optimization Algorithms to Achieve Maximum Channel Utliization Best-in-Class Bluetooth (RF) Performance (TX Power, RX Sensitivity, Blocking) – Class 1 TX Power up to +12 dBm – Internal Temperature Detection and Compensation to Ensure Minimal Variation in RF Performance Over Temperature, No External Calibration Required – Improved Adaptive Frequency Hopping (AFH) Algorithm With Minimum Adaptation Time – Longer Range, Including Twice the Range of Other Low-Energy-Only Solutions Advanced Power Management for Extended Battery Life and Ease of Design – On-Chip Power Management, Including Direct Connection to Battery – Low Power Consumption for Active, Standby, and Scan Bluetooth Modes – Shutdown and Sleep Modes to Minimize Power Consumption Physical Interfaces: – UART Interface With Support for Maximum Bluetooth Data Rates – UART Transport Layer (H4) With Maximum Rate of 4 Mbps – Three-Wire UART Transport Layer (H5) With Maximum Rate of 4 Mbps – Fully Programmable Digital Pulse-Code Modulation (PCM)–I2S Codec Interface Flexibility for Easy Stack Integration and Validation Into MCUs and MPUs HCI Tester Tool to Evaluate RF Performance of the Device and Configure Service Pack Applications Wireless Audio Solutions mPOS Medical Devices Set-Top Boxes (STBs) • • Wearable Devices Sensor Hub, Sensor Gateway – Home and Factory Automation 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 1.3 www.ti.com Description The CC2564C device from Texas Instruments™ is a complete Bluetooth® BR/EDR, and low energy HCI level solution, providing high performance and robust Bluetooth solution. Based on TI’s seventhgeneration Bluetooth core, the CC2564C device provides a product-proven solution that is Bluetooth 5.1compliant, adding LE security and enhancing support for complex topologies (dual mode and link layer topologies). This HCI device offers best-in-class RF performance with about twice the throughput of other Bluetooth low-energy solutions, and includes a royalty-free software stack compatible with several host MCUs and MPUs, for a complete Bluetooth solution. Furthermore, TI’s power-management hardware and software algorithms provide significant power savings in all commonly used Bluetooth BR, EDR, and low energy modes of operation. The TI dual-mode Bluetooth stack software is certified and provided royalty free for MCUs and MPUs. The iPod® (MFi) protocol is supported by add-on software packages. For more information, see TI Dual-Mode Bluetooth Stack. Multiple profiles and sample applications, including the following, are supported: Serial port profile (SPP) Advanced audio distribution profile (A2DP) Audio/video remote control profile (AVRCP) Hands-free profile (HFP) Human interface device (HID) Generic attribute profile (GATT) Several Bluetooth low energy profiles and services Device Information (1) PART NUMBER PACKAGE BODY SIZE RVM (76) 8.00 mm × 8.00 mm × 0.60 mm CC2564CRVM (1) For more information on these devices, see Mechanical, Packaging, and Orderable Information. 1.4 Functional Block Diagram CC2564C 2.4-GHz band-pass filter Coprocessor (See Note) PCM-I2S Modem arbitrator I/O interface DRP BR/EDR main processor UART HCI Power management Power Note: 2 Shutdown Clock management Slow clock Fast clock Copyright © 2016, Texas Instruments Incorporated The following technologies and assisted modes cannot be used simultaneously with the coprocessor: Bluetooth low energy, assisted HFP 1.6 (WBS), and assisted A2DP. Only one technology or assisted mode can be used at a time. Device Overview Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 Table of Contents Device Overview ......................................... 1 6.2 Functional Block Diagram ........................... 24 1.1 Features .............................................. 1 6.3 Clock Inputs ......................................... 24 1.2 Applications ........................................... 1 6.4 Functional Blocks.................................... 28 1.3 Description ............................................ 2 6.5 Bluetooth BR and EDR Features 1.4 Functional Block Diagram ............................ 2 6.6 Bluetooth Low Energy Description .................. 41 2 3 Revision History ......................................... 3 Device Comparison ..................................... 4 6.7 6.8 Bluetooth Transport Layers ......................... 42 Changes from the CC2564B Device to the CC2564C Device .................................... 42 4 Terminal Configuration and Functions 1 3.1 5 ............. 5 4.1 VQFNP-MR Package ................................. 5 Specifications ............................................ 9 5.1 Absolute Maximum Ratings .......................... 9 5.2 ESD Ratings .......................................... 9 5.3 Power-On Hours ...................................... 9 5.4 Recommended Operating Conditions ............... 10 5.5 Power Consumption Summary ...................... 10 5.6 Electrical Characteristics ............................ 12 7 8 7.1 Reference Design Schematics and BOM ........... 43 7.2 VQFNP-MR PCB Layout Guidelines ................ 46 Device and Documentation Support ............... 49 Third-Party Products Disclaimer 49 8.2 Tools and Software 49 8.3 8.4 8.5 5.8 Timing and Switching Characteristics ............... 13 8.8 5.9 RF Performance ..................................... 20 8.9 6.1 Overview ............................................ 24 8.7 9 .................... ................................. Device Nomenclature ............................... Documentation Support ............................. Support Resources .................................. Trademarks.......................................... Electrostatic Discharge Caution ..................... Export Control Notice ............................... Glossary ............................................. 8.1 Thermal Resistance Characteristics for VQFNP-MR (RVM) Package .................................... 12 Detailed Description ................................... 24 41 Applications, Implementation, and Layout........ 43 8.6 5.7 6 Related Products ..................................... 4 ................... 50 51 52 52 52 52 52 Mechanical, Packaging, and Orderable Information .............................................. 52 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from November 3, 2016 to June 22, 2020 • • • • • • • • • • • • • Page Changed Bluetooth 4.2 to Bluetooth 5.1 in Section 1.1, Features ............................................................ 1 Changed the Features bullet about the HCI Tester Tool ....................................................................... 1 Changed Bluetooth 4.2 to Bluetooth 5.1 in Section 1.3, Description .......................................................... 2 Changed "twice the range" to "twice the throughput" in Description ........................................................... 2 Changed Bluetooth 4.2 to Bluetooth 5.1 in Table 3-1, CC2564C Device Features ......................................... 4 Added footnote to Current Consumption for Different Bluetooth BR and EDR Scenarios ................................ 11 Added footnote to Current Consumption for Different Low-Energy Scenarios .............................................. 11 Changed Bluetooth 4.2 to Bluetooth 5.1 in Section 6.5, Bluetooth BR and EDR Features ............................... 41 Changed Bluetooth 4.2 to Bluetooth 5.1 in Section 6.6, Bluetooth Low Energy Description.............................. 41 Changed Reference Design Schematics and BOM ............................................................................ 43 Changed entries in the Device and Documentation Support section......................................................... 49 Changed the link to the HCI Tester Tool ........................................................................................ 49 Changed CC2564C Device Nomenclature image .............................................................................. 50 Revision History Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 3 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com 3 Device Comparison Table 3-1 lists the features of the CC2564C device. Table 3-1. CC2564C Device Features TECHNOLOGY SUPPORTED DEVICE CC2564C (1) 3.1 DESCRIPTION Bluetooth 5.1 + Bluetooth low energy ASSISTED MODES SUPPORTED (1) BR, EDR LOW ENERGY HFP 1.6 (WBS) A2DP ✓ ✓ ✓ ✓ The assisted modes (HFP 1.6 and A2DP) are not supported simultaneously. Furthermore, the assisted modes are not supported simultaneously with Bluetooth low energy. Related Products Wireless Connectivity The wireless connectivity portfolio offers a wide selection of low-power RF solutions suitable for a broad range of application. The offerings range from fully customized solutions to turnkey offerings with precertified hardware and software (protocol). Companion Products Review products that are frequently purchased or used with the CC2564C product. Reference Designs for CC2564 The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor, and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns. 4 Device Comparison Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 4 Terminal Configuration and Functions 4.1 4.1.1 VQFNP-MR Package Pin Diagram NC DIG_LDO_OUT A40 DIG_LDO_OUT B36 AUD_IN NC A39 B35 B33 B34 A38 VDD_IO AUD_OUT A37 NC AUD_CLK NC AUD_FSYNC A35 B32 A36 VDD_IO NC B30 B31 NC A34 NC HCI_TX A33 A32 B22 B6 DIG_LDO_OUT MLDO_OUT VSS_FREF B19 B9 A22 B10 MLDO_OUT NC NC A11 A10 NC NC A12 VSS_DCO DCO_LDO_OUT A13 NC NC NC B11 B12 A14 A15 NC NC B13 B14 A16 NC DIG_LDO_OUT NC A17 VDD_IO B15 B16 A18 NC NC A19 A20 NC VDD_IO ADC_PPA_LDO_OUT BT_RF A9 A21 CL1.5_LDO_OUT MLDO_OUT A8 B8 nSHUTD CL1.5_LDO_IN B7 B20 MLDO_OUT MLDO_IN A7 A23 XTALM/FREFM XTALP/FREFP A6 B21 VDD_IO NC B5 B17 NC B23 A24 NC A3 A5 NC NC DIG_LDO_OUT B4 A25 VDD_IO A2 A4 A26 NC SRAM_LDO_OUT B3 B24 VDD_IO VSS B29 B25 NC SLOW_CLK B2 A27 TX_DBG HCI_RX B26 A28 VDD_IO NC B1 A29 DIG_LDO_OUT VSS A1 B27 NC HCI_CTS B28 A30 B18 NC DIG_LDO_OUT HCI_RTS NC A31 NC Figure 4-1 shows the bottom view of the pin diagram (VQFNP-MR package). SWRS121-002 Figure 4-1. VQFNP-MR Package Pin Diagram Bottom View Terminal Configuration and Functions Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 5 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 4.1.2 www.ti.com Pin Attributes Table 4-1 describes the pin attributes for the VQFNP-MR package. SPACER Table 4-1. Pin Attributes (VQFNP-MR Package) NO. PULL AT RESET DEF. DIR. (1) I/O Type (2) AUD_CLK B32 PD I/O HY, 4 mA PCM clock Fail-safe AUD_FSYNC A35 PD I/O 4 mA PCM frame-sync signal Fail-safe AUD_IN B34 PD I 4 mA PCM data input Fail-safe AUD_OUT B33 PD O 4 mA PCM data output Fail-safe HCI_CTS A29 PU I 8 mA HCI UART clear-to-send The device is allowed to send data when HCI_CTS is low. HCI_RX A26 PU I 8 mA HCI universal asynchronous receiver/transmitter (UART) data receive HCI_RTS A32 PU O 8 mA HCI UART request-to-send The host is allowed to send data when HCI_RTS is low. HCI_TX A33 PU O 8 mA HCI UART data transmit TX_DBG B24 PU O 2 mA TI internal debug messages. TI recommends leaving an internal test point. NAME DESCRIPTION I/O Signals Clock Signals SLOW_CLK A25 I 32.768-kHz clock in Fail-safe XTALP/FREFP B4 I Fast clock in analog (sine wave) Output terminal of fast-clock crystal Fail-safe XTALM/FREFM A4 I Fast clock in digital (square wave) Input terminal of fast-clock crystal Fail-safe Analog Signals BT_RF B8 nSHUTD A6 I/O PD Bluetooth RF I/O I Shutdown input (active low) Power and Ground Signals ADC_PPA_LDO_OUT A8 O ADC/PPA LDO output CL1.5_LDO_IN B6 I Power amplifier (PA) LDO input Connect directly to battery CL1.5_LDO_OUT A7 O PA LDO output DCO_LDO_OUT A12 O DCO LDO output DIG_LDO_OUT A2, A3, B15, B26, B27, B35, B36 O Digital LDO output QFN pin B26 or B27 must be shorted to other DIG_LDO_OUT pins on the PCB. B5 I Main LDO input Connect directly to battery A5, A9, B2, B7 I/O Main LDO output (1.8-V nominal) B1 O SRAM LDO output MLDO_IN MLDO_OUT SRAM_LDO_OUT (1) (2) 6 I = input; O = output; I/O = bidirectional I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current Terminal Configuration and Functions Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 Table 4-1. Pin Attributes (VQFNP-MR Package) (continued) NAME NO. PULL AT RESET DEF. DIR. (1) I/O Type (2) DESCRIPTION VDD_IO A17, A34, A38, B18, B19, B21, B22, B25 I I/O power supply (1.8-V nominal) VSS A24, A28 I Ground VSS_DCO B11 I DCO ground VSS_FREF B3 I Fast clock ground 4.1.3 Connections for Unused Pins Section 4.1.3 lists the connections for unused signals for the VQFNP-MR package. SPACER PIN NUMBER FUNCTION DESCRIPTION A1 NC Not connected A10 NC Not connected A11 NC Not connected A14 NC Not connected A18 NC Not connected A19 NC Not connected A20 NC Not connected A21 NC Not connected A22 NC Not connected A23 NC Not connected A27 NC Not connected A30 NC Not connected A31 NC Not connected A40 NC Not connected B9 NC Not connected B10 NC Not connected B16 NC Not connected B17 NC Not connected B20 NC Not connected B23 NC Not connected A13 NC TI internal use A15 NC TI internal use A16 NC TI internal use A36 NC TI internal use A37 NC TI internal use A39 NC TI internal use B12 NC TI internal use B13 NC TI internal use B14 NC TI internal use B28 NC TI internal use B29 NC TI internal use B30 NC TI internal use B31 NC TI internal use Terminal Configuration and Functions Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 7 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 8 www.ti.com Terminal Configuration and Functions Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 5 Specifications Unless otherwise indicated, all measurements are taken at the device pins on the TI test evaluation board (EVB). All specifications are over process, voltage, and temperature, unless otherwise indicated. 5.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise indicated). All parameters are measured as follows: VDD_IN = 3.6 V and VDD_IO = 1.8 V (unless otherwise indicated). (1) Supply voltage MIN MAX VDD_IN –0.5 4.8 VDDIO_1.8 V UNIT V (2) –0.5 2.145 V Input voltage to analog pins (3) –0.5 2.1 V Input voltage to all other pins –0.5 VDD_IO + 0.5 V Bluetooth RF inputs 10 dBm Operating ambient temperature, TA (4) –40 85 °C Storage temperature, Tstg –55 125 °C (1) (2) (3) (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 7.1. Analog pins: BT_RF, XTALP, and XTALM The reference design supports a temperature range of –20°C to +70°C because of the operating conditions of the crystal. 5.2 ESD Ratings VALUE V(ESD) (1) (2) 5.3 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±500 Charged device model (CDM), per JEDEC specification JESD22C101 (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Power-On Hours This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. DEVICE CC2564C CONDITIONS Duty cycle = 25% active and 75% sleep Tambient = 85ºC POWER-ON HOURS 15,400 (7 years) Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 9 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 5.4 www.ti.com Recommended Operating Conditions MIN MAX 1.7 4.8 V 1.62 1.92 V Default condition 0.65 × VDD_IO VDD_IO V Default condition 0 0.35 × VDD_IO V I/O input rise and all times, 10% to 90%—asynchronous mode 1 10 ns I/O input rise and fall times, 10% to 90%—synchronous mode (PCM) 1 2.5 ns VDD_IN Power supply voltage VDD_IO I/O power supply voltage VIH High-level input voltage VIL Low-level input voltage tr and tf Maximum ripple on VDD_IN (sine wave) for 1.8 V (DC-DC) mode Condition: 0 to 0.1 MHz 60 Condition: 0.1 to 0.5 MHz 50 Condition: 0.5 to 2.5 MHz 30 Condition: 2.5 to 3.0 MHz 15 Condition: > 3.0 MHz Maximum ambient operating temperature (2) (1) (2) mV 85 °C –40 Power Consumption Summary 5.5.1 Static Current Consumption OPERATIONAL MODE Shutdown mode (1) Deep sleep mode (2) Total I/O current consumption in active mode Continuous transmission—GFSK (3) Continuous transmission—EDR (4) (5) 10 400 The device can be reliably operated for 7 years at Tambient of 85°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours). A crystal-based solution is limited by the temperature range required for the crystal to meet 20 ppm. 5.5 (1) (2) (3) (4) (5) mVp-p 5 Voltage dips on VDD_IN (VBAT) Duration = 577 µs to 2.31 ms, period = 4.6 ms (1) UNIT MIN TYP MAX 1 7 UNIT 40 105 µA 1 mA 107 mA 112.5 mA µA VBAT + VIO + VSHUTDOWN VBAT + VIO At maximum output power 12 dBm At maximum output power 10 dBm Both π/4 DQPSK and 8DPSK Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 5.5.2 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Dynamic Current Consumption 5.5.2.1 Current Consumption for Different Bluetooth BR and EDR Scenarios Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz XTAL, nominal unit, 10-dBm output power (1) MASTER AND SLAVE AVERAGE CURRENT UNIT SCO link HV3 OPERATIONAL MODE Master and slave 13.7 mA Extended SCO (eSCO) link EV3 64 kbps, no retransmission Master and slave 13.2 mA eSCO link 2-EV3 64 kbps, no retransmission Master and slave 10 mA GFSK full throughput: TX = DH1, RX = DH5 Master and slave 40.5 mA EDR full throughput: TX = 2-DH1, RX = 2-DH5 Master and slave 41.2 mA EDR full throughput: TX = 3-DH1, RX = 3-DH5 Master and slave 41.2 mA Sniff, four attempts, 1.28 seconds Master and slave 145 µA Page or inquiry scan 1.28 seconds, 11.25 ms Master and slave 320 µA Page (1.28 seconds) and inquiry (2.56 seconds) scans, 11.25 ms Master and slave 445 µA A2DP source Master 13.9 mA A2DP sink Master 15.2 mA Assisted A2DP source Master 16.9 mA Assisted A2DP sink Master 18.1 mA Assisted WBS EV3; retransmit effort = 2; maximum latency = 8 ms Master and slave 17.5 and 18.5 mA Assisted WBS 2EV3; retransmit effort = 2; maximum latency = 12 ms Master and slave 11.9 and 13 mA (1) To modify maximum output power, use an HCI VS command. 5.5.2.2 Current Consumption for Different Low-Energy Scenarios Conditions: VDD_IN = 3.6 V, 25°C, nominal unit, 10-dBm output power (1) MODE DESCRIPTION AVERAGE CURRENT UNIT Advertising, nonconnectable Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data 114 µA Advertising, discoverable Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data 138 µA Scanning Listening to a single frequency per window 1.28-seconds scan interval 11.25-ms scan window 324 µA Master role Connected (1) Slave role 500-ms connection interval 0-ms slave connection latency Empty TX and RX LL packets 169 199 µA To modify maximum output power, use an HCI VS command. Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 11 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 5.6 www.ti.com Electrical Characteristics RATING CONDITION High-level output voltage, VOH Low-level output voltage, VOL I/O input impedance PCM–I2S bus, TX_DBG All others 5.7 MAX 0.8 × VDD_IO VDD_IO At 0.1 mA VDD_IO – 0.2 VDD_IO At 2, 4, 8 mA 0 0.2 × VDD_IO At 0.1 mA 0 0.2 Resistance 1 Capacitance Output rise and fall times, 10% to 90% (digital pins) I/O pull currents MIN At 2, 4, 8 mA CL = 20 pF UNIT V V MΩ 5 pF 10 ns PU Typical = 6.5 3.5 PD Typical = 27 9.5 9.7 55 PU Typical = 100 50 300 PD Typical = 100 50 360 µA Thermal Resistance Characteristics for VQFNP-MR (RVM) Package over operating free-air temperature range (unless otherwise noted) THERMAL METRICS (1) C/W (2) Rθja Junction-to-free-air 34.6 Rθjctop Junction-to-case-top 17.9 Rθjcbottom Junction-to-case-bottom 1.6 Rθjb Junction-to-board 12.0 φjt Junction-to-package-top 0.2 φjb Junction-to-package-bottom 12.0 (1) (2) 12 For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Power dissipation of 2 W and an ambient temperature of 70ºC is assumed. Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 5.8 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Timing and Switching Characteristics 5.8.1 Device Power Supply The CC2564C power-management hardware and software algorithms provide significant power savings, which is a critical parameter in an MCU-based system. The power-management module is optimized for drawing extremely low currents. 5.8.1.1 Power Sources The CC2564C device requires two power sources: • VDD_IN: main power supply for the device • VDD_IO: power source for the 1.8-V I/O ring The HCI module includes several on-chip voltage regulators for increased noise immunity and can be connected directly to the battery. 5.8.1.2 Device Power-Up and Power-Down Sequencing The device includes the following power-up requirements (see Figure 5-1): • nSHUTD must be low. VDD_IN and VDD_IO are don't care I/O pins when nSHUTD is low. However, signals are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe. Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages with no VDD_IO and VDD_IN. • VDD_IO and VDD_IN must be stable before releasing nSHUTD. • The fast clock must be stable within 20 ms of nSHUTD going high. • The slow clock must be stable within 2 ms of nSHUTD going high. The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to 100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case, ensure that the sequence and requirements are met. Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 13 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com Shut down before VDD_IO removed 20 µs max nSHUTD VDD_IO VDD_IN 2 ms max SLOW CLOCK 20 ms max FAST CLOCK ± 100 ms HCI_RTS CC256x ready Copyright © 2016, Texas Instruments Incorporated Figure 5-1. Power-Up and Power-Down Sequencing 5.8.1.3 Power Supplies and Shutdown—Static States The nSHUTD signal puts the device in ultra-low-power mode and performs an internal reset to the device. The rise time for nSHUTD must not exceed 20 µs; nSHUTD must be low for a minimum of 5 ms. To prevent conflicts with external signals, all I/O pins are set to the high-impedance (Hi-Z) state during shutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in Section 4.1.2. Table 5-1 lists and describes the static operation states. Table 5-1. Power Modes VDD_IN (1) 14 (1) VDD_IO (1) nSHUTD (1) PM_MODE COMMENTS 1 None None Asserted Shutdown I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. 2 None None Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. 3 None Present Asserted Shutdown 4 None Present Deasserted Not allowed 5 Present None Asserted Shutdown 6 Present None Deasserted Not allowed 7 Present Present Asserted Shutdown 8 Present Present Deasserted Active I/Os are defined as tri-state pins with internal pullup or pulldown enabled. I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. I/O state is undefined. I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. I/Os are defined as tri-state pins with internal pullup or pulldown enabled. See Section 5.8.1.4. The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a pulldown resistor, or left NC or floating (high-impedance output stage). Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 5.8.1.4 SWRS199B – APRIL 2016 – REVISED JUNE 2020 I/O States in Various Power Modes CAUTION Some device I/Os are not fail-safe (see Section 4.1.2). Fail-safe means that the pins do not draw current from an external voltage applied to the pin when I/O power is not supplied to the device. External voltages are not allowed on these I/O pins when the I/O supply voltage is not supplied because of possible damage to the device. Table 5-2 lists the I/O states in various power modes. Table 5-2. I/O States in Various Power Modes I/O NAME SHUTDOWN (1) DEFAULT ACTIVE (1) DEEP SLEEP (1) I/O State Pull I/O State Pull I/O State Pull HCI_RX Z PU I PU I PU HCI_TX Z PU O-H HCI_RTS Z PU O-H HCI_CTS Z PU I PU I PU AUD_CLK Z PD I PD I PD AUD_FSYNC Z PD I PD I PD AUD_IN Z PD I PD I PD AUD_OUT Z PD Z PD Z PD TX_DBG Z PU O (1) O O I = input, O = output, Z = Hi-Z, – = no pull, PU = pullup, PD = pulldown, H = high, L = low 5.8.1.5 nSHUTD Requirements MIN MAX UNIT VIH Operation mode level (1) PARAMETER 1.42 1.98 V VIL Shutdown mode level (1) 0 0.4 Minimum time for nSHUT_DOWN low to reset the device 5 tr and tf (1) Rise and fall times V ms 20 µs An internal pulldown retains shutdown mode when no external signal is applied to this pin. Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 15 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 5.8.2 www.ti.com Clock Specifications 5.8.2.1 Slow Clock Requirements An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V. The accuracy of the slow-clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of nSHUTD. CHARACTERISTICS CONDITION MIN Input slow-clock frequency TYP MAX 32768 Input slow-clock accuracy (Initial + temp + aging) Hz Bluetooth Input transition time tr and tf (10% to 90%) tr and tf Frequency input duty cycle VIH 15% Slow-clock input voltage limits VIL Square wave, DC-coupled 50% 200 ns VDD_IO V peak 0 0.35 × VDD_IO V peak 1 MΩ 5 pF External Fast Clock Crystal Requirements and Operation CHARACTERISTICS CONDITION MIN Supported crystal frequencies TYP Iosc = 0.5 mA 26 MHz, external capacitance = 20 pF Iosc = 2.2 mA Specifications 650 UNIT MHz ±20 26 MHz, external capacitance = 8 pF Crystal oscillator negative resistance MAX 26, 38.4 Frequency accuracy (Initial + temperature + aging) 16 ppm 85% Input capacitance fin ±250 0.65 × VDD_IO Input impedance 5.8.2.2 UNIT ppm 940 Ω 490 710 Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 5.8.2.3 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Fast Clock Source Requirements (–40°C to +85°C) CHARACTERISTICS CONDITION MIN Supported frequencies, FREF MAX UNIT 26, 38.4 Reference frequency accuracy MHz Initial + temp + aging Square wave, DC-coupled Fast-clock input voltage limits Fast-clock input rise time (as % of clock period) ppm V –0.2 0.37 VIH 1.0 2.1 V Sine wave, AC-coupled 0.4 1.6 Vp-p Sine wave, DC-coupled 0.4 1.6 Vp-p Sine wave input limits, DC-coupled 0.0 1.6 V Square wave, DC-coupled 10% 35% Phase noise for 26 MHz ±20 VIL Duty cycle 5.8.3 TYP 50% 65% @ offset = 1 kHz –123.4 @ offset = 10 kHz –133.4 @ offset = 100 kHz –138.4 dBc/Hz Peripherals 5.8.3.1 UART Figure 5-2 shows the UART timing diagram. HCI_RTS t2 t1 HCI_RX t6 HCI_CTS t3 t4 HCI_TX Start bit Stop bit 10 bits td_uart_swrs064 Figure 5-2. UART Timing Table 5-3 lists the UART timing characteristics. Table 5-3. UART Timing Characteristics SYMBOL CHARACTERISTICS CONDITION Baud rate MIN TYP 37.5 MAX UNIT 4000 kbps Baud rate accuracy per byte Receive and transmit –2.5% 1.5% Baud rate accuracy per bit Receive and transmit –12.5% 12.5% t1 RTS low to RX_DATA on t2 RTS high to RX_DATA off t3 CTS low to TX_DATA on t4 CTS high to TX_DATA off t6 CTS-high pulse width 0 2 Interrupt set to 1/4 FIFO 0 Hardware flow control µs 16 byte 1 byte 2 µs 1 bit Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 17 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com Figure 5-3 shows the UART data frame. tb TX STR D0 D1 Dn D2 PAR STP td_uart_swrs064 Figure 5-3. Data Frame Table 5-4 describes the symbols used in Figure 5-3. Table 5-4. Data Frame Key SYMBOL DESCRIPTION STR 5.8.3.2 Start bit D0...Dn Data bits (LSB first) PAR Parity bit (optional) STP Stop bit PCM Figure 5-4 shows the interface timing for the PCM. Tclk Tw Tw AUD_CLK tis tih AUD_IN / FSYNC_IN top AUD_OUT / FSYNC_OUT td_aud_swrs064 Figure 5-4. PCM Interface Timing Table 5-5 lists the associated PCM master parameters. Table 5-5. PCM Master SYMBOL 18 PARAMETER CONDITION MIN MAX 244.14 (4.096 MHz) 15625 (64 kHz) UNIT tclk Cycle time tw High or low pulse width 50% of Tclk min ns tis AUD_IN setup time 25 ns tih AUD_IN hold time 0 ns top AUD_OUT propagation time 40-pF load 0 10 ns top FSYNC_OUT propagation time 40-pF load 0 10 ns Specifications ns Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 Table 5-6 lists the associated PCM slave parameters. Table 5-6. PCM Slave SYMBOL PARAMETER CONDITION MIN MAX UNIT 66.67 (15 MHz) ns 40% of Tclk ns tclk Cycle time tw High or low pulse width Tis AUD_IN setup time 8 ns tih AUD_IN hold time 0 ns tis AUD_FSYNC setup time 8 ns tih AUD_FSYNC hold time top AUD_OUT propagation time 0 40-pF load 0 ns 21 Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C ns 19 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 5.9 www.ti.com RF Performance 5.9.1 Bluetooth BR and EDR RF Performance All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL and 38.4-MHz TCXO. 5.9.1.1 Bluetooth Receiver—In-Band Signals CHARACTERISTICS CONDITION MIN Operation frequency range TYP 2402 1 Input impedance 50 Sensitivity, dirty TX on (1) π/4-DQPSK, BER = 0.01% 8DPSK, BER = 0.01% BER error floor at sensitivity + 10 dB, dirty TX off π/4-DQPSK 1E–6 8DPSK 1E–6 GFSK, BER = 0.1% Maximum usable input power Intermodulation characteristics –10 8DPSK, BER = 0.1% –10 Level of interferers (for n = 3, 4, and 5) –36 GFSK, cochannel EDR, adjacent, +2 MHz EDR, adjacent –2 MHz EDR, adjacent ≥ |±3| MHz –70 1E–7 1E–5 –20 dBm –30 –39 8 10 11 21 0 –10 –5 0 –5 –1 5 –38 –35 –30 π/4-DQPSK –38 –35 –30 8DPSK –38 –30 –25 π/4-DQPSK 8DPSK –28 –20 –20 π/4-DQPSK –28 –20 –20 8DPSK –22 –13 –13 –45 –43 –40 π/4-DQPSK –45 –43 –40 8DPSK –44 –36 –33 –10 RX mode LO leakage Frf = (received RF – 0.6 MHz) dBm 1E–5 –5 RF return loss –63 dBm dB dB –58 dBm Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast clock. Numbers show ratio of desired signal to interfering signal. Smaller numbers indicate better C/I performance. 5.9.1.2 Bluetooth Receiver—General Blocking CHARACTERISTICS CONDITION Blocking performance over full range, according to Bluetooth specification (1) 20 –87.5 –10 GFSK, adjacent ≥ |±3| MHz (1) –70 13 GFSK, adjacent –2 MHz (2) –94.5 20 GFSK, adjacent +2 MHz (1) –70 11 GFSK, adjacent ±1 MHz C/I performance (2) Image = –1 MHz Ω –95 9.5 8DPSK EDR, adjacent ±1 MHz, (image) MHz 16.5 π/4-DQPSK EDR, cochannel UNIT MHz –5 π/4-DQPSK, BER = 0.1% BLUETOOTH SPECIFICATION 2480 Channel spacing GFSK, BER = 0.1% MAX MIN TYP 30 to 2000 MHz –6 2000 to 2399 MHz –6 2484 to 3000 MHz –6 3 to 12.75 GHz –6 UNIT dBm Exceptions are taken out of the total 24 allowed in the Bluetooth specification. Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 5.9.1.3 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Bluetooth Transmitter—GFSK CHARACTERISTICS Maximum RF output power (1) MIN TYP VDD_IN = VBAT 12 VDD_IN = external regulator to 1.8 V 10 Power variation over Bluetooth band MAX BLUETOOTH SPECIFICATION UNIT dBm –1 1 dB Gain control range 30 Power control step 5 2 to 8 dB Adjacent channel power |M–N| = 2 –45 ≤ –20 dBm Adjacent channel power |M–N| > 2 –50 ≤ –40 dBm (1) dB To modify maximum output power, use an HCI VS command. 5.9.1.4 Bluetooth Transmitter—EDR CHARACTERISTICS π/4-DQPSK EDR output power (1) 8DPSK MIN TYP VDD_IN = VBAT 5.5 VDD_IN = external regulator to 1.8 V 5.5 VDD_IN = VBAT 5.5 VDD_IN = external regulator to 1.8 V MAX BLUETOOTH SPECIFICATION UNIT dBm 5.5 EDR relative power –2 Power variation over Bluetooth band –1 1 –4 to +1 dB 1 dB Gain control range 30 Power control step 5 2 to 8 dB Adjacent channel power |M–N| = 1 –36 ≤ –26 dBc Adjacent channel power |M–N| = 2 (2) –30 ≤ –20 dBm Adjacent channel power |M–N| > 2 (2) –42 ≤ –40 dBm (1) (2) dB To modify maximum output power, use an HCI VS command. Assumes 3-dB insertion loss from Bluetooth RF ball to antenna. 5.9.1.5 Bluetooth Modulation—GFSK CHARACTERISTICS –20-dB bandwidth F1 avg Modulation characteristics F2 max CONDITION MIN BLUETOOTH SPECIFICATION UNIT 925 ≤ 1000 kHz Δf1avg 165 140 to 175 kHz Δf2max ≥ limit for at least 99.9% of all Δf2max Mod data = 1010101... 130 > 115 kHz 88% > 80% DH1 –25 25 < ±25 DH3 and DH5 –35 35 < ±40 15 < 20 kHz/50 µs +75 < ±75 kHz Drift rate Initial carrier frequency tolerance MAX Mod data = 4 1 s, 4 0 s: 111100001111... GFSK Δf2avg, Δf1avg Absolute carrier frequency drift TYP f0–fTX –75 kHz Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 21 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 5.9.1.6 www.ti.com Bluetooth Modulation—EDR CHARACTERISTICS CONDITION MIN TYP BLUETOOTH SPECIFICATION UNIT ≤ 10 kHz ±5 ≤ 10 kHz ±75 ±75 kHz MAX Carrier frequency stability Carrier frequency stability Initial carrier frequency tolerance RMS DEVM (1) 99% DEVM (1) Peak DEVM (1) (1) π/4-DQPSK 6% 8DPSK 6% 13% π/4-DQPSK 30% 30% 8DPSK 20% 20% π/4-DQPSK 14% 35% 8DPSK 16% 25% Maximum performance refers to maximum TX power. 5.9.1.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions CHARACTERISTICS CONDITION Second harmonic (1) Third harmonic (1) Measured at maximum output power Fourth harmonics (1) (1) 20% TYP MAX UNIT –14 –2 dBm –10 –6 dBm –19 –11 dBm Meets FCC and ETSI requirements with the external filter listed in Table 7-1. 5.9.2 Bluetooth low energy RF Performance All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL and a 38.4-MHz TCXO. 5.9.2.1 Bluetooth low energy Receiver—In-Band Signals CHARACTERISTIC CONDITION Operation frequency range MIN TYP 2402 MAX BLUETOOTH low energy SPECIFICATION 2480 UNIT MHz Channel spacing 2 MHz Input impedance 50 Ω Sensitivity, dirty TX on (1) PER = 30.8%; dirty TX on Maximum usable input power GMSK, PER = 30.8% Intermodulation characteristics Level of interferers (for n = 3, 4, 5) RX mode LO leakage (1) (2) 22 dBm ≥ –10 dBm –30 ≥ –50 dBm 8 ≤ 21 GMSK, adjacent ±1 MHz –5 ≤ 15 GMSK, adjacent +2 MHz –45 ≤ –17 GMSK, adjacent –2 MHz –22 ≤ –15 GMSK, adjacent ≥ |±3| MHz –47 ≤ –27 Frf = (received RF – 0.6 MHz) –63 GMSK, cochannel C/I performance (2) Image = –1 MHz ≤ –70 –96 –5 dB dBm Sensitivity degradation up to 3 dB may occur where the Bluetooth low energy frequency is a harmonic of the fast clock. Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance. Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 5.9.2.2 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Bluetooth low energy Receiver—General Blocking CHARACTERISTICS CONDITION MIN 30 to 2000 MHz Blocking performance over full 2000 to 2399 MHz range, according to Bluetooth 2484 to 3000 MHz low energy specification (1) 3 to 12.75 GHz (1) TYP BLUETOOTH low energy SPECIFICATION –15 ≥ –30 –15 ≥ –35 –15 ≥ –35 –15 ≥ –30 UNIT dBm Exceptions are taken out of the total 10 allowed in the Bluetooth low energy specification. 5.9.2.3 Bluetooth low energy Transmitter CHARACTERISTICS RF output power MIN TYP VDD_IN = VBAT VDD_IN = External regulator to 1.8 V MAX BLUETOOTH low energy SPECIFICATION 12 (1) ≤10 10 ≤10 Power variation over Bluetooth low energy band UNIT dBm 1 dB Adjacent channel power |M-N| = 2 –45 ≤ –20 dBm Adjacent channel power |M-N| > 2 –50 ≤ –30 dBm (1) To achieve the Bluetooth low energy specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and the antenna. Otherwise, use an HCI VS command to modify the output power. 5.9.2.4 Bluetooth low energy Modulation CHARACTERISTICS Δf1 avg Δf2 max Modulation characteristics CONDITION MIN TYP MAX BLUETOOTH low energy SPECIFICATION UNIT 260 225 to 275 kHz kHz Δf1avg Mod data = 4 1s, 4 0s: 1111000011110000... 240 250 Δf2max ≥ limit for at least 99.9% of all Δf2max Mod data = 1010101... 185 210 ≥ 185 0.85 0.9 ≥ 0.8 Δf2avg, Δf1avg Absolute carrier frequency drift –25 Drift rate Initial carrier frequency tolerance 5.9.2.5 –75 ≤ ±50 kHz 15 ≤ 20 kHz/50 ms 75 ≤ ±100 kHz Bluetooth low energy Transceiver, Out-of-Band and Spurious Emissions CHARACTERISTICS CONDITION Second harmonic (1) Third harmonic (1) Measured at maximum output power Fourth harmonics (1) (1) 25 TYP MAX UNIT –14 –2 dBm –10 –6 dBm –19 –11 dBm Meets FCC and ETSI requirements with the external filter listed in Table 7-1. Specifications Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 23 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com 6 Detailed Description 6.1 Overview The CC2564C architecture comprises a DSP and a point-to-multipoint baseband core. The architecture is based on a single-processor ARM7TDMI® core. The device includes several on-chip peripherals to enable easy communication with a host system and the Bluetooth BR, EDR, and low energy core. 6.2 Functional Block Diagram CC2564C 2.4-GHz band-pass filter Coprocessor (See Note) PCM-I2S Modem arbitrator I/O interface DRP BR/EDR main processor UART HCI Power management Power Shutdown Clock management Slow clock Fast clock Copyright © 2016, Texas Instruments Incorporated NOTE: The following technologies and assisted modes cannot be used simultaneously with the coprocessor: Bluetooth low energy, assisted HFP 1.6 (WBS), and assisted A2DP. Only one technology or assisted mode can be used at a time. Figure 6-1. CC2564C Functional Block Diagram 6.3 Clock Inputs This section describes the available clock inputs. For specifications, see Section 5.8.2. 6.3.1 Slow Clock An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the host or external crystal oscillator). The source must be a digital signal in the range of 0 V to 1.8 V. The accuracy of the slow-clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of nSHUTD. 6.3.2 Fast Clock Using External Clock Source An external clock source is fed to an internal pulse-shaping cell to provide the fast-clock signal for the device. The device incorporates an internal, automatic clock-scheme detection mechanism that automatically detects the fast-clock scheme used and configures the FREF cell accordingly. This mechanism ensures that the electrical characteristics (loading) of the fast-clock input remain static regardless of the scheme used and eliminates any power-consumption penalty-versus-scheme used. The frequency variation of the fast-clock source must not exceed ±20 ppm (as defined by the Bluetooth specification). The external clock can be AC- or DC-coupled, sine or square wave. 24 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 6.3.2.1 SWRS199B – APRIL 2016 – REVISED JUNE 2020 External FREF DC-Coupled Figure 6-2 and Figure 6-3 show the clock configuration when using a square wave, DC-coupled external source for the fast-clock input. NOTE A shunt capacitor with a range of 10 nF must be added on the oscillator output to reject high harmonics and shape the signal to be close to a sinusoidal waveform. TI recommends using only a dedicated LDO to feed the oscillator. Do not use the same VIO for the oscillator and the CC2564C device. FREFP CC2564C FREFM Copyright © 2016, Texas Instruments Incorporated Figure 6-2. Clock Configuration (Square Wave, DC-Coupled) VFref [V] 2.1 1.0 0.37 Vhigh_min Vlow_max –0.2 t clksqtd_wrs064 Figure 6-3. External Fast Clock (Square Wave, DC-Coupled) Figure 6-4 and Figure 6-5 show the clock configuration when using a sine wave, DC-coupled external source for the fast clock input. FREFP CC2564C FREFM VDD_IO Copyright © 2016, Texas Instruments Incorporated Figure 6-4. Clock Configuration (Sine Wave, DC-Coupled) Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 25 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com VIN 1.6 V VPP = 0.4 – 1.6 Vp-p Vdc = 0.2 – 1.4 V 0 t SWRS097-023 Figure 6-5. External Fast Clock (Sine Wave, DC-Coupled) 6.3.2.2 External FREF Sine Wave, AC-Coupled Figure 6-6 and Figure 6-7 show the configuration when using a sine wave, AC-coupled external source for the fast-clock input. FREFP 68 pF CC2564C FREFM VDD_IO Copyright © 2016, Texas Instruments Incorporated Figure 6-6. Clock Configuration (Sine Wave, AC-Coupled) VIN [V] 1V VPP = 0.4 – 1.6 Vp-p 0.8 0.2 0 t –0.2 –0.8 SWRS097-022 Figure 6-7. External Fast Clock (Sine Wave, AC-Coupled) In cases where the input amplitude is greater than 1.6 Vp-p, the amplitude can be reduced to within limits. Using a small series capacitor forms a voltage divider with the internal input capacitance of approximately 2 pF to provide the required amplitude at the device input. 26 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 6.3.2.3 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Fast Clock Using External Crystal The CC2564C device incorporates an internal crystal oscillator buffer to support a crystal-based fast-clock scheme. The supported crystal frequencies are 26 and 38.4 MHz. The frequency accuracy of the fast-clock source must not exceed ±20 ppm (including the accuracy of the capacitors, as specified in the Bluetooth specification). Figure 6-8 shows the recommended fast-clock circuitry. CC2564C C1 XTALM Oscillator buffer XTAL XTALP C2 Copyright © 2016, Texas Instruments Incorporated Figure 6-8. Fast-Clock Crystal Circuit Table 6-1 lists component values for the fast-clock crystal circuit. Table 6-1. Fast-Clock Crystal Circuit Component Values (1) FREQ (MHz) C1 (pF) (1) C2 (pF) (1) 26 12 12 To achieve the required accuracy, values for C1 and C2 must be taken from the crystal manufacturer's data sheet and layout considerations. Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 27 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 6.4 www.ti.com Functional Blocks 6.4.1 RF TheCC2564C device is the third generation of Bluetooth single-chip devices using DRP architecture from TI. Modifications and new features added to the DRP further improve radio performance. Figure 6-9 shows the DRP block diagram. Transmitter path Amplitude TX digital data Digital ADPLL DPA Phase Receiver path RX digital data Demodulation ADC IFA Filter LNA SWRS092-005 Copyright © 2016, Texas Instruments Incorporated Figure 6-9. DRP Block Diagram 6.4.1.1 Receiver The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal received from the external antenna is input to a single-ended low-noise amplifier (LNA) and passed to a mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level. The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an adaptive-decision mechanism. The demodulator includes EDR processing with: • State-of-the-art performance • A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK sensitivity • Adaptive equalization to enhance EDR modulation New features include: • LNA input range narrowed to increase blocking performance • Active spur cancellation to increase robustness to spurs 28 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 6.4.1.2 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Transmitter The transmitter is an all-digital, sigma-delta phase-locked loop (ADPLL) based with a digitally controlled oscillator (DCO) at 2.4 GHz as the RF clock. The transmitter directly modulates the digital PLL. The power amplifier is also digitally controlled. The transmitter uses the polar-modulation technique. While the phasemodulated control word is fed to the ADPLL, the amplitude-modulated controlled word is fed to the class-E amplifier to generate a Bluetooth standard-compliant RF signal. New features include: • Improved TX output power • LMS algorithm to improve the differential error vector magnitude (DEVM) 6.4.2 Host Controller Interface The CC2564C device incorporates one UART module dedicated to the HCI transport layer. The HCI transports commands, events, and ACL between the device and the host using HCI data packets. The CC2564C device supports the H4 protocol (4-wire UART) with hardware flow control and the H5 protocol (3-wire UART) with software flow control. The CC2564C device automatically detects the protocol on reception of the first command. The maximum baud rate of the UART module is 4 Mbps; however, the default baud rate after power up is set to 115.2 kbps. The baud rate can thereafter be changed with a VS command. The device responds with a command complete event (still at 115.2 kbps), after which the baud rate change occurs. The UART module includes the following features: • Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions • Transmitter underflow detection • CTS and RTS hardware flow control (H4 protocol) • XON and XOFF software flow control (H5 protocol) Table 6-2 lists the UART module default settings. Table 6-2. UART Module Default Settings PARAMETER VALUE Bit rate 115.2 kbps Data length 8 bits Stop bit 1 Parity None Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 29 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 6.4.2.1 www.ti.com 4-Wire UART Interface—H4 Protocol The H4 UART Interface includes four signals: • TX • RX • CTS • RTS Flow control between the host and the CC2564C device is bytewise by hardware. Figure 6-10 shows the H4 UART interface. Host Host_RX HCI_RX Host_TX HCI_TX Host_CTS HCI_CTS Host_RTS HCI_RTS CC2564C Copyright © 2016, Texas Instruments Incorporated Figure 6-10. H4 UART Interface When the UART RX buffer of the device passes the flow control threshold, it sets the HCI_RTS signal high to stop transmission from the host. When the HCI_CTS signal is set high, the device stops transmission on the interface. If HCI_CTS is set high while transmitting a byte, the device finishes transmitting the byte and stops the transmission. The H4 protocol device includes a mechanism that handles the transition between active mode and sleep mode. The protocol occurs through the CTS and RTS UART lines and is known as the enhanced HCI low level (eHCILL) power-management protocol. For more information on the H4 UART protocol, see Volume 4 Host Controller Interface, Part A UART Transport Layer of the Bluetooth Core Specifications (www.bluetooth.org/en-us/specification/adoptedspecifications). 30 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 6.4.2.2 SWRS199B – APRIL 2016 – REVISED JUNE 2020 3-Wire UART Interface—H5 Protocol The H5 UART interface consists of three signals (see Figure 6-11): • TX • RX • GND Host Host_RX HCI_RX Host_TX HCI_TX CC2564C GND GND Copyright © 2016, Texas Instruments Incorporated Figure 6-11. H5 UART Interface The H5 protocol supports the following features: • Software flow control (XON/XOFF) • Power management using the software messages: – WAKEUP – WOKEN – SLEEP • CRC data integrity check For more information on the H5 UART protocol, see Volume 4 Host Controller Interface, Part D ThreeWire UART Transport Layer of the Bluetooth Core Specifications (www.bluetooth.org/en-us/specification/adoptedspecifications). 6.4.3 Digital Codec Interface The codec interface is a fully programmable port to support seamless interfacing with different PCM and I2S codec devices. The interface includes the following features: • Two voice channels • Master and slave modes • All voice coding schemes defined by the Bluetooth specification: linear, A-Law, and µ-Law • Long and short frames • Different data sizes, order, and positions • High flexibility to support a variety of codecs • Bus sharing: Data_Out is in the Hi-Z state when the interface is not transmitting voice data. Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 31 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 6.4.3.1 www.ti.com Hardware Interface The interface includes four signals: • Clock: configurable direction (input or output) • Frame_Sync and Word_Sync: configurable direction (input or output) • Data_In: input • Data_Out: output or tri-state signal The CC2564C device can be the master of the interface when generating the Clock and Frame_Sync signals or the slave when receiving these two signals. For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the device can generate any clock frequency from 64 kHz to 4.096 MHz. 6.4.3.2 I2S When the codec interface is configured to support the I2S protocol, these settings are recommended: • Bidirectional, full-duplex interface • Two time slots per frame: time slot 0 for the left channel audio data; and time slot 1 for the right channel audio data • The length of each time slot is configurable up to 40 serial clock cycles, and the length of the frame is configurable up to 80 serial clock cycles 6.4.3.3 Data Format The data format is fully configurable: • The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to 640 bits when working with 1 channel. The data length can be set independently for each channel. • The data position within a frame is also configurable within 1 clock (bit) resolution and can be set independently (relative to the edge of the Frame_Sync signal) for each channel. • The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for sample sizes up to 24 bits. • Data_In and Data_Out are not required to be the same length. • The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for permanent Hi-Z output, regardless of the data output. This configuration allows the device to be a bus slave in a multislave PCM environment. At power up, Data_Out is configured as Hi-Z output. 6.4.3.4 Frame-Idle Period The codec interface handles frame-idle periods, during which the clock pauses and becomes 0 at the end of the frame after all data are transferred. The device supports frame-idle periods both as master and slave of the codec bus. When the device is the master of the interface, the frame-idle period is configurable. There are two configurable parameters: • Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of the frame-idle period. After Clk_Idle_Start clock cycles, the clock becomes 0. • Clk_Idle_End: indicates the time from the beginning of the frame to the end of the frame-idle period. The time is given in multiples of clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period. For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90. 32 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. Thus, the idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end before the beginning of the idle period. Figure 6-12 shows the frame idle timing. Frame period Frame_Sync Data_In Data_Out Frame idle Clock Clk_Idle_Start Clk_Idle_End frmidle_swrs064 Figure 6-12. Frame Idle Period 6.4.3.5 Clock-Edge Operation The codec interface of the device can work on the rising or the falling edge of the clock and can sample the Frame_Sync signal and the data at inversed polarity. Figure 6-13 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus. The Frame_Sync signal is updated (by the codec) on the falling edge of the clock and is therefore sampled (by the device) on the next rising clock. The data from the codec is sampled (by the device) on the falling edge of the clock. PCM FSYNC PCM CLK D7 PCM DATA IN D6 D5 D4 D3 D2 D1 D0 CC256x SAMPLE TIME SWRS121-004 Copyright © 2016, Texas Instruments Incorporated Figure 6-13. Negative Clock Edge Operation Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 33 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 6.4.3.6 www.ti.com Two-Channel Bus Example Figure 6-14 shows a 2-channel bus in which the two channels have different word sizes and arbitrary positions in the bus frame. ... Clock FT 127 0 1 2 3 4 5 6 7 ... 42 43 44 8 9 127 0 Fsync MSB MSB LSB LSB Data_Out bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 ... Data_In bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 ... PCM_data_window CH1 data start FT = 0 CH1 data length = 11 CH2 data start FT = 43 CH2 data length = 8 Fsync period = 128 Fsync length = 1 twochpcm_swrs064 NOTE: FT stands for frame timer. Figure 6-14. 2-Channel Bus Timing 34 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 6.4.4 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Assisted Modes The CC2564C device contains an embedded coprocessor that can be used for multiple purposes (see Section 1.4). The CC2564C device uses the coprocessor to perform the LE functionality or to execute the assisted HFP 1.6 (WBS) or assisted A2DP functions. Only one of these functions can be executed at a time because they all use the same resources (that is, the coprocessor; see Table 3-1 for the modes of operation supported by each device). This section describes the assisted HFP 1.6 (WBS) and assisted A2DP modes of operation. These modes of operation minimize host processing and power by taking advantage of the device coprocessor to perform the voice and audio SBC processing required in HFP 1.6 (WBS) and A2DP profiles. This section also compares the architecture of the assisted modes with the common implementation of the HFP 1.6 and A2DP profiles. The assisted HFP 1.6 (WBS) and assisted A2DP modes of operation comply fully with the HFP 1.6 and A2DP Bluetooth specifications. For more information on these profiles, see the corresponding Bluetooth Profile Specification (www.bluetooth.org/en-us/specification/adopted-specifications). 6.4.4.1 Assisted HFP 1.6 (WBS) The HFP 1.6 Profile Specification adds the requirement for WBS support. The WBS feature allows twice the voice quality versus legacy voice coding schemes at the same air bandwidth (64 kbps). This feature is achieved using a voice sampling rate of 16 kHz, a modified subband coding (mSBC) scheme, and a packet loss concealment (PLC) algorithm. The mSBC scheme is a modified version of the mandatory audio coding scheme used in the A2DP profile with the parameters listed in Table 6-3. Table 6-3. mSBC Parameters PARAMETER VALUE Channel mode Mono Sampling rate 16 kHz Allocation method Loudness Subbands 8 Block length 15 Bitpool 26 The assisted HFP 1.6 mode of operation implements this WBS feature on the embedded CC2564C coprocessor. That is, the mSBC voice coding scheme and the PLC algorithm are executed in the CC2564C coprocessor rather than in the host, thus minimizing host processing and power. One WBS connection at a time is supported, and WBS and NBS connections cannot be used simultaneously in this mode of operation. Figure 6-15 shows the architecture comparison between the common implementation of the HFP 1.6 profile and the assisted HFP 1.6 solution. Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 35 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com HFP 1.6 Architecture Assisted HFP 1.6 Architecture Host Processor Host Processor PCM / I2S HFP1.6 Profile Control 16 kHz 16 bits Audio codec HFP1.6 Profile mSBC + PLC Control Data Bluetooth Stack Bluetooth Stack SCO L2CAP L2CAP HCI Control HCI Data Control HCI HCI CC256x Bluetooth Controller PCM / I2S 16 kHz 16 bits Data Audio codec CC256x Bluetooth Controller mSBC + PLC Copyright © 2016, Texas Instruments Incorporated Figure 6-15. HFP 1.6 Architecture Versus Assisted HFP 1.6 Architecture For detailed information on the HFP 1.6 profile, see the Hands-Free Profile 1.6 Specification (www.bluetooth.org/en-us/specification/adopted-specifications). 6.4.4.2 Assisted A2DP The advanced audio distribution profile (A2DP) enables wireless transmission of high-quality mono or stereo audio between two devices. A2DP defines two roles: • A2DP source is the transmitter of the audio stream. • A2DP sink is the receiver of the audio stream. A typical use case streams music from a tablet, phone, or PC (the A2DP source) to headphones or speakers (the A2DP sink). This section describes the architecture of these roles and compares them with the corresponding assisted-A2DP architecture. To use the air bandwidth efficiently, the audio data must be compressed in a proper format. The A2DP mandates support of the SBC scheme. Other audio coding algorithms can be used; however, both Bluetooth devices must support the same coding scheme. SBC is the only coding scheme spread out in all A2DP Bluetooth devices; thus, it is the only coding scheme supported in the assisted A2DP modes. Table 6-4 lists the recommended parameters for the SBC scheme in the assisted A2DP modes. 36 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 Table 6-4. Recommended Parameters for the SBC Scheme in Assisted A2DP Modes SBC ENCODER SETTINGS (1) Sampling frequency (kHz) MID QUALITY MONO HIGH QUALITY JOINT STEREO MONO JOINT STEREO 44.1 48 44.1 48 44.1 48 44.1 48 Bitpool value 19 18 35 33 31 29 53 51 Resulting frame length (bytes) 46 44 83 79 70 66 119 115 Resulting bit rate (Kbps) 127 132 229 237 193 198 328 345 (1) Other settings: Block length = 16; allocation method = loudness; subbands = 8. The SBC scheme supports a wide variety of configurations to adjust the audio quality. Table 6-5 through Table 6-12 list the supported SBC capabilities in the assisted A2DP modes. Table 6-5. Channel Modes CHANNEL MODE STATUS Mono Supported Dual channel Supported Stereo Supported Joint stereo Supported Table 6-6. Sampling Frequency SAMPLING FREQUENCY (kHz) STATUS 16 Supported 44.1 Supported 48 Supported Table 6-7. Block Length BLOCK LENGTH STATUS 4 Supported 8 Supported 12 Supported 16 Supported Table 6-8. Subbands SUBBANDS STATUS 4 Supported 8 Supported Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 37 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com Table 6-9. Allocation Method ALLOCATION METHOD STATUS SNR Supported Loudness Supported Table 6-10. Bitpool Values BITPOOL RANGE STATUS Assisted A2DP sink: 2–54 Supported Assisted A2DP source: 2–57 Supported Table 6-11. L2CAP MTU Size L2CAP MTU SIZE (BYTES) STATUS Assisted A2DP sink: 260–800 Supported Assisted A2DP source: 260–1021 Supported Table 6-12. Miscellaneous Parameters ITEM VALUE STATUS A2DP content protection Protected Not supported AVDTP service Basic type Supported L2CAP mode Basic mode Supported L2CAP flush Nonflushable Supported For detailed information on the A2DP profile, see the A2DP Profile Specification at Adopted Bluetooth Core Specifications. 38 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 6.4.4.2.1 Assisted A2DP Sink The role of the A2DP sink is to receive the audio stream in an A2DP Bluetooth connection. In this role, the A2DP layer and its underlying layers are responsible for link management and data decoding. To handle these tasks, two logic transports are defined: • Control and signaling logic transport • Data packet logic transport The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the CC2564C device. First, the assisted A2DP implements a light L2CAP layer (L-L2CAP) and light AVDTP layer (L-AVDTP) to defragment the packets. Then the assisted A2DP performs the SBC decoding on-chip to deliver raw audio data through the device PCM–I2S interface. Figure 6-16 shows the comparison between a common A2DP sink architecture and the assisted A2DP sink architecture. Assisted A2DP Sink Architecture A2DP Sink Architecture Host Processor Host Processor Bluetooth Stack PCM / I2S A2DP Profile 44.1 kHz 48 kHz 16 bits Bluetooth Stack Audio codec A2DP Profile SBC AVDTP Control AVDTP Data Control L2CAP L2CAP HCI HCI Control Contro l Data HCI Data HCI CC256x Bluetooth Controller PCM / I2S CC256x Bluetooth Controller 44.1 kHz 48 kHz 16 bits Audio codec SBC L-AVDTP L-L2CAP Copyright © 2016, Texas Instruments Incorporated Figure 6-16. A2DP Sink Architecture Versus Assisted A2DP Sink Architecture For more information on the A2DP sink role, see the A2DP Profile Specification at Adopted Bluetooth Core Specifications. Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 39 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com 6.4.4.2.2 Assisted A2DP Source The role of the A2DP source is to transmit the audio stream in an A2DP Bluetooth connection. In this role, the A2DP layer and its underlying layers are responsible for link management and data encoding. To handle these tasks, two logic transports are defined: • Control and signaling logic transport • Data packet logic transport The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the CC2564C device. First, the assisted A2DP encodes the raw data from the CC2564C PCM–I2S interface using an on-chip SBC encoder. Then the assisted A2DP implements an L-L2CAP layer and an L-AVDTP layer to fragment and packetize the encoded audio data. Figure 6-17 shows the comparison between a common A2DP source architecture and the assisted A2DP source architecture. A2DP Source Architecture Assisted A2DP Source Architecture Host Processor Host Processor Bluetooth Stack PCM / I2S A2DP Profile 44.1 kHz 48 kHz 16 bits Bluetooth Stack Audio codec A2DP Profile SBC AVDTP Control AVDTP Data Control L2CAP L2CAP HCI HCI Control Data Control HCI Data HCI CC256x Bluetooth Controller PCM / I2S CC256x Bluetooth Controller 44.1 kHz 48 kHz 16 bits Audio codec SBC L-AVDTP L-L2CAP Copyright © 2016, Texas Instruments Incorporated Figure 6-17. A2DP Source Architecture Versus Assisted A2DP Source Architecture For more information on the A2DP source role, see the A2DP Profile Specification at Adopted Bluetooth Core Specifications. 40 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 6.5 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Bluetooth BR and EDR Features The CC2564C device complies with the Bluetooth 5.1 specification up to the HCI layer (for family members and technology supported, see Table 3-1): • Up to seven active devices • Scatternet: Up to three piconets simultaneously, one as master and two as slaves • Up to two SCO links on the same piconet • Very fast AFH algorithm for asynchronous connection-oriented link (ACL) and eSCO link • Supports typical 12-dBm TX power without an external power amplifier (PA), thus improving Bluetooth link robustness • DRP single-ended 50-Ω I/O for easy RF interfacing • Internal temperature detection and compensation to ensure minimal variation in RF performance over temperature • Includes a 128-bit hardware encryption accelerator as defined by the Bluetooth specifications • Flexible PCM and I2S digital codec interface: – Full flexibility of data format (linear, A-Law, µ-Law) – Data width – Data order – Sampling – Slot positioning – Master and slave modes – High clock rates up to 15 MHz for slave mode (or 4.096 MHz for master mode) • Support for all voice air-coding – CVSD – A-Law – µ-Law – Transparent (uncoded) – mSBC • The CC2564C device provides an assisted mode for the HFP 1.6 (wideband speech [WBS]) profile or A2DP profile to reduce host processing and power. 6.6 Bluetooth Low Energy Description The CC2564C device complies with the Bluetooth 5.1 specification up to the HCI layer (for the family members and technology supported, see Table 3-1): • Solution optimized for proximity and sports use cases • Supports up to 10 simultaneous connections • Multiple sniff instances that are tightly coupled to achieve minimum power consumption • Independent buffering for low energy, allowing large numbers of multiple connections without affecting BR or EDR performance • Built-in coexistence and prioritization handling NOTE The assisted modes (HFP 1.6 and A2DP) are not available when Bluetooth low energy is enabled. Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 41 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 6.7 www.ti.com Bluetooth Transport Layers Figure 6-18 shows the Bluetooth transport layers. UART transport layer Host controller interface Data Control HCI data handler General modules: Event HCI command handler HCI vendorspecific Trace Data Link manager Timers Data Sleep Link controller RF SWRS121-016 Copyright © 2016, Texas Instruments Incorporated Figure 6-18. Bluetooth Transport Layers 6.8 Changes from the CC2564B Device to the CC2564C Device The CC2564C device includes the following changes: • Support added for standard HCI command for WBS to replace HCI VS command sequence – Part of the Core Specification Addendum 2 (CSA2) • Easy PCM interface integration when using both WBS (16 kHz) and NBS (8 kHz) • PLC support added for NBS (8 kHz) when working at 16-kHz PCM clock • Option added to start and stop the PCM clock as master on the PCM bus even when voice call is not active or set a timer to extend the clock after voice or audio is removed • Link layer topology support—Acts concurrently as peripheral and central low-energy device • AFH algorithm enhancements—Improvements to the automatic frequency hopping algorithms 42 Detailed Description Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 7 Applications, Implementation, and Layout NOTE Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 7.1 7.1.1 Reference Design Schematics and BOM VQFNP-MR Schematic and BOM Figure 7-1 shows the reference schematics for the VQFNP-MR package. For complete schematics and PCB layout guidelines, contact your TI representative. Applications, Implementation, and Layout Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 43 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 www.ti.com C1 50 Ohm 4 IN 22pF OUT 2 GND GND 3 1 2 ANT1 1 Antenna match. Pi network might be required depending on type of antenna. L1 can be replaced with 0 ohms and C2 DNP if no matching is required. L1 GND C2 GND FL1 GND U1A GND BT_RF B8 VDD_IO (1.62 V to 1.92 V) VCC_1V8_32K A26 A33 A32 A29 CC_HCI_TX_1V8 CC_HCI_RX_1V8 CC_HCI_RTS_1V8 CC_HCI_CTS_1V8 R1 10k 2 E/D VCC GND OUT 4 C18 0.1µF 3 32.768kHz A35 B32 B34 B33 CC_AUD_FSYNC_1V8 CC_AUD_CLK_1V8 CC_AUD_IN_1V8 CC_AUD_OUT_1V8 Y1 1 SLOW_CLK_INT_1V8 A25 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO HCI_RX HCI_TX HCI_RTS HCI_CTS AUD_FSYNC AUD_CLK AUD_IN AUD_OUT CL1.5_LDO_IN MLDO_IN SLOW_CLK MLDO_OUT MLDO_OUT MLDO_OUT MLDO_OUT GND GND A6 nSHUTDOWN_1V8 TX_DBG TP1 B24 A14 SHUTD TX_DBG NC G G XTALP XTALM 1 3 B4 A4 C19 10pF GND DIG_LDO_OUT DIG_LDO_OUT DIG_LDO_OUT DIG_LDO_OUT DIG_LDO_OUT DIG_LDO_OUT DIG_LDO_OUT A2 A3 B15 B27 B26 B36 B35 XTALP/FREFP XTALM/FREFM C20 10pF C4 0.1µF GND C5 0.1µF GND C6 0.1µF GND VBAT MLD_OUT B7 B2 A9 A5 B1 A8 A7 A12 26MHz C3 0.1µF B6 B5 SRAM_LDO_OUT ADC_PPA_LDO_OUT CL1.5_LDO_OUT DCO_LDO_OUT Y2 2 4 B25 B21 B22 B19 B18 A38 A34 A17 C7 1µF SLO C8 1µF C9 1µF ALO CLO DCLOl GND C10 0.1µF GND C11 0.1µF GND C12 0.1µF GND GND GND C13 0.1µF GND DIG_LDO_OUT GND CC2564CRV MR C14 0.1µF C15 0.47µF C16 0.47µF C17 0.1µF GND U1B GND A1 A10 A11 A13 A15 A16 A18 A19 A20 A21 A22 A23 A27 A30 A31 A36 A37 A39 A40 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS_FREF VSS_DCO VSS VSS EPAD GND B31 B30 B29 B28 B23 B20 B17 B16 B14 B13 B12 B10 B9 GND GND GND A10, A11, B9 and B9 are GND for improved RF performance B3 B11 GND A28 A24 D1 MR GND Copyright © 2017, Texas Instruments Incorporated Figure 7-1. Reference Schematics 44 Applications, Implementation, and Layout Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 Table 7-1 lists the BOM for the VQFNP-MR package. Table 7-1. Bill of Materials QUANTITY REFERENCE DESIGNATOR VALUE 1 ANT1 2.45-GHz Antenna ANT_IIFA_CC2420_32mil_MIR N/A IIFA_CC2420 1 C1 22 pF CAP, CERM, 22 pF, 50 V, ±5%, C0G/NP0, 0402 TDK C1005C0G1H220J050BA 0 - DNP C2 0.5 pF CAP, CERM, 0.5 pF, 50 V, ±10%, C0G/NP0, 0402 MuRata GRM1555C1HR50WA01 11 C3, C4, C5, C6, C10, C11, C12, C13, C14, C17, C18 0.1 µF "Capacitor, ceramic; 0.1-μF 6.3-V 10% X7R 0402" Kemet C0402C104K9RACTU 3 C7, C8, C9 1 µF "Capacitor, ceramic; 1.0-μF 6.3-V 10% X5R 0402" Taiyo Yuden JMK105BJ105KV-F 2 C15, C16 0.47 µF "Capacitor, ceramic; 0.47-μF 6.3-V X5R ±10% 0402" Taiyo Yuden JMK105BJ474KV-F 2 C19, C20 10 pF CAP, CERM, 10 pF, 50 V, ±5%, C0G/NP0, 0402 MuRata GRM1555C1H100JA01D 1 FL1 2.45-GHz Center Multilayer Band Pass Filter, SMD MuRata LFB212G45SG8C341 1 L1 0Ω RES, 0, 5%, 0.063 W, 0402 Vishay-Dale CRCW04020000Z0ED 1 R1 10k RES, 10 k, 5%, 0.063 W, 0402 Vishay-Dale CRCW040210K0JNED 1 U1 CC2564CRVM CC2564C dual-mode Bluetooth controller Texas Instruments CC2564CRVM 1 Y1 XO Oscillator XO Oscillator, 32.768 kHz, CMOS, 3.3 V, SMD Abracon Corporation ASH7K-32.768KHZ-T 1 Y2 Crystal Crystal, 26 MHz, 8 pF, SMD NDK NX2016SA-26.000M-STD-CZS-2 DESCRIPTION MANUFACTURER MANUFACTURER PART NUMBER Applications, Implementation, and Layout Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 45 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 7.2 www.ti.com VQFNP-MR PCB Layout Guidelines This section describes the PCB guidelines to speed up the PCB design using the CC256x VQFNP-MR device. Following these guidelines ensures that the design will pass Bluetooth SIG certification and also minimizes risk for regulatory certifications including FCC, ETSI, and CE. For more information, see CC256x QFN PCB Guidelines. 7.2.1 Power Supply Guidelines Guidelines for the power supply follow: • The trace width must be at least 10 mils for the VBAT and VIO traces. • The length of the traces must be as short as possible (pin to pin). • Decoupling capacitors must be as close as possible to the QFN device: – The MLDO_IN capacitor must be close to pin B5. – The VDD_IO capacitor must be close to pins B18 and A17. Guidelines for the LDOs follow: • The trace width for the trace between x_LDO_x pins and decoupling capacitors is at least 5 mils; where possible, the recommended trace width is 10 mils. • Place the decoupling capacitor of MLDO_OUT (C20) as close as possible to pin A5. • These capacitors must close to the following pins: – The DIG_LDO_OUT capacitor must be close to ball B15. – The DIG_LDO_OUT capacitor must be close to ball B27. – The DIG_LDO_OUT capacitor must be close to ball B36. • The DIG_LDO_OUT capacitor connected to ball B36 must be isolated from the top layer GND (see the Low-Dropout Capacitors section in CC256x QFN PCB Guidelines). • The decoupling capacitors for SRAM, ADCPPA, and CL1.5 LDO_OUT must be as close as possible to their corresponding pins on the CC256x device. • Place the device and capacitors together on the top side. • The ground connection of each capacitor must be directly connected to solid ground layer (layer 2). • The capacitor that is directly connected to pin A12 should be close to the device. • Connect the DCO_LDO_OUT capacitor isolated from layer 1 ground directly to layer 2 solid ground. Guidelines for the ground layer follow: • Layer 2 must be a solid ground plane. • Isolate VSS_FREF from ground on the top layer and route it directly to ground on the second layer (see the Key VSS Ball section in CC256x QFN PCB Guidelines). • Isolate VSS_DCO (ball B11) from ground. Include VSS_DCO in the illustration of the DCO_LDO_OUT capacitor (see the DCO_LDO_OUT section in CC256x QFN PCB Guidelines). • A minimum of 13 vias on the thermal pad are required to increase ground coupling. • Connect VSS_FREF (ball B3) directly to solid ground, not to the thermal pad. 46 Applications, Implementation, and Layout Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 7.2.2 SWRS199B – APRIL 2016 – REVISED JUNE 2020 User Interfaces Guidelines for the UART follow: • The trace width for the UART must be at least 5 mils. • Run the four UART lines as a bus interface. • Determine if clocks, DC supply, or RF traces are not near these UART traces. • The ground plane on layer 2 is solid below these lines and there is ground around these traces on the top layer. Guidelines for the PCM follow: • The trace width for the PCM must be at least 5 mils. • Run the four PCM lines as a bus interface and approximately the same length. • Determine if clocks, DC supply, RF traces, and LDO capacitors are not near these PCM traces. • The ground plane on layer 2 is solid below these lines and there is ground around these traces on the top layer. Guidelines for TX_DBG follow: • Check for an accessible test point on the board from TX_DBG pin H2. 7.2.3 Clock Interfaces Guidelines for the slow clock follow: • The trace width for the slow clock must be at least 5 mils. • The signal lines for the slow clock must be as short as possible. • The ground plane on layer 2 is solid below these lines and there is ground around these traces on the top layer. Guidelines for the fast clock follow: • The trace width for the fast clock must be at least 5 mils. • Ensure that crystal tuning capacitors are close to crystal pads. • Make both traces (XTALM and XTALP) parallel as much as possible and approximately the same length. • The ground plane on layer 2 is solid below these lines and there is ground around these traces on the top layer. Applications, Implementation, and Layout Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 47 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 7.2.4 www.ti.com RF Interface Guidelines for the RF Interface follow: • TI recommends using an RF shield (not mandatory). • Verify that RF traces are routed on the top layer and matched at 50 Ω with reference to ground. • Route the RF line between these NC pins: – NC_2 (A10) – NC_3 (A11) – NC_14 (B9) – NC_15 (B10) These NC pins are grounded for better RF isolation. NOTE These pins are NC at the chip level, but TI recommends grounding them on the PCB layout for better RF isolation. • • • • • • 48 Ensure the area underneath the BPF pads is grounded on layer 1 and layer 2. Keep RF_IN and RF_OUT of the BPF pads clear of any ground fill (see the RF Trace section in CC256x QFN PCB Guidelines). Follow guidelines specified in the vendor-specific antenna design guides (including placement of antenna). Follow guidelines specified in the vendor-specific BPF design guides. Verify that the Bluetooth RF trace is a 50-Ω, impedance-controlled trace with reference to solid ground. Ensure that the RF trace length is as short as possible. Applications, Implementation, and Layout Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com SWRS199B – APRIL 2016 – REVISED JUNE 2020 8 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed in the following sections. 8.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 8.2 Tools and Software Design Kits and Evaluation Modules HCI Tester This intuitive, user-friendly TI tool is used to evaluate TI's Bluetooth chips and can be downloaded as a complete package from the TI web site at WILINK-BT_WIFIWIRELESS_TOOLS. More specifically, the tool is used to configure the properties of the Bluetooth chip through the Service Pack (SP) and also allows testing of RF performance. Software TI offers the flexibility to choose from a number of application processors with a royalty-free stack. For more details on the different combinations, see the CC256x Getting Started Selection Guide. For a complete listing of development-support tools, see the TI CC256x wiki. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Device and Documentation Support Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 49 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 8.3 www.ti.com Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, CC2564CRVMR). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RVM), and the temperature range (for example, blank is the default commercial temperature range). Figure 8-1 provides a legend for reading the complete device name for any CC2564CRVMR device. For orderable part numbers of CC2564CRVMR devices in the RVM package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative. CC2564C XXX X Prefix X = Experimental device Blank = Qualified device R = Large Reel T = Small Reel Package Designator Generic Part Number RVM = VQFNP-MR Copyright © 2016, Texas Instruments Incorporated Figure 8-1. CC2564C Device Nomenclature 50 Device and Documentation Support Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C CC2564C www.ti.com 8.4 SWRS199B – APRIL 2016 – REVISED JUNE 2020 Documentation Support To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The current documentation that describes the DSP, related peripherals, and other technical collateral is listed in the following. Application Reports Application Notes for CC2564C Bluetooth® 4.1 and 4.2 The CC2564C device is the successor of the CC2564B device as a dual-mode Bluetooth® Classic and Bluetooth low energy chip. The CC2564C adds new and significant capabilities to the CC2564B. QFN/SON PCB Attachment Quad flatpack no leads (QFNs) and small-outline no leads (SONs) are leadless packages with electrical connections made via lands on the bottom side of the component to the surface of the connecting substrate (PCB, ceramic). This application report presents users with introductory information about attaching QFN/SON devices to printed circuit boards (PCBs). User's Guides CC2564B to CC2564C Migration Guide The CC2564C device is TI’s third generation of the CC2564 dual mode Bluetooth® and Bluetooth low energy single-chip solution. Support for both Bluetooth 4.1 and Bluetooth 4.2 support is implemented. CC256xC QFN EM User’s Guide This user's guide is intended for use with TI's Bluetooth® development platform, the CC256xCQFN-EM board. This guide helps users quickly get started integrating the board with TI's evaluation platforms and software SDKs. In addition, this user's guide describes the components and configurations of the board so that users can quickly get started using it for various Bluetooth applications. This guide provides information about the module so that developers can use the board specifics to apply it to their applications. Module information and capabilities, including pin descriptions as well as available software and tools, enhance the user's out-of-box experience. White Papers CC256x Series: Why Classic Bluetooth® (BR/EDR)? Bluetooth® technology is a proven, robust, and widely spread technology. According to Bluetooth SIG®, there are more than 8 billion devices are in circulation, including a strong presence in approximately 95% of all existing mobile phones and smartphones. This technology presents a complete solution for wirelessly transmitting audio, voice, and data. Bluetooth is a well-defined protocol up to the application level, which creates leading interoperability and compatibility between different devices and manufacturers. Which TI Bluetooth® Solution Should I Choose? Texas Instruments™ offers multiple Bluetooth® solutions, so it might be confusing to choose the correct part. Whether you want to add Bluetooth technology to an existing device or create a new Bluetooth product, the question is: which TI device should be chosen? Design Files CC256x Reference Design Files CC2564 Audio Sink Reference Design CC256x Hardware Design Checklist More Literature TI Bluetooth® CC2564C Solution The TI dual-mode CC2564C solution is a complete Bluetooth® BR / EDR / LE HCI or Bluetooth + Bluetooth low energy solution that reduces design effort and enables fast time to market. Dual-Mode Bluetooth® CC2564CQFN-EM Evaluation Board This quick start guide offers an overview of the Dual-Mode Bluetooth® CC256XCQFN-EM evaluation board, including the required hardware and software tools, and describes the basic settings. For more information on using the CC256XCQFN-EM board, see the Dual-Mode Bluetooth® CC2564C Evaluation Board User's Guide. Device and Documentation Support Copyright © 2016–2020, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564C 51 CC2564C SWRS199B – APRIL 2016 – REVISED JUNE 2020 8.5 www.ti.com Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 8.6 Trademarks Texas Instruments, TI E2E are trademarks of Texas Instruments. ARM7TDMI is a registered trademark of ARM Limited. iPod is a registered trademark of Apple, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. 8.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.8 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 8.9 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 52 Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564C Copyright © 2016–2020, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 29-Dec-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CC2564CRVMR ACTIVE VQFNP-MR RVM 76 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 CC2564C CC2564CRVMT ACTIVE VQFNP-MR RVM 76 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 CC2564C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of