CD74HC4017QPWRG4Q1

CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25°C Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads D Significant Power Reduction Compared to LSTTL Logic ICs D VCC Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V M OR PW PACKAGE (TOP VIEW) 5 1 0 2 6 7 3 GND D Balanced Propagation Delay and Transition Times description/ordering information 1 16 2 15 3 14 4 13 5 12 6 11 7 10 VCC MR CP CE TC 9 4 8 8 9 The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low. The device can drive up to ten low-power Schottky equivalent loads. ORDERING INFORMATION{ SOIC − M −40°C 40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA Tape and reel TSSOP − PW Tape and reel TOP-SIDE MARKING CD74HC4017QM96Q1 HC4017Q CD74HC4017QPWRQ1 HC4017Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE INPUTS CP CE MR OUTPUT STATE† L X L No change X H L No change X X H 0 = H, 1−9 = L ↑ L L Increments counter ↓ X L No change X ↑ L No change H ↓ L Increments counter NOTE: H = high voltage level, L = low voltage level, X = don’t care, ↑ = transition from low to high level, ↓ = transition from high to low level † If n < 5, TC = H, otherwise TC = L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 logic diagram (positive logic) 3 CP 2 14 4 CE 13 7 10 MR 15 1 5 6 9 11 12 0 1 2 3 4 5 Decoded Decimal Out 6 7 8 9 TC absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < −0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Source or sink current per output pin, IO (VO > −0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to GND unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level High level input voltage VCC = 2 V MIN MAX 2 6 UNIT V 1.5 VCC = 4.5 V 3.15 VCC = 6 V V 4.2 VCC = 2 V 0.5 VCC = 4.5 V 1.35 VIL Low-level Low level input voltage VI Input voltage 0 VCC V VO Output voltage 0 VCC V tt Input transition (rise and fall) time VCC = 6 V TA V 1.8 VCC = 2 V 0 1000 VCC = 4.5 V 0 500 VCC = 6 V 0 400 −40 125 Operating free-air temperature ns °C NOTES: 3. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS CMOS loads VOH VI = VIH or VIL TTL loads CMOS loads VOL VI = VIH or VIL TTL loads II VI = VCC or GND ICC VI = VCC or GND CIN CL = 50 pF VCC −0.02 2V 1.9 1.9 −0.02 4.5 V 4.4 4.4 −0.02 6V 5.9 5.9 3.7 MIN MAX MIN MAX UNIT V −4 4.5 V 3.98 −5.2 6V 5.48 0.02 2V 0.1 0.1 0.02 4.5 V 0.1 0.1 0.02 6V 0.1 0.1 4 4.5 V 0.26 0.4 5.2 6V 0.26 0.4 6V ±0.1 ±1 µA 6V 8 160 µA 10 10 pF 0 POST OFFICE BOX 655303 TA = 25°C IO (mA) • DALLAS, TEXAS 75265 5.2 V 3 CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER fmax VCC Maximum clock frequency CP tw Pulse duration MR CE to CP tsu Setup time MR inactive th 4 Hold time,, CE to CP POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA = 25°C MIN MAX MIN 2V 6 4 4.5 V 30 20 6V 35 23 2V 80 120 4.5 V 16 24 6V 14 20 2V 80 120 4.5 V 16 24 6V 14 20 2V 75 110 4.5 V 15 22 6V 13 19 2V 5 5 4.5 V 5 5 6V 5 5 2V 0 0 4.5 V 0 0 6V 0 0 MAX UNIT MHz ns ns ns CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) Decade out VCC 2V 230 345 CL = 50 pF 4.5 V 46 69 6V 39 59 2V 230 345 4.5 V 46 69 39 59 2V 250 375 4.5 V 50 75 6V 43 64 2V 250 375 4.5 V 50 75 43 64 2V 230 345 4.5 V 46 69 6V 39 59 CL = 15 pF CP CL = 50 pF TC Decade out CL = 50 pF CL = 15 pF CE CL = 50 pF TC Decade out MR TC CL = 50 pF TC, Decade out CP MAX 5V 5V 5V MIN MAX 19 21 2V 230 345 CL = 50 pF 4.5 V 46 69 6V 39 59 2V 75 110 4.5 V 15 22 6V 13 19 CL = 50 pF CL = 15 pF 5V ns 21 5V 5V UNIT 19 CL = 15 pF CL = 15 pF fmax TYP 6V CL = 15 pF tt 5V MIN 6V CL = 15 pF tpd TA = 25°C LOAD CAPACITANCE 19 19 60 ns MHz operating characteristics, VCC = 5 V, TA = 25°C, input tr, tf = 6 ns, CL = 15 pF PARAMETER Cpd TYP Power dissipation capacitance (see Note 4) 39 UNIT pF NOTE 4: Cpd is used to determine the dynamic power consumption per package. PD = (Cpd × VCC2 × fi) + Σ(CL × VCC2 × fO) fI = input frequency fO = output frequency CL = output load capacitance VCC = supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0V tPLH VCC Reference Input In-Phase Output 50% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 CL CL P P N N D Q CL CL CL CL P CL C N CL P Q N CL R Figure 2. Flip-Flop Detail CP MR CE 0 1 2 3 4 5 6 0 0 1 1 2 2 3 4 5 6 7 7 8 8 9 9 TC Figure 3. Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CD74HC4017QPWRG4Q1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC4017Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of