CSD17303Q5
www.ti.com
SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
30V N-Channel NexFET™ Power MOSFET
Check for Samples: CSD17303Q5
FEATURES
1
•
•
•
•
•
•
•
•
2
PRODUCT SUMMARY
Optimized for 5V Gate Drive
Ultralow Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
VDS
Drain to Source Voltage
30
V
Qg
Gate Charge Total (4.5V)
18
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
•
DESCRIPTION
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications,
and optimized for 5V gate drive applications.
Top View
8
1
2
7
D
S
3
6
D
G
4
VGS = 4.5V
2
mΩ
VGS = 8V
1.7
mΩ
Threshold Voltage
1.1
V
Package
Media
CSD17303Q5
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Qty
Ship
2500
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
+10 / –8
V
Continuous Drain Current, TC = 25°C
100
A
Continuous Drain Current(1)
32
A
IDM
Pulsed Drain Current, TA = 25°C(2)
200
A
PD
Power Dissipation(1)
3.2
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 103A, L = 0.1mH, RG = 25Ω
530
mJ
ID
(1) RqJA = 39°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick)
Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
(2) Pulse duration ≤300ms, duty cycle ≤2%
D
5
mΩ
Device
D
S
nC
2.7
ORDERING INFORMATION
Notebook Point-of-Load
Point-of-Load Synchronous Buck in
Networking, Telecom and Computing Systems
Optimized for Synchronous FET Applications
S
Drain to Source On Resistance
VGS(th)
APPLICATIONS
•
•
4
VGS = 3V
D
P0094-01
RDS(on) vs VGS
GATE CHARGE
8
ID = 25A
VGS - Gate-to-Source Voltage - V
RDS(on) - On-State Resistance - mΩ
6
5
T C = 125°C
4
3
2
T C = 25°C
1
0
ID = 25A
VDS = 15V
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
0
5
10
15
20
25
Qg - Gate Charge - nC
30
35
G003
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CSD17303Q5
SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, ID = 250mA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = +10/–8V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, ID = 250mA
30
0.9
Drain to Source On Resistance
gfs
Transconductance
mA
100
nA
1.1
1.6
V
2.7
3.7
mΩ
2
2.6
mΩ
VGS = 8V, ID = 25A
1.7
2.4
mΩ
VDS = 15V, ID = 25A
114
VGS = 3V, ID = 25A
RDS(on)
V
1
VGS = 4.5V, ID = 25A
S
Dynamic Characteristics
Ciss
Input Capacitance
VGS = 0V, VDS = 15V,
f = 1MHz
2630 3420
pF
1440 1870
pF
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
83
108
pF
RG
Series Gate Resistance
1.4
2.8
Ω
Qg
Gate Charge Total (4.5V)
18
23
nC
Qgd
Gate Charge Gate to Drain
Qgs
Gate Charge Gate to Source
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
td(off)
Turn Off Delay Time
tf
Fall Time
VDS = 15V,
IDS = 25A
4
nC
5.6
nC
3
nC
VDS = 13.7V, VGS = 0V
34
nC
11.4
ns
16
ns
27
ns
10.4
ns
VDS = 15V, VGS = 4.5V,
IDS = 25A, RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 25A, VGS = 0V
0.8
VDD = 13.7V, IF = 25A, di/dt = 300A/ms
1
V
50
nC
33
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
MAX
UNIT
RqJC
Thermal Resistance Junction to Case (1)
PARAMETER
1.1
°C/W
RqJA
Thermal Resistance Junction to Ambient (1) (2)
49
°C/W
(1)
(2)
2
MIN
TYP
RqJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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CSD17303Q5
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SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
GATE
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RqJA = 49°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Source
Max RqJA = 124°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
Text
Text
Text
and
and
and
br
br
br
Added
Added
Added
for
for
for
Spacing
Spacing
Spacing
TYPICAL MOSFET CHARACTERISTICS
TA = 25°C, unless otherwise specified
ZqJA - Normalized Thermal Impedance
10
1
0.5
0.3
0.1
Duty Cycle = t1/t2
0.1
0.05
P
0.02
0.01
t1
0.01
t2
Typical RqJA = 99°C/W (min Cu)
TJ = P ´ ZqJA ´ RqJA
Single Pulse
0.001
0.001
0.01
0.1
1
tp - Pulse Duration - s
10
100
1k
G012
Figure 1. Transient Thermal Impedance
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CSD17303Q5
SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless otherwise specified
TEXT ADDED FOR SPACING
80
45
70
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
TEXT ADDED FOR SPACING
50
40
VGS = 8V
35
30
VGS = 4.5V
25
VGS = 3.5V
20
15
VGS = 3V
10
5
VGS = 2.5V
0
0
0.1
0.2
0.3
0.4
VDS - Drain-to-Source Voltage - V
0.5
VDS = 5V
60
50
T C = 125°C
40
T C = 25°C
30
T C = -55°C
20
10
0
1.1
0.6
1.3
1.5
1.7
1.9
2.1
2.3
VGS - Gate-to-Source Voltage - V
G001
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
ID = 25A
VDS = 15V
7
f = 1MHz
VGS = 0V
6
6
C - Capacitance - nF
VGS - Gate-to-Source Voltage - V
G002
7
5
4
3
2
5
Coss = Cds + Cgd
4
Ciss = Cgd + Cgs
3
2
Crss = Cgd
1
1
0
0
0
5
10
15
20
25
Qg - Gate Charge - nC
30
35
0
5
10
15
20
VDS - Drain-to-Source Voltage - V
G003
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
30
G004
TEXT ADDED FOR SPACING
6
RDS(on) - On-State Resistance - mΩ
ID = 250µA
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-75
25
Figure 5. Capacitance
1.6
VGS(th) - Threshold Voltage - V
2.7
Figure 3. Transfer Characteristics
8
ID = 25A
5
T C = 125°C
4
3
2
T C = 25°C
1
0
-25
25
75
T C - Case Temperature - °C
125
175
0
1
G005
Figure 6. Threshold Voltage vs. Temperature
4
2.5
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
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SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless otherwise specified
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
ID = 25A
VGS = 8V
1.4
ISD - Source-to-Drain Current - A
Normalized On-State Resistance
1.6
1.2
1
0.8
0.6
0.4
0.2
-75
10
1
T C = 125°C
0.1
T C = 25°C
0.01
0.001
0.0001
-25
25
75
T C - Case Temperature - °C
125
175
0
0.2
G007
Figure 8. Normalized On-State Resistance vs. Temperature
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
I(AV) - Peak Avalanche Current - A
IDS - Drain-to-Source Current - A
1ms
10
0.01
0.01
G008
1k
100
0.1
1
Figure 9. Typical Diode Forward Voltage
1k
1
0.4
0.6
0.8
VSD - Source-to-Drain Voltage - V
10ms
100ms
1001
Area Limited
by RDS(on)
1s
Single Pulse
Typical R θJA = 99°C/W (min Cu)
DC
0.1
1
10
VDS - Drain-to-Source Voltage - V
100
T C = 25°C
100
T C = 125°C
10
1
0.01
0.1
1
10
t(AV) - Time in Avalanche - ms
G009
Figure 10. Maximum Safe Operating Area
100
G010
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain-to-Source Current - A
120
100
80
60
40
20
0
-50
-25
0
25
50
75
100 125
T C - Case Temperature - °C
150
175
G011
Figure 12. Maximum Drain Current vs. Temperature
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CSD17303Q5
SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
www.ti.com
MECHANICAL DATA
Q5 Package Dimensions
K
L
L
c1
E1
E2
b
D2
4
4
5
5
e
3
6
3
6
E
D1
7
7
2
2
8
8
1
1
q
Top View
Bottom View
Side View
c
E1
A
q
Front View
M0140-01
DIM
MILLIMETERS
MAX
MIN
MAX
A
0.950
1.050
0.037
0.039
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
D1
4.900
5.100
0.193
0.201
D2
4.320
4.520
0.170
0.178
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.920
4.12
0.154
e
6
INCHES
MIN
1.27 TYP
K
0.760
L
0.510
q
0.00
0.162
0.050
0.030
0.710
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0.020
0.028
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17303Q5
CSD17303Q5
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SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
DIM
Recommended PCB Pattern
F1
F7
F3
8
1
F2
F11
F5
F9
5
4
F6
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
F1
6.205
6.305
0.244
0.248
F2
4.460
4.560
0.176
0.180
F3
4.460
4.560
0.176
0.180
F4
0.650
0.700
0.026
0.028
F5
0.620
0.670
0.024
0.026
F6
0.630
0.680
0.025
0.027
F7
0.700
0.800
0.028
0.031
F8
0.650
0.700
0.026
0.028
F9
0.620
0.670
0.024
0.026
F10
4.900
5.000
0.193
0.197
F11
4.460
4.560
0.176
0.180
F8
F4
F10
M0139-01
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
Q5 Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
R 0.30 TYP
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
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CSD17303Q5
SLPS246B – JANUARY 2010 – REVISED SEPTEMBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (January 2010) to Revision A
Page
•
Changed the Abs Max Ratings table, Avalanche Energy, single pulse From: ID = 85A, L = 0.1mH, RG = 25Ω Value =
361 To: ID = 103A, L = 0.1mH, RG = 25Ω Value = 530 ........................................................................................................ 1
•
Changed Figure 11 ............................................................................................................................................................... 5
Changes from Revision A (February 2010) to Revision B
•
8
Page
Deleted the Package Marking Information section ............................................................................................................... 7
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD17303Q5
ACTIVE
VSON-CLIP
DQH
8
2500
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-55 to 150
CSD17303
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of