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CSD17552Q3A
SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
CSD17552Q3A 30 V N-Channel NexFET™ Power MOSFETs
1 Features
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free
RoHS Compliant
Halogen Free
SON 3.3 mm × 3.3 mm Plastic Package
TA = 25°C
TYPICAL VALUE
Drain-to-Source Voltage
30
V
Qg
Gate Charge Total (4.5 V)
9.0
nC
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
•
Point-of-Load Synchronous Buck in Networking,
Telecom, and Computing Systems
Optimized for Control FET Applications
This 30 V, 5.5 mΩ, 3.3 mm × 3.3 mm SON
NexFET™ power MOSFET is designed to minimize
losses in power conversion applications.
S
VGS = 10 V
5.5
mΩ
1.5
V
DEVICE
QTY
MEDIA
PACKAGE
SHIP
CSD17552Q3A
2500
13-Inch Reel
CSD17552Q3AT
250
7-Inch Reel
SON
3.3 mm × 3.3 mm
Plastic Package
Tape and
Reel
8
1
7
2
6
3
5
4
Absolute Maximum Ratings
VALUE
UNIT
Drain-to-Source Voltage
30
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current, TC = 25°C
60
TA = 25°C unless otherwise stated
A
Continuous Drain Current, Silicon Limited
74
A
Continuous Drain Current, TA = 25°C(1)
15
A
IDM
Pulsed Drain Current, TA = 25°C(2)
84
A
PD
Power Dissipation(1)
2.6
W
D
TJ,
Tstg
Operating Junction Temperature,
Storage Temperature
–55 to 150
°C
D
EAS
Avalanche Energy, single pulse
ID = 30 A, L = 0.1 mH, RG = 25 Ω
45
mJ
ID
D
D
D
G
mΩ
VDS
Top View
S
nC
6.5
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
S
2.3
VGS = 4.5 V
Ordering Information(1)
2 Applications
•
UNIT
VDS
P0093-01
(1) Typical RθJA = 48°C/W on a 1 inch2 (6.45 cm2),
2 oz. (0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick
FR4 PCB.
(2) Pulse duration ≤300 μs, duty cycle ≤2%
SPACE
SPACE
RDS(on) vs VGS
Gate Charge
10
TC = 25°C Id = 11A
TC = 125ºC Id = 11A
16
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
18
14
12
10
8
6
4
2
0
0
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
12
G001
ID = 11A
VDS =15V
8
6
4
2
0
0
5
10
15
Qg - Gate Charge (nC)
20
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD17552Q3A
SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1
6.2
6.3
6.4
7
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1
7.2
7.3
7.4
Q3A Package Dimensions ........................................ 8
Q3A Recommended PCB Pattern ............................ 9
Q3A Recommended Stencil Pattern ......................... 9
Q3A Tape and Reel Information ............................. 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2014) to Revision B
Page
•
Enhanced Description text ..................................................................................................................................................... 1
•
Added Community Resources section ................................................................................................................................... 7
•
Updated package drawing ...................................................................................................................................................... 8
•
Updated PCB drawing ............................................................................................................................................................ 9
•
Updated Stencil Pattern drawing ............................................................................................................................................ 9
Changes from Original (September 2012) to Revision A
Page
•
Changed "Pb-Free terminal plating" feature to state "Pb Free" ............................................................................................ 1
•
Updated package dimensions ................................................................................................................................................ 8
2
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SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 24 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
30
1.1
V
1.5
1.9
V
VGS = 4.5 V, ID = 11 A
6.5
8.1
mΩ
VGS = 10 V, ID = 11 A
5.5
6.0
mΩ
VDS = 15 V, ID = 11 A
106
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (4.5 V)
Qgd
Gate charge gate to drain
Qgs
Gate charge gate to source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
Turn on delay time
tr
Rise time
7.4
ns
td(off)
Turn off delay time
11.0
ns
tf
Fall time
3.4
ns
VGS = 0 V, VDS = 15 V, ƒ = 1 MHz
VDS = 15 V, ID = 11 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 11 A, RG = 2 Ω
1580
2050
pF
385
500
pF
28
36
pF
.9
1.8
Ω
9
12
nC
2.3
nC
3.6
nC
1.8
nC
11
nC
7.2
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
ISD = 11 A, VGS = 0 V
0.8
1
V
Qrr
Reverse recovery charge
nC
Reverse recovery time
VDS= 13.5 V, IF = 11 A,
di/dt = 300 A/μs
17
trr
15
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance (1)
THERMAL METRIC
2.3
°C/W
RθJA
Junction-to-ambient thermal resistance (1) (2)
60
°C/W
(1)
(2)
MIN
TYP
RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
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3
CSD17552Q3A
SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
GATE
www.ti.com
GATE
Source
Source
Max RθJA = 60°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick)
Cu.
Max RθJA = 146°C/W
when mounted on a
minimum pad area of 2
oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
60
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
100
80
60
40
VGS =10V
VGS =6.5V
VGS =4.5V
20
0
0
0.5
1
VDS - Drain-to-Source Voltage (V)
VDS = 5V
40
20
TC = 125°C
TC = 25°C
TC = −55°C
0
1.5
0
Figure 2. Saturation Characteristics
5
G001
10000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 11A
VDS =15V
C − Capacitance (pF)
8
6
4
1000
100
2
0
0
5
10
15
Qg - Gate Charge (nC)
10
20
0
10
20
VDS - Drain-to-Source Voltage (V)
G001
Figure 4. Gate Charge
30
G001
Figure 5. Capacitance
2.5
18
RDS(on) - On-State Resistance (mΩ)
ID = 250uA
VGS(th) - Threshold Voltage (V)
2
3
4
VGS - Gate-to-Source Voltage (V)
Figure 3. Transfer Characteristics
10
VGS - Gate-to-Source Voltage (V)
1
G001
2
1.5
1
0.5
0
−75
−25
25
75
125
TC - Case Temperature (ºC)
Figure 6. Threshold Voltage vs Temperature
175
TC = 25°C Id = 11A
TC = 125ºC Id = 11A
16
14
12
10
8
6
4
2
0
0
G001
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
12
G001
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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CSD17552Q3A
SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
www.ti.com
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100
VGS = 4.5V
VGS = 10V
2.1
ID =11A
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
2.4
1.8
1.5
1.2
0.9
0.6
0.3
−75
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs Temperature
80
1ms
10ms
1000
100ms
1s
DC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
G001
Figure 9. Typical Diode Forward Voltage
5000
100
10
1
0.1
1
Single Pulse
Typical RthetaJA =146ºC/W(min Cu)
0.01
0.01
0.1
1
10
VDS - Drain-to-Source Voltage (V)
50
TC = 25ºC
TC = 125ºC
10
1
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain- to- Source Current (A)
140.0
Silicon limited
Package limited
120.0
100.0
80.0
60.0
40.0
20.0
0.0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD17552Q3A
SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3A Package Dimensions
3.1
2.9
B
A
PIN 1 INDEX AREA
3.25
3.05
2X 0.15 MAX
2X (0.2)
3.5
TYP
3.1
C
0.9 MAX
SEATING PLANE
0.05
0.00
(0.2)
1.74±0.1
4X
0.52
0.32
0.565±0.1
(0.15) TYP
EXPOSED THERMAL PAD
NOTE 3
4
5
9
2X 1.95
2.45±0.1
0.65 TYP
8
1
4X
0.55
0.25
8X
4X 1.45
2X
NOTE 4
0.35
0.25
0.1
0.05
C B
C
A
4222499/A 12/2015
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
performance.
4. Metalized features are supplier options and may not be on the package.
5. All dimensions do not include mold flash or protrusions.
8
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SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
7.2 Q3A Recommended PCB Pattern
(1.775)
PKG
0.05 MIN
ALL SIDES
(0.635)
TYP
(0.56)
4X (0.3)
4X (0.6)
1
8
4X (0.3)
(R0.05)
TYP
(0.975)
TYP
9
SYMM
(2.45)
3X (0.65)
3X (0.65)
4
5
(R0.05) TYP
SOLDER MASK
OPENING
(0.207)
METAL UNDER
SOLDER MASK
(0.245)
( 0.2) VIA
TYP
(0.905)
TYP
(1.55)
LAND PATTERN EXAMPLE
1. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON
PCB Attachment application report, SLUA271.
2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
7.3 Q3A Recommended Stencil Pattern
(0.905)
PKG
8X (0.6)
(0.208)
SOLDER MASK EDGE
1
8
8X (0.3)
(0.663)
SYMM
9
(1.325)
6X (0.65)
4X 1.125
5
4
(R0.05) TYP
4X 0.705
METAL
TYP
(3.1)
1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
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CSD17552Q3A
SLPS387B – SEPTEMBER 2012 – REVISED JANUARY 2016
www.ti.com
1.75 ±0.10
7.4 Q3A Tape and Reel Information
4.00 ±0.10 (See Note 1)
Ø 1.50
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
2.00 ±0.05
3.60
M0144-01
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, non-cumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and convection) PbF-reflow compatible
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD17552Q3A
ACTIVE
VSONP
DNH
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-55 to 150
17552
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of