CSD18537NQ5AT

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents CSD18537NQ5A SLPS391B – JUNE 2013 – REVISED JULY 2014 CSD18537NQ5A 60-V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • 1 Product Summary Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5 mm × 6 mm Plastic Package TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 60 V Qg Gate Charge Total (10 V) 14 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On Resistance VGS(th) Threshold Voltage 2.3 nC VGS = 6 V VGS = 10 V 13 mΩ 10 mΩ 3 V Ordering Information(1) 2 Applications • • UNIT VDS High-Side Synchronous Buck Converter Motor Control Device Qty Media Package Ship CSD18537NQ5A 2500 13-Inch Reel CSD18537NQ5AT 250 7-Inch Reel SON 5 x 6 mm Plastic Package Tape and Reel 3 Description (1) For all available packages, see the orderable addendum at the end of the data sheet. This 10 mΩ, 60 V, SON 5 mm x 6 mm NexFET™ power MOSFET is designed to minimize losses in power conversion applications. TA = 25°C Top View S 8 1 Absolute Maximum Ratings VALUE UNIT VDS Drain-to-Source Voltage 60 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 50 Continuous Drain Current (Silicon limited), TC = 25°C 54 D ID S 7 2 D IDM S 3 G 4 Continuous Drain Current(1) 11 Pulsed Drain Current(2) 151 Power Dissipation(1) 3.2 Power Dissipation, TC = 25°C 75 –55 to 150 °C 55 mJ 6 D PD 5 D TJ, Tstg Operating Junction and Storage Temperature Range EAS Avalanche Energy, single pulse ID = 33 A, L = 0.1 mH, RG = 25 Ω D P0093-01 A A W (1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06-inch thick FR4 PCB. (2) Max RθJC = 2.1°C/W, pulse duration ≤100 µs, duty cycle ≤1% RDS(on) vs VGS Gate Charge 10 TC = 25°C Id = 12A TC = 125ºC Id = 12A 32 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 36 28 24 20 16 12 8 4 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 12A VDS = 30V 9 8 7 6 5 4 3 2 1 0 0 3 6 9 Qg - Gate Charge (nC) 12 15 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD18537NQ5A SLPS391B – JUNE 2013 – REVISED JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q5A Package Dimensions ........................................ 9 Recommended PCB Pattern................................... 10 Recommended Stencil Opening ............................. 11 Q5A Tape and Reel Information ............................. 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2014) to Revision B Page • Reduced silicon current limit to 54 A due to increase in RθJC ............................................................................................... 1 • Increased pulsed current limit to 151 .................................................................................................................................... 1 • Added line for maximum power dissipation with case temperature held to 25ºC ................................................................. 1 • Updated the pulsed current conditions .................................................................................................................................. 1 • Increased the maximum RθJC to 2.1 ºC/W ............................................................................................................................. 3 • Updated Figure 1 from a normalized RθJA curve to an RθJC curve ......................................................................................... 4 • Updated Figure 10 to show an improved SOA....................................................................................................................... 5 • Updated Figure 12 to show a 50-A package current limit ..................................................................................................... 5 Changes from Original (June 2013) to Revision A Page • Added part number to title ...................................................................................................................................................... 1 • Added more information to description................................................................................................................................... 1 • Updated ordering information to include small reel information ............................................................................................. 1 • Removed TC = 25°C condition from package limited continuous drain current ..................................................................... 1 2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A CSD18537NQ5A www.ti.com SLPS391B – JUNE 2013 – REVISED JULY 2014 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 48 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On Resistance gƒs Transconductance 60 2.6 V 3 3.5 V VGS = 6 V, ID = 12 A 13 17 mΩ VGS = 10 V, ID = 12 A 10 13 mΩ VDS = 30 V, ID = 12 A 62 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (10 V) 14 Qgd Gate Charge Gate-to-Drain Qgs Gate Charge Gate-to-Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tƒ Fall Time VGS = 0 V, VDS = 30 V, ƒ = 1 MHz VDS = 30 V, ID = 12 A VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 10 V, IDS = 12 A, RG = 0 Ω 1140 1480 pF 136 177 pF 4 5.2 pF 5.5 11 Ω 18 nC 2.3 nC 4.7 nC 3.3 nC 25 nC 5.8 ns 4 ns 14.4 ns 3.2 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 12 A, VGS = 0 V 0.8 VDS= 30 V, IF = 12 A, di/dt = 300 A/μs 1 V 54 nC 40 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC (1) RθJC Junction-to-Case Thermal Resistance RθJA Junction-to-Ambient Thermal Resistance (1) (2) MIN TYP MAX 2.1 (1) (2) 50 UNIT °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A 3 CSD18537NQ5A SLPS391B – JUNE 2013 – REVISED JULY 2014 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A CSD18537NQ5A www.ti.com SLPS391B – JUNE 2013 – REVISED JULY 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 50 45 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 50 40 35 30 25 20 15 VGS =10V VGS =8V VGS =6V 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VDS - Drain-to-Source Voltage (V) 0.7 VDS = 5V 40 30 20 0 0.8 TC = 125°C TC = 25°C TC = −55°C 10 0 1 Figure 2. Saturation Characteristics C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) ID = 12A VDS = 30V 8 7 6 5 4 3 8 G001 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1000 100 10 2 1 0 0 3 6 9 Qg - Gate Charge (nC) 12 1 15 0 10 20 30 40 50 VDS - Drain-to-Source Voltage (V) G001 Figure 4. Gate Charge 60 G001 Figure 5. Capacitance 3.6 36 RDS(on) - On-State Resistance (mΩ) ID = 250uA VGS(th) - Threshold Voltage (V) 7 Figure 3. Transfer Characteristics 20000 10000 10 9 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) G001 3.4 3.2 3 2.8 2.6 2.4 2.2 2 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs Temperature 175 TC = 25°C Id = 12A TC = 125ºC Id = 12A 32 28 24 20 16 12 8 4 0 0 2 G001 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A 5 CSD18537NQ5A SLPS391B – JUNE 2013 – REVISED JULY 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 2 100 VGS = 6V VGS = 10V ISD − Source-to-Drain Current (A) Normalized On-State Resistance 2.2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 −75 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 ID =12A −25 25 75 125 TC - Case Temperature (ºC) 175 0.0001 0 Figure 8. Normalized On-State Resistance vs Temperature G001 Figure 9. Typical Diode Forward Voltage 10us 100us 1ms 10ms DC TC = 25ºC TC = 125ºC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1 100 1000 100 10 1 Single Pulse Max RthetaJC = 2.1ºC/W 0.1 0.1 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 1 10 VDS - Drain-to-Source Voltage (V) 100 10 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain- to- Source Current (A) 60 50 40 30 20 10 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A CSD18537NQ5A www.ti.com SLPS391B – JUNE 2013 – REVISED JULY 2014 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A 7 CSD18537NQ5A SLPS391B – JUNE 2013 – REVISED JULY 2014 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A CSD18537NQ5A www.ti.com SLPS391B – JUNE 2013 – REVISED JULY 2014 2 3 4 5 4 5 6 3 6 7 2 7 1 8 1 8 7.1 Q5A Package Dimensions DIM MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 E3 3.03 3.13 3.23 e 1.17 1.27 1.37 e1 0.27 0.37 0.47 e2 0.15 0.25 0.35 H 0.41 0.56 0.71 K 1.10 — — L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° — 12° Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A 9 CSD18537NQ5A SLPS391B – JUNE 2013 – REVISED JULY 2014 www.ti.com 7.2 Recommended PCB Pattern F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 DIM MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A CSD18537NQ5A www.ti.com SLPS391B – JUNE 2013 – REVISED JULY 2014 7.3 Recommended Stencil Opening (0.020) 8x 0.500 (0.020) 0.500 5 4 0.500 (0.020) 8x 1.585 (0.062) 1.235 (0.049) (0.024) 0.620 (0.170) 4.310 0.385 (0.015) 1.270 (0.050) 1 8 1.570 (0.062) 4x 0.615 (0.024) 1.105 (0.044) 3.020 (0.119) K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD18537NQ5A 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD18537NQ5A ACTIVE VSONP DQJ 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 18537N CSD18537NQ5AT ACTIVE VSONP DQJ 8 250 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 18537N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of