DRV8836DSSR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 DRV8836 Dual Low-Voltage H-Bridge IC 1 Features 3 Description • The DRV8836 provides an integrated motor driver solution for cameras, consumer products, toys, and other low-voltage or battery-powered motion control applications. The device has two H-bridge drivers, and can drive two DC motors or one stepper motor, as well as other devices like solenoids. The output driver block for each consists of N-channel power MOSFET configured as an H-bridge to drive the motor winding. An internal charge pump generates gate drive voltages. 1 • • • • • • • Dual-H-Bridge Motor Driver – Capable of Driving Two DC Motors or One Stepper Motor – Low MOSFET On-Resistance: HS + LS 305 mΩ 1.5-A Maximum Drive Current Per H-Bridge Configure Bridges Parallel for 3-A Drive Current 2-V to 7-V Operating Supply Voltage Flexible PWM or PHASE/ENABLE Interface Low-Power Sleep Mode With 95-nA Maximum Supply Current Dedicated nSLEEP Input Pin Tiny 2.00-mm × 3.00-mm WSON Package 2 Applications • Battery-Powered: – DSLR Lenses – Consumer Products – Toys – Robotics – Cameras – Medical Devices The DRV8836 supplies up to 1.5-A of output current per H-bridge. It operates on a power supply voltage from 2 V to 7 V. PHASE/ENABLE and IN/IN interfaces can be selected which are compatible with industry-standard devices. A low-power sleep mode is provided which turns off all unnecessary logic to provide a very low current state. Internal shutdown functions are provided for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature. The DRV8836 is packaged in a tiny 12-pin WSON package (Eco-friendly: RoHS and no Sb/Br). Device Information(1) PART NUMBER DRV8836 PACKAGE WSON (12) BODY SIZE (NOM) 2.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic 2 V to 7 V M 1.5 A ± Controller DRV8836 + PWM nSLEEP Stepper or Brushed DC Motor Driver + ± 1.5 A Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 9 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 11 9 Power Supply Recommendations...................... 13 9.1 Bulk Capacitance .................................................... 13 10 Layout................................................................... 13 10.1 Layout Guidelines ................................................. 13 10.2 Layout Example .................................................... 14 10.3 Thermal Considerations ........................................ 14 11 Device and Documentation Support ................. 16 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 16 12 Mechanical, Packaging, and Orderable Information ........................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (December 2015) to Revision D • Deleted nFAULT from the Simplified Schematic in the Description section ......................................................................... 1 Changes from Revision B (January 2014) to Revision C • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision A (September 2013) to Revision B • Page Page Added tOCR and tDEAD parameters to Electrical Characteristics .............................................................................................. 5 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 DRV8836 www.ti.com SLVSB17D – MARCH 2012 – REVISED APRIL 2016 5 Pin Configuration and Functions DSS Package 12-Pin WSON Top View VCC AOUT1 AOUT2 BOUT1 BOUT2 GND 1 12 2 11 3 4 GND Thermal Pad 10 9 5 8 6 7 nSLEEP MODE AIN1 / APHASE AIN2 / AENBL BIN1 / BPHASE BIN2 / BENBL Pin Functions PIN NAME NO. I/O (1) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND, Thermal pad 6 — Device ground VCC 1 — Device and motor supply Bypass to GND with a 0.1-μF (minimum) ceramic capacitor AIN1/APHASE 10 I Bridge A input 1/PHASE input IN/IN mode: Logic high sets AOUT1 high PH/EN mode: Sets direction of H-bridge A Internal pulldown resistor AIN2/AENBL 9 I Bridge A input 2/ENABLE input IN/IN mode: Logic high sets AOUT2 high PH/EN mode: Logic high enables H-bridge A Internal pulldown resistor BIN1/BPHASE 8 I Bridge B input 1/PHASE input IN/IN mode: Logic high sets BOUT1 high PH/EN mode: Sets direction of H-bridge B Internal pulldown resistor BIN2/BENBL 7 I Bridge B input 2/ENABLE input IN/IN mode: Logic high sets BOUT2 high PH/EN mode: Logic high enables H-bridge B Internal pulldown resistor MODE 11 I Input mode select Logic low selects IN/IN mode Logic high selects PH/EN mode Internal pulldown resistor nSLEEP 12 I Sleep input Active low places part in low-power sleep state Internal pulldown resistor AOUT1 2 O Bridge A output 1 AOUT2 3 O Bridge A output 2 BOUT1 4 O Bridge B output 1 BOUT2 5 O Bridge B output 2 CONTROL OUTPUT (1) Connect to motor winding A Connect to motor winding B Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 3 DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT Power supply voltage, VCC –0.3 7 V Digital input pin voltage –0.5 VCC + 0.5 V Peak motor drive output current Internally limited Continuous motor drive output current per H-bridge (3) A –1.5 1.5 A TJ Operating junction temperature –40 150 °C Tstg Storage temperature –60 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values pertain to network ground terminal. Power dissipation and thermal limits must be observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions TA = 25°C (unless otherwise noted) MIN MAX UNIT VCC Device power supply voltage 2 7 V VIN Logic level input voltage 0 VCC V IOUT H-bridge output current (1) 0 1.5 A fPWM Externally applied PWM frequency 0 250 kHz (1) Power dissipation and thermal limits must be observed. 6.4 Thermal Information DRV8836 THERMAL METRIC (1) DSS (WSON) UNIT 12 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 50.4 °C/W 58 RθJB °C/W Junction-to-board thermal resistance 19.9 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 20 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 DRV8836 www.ti.com SLVSB17D – MARCH 2012 – REVISED APRIL 2016 6.5 Electrical Characteristics TA = 25°C, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX fPWM = 50 kHz, no load 1.7 2.5 nSLEEP = 0 V, all inputs 0 V 40 95 VCC = 3 V, nSLEEP = 0 V, all inputs 0 V 10 UNIT POWER SUPPLY IVCC VCC operating supply current ICCQ VCC sleep mode supply current VUVLO VCC undervoltage lockout voltage VCC rising 2 VCC falling 1.9 mA nA V LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V RPD Pulldown resistance 0.25 ×s VCC V 5 μA 0.5 × VCC V –5 50 100 μA kΩ H-BRIDGE FETS RDS(ON) HS + LS FET on resistance IOFF OFF-state leakage current VCC = 3 V, I = 800 mA, TJ = 25°C 370 420 VCC = 5 V, IO = 800 mA, TJ = 25°C 305 355 O ±200 mΩ nA PROTECTION CIRCUITS IOCP Overcurrent protection trip level tDEG Overcurrent deglitch time 1.6 1 3.5 µs tOCR Overcurrent protection retry time 1 ms tDEAD Output dead time tTSD Thermal shutdown temperature 100 Die temperature 150 160 ns 180 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 A °C 5 DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com 6.6 Timing Requirements (1) TA = 25°C, VCC = 5 V, RL = 20 Ω NO. (1) MIN MAX UNIT 1 t1 Delay time, xPHASE high to xOUT1 low 210 ns 2 t2 Delay time, xPHASE high to xOUT2 high 150 ns 3 t3 Delay time, xPHASE low to xOUT1 high 150 ns 4 t4 Delay time, xPHASE low to xOUT2 low 210 ns 5 t5 Delay time, xENBL high to xOUTx high 150 ns 6 t6 Delay time, xENBL high to xOUTx low 150 ns 7 t7 Output enable time 210 ns 8 t8 Output disable time 210 ns 9 t9 Delay time, xINx high to xOUTx high 125 ns 10 t10 Delay time, xINx low to xOUTx low 125 ns 11 tR Output rise time 20 188 ns 12 tF Output fall time 8 30 ns Not production tested – ensured by design xENBL IN1 xPHASE IN2 7 9 8 3 5 z z OUT1 xOUT1 10 1 xOUT2 6 5 2 4 6 z OUT2 z IN/IN mode PHASE/ENBL mode 80% 80% OUTx 20% 20% 11 12 Figure 1. Timing Requirements 6 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 DRV8836 www.ti.com SLVSB17D – MARCH 2012 – REVISED APRIL 2016 6.7 Typical Characteristics 2.4 900 -40qC 25qC 85qC 700 2.2 VCC = 2 VCC = 5 VCC = 7 2 600 IVCC (mA) RDS(ON) (HS+LS) (m:) 800 500 400 300 1.8 1.6 1.4 200 1.2 100 1 -40 0 2 2.5 3 3.5 4 4.5 5 VVCC (V) 5.5 6 6.5 7 -20 0 20 40 Temperature (qC) D001 60 80 100 D001 Figure 3. VCC Operating Current, fPWM = 50 kHz, No Load Figure 2. RDS(ON) (HS + LS) 0.55 -40qC 25qC 85qC 0.5 0.45 0.4 IVCC (PA) 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 2 2.5 3 3.5 4 4.5 5 VVCC (V) 5.5 6 6.5 7 D003 Figure 4. VCC Sleep Current Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 7 DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com 7 Detailed Description 7.1 Overview The DRV8836 is an integrated motor driver solution used for brushed motor control. The device integrates two H-bridges, and can drive two DC motor or one stepper motor. The output driver block for each H-bridge consists of N-channel power MOSFETs. An internal charge pump generates the gate drive voltages. Protection features include overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature protection. The bridges connect in parallel for additional current capability. The mode pin allows selection of either a PHASE/ENABLE or IN/IN interface. 7.2 Functional Block Diagram 2.0 to 7V VCC VCC VCC Drives 2x DC motor or 1x Stepper Gate Drive Charge Pump AOUT1 OCP Step Motor OverTemp DCM VCC Osc AOUT2 Gate Drive OCP AIN1/APHASE AIN2/AENBL Logic VCC BIN1/BPHASE Gate Drive BIN2/BENBL BOUT1 OCP DCM MODE VCC nSLEEP Gate Drive BOUT2 OCP GND Copyright © 2016, Texas Instruments Incorporated 8 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 DRV8836 www.ti.com SLVSB17D – MARCH 2012 – REVISED APRIL 2016 7.3 Feature Description 7.3.1 Sleep Mode If the nSLEEP pin enters a logic-low state, the DRV8836 enters a low-power sleep mode. In this state all unnecessary internal circuitry is powered down. 7.3.2 Power Supplies and Input Pins There is a weak pulldown resistor (approximately 100 kΩ) to ground on the input pins. 7.3.3 Protection Circuits The DRV8836 is fully protected against undervoltage, overcurrent, and overtemperature events. 7.3.3.1 Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge disable. After approximately 1 ms, the bridge re-enables automatically. Overcurrent conditions on both high and low side devices, like a short to ground, supply, or across the motor winding results in an overcurrent shutdown. 7.3.3.2 Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge disable. Once the die temperature has fallen to a safe level operation automatically resumes. 7.3.3.3 Undervoltage Lockout (UVLO) If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in the device disables, and internal logic resets. Operation resumes when VCC rises above the UVLO threshold. Table 1. Device Protection FAULT CONDITION ERROR REPORT H-BRIDGE INTERNAL CIRCUITS RECOVERY VCC undervoltage (UVLO) VCC < VUVLO None Disabled Disabled VCC > VUVLO Overcurrent (OCP) IOUT > IOCP None Disabled Operating tOCR Thermal shutdown (TSD) TJ > TTSD None Disabled Operating TJ < TTSD – THYS 7.4 Device Functional Modes The DRV8836 is active when the nSLEEP pin is set to a logic high. When in sleep mode, the H-bridge FETs disable (Hi-Z). Table 2. Device Operating Modes OPERATING MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Operating nSLEEP high Operating Operating Sleep mode nSLEEP low Disabled Disabled Fault encountered Any fault condition met Disabled See Table 1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 9 DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com 7.4.1 Bridge Control Two control modes are available in the DRV8836: IN/IN mode and PHASE/ENABLE mode. IN/IN mode is selected if the MODE pin is driven low or left unconnected; PHASE/ENABLE mode is selected if the MODE pin is driven to logic high. The following tables show the logic for these modes. Table 3. IN/IN Mode xOUT2 FUNCTION (DC MOTOR) MODE xIN1 xIN2 xOUT1 0 0 0 Z Z Coast 0 0 1 L H Reverse 0 1 0 H L Forward 0 1 1 L L Brake Table 4. PHASE/ENABLE Mode 10 MODE xENABLE xPHASE xOUT1 xOUT2 FUNCTION (DC MOTOR) 1 0 X L L Brake 1 1 1 L H Reverse 1 1 0 H L Forward Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 DRV8836 www.ti.com SLVSB17D – MARCH 2012 – REVISED APRIL 2016 8 Application and Implementation NOTE The information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8836 is used in one or two motor control applications. When configured in parallel, the DRV8836 provides double the current to one motor. 8.2 Typical Application The two H-bridges in the DRV8836 can be connected in parallel for double the current of a single H-bridge. Figure 5 shows the connections. The following design is a common application of the DRV8836. VCC 10 µF 10 AIN1/APHASE 9 AIN2/AENBL IN1/PHASE IN2/DIR VCC 1 From Controller PP GNDP 6 GND 11 MODE 12 nSLEEP M BOUT1 4 BOUT2 5 8 BIN1/BPHASE 7 BIN2/BENBL LOW = IN/IN; HIGH = PHASE/ENBL LOW = SLEEP; HIGH = RUN AOUT1 2 AOUT2 3 Copyright © 2016, Texas Instruments Incorporated Figure 5. Parallel Mode Connections 8.2.1 Design Requirements The design requirements are shown in Table 5. Table 5. Design Requirements DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VCC 4V Motor RMS current IRMS 0.3 A Motor startup current ISTART 0.6 A Motor current trip point ILIMIT 0.5 A Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 11 DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com 8.2.2 Detailed Design Procedure The following design procedure can be used to configure the DRV8836 in a brushed motor application. 8.2.2.1 Motor Voltage The appropriate motor voltage depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. 8.2.2.2 Low-Power Operation When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power. 8.2.3 Application Curve The following scope captures motor startup as VCC ramps from 0 V to 6 V. Channel 1 is VCC, and Channel 4 is the motor current of an unloaded motor during startup. The motor used is a NMB Technologies Corporation OOB7PA12C, PPN7PA12C1. As VCC ramps the current in the motor increases until the motor speed builds up. The motor current then reduces for normal operation. Inputs are set as follows: • Mode: IN/IN • AIN1: High • AIN2: Low Figure 6. Motor Startup With No Load 12 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 DRV8836 www.ti.com SLVSB17D – MARCH 2012 – REVISED APRIL 2016 9 Power Supply Recommendations 9.1 Bulk Capacitance The appropriate local bulk capacitance is an important factor in motor drive system design. More bulk capacitance is generally beneficial but may increase costs and physical size. The amount of local capacitance needed depends on a variety of factors, including: • The highest current required by the motor system • The power supply’s capacitance and ability to source current • The amount of parasitic inductance between the power supply and motor system • The acceptable voltage ripple • The type of motor used (brushed DC, brushless DC, stepper) • The motor braking method The inductance between the power supply and motor drive system limits the rate current changes from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The datasheet provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Parasitic Wire Inductance Motor Drive System Power Supply VM + + Motor Driver ± GND Local Bulk Capacitor IC Bypass Capacitor Copyright © 2016, Texas Instruments Incorporated Figure 7. Bulk Capacitor 10 Layout 10.1 Layout Guidelines The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1-μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace or ground plane connection to the device GND pin. The VCC pin must bypass to ground using an appropriate bulk capacitor. This component may be an electrolytic and should be located close to the DRV8836. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 13 DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com 10.2 Layout Example 10 µF VCC nSLEEP AOUT1 MODE AOUT2 AIN1/APHASE BOUT1 AIN2/AENBL BOUT2 BIN1/BPHASE GND BIN2/BENBL Figure 8. Layout Recommendation 10.3 Thermal Considerations The DRV8836 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature exceeds approximately 150°C, the device disables until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or an ambient temperature that is too high. 10.3.1 Power Dissipation The power dissipated in the output FET resistance or RDS(on) dominates the power dissipation in the DRV8836. The average power dissipation when running both H-bridges can be roughly estimated by Equation 1: PTOT = 2 × RDS(ON) × (IOUT(RMS))2 where • PTOT is the total power dissipation, RDS(ON) is the resistance of the HS plus LS FETs, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to approximately 0.7× the full-scale output current setting. The factor of 2 comes from the fact that there are two H-bridges. (1) The maximum amount of power dissipated in the device is dependent on ambient temperature and heatsinking. 14 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 DRV8836 www.ti.com SLVSB17D – MARCH 2012 – REVISED APRIL 2016 Thermal Considerations (continued) NOTE RDS(ON) increases with temperature. As the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. 10.3.2 Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For more information on PCB design, refer to TI application report SLMA002, PowerPAD™ Thermally Enhanced Package, and TI application brief SLMA004, PowerPAD™ Made Easy, available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 15 DRV8836 SLVSB17D – MARCH 2012 – REVISED APRIL 2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Calculating Motor Driver Power Dissipation, SLVA504 • DRV8835/DRV8836 Evaluation Module, SLVU694 • Understanding Motor Driver Current Ratings, SLVA505 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8836 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) DRV8836DSSR ACTIVE WSON DSS 12 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 836 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of