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DS100KR800
SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
DS100KR800 8-Channel Repeater for Data-Rates Up to 10.3 Gbps
1 Features
3 Description
•
The DS100KR800 device is a high performance
repeater
designed
to
support
8-channel
(unidirectional), 10G-KR, and other high-speed
interface serial protocols up to 10.3 Gbps. The
continuous time linear equalizer (CTLE) of the
receiver provides a boost of up to 36 dB at 5 GHz
(10.3125 Gbps) in each of its eight channels. This
equalizer is capable of opening an input eye that is
completely closed due to inter symbol interference
(ISI) induced by interconnect medium such as long
backplanes or cables. The transmitter provides a deemphasis boost of up to –12 dB and output voltage
amplitude control from 700 mV to 1300 mV.
Comprehensive Product Family:
– DS125BR820: 8-Channel Repeater
– DS125BR401A: 4x Lane Repeater
– DS125BR111: 1x Lane Repeater
Transparent Management of 10G-KR (802.3ap)
Link Training Protocol
65 mW/Channel (Typical) Power Consumption
Advanced Signal Conditioning Features
– Receive Equalization up to 36 dB at 5 GHz
– Transmit De-emphasis up to –12 dB
– Transmit Voltage Control: 700 mV to 1300 mV
Programmable Through Pin Selection, EEPROM
or SMBus Interface
Selectable 2.5-V or 3.3-V Supply Voltage
–40°C to +85°C Operating Temperature Range
Flow-thru Pinout in Leadless WQFN Package
1
•
•
•
•
•
•
•
2 Applications
•
•
Front-Port 40G-CR4/SR4/LR4 Link Extensions
Backplane 40G-KR4 Link Extensions
Simplified Functional Block Diagram
When operating in 10G-KR mode, the DS100KR800
transparently allows the host controller and the end
point to optimize the full link and negotiate transmit
equalizer coefficients as defined in the 802.3ap
standard. This seamless management of the link
training protocol ensures system level interoperability
with minimum latency.
The programmable settings can be applied through
pin settings, SMBus (I2C) protocol or an external
EEPROM. When operating in the EEPROM mode,
the configuration information is automatically loaded
on power-up. This eliminates the need for an external
microprocessor or software driver.
Device Information(1)
DS100KR800
.
.
.
INB_0+
INB_0-
.
.
.
.
.
.
INB_3+
INB_3-
.
.
.
INA_0+
INA_0-
.
.
.
INA_3+
INA_3-
OUTB_0+
OUTB_0-
.
.
.
PART NUMBER
.
.
.
DS100KR800
OUTB_3+
OUTB_3-
.
.
.
OUTA_0+
OUTA_0-
.
.
.
PACKAGE
WQFN (54)
BODY SIZE (NOM)
10.00 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Block Diagram
.
.
.
OUTA_3+
OUTA_32x40G
AD0
Address straps
(pull-up to VIN or
pull-down to GND)(1)
DS100KR800
VIN
AD1
AD2
AD3
SMBus Slave Mode(1)
READ_EN / SD_TH
SMBus Slave Mode(1)
ALL_DONE
DS100KR800
3.3 V
INPUT_EN
VIN (3.3 V)
ASIC
VIN
FPGA
1 F
VDD_SEL
VDD (2.5 V)
8x10G
SMBus Slave Mode(1)
SDA(2)
SCL(2)
Stacked QSFP+
40 GbE Copper CR4 or
40 GbE SR4/LR4 Optical
2x40G
10G-KR Mode(4)
MODE
ENSMB
(3)
10 F
RESERVED
DS100KR800
DS100KR800
To SMBus/I2C
Host Controller
Stacked QSFP+
1xQSFP+ to 4xSFP+
Breakout
8x10G
RESET
GND (DAP)
0.1 F (x5)
(1) Schematic shows connection for SMBus Slave Mode (ENSMB=1 kW to VIN)
For SMBus Master Mode or Pin Mode configuration, the connections are different.
(2) SMBus signals need to be pulled up elsewhere in the system.
(3) Schematic requires different connections for 2.5 V mode.
(4) Schematic requires pull-down resistor for 10G Mode.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS100KR800
SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Electrical Characteristics – Serial Management Bus
Interface .................................................................... 8
6.7 Timing Requirements – Serial Bus Interface Timing
Specifications ............................................................. 9
6.8 Typical Characteristics ............................................ 11
7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 16
7.6 Register Maps ......................................................... 17
8
Application and Implementation ........................ 39
8.1 Application Information............................................ 39
8.2 Typical Application ................................................. 39
9
Power Supply Recommendations...................... 41
9.1 3.3-V or 2.5-V Supply Mode Operation................ 41
9.2 Power Supply Bypassing ........................................ 42
10 Layout................................................................... 42
10.1 Layout Guidelines ................................................. 42
10.2 Layout Example .................................................... 43
11 Device and Documentation Support ................. 44
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
44
44
44
44
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2013) to Revision E
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed Signal detect pattern at 8 Gbps .............................................................................................................................. 7
Changes from Revision C (April 2013) to Revision D
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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Product Folder Links: DS100KR800
DS100KR800
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SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
DEMA0/SDA
ENSMB
EQB1/AD2
EQB0/AD3
47
46
DEMA1/SCL
50
48
VDD
49
RESET
51
DEMB0/AD1
53
52
DEMB1/AD0
54
NJY Package
54-Pin WQFN
Top View
SMBUS AND CONTROL
IN_B_0+
1
45
OUT_B_0+
IN_B_0-
2
44
OUT_B_0-
IN_B_1+
3
43
OUT_B_1+
IN_B_1-
4
42
OUT_B_1-
IN_B_2+
5
41
VDD
IN_B_2-
6
40
OUT_B_2+
IN_B_3+
7
39
OUT_B_2-
IN_B_3-
8
38
OUT_B_3+
VDD
9
37
OUT_B_3-
IN_A_0+
10
36
VDD
IN_A_0-
11
35
OUT_A_0+
IN_A_1+
12
34
OUT_A_0-
IN_A_1-
13
33
OUT_A_1+
DAP = GND
VDD
14
32
OUT_A_1-
IN_A_2+
15
31
OUT_A_2+
IN_A_2-
16
30
OUT_A_2-
IN_A_3+
17
29
OUT_A_3+
IN_A_3-
18
28
OUT_A_3-
26
ALL_DONE
24
VIN
27
23
RESERVED
25
22
INPUT_EN
VDD_SEL
21
SD_THA/READ_EN
20
EQA0
MODE
EQA1
19
Vreg
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3
DS100KR800
SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
www.ti.com
Pin Functions: Common Connections (1) (2) (3) (4)
PIN
NAME
NO.
TYPE
DESCRIPTION
DIFFERENTIAL HIGH SPEED INPUTS AND OUTPUTS
IN_A_0+, IN_A_0-,
IN_A_1+, IN_A_1-,
IN_A_2+, IN_A_2-,
IN_A_3+, IN_A_3-
10, 11,
12, 13,
15, 16,
17, 18
I
Inverting and noninverting differential inputs to bank A equalizer. A
gated on-chip 50-Ω termination resistor connects INA_n+ to VDD and
INA_n- to VDD when enabled. AC coupling required on high-speed
I/O.
IN_B_0+, IN_B_0-,
IN_B_1+, IN_B_1-,
IN_B_2+, IN_B_2-,
IN_B_3+, IN_B_3-,
1, 2,
3, 4,
5, 6,
7, 8
I
Inverting and noninverting differential inputs to bank B equalizer. A
gated on-chip 50-Ω termination resistor connects INB_n+ to VDD and
INB_n- to VDD when enabled. AC coupling required on high-speed
I/O.
OUT_A_0+, OUT_A_0-,
OUT_A_1+, OUT_A_1-,
OUT_A_2+, OUT_A_2-,
OUT_A_3+, OUT_A_3-
35, 34,
33, 32,
31, 30,
29, 28
O
Inverting and noninverting 50-Ω driver bank A outputs with deemphasis. Compatible with AC-coupled CML inputs. AC coupling
required on high-speed I/O.
OUT_B_0+, OUT_B_0-,
OUT_B_1+, OUT_B_1-,
OUT_B_2+, OUT_B_2-,
OUT_B_3+, OUT_B_3-,
45, 44,
43, 42,
40, 39,
38, 37
O
Inverting and noninverting 50-Ω driver bank B outputs with deemphasis. Compatible with AC-coupled CML inputs. AC coupling
required on high-speed I/O.
CONTROL PINS — SHARED (LVCMOS)
ENSMB
48
I, LVCMOS
System Management Bus (SMBus) enable pin
Tie 1 kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1 kΩ to GND = Pin Mode
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
LOW = Device is enabled (Normal Operation)
HIGH = Low Power Mode
RESET
52
I, LVCMOS
VDD_SEL
25
I, FLOAT
GND
DAP
Power
Ground pad (DAP - die attach pad).
VDD
9, 14, 36, 41, 51
Power
Power supply pins CML/analog
2.5-V mode, connect to 2.5 V
3.3-V mode, connect 0.1-µF cap to each VDD pin
VIN
24
Power
In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating.
Controls the internal regulator
Float = 2.5-V mode
Tie GND = 3.3-V mode
POWER
(1)
(2)
(3)
(4)
4
LVCMOS inputs without the Float conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.
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DS100KR800
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SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
Pin Functions: SMBus/EEPROM Control
PIN
NAME
NO.
TYPE
DESCRIPTION
ENSMB = 1 (SMBUS MODE)
AD0-AD3
54, 53, 47,
46
I, LVCMOS
ENSMB master or slave mode
User set SMBus Slave Address Inputs in SMBus mode.
READ_EN
26
I, 4-LEVEL,
LVCMOS
When using an external EEPROM, a transition from high to low starts the load from the
external EEPROM
SCL
50
I, LVCMOS,
O, OPENDrain
ENSMB master or slave mode
SMBUS clock input pin is enabled.
Clock output when loading EEPROM configuration (master mode).
SDA
49
I, LVCMOS,
O, OPENDrain
ENSMB master or slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open-drain output.
ENSMB = 0 (PIN MODE)
MODE
21
I, 4-LEVEL,
LVCMOS
Tie 1 kΩ to VDD = 10G-KR mode operation
Tie 1 kΩ to GND = 10G mode operation
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal signal detect threshold
See Table 4
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN
22
I, 4-LEVEL,
LVCMOS
Tie 1 kΩ to VDD = normal operation
27
O, LVCMOS
Valid register load status output
HIGH = external EEPROM load failed
LOW = external EEPROM load passed
OUTPUTS
ALL_DONE
Pin Functions: Pin Control
PIN
NAME
NO.
TYPE
DESCRIPTION
ENSMB = 0 (PIN MODE)
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output driver when in
Gen1/2 mode. The pins are only active when ENSMB is deasserted (low). The 8 channels
are organized into two banks. Bank A is controlled with the DEMA [1:0] pins and bank B is
controlled with the DEMB[1:0] pins. When ENSMB is high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are converted to SMBUS
SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 3
20, 19, 46,
47
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The pins are active
only when ENSMB is deasserted (low). The 8 channels are organized into two banks. Bank
A is controlled with the EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB is high the SMBus registers provide independent control of each channel. The
EQB[1:0] pins are converted to SMBUS AD2/ AD3 inputs.
See Table 2
MODE
21
I, 4-LEVEL,
LVCMOS
Tie 1 kΩ to VDD = 10G-KR mode operation
Tie 1 kΩ to GND = 10G mode operation
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal signal detect threshold
See Table 4
DEMA0,
DEMA1,
DEMB0,
DEMB1
EQA0,
EQA1,
EQB0, EQB1
49, 50, 53,
54
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN
22
I, 4-LEVEL,
LVCMOS
RESERVED
23
I, FLOAT
Tie 1 kΩ to VDD = normal operation
Float = normal operation
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5
DS100KR800
SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
Supply voltage (VDD = 2.5-V mode)
–0.5
2.75
V
Supply voltage (VIN = 3.3-V mode)
–0.5
4
V
LVCMOS input or output voltage
–0.5
4
V
CML input voltage
–0.5
(VDD + 0.5)
V
CML input current
–30
Junction temperature
Soldering (4 sec.) (2)
Lead temperature
Derate NJY0054A package
Storage temperature, Tstg
(1)
(2)
–40
30
ma
125
°C
260
°C
52.6
mW/°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications: see product folder at SNOA549.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1000
Machine model, STD - JESD22-A115-A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
2.5-V mode
Supply voltage
3.3-V mode
Ambient temperature
MIN
NOM
MAX
UNIT
2.375
2.5
2.625
V
3.0
3.3
3.6
V
–40
25
85
°C
3.6
V
SMBus (SDA, SCL)
Supply noise up to 50 MHz
(1)
(1)
100 mVp-p
Allowed supply noise (mVp-p sine wave) under typical conditions.
6.4 Thermal Information
DS100KR800
THERMAL METRIC (1)
NJY (WQFN)
UNIT
54 PINS
RθJA
Junction-to-ambient thermal resistance, No Airflow, 4-layer JEDEC
26.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.8
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
6.5 Electrical Characteristics
See
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP (3) MAX UNIT
POWER
PD
Power dissipation
EQ enabled, VOD = 1 Vp-p,
INPUT_EN = 1, RESET = 0
VDD = 2.5-V supply
500
700
mW
VIN = 3.3-V supply
660
900
mW
LVCMOS / LVTTL DC SPECIFICATIONS
Vih
High level Input voltage
3.3-V mode operation (VIN = 3.3 V)
2
3.6
V
Vil
Low level Input voltage
3.3-V mode operation (VIN = 3.3 V)
0
0.8
V
Voh
High level output voltage
(ALL_DONE pin)
Ioh = –4 mA
2
Vol
Low level output voltage
(ALL_DONE pin)
Iol = 4 mA
Input high current (RESET
pin)
VIN = 3.6 V, LVCMOS = 3.6 V
Input high current
with internal resistors
(4–level input pin)
VIN = 3.6 V, LVCMOS = 3.6 V
Input low current (RESET
pin)
Input low current
with internal resistors
(4–level input pin)
Iih
Iil
V
0.4
V
–15
15
µA
20
150
µA
VIN = 3.6 V, LVCMOS = 0 V
–15
15
µA
VIN = 3.6 V, LVCMOS = 0 V
–160
–40
µA
CML RECEIVER INPUTS (IN_n+, IN_n-)
0.05 GHz - 7.5 GHz
–15
dB
7.5 GHz - 15 GHz
–5
dB
0.05 GHz - 5 GHz
–10
dB
RLrx-diff
RX package pins plus Si
differential return loss
RLrx-cm
Common-mode RX return
loss
Zrx-dc
RX DC common-mode
impedance
Tested at VDD = 0
40
50
60
Ω
Zrx-diff-dc
RX DC differential mode
impedance
Tested at VDD = 0
80
100
120
Ω
Vrx-diff-dc
Differential RX peak-topeak voltage
Tested at pins
0.6
1.2
V
Vrx-signal-detdiff-pp
Signal detect assert level
for active data signal
SD_TH = F (float),
0101 pattern at 8 Gbps
180
mVpp
Vrx-idle-detdiff-pp
Signal detect deassert level SD_TH = F (float),
for electrical idle
0101 pattern at 8 Gbps
110
mVpp
1
1.2 Vp-p
HIGH SPEED OUTPUTS
Vtx-diff-pp
Output voltage differential
swing
Differential measurement with Out_n+ and OUT_n-,
terminated by 50Ω to GND, AC-Coupled,
VID = 1 Vp-p,
DEM0 = 1, DEM1 = 0
Vtx-de-ratio_3.5
TXde-emphasis ratio
VOD = 1 Vp-p,
DEM0 = 0,
DEM1 = R
Vtx-de-ratio_6
TX de-emphasis ratio
VOD = 1 Vp-p,
DEM0 = R, DEM1= R
tTX-DJ
Deterministic jitter
VID = 800 mV, PRBS15 pattern, 8.0 0.05 Gbps, VOD = 1
V, UIpp EQ = 0x00, DE = 0 dB (no input or output trace
loss)
(1)
(2)
(3)
0.8
−3.5
dB
–6
dB
0.05
UIpp
Ensured by device characterization.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
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SNLS340E – NOVEMBER 2011 – REVISED NOVEMBER 2015
www.ti.com
Electrical Characteristics (continued)
See (1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP (3) MAX UNIT
tTX-RJ
Random jitter
VID = 800 mV, 0101 pattern, 8.0 Gbps, 0.3 VOD = 1 V, ps
RMS EQ = 0x00, DE = 0 dB, (no input or output trace loss)
TTX-RISE-FALL
Transmitter rise/fall time
20% to 80% of differential output voltage
TRF-MISMATCH
Transmitter rise/fall
mismatch
20% to 80% of differential output voltage
0.01
RLTX-DIFF
Differential return loss
0.05 GHz - 7.5 GHz
RLTX-CM
Common-mode return loss
ZTX-DIFF-DC
DC differential TX
impedance
VTX-CM-AC-PP
TX AC common-mode
voltage
VOD = 1 Vp-p,
DEM0 = 1, DEM1 = 0
ITX-SHORT
Transmitter short circuit
current-limit
Total current the transmitter can supply when shorted to
VDD or GND
TPDEQ
Differential propagation
delay
EQ = 00,
TLSK
Lane-to-lane skew
TPPSK
Part-to-part propagation
delay skew
35
0.3
ps
RMS
45
ps
0.1
UI
–15
dB
7.5 GHz - 15 GHz
–5
dB
0.05 GHz - 5 GHz
–10
dB
100
Ω
100
mVp
p
20
mA
200
ps
T = 25°C, VDD = 2.5 V
25
ps
T = 25°C, VDD = 2.5 V
40
ps
DJE1
Residual deterministic jitter
at 10.3 Gbps
35-in 4 mil FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.3
UI
DJE2
Residual deterministic jitter
at 10.3 Gbps
10 meters 30 awg cable,
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.3
UI
Residual deterministic jitter
at 10.3 Gbps
20-in 4 mil FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 00,
VOD = 1 Vp-p,
DEM = −9 dB
0.1
UI
(4)
EQUALIZATION
DE-EMPHASIS
DJD1
(4)
Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
6.6 Electrical Characteristics – Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, clock input low voltage
VIH
Data, clock input high voltage
IPULLUP
Current through pullup resistor or
current source
VDD
Nominal bus voltage
ILEAK-Bus
Input leakage per bus segment
ILEAK-Pin
Input leakage per device pin
CI
Capacitance for SDA and SCL
(1)
(2)
8
2.1
High power specification
See
V
3.6
V
4
mA
2.375
(1)
0.8
–200
3.6
V
200
µA
–15
See
(1) (2)
µA
10
pF
Recommended value.
Recommended maximum capacitance load per bus segment is 400pF.
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Electrical Characteristics – Serial Management Bus Interface (continued)
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
RTERM
(3)
TEST CONDITIONS
External termination resistance pull
to VDD = 2.5 V ± 5% OR 3.3 V ±
10%
MIN
TYP
MAX
UNIT
Pullup VDD = 3.3 V,
See (1) (2) (3)
2000
Ω
Pullup VDD = 2.5 V,
See (1) (2) (3)
1000
Ω
Maximum termination voltage should be identical to the device supply voltage.
6.7 Timing Requirements – Serial Bus Interface Timing Specifications
PARAMETER
FSMB
Bus operating frequency
TBUF
Bus free time between
stop and start condition
THD:STA
Hold time after (repeated)
start condition. After this
period, the first clock is
generated.
TSU:STA
TEST CONDITIONS
MIN
TYP
ENSMB = VDD (slave mode)
ENSMB = FLOAT (master mode)
280
400
MAX
UNIT
400
kHz
520
kHz
1.3
µs
0.6
µs
Repeated start condition
set-up time
0.6
µs
TSU:STO
Stop condition set-up time
0.6
µs
THD:DAT
Data hold time
0
ns
TSU:DAT
Data set-up time
100
ns
TLOW
Clock low period
THIGH
Clock high period
See
(1)
tF
Clock/Data fall time
See
tR
Clock/Data rise time
tPOR
Time in which a device
must be operational after
power-on reset
(1)
(2)
At IPULLUP, maximum
1.3
0.6
µs
50
µs
(1)
300
ns
See
(1)
300
ns
See
(1) (2)
500
ms
Compatible with SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
Ensured by Design. Parameter not tested in production.
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(OUT+)
80%
80%
VOD (p-p) = (OUT+) ± (OUT-)
0V
20%
20%
(OUT-)
tRISE
tFALL
Figure 1. CML Output and Rise and Fall Transition Time
+
IN
0V
tPLHD
tPHLD
+
OUT
0V
-
Figure 2. Propagation Delay Timing Diagram
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 3. SMBus Timing Parameters
10
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6.8 Typical Characteristics
6.8.1 Electrical Performance
1021
640.0
VDD = 2.625V
620.0
T = 25°C
VDD = 2.5V
600.0
1019
VDD = 2.375V
580.0
VOD (mVp-p)
PD (mW)
560.0
540.0
520.0
500.0
1016
1013
480.0
1010
T = 25°C
460.0
440.0
1007
2.375
420.0
0.8
0.9
1
1.1
1.2
1.3
2.5
2.625
VDD (V)
VOD (Vp-p)
Figure 4. Power Dissipation (PD) vs Output Differential
Voltage (VOD)
Figure 5. Output Differential Voltage (VOD = 1 Vp-p) vs
Supply Voltage (VDD)
1020
VDD = 2.5V
VOD (mVp-p)
1018
1016
1014
1012
- 40
-15
10
35
60
85
TEMPERATURE (°C)
Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature
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7 Detailed Description
7.1 Overview
The DS100KR800 is a low-power media compensation, 8-channel repeater optimized for 10G–KR. The
DS100KR800 compensates for lossy FR-4 printed-circuit-board backplanes and balanced cables. The
DS100KR800 operates in 3 modes: Pin control mode (ENSMB = 0), SMBus slave mode (ENSMB = 1) and
SMBus master mode (ENSMB = float) to load register information from external EEPROM; refer to SMBUS
master mode for additional information.
7.2 Functional Block Diagram
One channel of four A Channels
VDD
INA_n+
EQ
INA_n-
OUTA_n+
Predriver
Driver
OUTA_n-
ENSMB
EQA[1:0]
DEMA[1:0]
READ_EN
ALL_DONE
AD[3:0]
SCL
Internal Voltage
Regulator
Digital Core and SMBus Registers
SDA
RESET
VDD_SEL
VIN
VDD
INB_n+
EQ
INB_n-
Predriver
OUTB_n+
Driver
OUTB_n-
ENSMB
EQB[1:0]
DEMB[1:0]
One channel of four B Channels
12
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7.3 Feature Description
7.3.1 4-Level Input Configuration Guidelines
The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of
control settings when ENSMB = 0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the
package pin. These resistors, together with the external resistor connection, combine to achieve the desired
voltage level. By using the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage
levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
RESULTING PIN VOLTAGE
LEVEL
SETTING
0
Tie 1 kΩ to GND
0.1 V
0.08 V
R
Tie 20 kΩ to GND
1/3 x VIN
1/3 x VDD
3.3-V MODE
2.5-V MODE
F
Float (leave pin open)
2/3 x VIN
2/3 x VDD
1
Tie 1 kΩ to VIN or VDD
VIN – 0.05 V
VDD – 0.04 V
The typical 4-level input thresholds are as follows:
• Internal Threshold between 0 and R = 0.2 × VIN or VDD
• Internal Threshold between R and F = 0.5 × VIN or VDD
• Internal Threshold between F and 1 = 0.8 × VIN or VDD
In order to minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and
pulldown resistors are recommended. If several four level inputs require the same setting, it is possible to
combine two or more 1-kΩ resistors into a single lower value resistor. As an example, combining two inputs with
a single 500-Ω resistor is a valid way to save board space.
7.4 Device Functional Modes
7.4.1 Pin Control Mode
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically
adjusted per the Table 3. The receiver electrical idle detect threshold is also adjustable through the SD_TH pin.
7.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain
active unless their respective registers are written to and the appropriate override bit is set, in which case they
are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is driven low all registers are
reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible through the pin controls were chosen to meet the needs of most applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the
SMBus registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting
when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are
set by registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control
settings when ENSMB=0.
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Device Functional Modes (continued)
Table 2. Equalizer Settings
LEVEL
EQA1
EQB1
EQA0
EQB0
EQ – 8 BITS [7:0]
dB AT
1 GHz
dB AT
3 GHz
dB AT
5 GHz
SUGGESTED USE
1
0
0
0000 0000 = 0x00
1.7
4.2
5.3
FR4 < 5 inch trace
2
0
R
0000 0001 = 0x01
2.8
6.6
8.7
FR4 5 inch 5–mil trace
3
0
Float
0000 0010 = 0x02
4.1
8.6
10.6
FR4 5 inch 4–mil trace
4
0
1
0000 0011 = 0x03
5.1
9.8
11.7
FR4 10 inch 5–mil trace
5
R
0
0000 0111 = 0x07
6.2
12.4
15.6
FR4 10 inch 4–mil trace
6
R
R
0001 0101 = 0x15
5.1
12
16.6
FR4 15 inch 4–mil trace
7
R
Float
0000 1011 = 0x0B
7.7
15
18.3
FR4 20 inch 4–mil trace
8
R
1
0000 1111 = 0x0F
8.8
16.5
19.7
FR4 25 to 30 inch 4–mil trace
14
9
Float
0
0101 0101 = 0x55
6.3
14.8
20.3
FR4 30 inch 4–mil trace
10
Float
R
0001 1111 = 0x1F
9.9
19.2
23.6
FR4 35 inch 4–mil trace
11
Float
Float
0010 1111 = 0x2F
11.3
21.7
25.8
10m, 30awg cable
12
Float
1
0011 1111 = 0x3F
12.4
23.2
27
10m – 12m cable
13
1
0
1010 1010 = 0xAA
11.9
24.1
29.1
14
1
R
0111 1111 = 0x7F
13.6
26
30.7
15
1
Float
1011 1111 = 0xBF
15.1
28.3
32.7
16
1
1
1111 1111 = 0xFF
16.1
29.7
33.8
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Table 3. De-emphasis Settings
LEVEL
DEMA1
DEMB1
DEMA0
DEMB0
VOD Vp-p
DEM dB
INNER AMPLITUDE
Vp-p
SUGGESTED USE
1
0
0
0.8
0
0.8
FR4
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