DS100KR401
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SNLS395B – JANUARY 2012 – REVISED MARCH 2012
DS100KR401 Ultra Low Power, 4 Lane (8-channel, bi-directional) Repeater for Data-rates
up to 10.3 Gbps
Check for Samples: DS100KR401
FEATURES
DESCRIPTION
•
The DS100KR401 is an extremely low power, high
performance repeater designed to support 4 lane (bidirectional) 10G-KR and other high speed interface
serial protocols up to 10.3 Gbps. The receiver's
continuous time linear equalizer (CTLE) provides a
boost of up to +36 dB at 5 GHz (10.3125 Gbps) in
each of its eight channels and is capable of opening
an input eye that is completely closed due to inter
symbol interference (ISI) induced by interconnect
medium such as long backplanes or cables, hence
enabling host controllers to ensure an error free endto-end link. The transmitter provides a de-emphasis
boost of up to -12 dB and output voltage amplitude
control from 700 mV to 1300 mV to allow maximum
flexibility in the physical placement within the
interconnect channel.
1
2
•
•
•
•
•
•
•
•
•
Comprehensive Product Family:
– DS100KR800: 8-channel, Uni-directional
Repeater
– DS100KR401: 4x Lane, Bi-directional
Repeater
– DS100BR210: 2-channel, Uni-directional
Repeater
– DS100BR111: 1x Lane, Bi-directional
Repeater
4 Lane (8-channel, Bi-directional) Repeater for
4x 10G-KR and Other Serial Standards up to
10.3 Gbps
Transparent Management of 10G-KR (802.3ap)
Link Training Protocol
Low 65 mW/channel (Typ) Power
Consumption, with Option to Power Down
Unused Channels
Advanced Signal Conditioning Features
– Receive Equalization up to 36 dB at 5 GHz
– Transmit De-emphasis up to -12 dB
– Transmit Output Voltage Control: 700 mV to
1300 mV
Programmable via Pin Selection, EEPROM or
SMBus Interface
Single Supply Operation Selectable: 2.5V or
3.3V
–40°C to +85°C Operating Temperature Range
3 kV HBM ESD Rating
Flow-thru Pinout in 10mm×5.5mm 54-pin
Leadless WQFN Package
When operating in 10G-KR mode, the DS100KR401
transparently allows the host controller and the end
point to optimize the full link and negotiate transmit
equalizer coefficients as defined in the 802.3ap
standard. This seamless management of the link
training protocol ensures guaranteed system level
interoperability with minimum latency.
With a low power consumption of 65 mW/channel
(typ) and option to turn-off unused channels, the
DS100KR401 enables energy efficient system
design. A single supply of 3.3v or 2.5v is required to
power the device.
The programmable settings can be applied via pin
settings, SMBus (I2C) protocol or an external
EEPROM. When operating in the EEPROM mode,
the configuration information is automatically loaded
on power up. This eliminates the need for an external
microprocessor or software driver.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
DS100KR401
SNLS395B – JANUARY 2012 – REVISED MARCH 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION
10 Gbps KR
ASIC
DS100KR401
10 Gbps KR
ASIC
DS100KR401
Server Card
Application Card
ck
Ba ne
Pla
BLOCK DIAGRAM - DETAIL VIEW OF CHANNEL (1 of 8)
VOD/ DeEMPHASIS
CONTROL
VDD
DEMA/B
SMBus
EQ
INx_n+
OUTBUF
INx_n-
OUTx_n+
OUTx_n-
EQA/B
SMBus
Equalizer CONTROL
2
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SNLS395B – JANUARY 2012 – REVISED MARCH 2012
DEMA1/SCL
DEMA0/SDA
ENSMB
EQB1/AD2
EQB0/AD3
49
48
47
46
VDD
50
RESET
51
DEMB0/AD1
53
52
DEMB1/AD0
54
PIN DIAGRAM
SMBUS AND CONTROL
OUT_B_0+
1
45
IN_B_0+
OUT_B_0-
2
44
IN_B_0-
OUT_B_1+
3
43
IN_B_1+
OUT_B_1-
4
42
IN_B_1-
OUT_B_2+
5
41
VDD
OUT_B_2-
6
40
IN_B_2+
OUT_B_3+
7
39
IN_B_2-
OUT_B_3-
8
38
IN_B_3+
37
IN_B_3-
DAP = GND
VDD
9
IN_A_0+
10
36
VDD
IN_A_0-
11
35
OUT_A_0+
IN_A_1+
12
34
OUT_A_0-
IN_A_1-
13
33
OUT_A_1+
VDD
14
32
OUT_A_1-
IN_A_2+
15
31
OUT_A_2+
IN_A_2-
16
30
OUT_A_2-
IN_A_3+
17
29
OUT_A_3+
IN_A_3-
18
28
OUT_A_3-
20
21
22
23
24
25
26
27
EQA0
MODE
INPUT_EN
LPBK
VIN
VDD_SEL
SD_THA / READ_EN
ALL_DONE
EQA1
19
Vreg
Figure 1. DS100KR401 Pin Diagram 54 lead
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PIN DESCRIPTIONS (1)
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
OUT_B_0+, OUT_B_0,
OUT_B_1+, OUT_B_1,
OUT_B_2+, OUT_B_2,
OUT_B_3+, OUT_B_3-
1, 2,
3, 4,
5, 6,
7, 8
O
Inverting and non-inverting 50Ω driver bank B outputs with de-emphasis.
Compatible with AC coupled CML inputs.
IN_A_0+,
IN_A_1+,
IN_A_2+,
IN_A_3+,
IN_A_0-,
IN_A_1-,
IN_A_2-,
IN_A_3-
10,
12,
15,
17,
11,
13,
16,
18
I
Inverting and non-inverting differential inputs to bank A equalizer. A gated onchip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD
when enabled.
IN_B_0+,
IN_B_1+,
IN_B_2+,
IN_B_3+,
IN_B_0-,
IN_B_1-,
IN_B_2-,
IN_B_3-
45,
43,
40,
38,
44,
42,
39,
37
I
Inverting and non-inverting differential inputs to bank B equalizer. A gated onchip 50Ω termination resistor connects INB_n+ to VDD and INB_n- to VDD
when enabled.
35,
33,
31,
29,
34,
32,
30,
28
O
Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
Compatible with AC coupled CML inputs.
I, LVCMOS
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
OUT_A_0+, OUT_A_0,
OUT_A_1+, OUT_A_1,
OUT_A_2+, OUT_A_2,
OUT_A_3+, OUT_A_3-
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS,
O, OPEN
Drain
ENSMB Master or Slave mode
SMBUS clock input pin is enabled.
Clock output when loading EEPROM configuration (master mode).
SDA
49
I, LVCMOS,
O, OPEN
Drain
ENSMB Master or Slave mode
The SMBus bi-directional SDA pin is enabled. Data input or open drain (pulldown only) output.
AD0-AD3
54, 53, 47, 46
I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set
SMBus slave address inputs.
READ_EN
26
I, 4-LEVEL,
LVCMOS
When using an External EEPROM, a transition from high to low starts the
load from the external EEPROM
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
20, 19, 46, 47
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The
pins are active only when ENSMB is deasserted (low). The 8 channels are
organized into two banks. Bank A is controlled with the EQA[1:0] pins and
bank B is controlled with the EQB[1:0] pins. When ENSMB is high the SMBus
registers provide independent control of each channel. The EQB[1:0] pins are
converted to SMBUS AD2/ AD3 inputs.
See Table 2
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50, 53, 54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver when in Gen1/2 mode. The pins are only active when ENSMB is deasserted (low). The 8 channels are organized into two banks. Bank A is
controlled with the DEMA [1:0] pins and bank B is controlled with the
DEMB[1:0] pins. When ENSMB is high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are converted to
SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 3
(1)
4
Notes:
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
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PIN DESCRIPTIONS(1) (continued)
Pin Name
Pin Number
I/O, Type
Pin Description
MODE
21
I, 4-LEVEL,
LVCMOS
Tie 1kΩ to VDD = 10G-KR Mode Operation
Tie 1kΩ to GND = 10G Mode Operation
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Threshold
See Table 4
Control Pins — Both Pin and SMBus Modes (LVCMOS)
INPUT_EN
22
I, 4-LEVEL,
LVCMOS
Tie 1kΩ to VDD = Normal Operation
LPBK
23
I, 4-LEVEL,
LVCMOS
Controls the loopback function
Tie 1kΩ to GND = INA_n to OUTB_n loopback
Float = Normal Operation (loopback is disabled)
Tie 1kΩ to VDD = INB_n to OUTA_n loopback
VDD_SEL
25
I, FLOAT
Controls the internal regulator
Float = 2.5V mode
Tie GND = 3.3V mode
RESET
52
I, LVCMOS
LOW = Device is enabled (Normal Operation)
HIGH = Low Power Mode
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
VIN
24
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating.
VDD
9, 14, 36, 41, 51
Power
Power supply pins CML/analog
2.5V mode, connect to 2.5V
3.3V mode, connect 0.1 uF cap to each VDD pin
GND
DAP
Power
Ground pad (DAP - die attach pad).
Outputs
ALL_DONE
Power
ABSOLUTE MAXIMUM RATINGS
(1) (2)
Supply Voltage (VDD = 2.5V mode)
-0.5V to +2.75V
Supply Voltage (VIN = 3.3V mode)
-0.5V to +4.0V
LVCMOS Input/Output Voltage
-0.5V to +4.0V
CML Input Voltage
-0.5V to (VDD+0.5)
CML Input Current
-30 to +30 mA
Junction Temperature
125°C
Storage Temperature
-40°C to +125°C
Lead Temperature Range Soldering (4 sec.)
+260°C
Derate NJY0054A Package
ESD Rating
52.6mW/°C above +25°C
HBM, STD - JESD22-A114F
5 kV
MM, STD - JESD22-A115-A
150 V
CDM, STD - JESD22-C101-D
Thermal Resistance
1000 V
θJC
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
19.1°C/W
For soldering specifications: see product folder at www.ti.com , and SNOA549
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are specified for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
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RECOMMENDED OPERATING CONDITIONS
Min
Typ
Max
Units
Supply Voltage (2.5V mode)
2.375
2.5
2.625
V
Supply Voltage (3.3V mode)
3.0
3.3
3.6
V
Ambient Temperature
-40
25
+85
°C
3.6
V
100
mVp-p
SMBus (SDA, SCL)
Supply Noise up to 50 MHz
(1)
(1)
Allowed supply noise (mVp-p sine wave) under typical conditions.
ELECTRICAL CHARACTERISTICS (1)
Symbol
Typ (2)
Max
Units
VDD = 2.5 V supply, EQ Enabled,
VOD = 1.0 Vp-p, INPUT_EN = 1, RESET = 0
500
700
mW
VIN = 3.3 V supply, EQ Enabled,
VOD = 1.0 Vp-p, INPUT_EN = 1, RESET = 0
660
900
mW
2.0
3.6
V
0
0.8
V
Parameter
Conditions
Power Dissipation
Min
Power
PD
LVCMOS / LVTTL DC Specifications
Vih
High Level Input Voltage
Vil
Low Level Input Voltage
Voh
High Level Output Voltage
(ALL_DONE pin)
Ioh = −4mA
Vol
Low Level Output Voltage
(ALL_DONE pin)
Iol = 4mA
Iih
Input High Current (RESET pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
Input High Current with internal
resistors (4–level input pin)
Iil
Input Low Current (RESET pin)
3.3V Mode Operation (VIN = 3.3V)
2.0
VIN = 3.6 V, LVCMOS = 0 V
Input Low Current with internal
resistors (4–level input pin)
V
0.4
V
-15
+15
uA
+20
+150
uA
-15
+15
uA
-160
-40
uA
CML Receiver Inputs (IN_n+, IN_n-)
RLrx-diff
RX package pins plus Si
differential return loss
0.05 GHz - 7.5 GHz
-15
dB
7.5 GHz - 15 GHz
-5
dB
RLrx-cm
Common mode RX return loss
0.05 GHz - 5 GHz
Zrx-dc
RX DC common mode impedance
Tested at VDD = 0
40
50
60
Ω
Zrx-diff-dc
RX DC differntial mode impedance Tested at VDD = 0
80
100
120
Ω
Vrx-diff-dc
Differential RX peak to peak
voltage
0.6
1.2
V
Vrx-signal-detdiff-pp
Signal detect assert level for active SD_TH = F (float), 0101 pattern at 10.3 Gbps
data signal
180
mVp-p
Vrx-idle-detdiff-pp
Signal detect de-assert level for
electrical idle
110
mVp-p
-10
Tested at pins
SD_TH = F (float), 0101 pattern at 10.3 Gbps
dB
High Speed Outputs
Vtx-diff-pp
Output Voltage Differential Swing
Differential measurement with Out_n+ and
OUT_n-, terminated by 50Ω to GND,
AC-Coupled, VID = 1.0 Vp-p, DEM0 = 1,
DEM1 = 0
0.8
1.0
1.2
Vp-p
Vtx-de-ratio_3.5
TXde-emphasis ratio
VOD = 1.0 Vp-p, DEM0 = 0, DEM1 = R
−3.5
Vtx-de-ratio_6
TX de-emphasis ratio
VOD = 1.0 Vp-p, DEM0 = R, DEM1= R
−6
TTX-HF-DJ-DD
TX Dj > 1.5 MHz
0.15
UI
TTX-HF-DJ-DD
TX RMS jitter < 1.5 MHz
3.0
ps RMS
(1)
(2)
6
dB
dB
The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are NOT
guaranteed.
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at
the time of product characterization and are NOT guaranteed.
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ELECTRICAL CHARACTERISTICS(1) (continued)
Symbol
Parameter
Conditions
Min
Typ (2)
TTX-RISE-FALL
Transmitter rise/fall time
20% to 80% of differential output voltage
35
45
TRF-MISMATCH
Transmitter rise/fall mismatch
20% to 80% of differential output voltage
0.01
RLTX-DIFF
Differential return loss
0.05 GHz - 7.5 GHz
-15
dB
7.5 GHz - 15 GHz
-5
dB
RLTX-CM
Common mode return loss
0.05 GHz - 5 GHz
-10
dB
ZTX-DIFF-DC
DC differential TX impedance
100
Ω
VTX-CM-AC-PP
TX AC common mode voltage
VOD = 1.0 Vp-p, DEM0 = 1, DEM1 = 0
ITX-SHORT
Transmitter short circuit current
limit
Total current the transmitter can supply when
shorted to VDD or GND
TPDEQ
Differential propagation delay
EQ = 00,
TLSK
TPPSK
Max
Units
ps
0.1
100
UI
mVpp
20
mA
(3)
200
ps
Lane to lane skew
T = 25C, VDD = 2.5V
25
ps
Part to part propagation delay
skew
T = 25C, VDD = 2.5V
40
ps
DJE1
Residual deterministic jitter at
10.3 Gbps
35” 4 mil FR4, VID = 0.8 Vp-p, PRBS15,
EQ = 1F'h, DEM = 0 dB
0.3
UI
DJE2
Residual deterministic jitter at
10.3 Gbps
10 meters 30 awg cable, VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h, DEM = 0 dB
0.3
UI
Residual deterministic jitter at
10.3 Gbps
20” 4mils FR4, VID = 0.8 Vp-p, PRBS15,
EQ = 00, VOD = 1.0 Vp-p, DEM = −9 dB
0.1
UI
Equalization
De-emphasis
DJD1
(3)
Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
RTERM
External Termination Resistance
pull to VDD = 2.5V ± 5%
OR 3.3V ± 10%
2.1
High Power Specification
4
mA
2.375
See
(1)
-200
3.6
V
+200
µA
-15
See
(1) (2)
µA
10
Pullup VDD = 3.3V, See
(1) (2) (3)
Pullup VDD = 2.5V, See
(1) (2) (3)
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the
first clock is generated.
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
TSU:STA
(1)
(2)
(3)
280
400
400
kHz
520
kHz
1.3
µs
0.6
µs
0.6
µs
At IPULLUP, Max
Repeated Start Condition Setup
Time
Recommended value.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
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ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
TLOW
Clock Low Period
1.3
µs
THIGH
Clock High Period
See
tF
Clock/Data Fall Time
See
tR
Clock/Data Rise Time
See
(4)
See
(4) (5)
tPOR
(4)
(5)
Time in which a device must be
operational after power-on reset
(4)
0.6
(4)
50
µs
300
ns
300
ns
500
ms
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
Specified by Design. Parameter not tested in production.
TIMING DIAGRAMS
(OUT+)
80%
80%
VOD (p-p) = (OUT+) ± (OUT-)
0V
20%
20%
(OUT-)
tRISE
tFALL
Figure 2. CML Output and Rise and FALL Transition Time
+
IN
0V
tPHLD
tPLHD
+
OUT
0V
-
Figure 3. Propagation Delay Timing Diagram
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
ST
SP
Figure 4. SMBus Timing Parameters
8
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FUNCTIONAL DESCRIPTIONS
The DS100KR401 is a low power media compensation 4 lane repeater optimized for 10G–KR. The DS100KR401
compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The DS100KR401 operates
in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode
(ENSMB = float) to load register informations from external EEPROM; please refer to SMBUS Master Mode for
additional information.
Pin Control Mode:
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically
adjusted per the De-Emphasis table below. The receiver electrical idle detect threshold is also adjustable via the
SD_TH pin.
SMBUS Mode:
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain
active unless their respective registers are written to and the appropriate override bit is set, in which case they
are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is driven low all registers are
reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting when the
device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are set by
registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control
settings when ENSMB=0.
Table 1. 4–Level Control Pin Settings (1)
Pin Setting
Description
Voltage at Pin
0
Tie 1kΩ to GND
0.03 x VDD
R
Tie 20kΩ to GND
1/3 x VDD
Float
Float (leave pin open)
2/3 x VDD
1
Tie 1kΩ to VDD
0.98 x VDD
(1)
The above required resistor value is for a single device. When there are multiple devices connected to the pull-up / pull-down resistor,
the value must scale with the number of devices. If 4 devices are connected to a single pull-up or pull-down, the 1kΩ resistor value
should be 250Ω. For the 20kΩ to GND, this should also scale to 5kΩ.
3.3V or 2.5V Supply Mode Operation
The DS100KR401 has an optional internal voltage regulator to provide the 2.5V supply to the device. In 3.3V
mode, the VIN pin = 3.3V is used to supply power to the device and the VDD pins should be left open. The
internal regulator will provide the 2.5V to the VDD pins of the device and a 0.1 µF cap is needed at each of 5
VDD pins for power supply de-coupling (total capacitance should be ≤0.5 µF). The VDD_SEL pin must be tied to
GND to enable the internal regulator. In 2.5V mode, the VIN pin should be left open and 2.5V supply must be
applied to the VDD pins. The VDD_SEL pin must be left open (no connect) to disable the internal regulator.
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Product Folder Links: DS100KR401
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3.3V mode
2.5V mode
VDD_SEL
Enable
VDD_SEL
open
VIN
open
Disable
3.3V
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
Internal
voltage
regulator
2.5V
VDD
0.1 uF
0.1 uF
VDD
VDD
0.1 uF
0.1 uF
VDD
1 uF
VDD
10 uF
2.5V
1 uF
VIN
10 uF
Internal
voltage
regulator
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
VDD
0.1 uF
0.1 uF
VDD
VDD
0.1 uF
0.1 uF
VDD
VDD
0.1 uF
0.1 uF
Place 0.1 uF close to VDD Pin
Total capacitance should be 7 0.5 uF
Place capcitors close to VDD Pin
Figure 5. 3.3V or 2.5V Supply Connection Diagram
Table 2. Equalizer Settings
Level
EQA1
EQB1
1
2
10
EQA0
EQB0
EQ – 8 bits [7:0]
dB at
1.0 GHz
dB at
3.0 GHz
dB at
5.0 GHz
0
0
0000 0000 = 0x00
1.7
4.2
5.3
FR4 < 5 inch trace
0
R
0000 0001 = 0x01
2.8
6.6
8.7
FR4 5 inch 5–mil trace
3
0
Float
0000 0010 = 0x02
4.1
8.6
10.6
FR4 5 inch 4–mil trace
4
0
1
0000 0011 = 0x03
5.1
9.8
11.7
FR4 10 inch 5–mil trace
5
R
0
0000 0111 = 0x07
6.2
12.4
15.6
FR4 10 inch 4–mil trace
6
R
R
0001 0101 = 0x15
5.1
12.0
16.6
FR4 15 inch 4–mil trace
7
R
Float
0000 1011 = 0x0B
7.7
15.0
18.3
FR4 20 inch 4–mil trace
8
R
1
0000 1111 = 0x0F
8.8
16.5
19.7
FR4 25 to 30 inch 4–mil trace
9
Float
0
0101 0101 = 0x55
6.3
14.8
20.3
FR4 30 inch 4–mil trace
10
Float
R
0001 1111 = 0x1F
9.9
19.2
23.6
FR4 35 inch 4–mil trace
11
Float
Float
0010 1111 = 0x2F
11.3
21.7
25.8
10m, 30awg cable
12
Float
1
0011 1111 = 0x3F
12.4
23.2
27.0
10m – 12m cable
13
1
0
1010 1010 = 0xAA
11.9
24.1
29.1
14
1
R
0111 1111 = 0x7F
13.6
26.0
30.7
15
1
Float
1011 1111 = 0xBF
15.1
28.3
32.7
16
1
1
1111 1111 = 0xFF
16.1
29.7
33.8
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Suggested Use
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DS100KR401
DS100KR401
www.ti.com
SNLS395B – JANUARY 2012 – REVISED MARCH 2012
Table 3. De-emphasis and Output Voltage Settings
Level
DEMA1
DEMB1
DEMA0
DEMB0
VOD Vp-p
DEM dB
Inner Amplitude
Vp-p
Suggested Use
1
0
0
0.8
0
0.8
FR4