DS91M040
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SNLS283M – FEBRUARY 2008 – REVISED APRIL 2013
DS91M040 125 MHz Quad M-LVDS Transceiver
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FEATURES
DESCRIPTION
•
The DS91M040 is a quad M-LVDS transceiver
designed for driving / receiving clock or data signals
to / from up to four multipoint networks.
1
2
•
•
•
•
•
•
•
DC - 125 MHz / 250 Mbps Low Jitter, Low
Skew, Low Power Operation
Wide Input Common Mode Voltage Range
Allows up to ±1V of GND Noise
Conforms to TIA/EIA-899 M-LVDS Standard
Pin Selectable M-LVDS Receiver Type (1 or 2)
Controlled Transition Times (2.0 ns typ)
Minimize Reflections
8 kV ESD on M-LVDS I/O pins protects
adjoining components
Flow-Through Pinout Simplifies PCB Layout
Small 5 mm x 5 mm WQFN-32 Space Saving
Package
APPLICATIONS
•
•
•
Multidrop / Multipoint Clock and Data
Distribution
High-Speed, Low Power, Short-Reach
Alternative to TIA/EIA-485/422
Clock Distribution in AdvancedTCA (ATCA)
and MicroTCA (μTCA, uTCA) Backplanes
M-LVDS (Multipoint LVDS) is a new family of bus
interface devices based on LVDS technology
specifically designed for multipoint and multidrop
cable and backplane applications. It differs from
standard LVDS in providing increased drive current to
handle double terminations that are required in multipoint applications. Controlled transition times
minimize reflections that are common in multipoint
configurations due to unterminated stubs. M-LVDS
devices also have a very large input common mode
voltage range for additional noise margin in heavily
loaded and noisy backplane environments.
A single DS91M040 channel is a half-duplex
transceiver that accepts LVTTL/LVCMOS signals at
the driver inputs and converts them to differential MLVDS signal levels. The receiver inputs accept low
voltage differential signals (LVDS, BLVDS, M-LVDS,
LVPECL and CML) and convert them to 3V LVCMOS
signals. The DS91M040 supports both M-LVDS type
1 and type 2 receiver inputs.
System Diagram
Line Card in SLOT 1
DS91M040
Line Card in SLOT N-1
Line Card in SLOT N
M-LVDS Receivers
M-LVDS Receivers
RT
Z0
RT
RT
Z0
RT
RT
Z0
RT
RT
Z0
RT
RT = ZLOADED
BACKPLANE
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS91M040
SNLS283M – FEBRUARY 2008 – REVISED APRIL 2013
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FSEN1
GND
VDD
VDD
RE1
DE1
RE0
DE0
32
31
30
29
28
27
26
25
Connection Diagram
RO0
1
24
B0
DI0
2
23
A0
RO1
3
22
B1
21
A1
20
B2
DI1
4
RO2
5
DAP
(GND)
12
13
14
15
16
RE2
DE2
RE3
DE3
A3
VDD
17
11
8
VDD
B3
DI3
9
A2
18
10
19
7
MDE
6
FSEN2
DI2
RO3
Logic Diagram
FSEN1
DE0
B0
DI0
A0
RE0
RO0
DE1
B1
DI1
A1
RE1
RO1
MDE
DE2
B2
DI2
A2
RE2
RO2
DE3
B3
DI3
A3
RE3
RO3
FSEN2
2
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PIN DESCRIPTIONS
Number
Name
I/O, Type
Description
1, 3, 5, 7
RO
O, LVCMOS
Receiver output pin.
26, 28, 13, 15
RE
I, LVCMOS
Receiver enable pin: When RE is high, the receiver is disabled. When RE is
low, the receiver is enabled. There is a 300 kΩ pullup resistor on this pin.
25, 27, 14, 16
DE
I, LVCMOS
Driver enable pin: When DE is low, the driver is disabled. When DE is high, the
driver is enabled. There is a 300 kΩ pulldown resistor on this pin.
2, 4, 6, 8
DI
I, LVCMOS
Driver input pin.
31, DAP
GND
Power
17, 19, 21, 23
A
I/O, M-LVDS
Non-inverting driver output pin/Non-inverting receiver input pin
18, 20, 22, 24
B
I/O, M-LVDS
Inverting driver output pin/Inverting receiver input pin
11, 12, 29, 30
VDD
Power
32
FSEN1
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2
receiver on inputs 0 and 2.
FSEN1 = L --> Type 1 receiver inputs
FSEN1 = H --> Type 2 receiver inputs
9
FSEN2
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2
receiver on inputs 1 and 3.
FSEN2 = L --> Type 1 receiver inputs
FSEN2 = H --> Type 2 receiver inputs
10
MDE
I, LVCMOS
Master enable pin. When MDE is H, the device is powered up. When MDE is L,
the device overrides all other control and powers down.
Ground pin and pad.
Power supply pin, +3.3V ± 0.3V
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater then VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
xxx
x
xx
xxx
Type 1
High
Type 2
2.4 V
High
150 mV
VID
Low
50 mV
0V
-50 mV
Low
-2.4 V
Transition Region
Figure 1. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Power Supply Voltage
LVCMOS Input Voltage
−0.3V to (VDD + 0.3V)
LVCMOS Output Voltage
−0.3V to (VDD + 0.3V)
−1.9V to +5.5V
M-LVDS I/O Voltage
M-LVDS Output Short Circuit Current Duration
Continuous
Junction Temperature
+140°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range Soldering (4 sec.)
Maximum Package Power Dissipation @ +25°C
+260°C
RTV Package
3.91W
Derate RTV Package
34 mW/°C above +25°C
Package Thermal Resistance (4-Layer, 2 oz. Cu,
JEDEC)
θJA
+29.4°C/W
θJC
+2.8°C/W
ESD Susceptibility
HBM (3)
≥8 kV
MM (4)
≥250V
CDM (5)
(1)
(2)
(3)
(4)
(5)
≥1250V
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Human Body Model, applicable std. JESD22-A114C
Machine Model, applicable std. JESD22-A115-A
Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage, VDD
3.0
3.3
3.6
V
Voltage at Any Bus Terminal (Separate or Common-Mode)
−1.4
+3.8
V
2.4
V
LVTTL Input Voltage High VIH
2.0
VDD
V
LVTTL Input Voltage Low VIL
0
0.8
V
+85
°C
Differential Input Voltage VID
Operating Free Air Temperature TA
4
−40
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+25
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DC Electrical Characteristics (1) (2) (3) (4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
650
mV
M-LVDS Driver
|VAB|
Differential output voltage magnitude
RL = 50Ω, CL = 5 pF
480
ΔVAB
Change in differential output voltage magnitude
between logic states
Figure 2
Figure 4
−50
0
+50
mV
VOS(SS)
Steady-state common-mode output voltage
RL = 50Ω, CL = 5 pF
0.3
1.6
2.1
V
|ΔVOS(SS)|
Change in steady-state common-mode output voltage Figure 2
between logic states
Figure 3
0
+50
mV
VA(OC)
Maximum steady-state open-circuit output voltage
0
2.4
V
VB(OC)
Maximum steady-state open-circuit output voltage
0
2.4
V
VP(H)
Voltage overshoot, low-to-high level output (5)
1.2VSS
V
VP(L)
Voltage overshoot, high-to-low level output (5)
Figure 5
RL = 50Ω, CL = 5pF,CD = 0.5 pF
Figure 7
Figure 8
−0.2V
V
SS
IIH
High-level input current (LVTTL inputs)
VIH = 3.6V
-15
15
μA
IIL
Low-level input current (LVTTL inputs)
VIL = 0.0V
-15
15
μA
VCL
Input Clamp Voltage (LVTTL inputs)
IIN = -18 mA
-1.5
IOS
Differential short-circuit output current (6)
Figure 6
-43
43
mA
16
50
mV
100
150
mV
V
M-LVDS Receiver
VIT+
Positive-going differential input voltage threshold
See Truth Tables
VIT−
Negative-going differential input voltage threshold
See Truth Tables
Type 1
Type 2
VOH
High-level output voltage (LVTTL output)
IOH = −8mA
VOL
Low-level output voltage (LVTTL output)
IOL = 8mA
IOZ
TRI-STATE output current
VO = 0V or 3.6V
IOSR
Short-circuit receiver output current (LVTTL output)
VO = 0V
(1)
(2)
(3)
(4)
(5)
(6)
Type 1
−50
20
mV
Type 2
50
94
mV
2.4
2.7
0.28
−10
-50
V
0.4
V
10
μA
-90
mA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not specified.
CL includes fixture capacitance and CD includes probe capacitance.
Specification is ensured by characterization and is not tested in production.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DC Electrical Characteristics(1)(2)(3)(4) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
32
µA
+20
µA
M-LVDS Bus (Input and Output) Pins
IA
IB
Transceiver input/output current
VA = 3.8V, VB = 1.2V
Transceiver input/output current
VA = 0V or 2.4V, VB = 1.2V
−20
VA = −1.4V, VB = 1.2V
−32
VB = 3.8V, VA = 1.2V
VB = 0V or 2.4V, VA = 1.2V
−20
VB = −1.4V, VA = 1.2V
−32
−4
IAB
Transceiver input/output differential current (IA − IB)
VA = VB, −1.4V ≤ V ≤ 3.8V
IA(OFF)
Transceiver input/output power-off current
VA = 3.8V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
IB(OFF)
Transceiver input/output power-off current
VA = 0V or 2.4V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−20
VA = −1.4V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−32
−20
VB = −1.4V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−32
Transceiver input/output power-off differential current
(IA(OFF) − IB(OFF))
VA = VB, −1.4V ≤ V ≤ 3.8V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−4
CA
Transceiver input/output capacitance
VDD = OPEN
CB
Transceiver input/output capacitance
CAB
CA/B
32
µA
+20
µA
µA
+4
µA
32
µA
+20
µA
µA
VB = 3.8V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
VB = 0V or 2.4V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
IAB(OFF)
µA
32
µA
+20
µA
µA
+4
µA
7.8
pF
7.8
pF
Transceiver input/output differential capacitance
3
pF
Transceiver input/output capacitance balance (CA/CB)
1
SUPPLY CURRENT (VCC)
ICCD
Driver Supply Current
RL = 50Ω, DE = H, RE = H
67
75
mA
ICCZ
TRI-STATE Supply Current
DE = L, RE = H
22
26
mA
ICCR
Receiver Supply Current
DE = L, RE = L
32
38
mA
ICCPD
Power Down Supply Current
MDE = L
3
5
mA
6
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Switching Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AC SPECIFICATIONS
tPLH
Differential Propagation Delay Low to High
RL = 50Ω, CL = 5 pF,
1.5
3.3
5.5
ns
tPHL
Differential Propagation Delay High to Low
CD = 0.5 pF
1.5
3.3
5.5
ns
tSKD1
Pulse Skew (4) (5)
Figure 7
Figure 8
30
125
ps
tSKD2
Channel-to-Channel Skew (4) (6)
100
200
ps
tSKD3
Part-to-Part Skew (4) (7)
0.8
1.6
ns
tSKD4
Part-to-Part Skew
(4) (8)
4
ns
tTLH
Rise Time (4)
1.2
2.0
3.0
ns
tTHL
Fall Time (4)
1.2
2.0
3.0
ns
tPZH
Enable Time (Z to Active High)
RL = 50Ω, CL = 5 pF,
7.5
11.5
ns
tPZL
Enable Time (Z to Active Low )
CD = 0.5 pF
8.0
11.5
ns
tPLZ
Disable Time (Active Low to Z)
Figure 9
Figure 10
7.0
11.5
ns
tPHZ
Disable Time (Active High to Z)
7.0
11.5
ns
RECEIVER AC SPECIFICATIONS
tPLH
Propagation Delay Low to High
CL = 15 pF
1.5
3.0
4.5
ns
tPHL
Propagation Delay High to Low
Figure 11
Figure 12
Figure 13
1.5
3.1
4.5
ns
tSKD1A
Pulse Skew (Receiver Type 1) (4) (5)
55
325
ps
tSKD1B
Pulse Skew (Receiver Type 2)
(4) (5)
475
800
ps
tSKD2
Channel-to-Channel Skew (4) (6)
60
300
ps
tSKD3
Part-to-Part Skew (4) (7)
0.6
1.2
ns
(8)
tSKD4
Part-to-Part Skew
3
ns
tTLH
Rise Time (4)
0.3
1.1
1.6
ns
tTHL
Fall Time (4)
0.3
0.65
1.6
ns
tPZH
Enable Time (Z to Active High)
RL = 500Ω, CL = 15 pF
3
5.5
ns
tPZL
Enable Time (Z to Active Low)
Figure 14
Figure 15
3
5.5
ns
tPLZ
Disable Time (Active Low to Z)
3.5
5.5
ns
tPHZ
Disable Time (Active High to Z)
3.5
5.5
ns
500
ms
GENERIC AC SPECIFICATIONS
tWKUP
Wake Up Time (4)
(Master Device Enable (MDE) time)
fMAX
Maximum Operating Frequency (4)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
125
MHz
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not specified.
CL includes fixture capacitance and CD includes probe capacitance.
Specification is ensured by characterization and is not tested in production.
tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels.
tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
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Test Circuits and Waveforms
Figure 2. Differential Driver Test Circuit
A
~ 1.9V
B
~ 1.3V
'VOS(SS)
VOS
VOS(PP)
Figure 3. Differential Driver Waveforms
Figure 4. Differential Driver Full Load Test Circuit
Figure 5. Differential Driver DC Open Test Circuit
8
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Figure 6. Differential Driver Short-Circuit Test Circuit
Figure 7. Driver Propagation Delay and Transition Time Test Circuit
Figure 8. Driver Propagation Delays and Transition Time Waveforms
Figure 9. Driver TRI-STATE Delay Test Circuit
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Figure 10. Driver TRI-STATE Delay Waveforms
Figure 11. Receiver Propagation Delay and Transition Time Test Circuit
Figure 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms
10
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Figure 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 14. Receiver TRI-STATE Delay Test Circuit
Figure 15. Receiver TRI-STATE Delay Waveforms
TRUTH TABLES
DS91M040 Transmitting (1)
Inputs
(1)
Outputs
RE
DE
DI
B
A
X
H
X
H
H
L
H
L
H
X
L
L
X
Z
Z
X — Don't care condition
Z — High impedance state
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DS91M040 as Type 1 Receiving (1)
Inputs
(1)
Output
FSEN
RE
DE
A−B
RO
L
L
X
≥ +0.05V
H
L
L
X
≤ −0.05V
L
L
L
X
−0.05V
≤ A-B ≤ +0.05V
Undefined
L
H
X
X
Z
X — Don't care condition
Z — High impedance state
DS91M040 as Type 2 Receiving (1)
Inputs
(1)
Output
FSEN
RE
DE
A−B
RO
H
L
X
≥ +0.15V
H
H
L
X
≤ +0.05V
L
H
L
X
+0.05V
≤ A-B ≤ +0.15V
Undefined
H
H
X
X
Z
X — Don't care condition
Z — High impedance state
DS91M040 Type 1 Receiver Input Threshold Test Voltages (1)
Applied Voltages
(1)
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VIA
VIB
VID
VICM
R
2.400V
0.000V
2.400V
1.200V
H
0.000V
2.400V
−2.400V
1.200V
L
3.800V
3.750V
0.050V
3.775V
H
3.750V
3.800V
−0.050V
3.775V
L
−1.350V
−1.400V
0.050V
−1.375V
H
−1.400V
−1.350V
−0.050V
−1.375V
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
DS91M040 Type 2 Receiver Input Threshold Test Voltages (1)
Applied Voltages
(1)
12
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VIA
VIB
VID
VIC
R
2.400V
0.000V
2.400V
1.200V
H
0.000V
2.400V
−2.400V
1.200V
L
3.800V
3.650V
0.150V
3.725V
H
3.800V
3.750V
0.050V
3.775V
L
−1.250V
−1.400V
0.150V
−1.325V
H
−1.350V
−1.400V
0.050V
−1.375V
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
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Typical Performance Characteristics
2.8
2.8
f = 125 MHz
VCC = 3.0 V
DRIVER FALL TIME (10-90%) (ns)
DRIVER RISE TIME (10-90%) (ns)
f = 125 MHz
2.5
2.2
1.9
VCC = 3.6 V
1.6
VCC = 3.3 V
1.3
1.0
-50
-10
30
70
110
2.2
1.9
VCC = 3.6 V
1.6
VCC = 3.3 V
1.3
1.0
-50
150
-10
TEMPERATURE (°C)
750
600
450
300
f = 1 MHz
VCC = 3.3V
150
TA = 25°C
0
50
75
100
125
VCC = 3.0 V
4.0
3.5
3.0
VCC = 3.6 V
2.5
VCC = 3.3 V
2.0
30
70
VCC = 3.0 V
f = 125 MHz
4.0
3.5
3.0
VCC = 3.6 V
2.5
VCC = 3.3 V
2.0
1.5
-50
-10
30
70
110
150
110
Figure 19. Driver Propagation Delay (tPLHD) as a Function
of Temperature
DRIVER POWER SUPPLY CURRENT (mA)
DRIVER PROPAGATION DELAY (tPHLD) (ns)
4.5
-10
150
TEMPERATURE (°C)
Figure 18. Driver Output Signal Amplitude as a Function of
Resistive Load
1.5
-50
110
4.5
RESISTIVE LOAD (:)
f = 125 MHz
70
Figure 17. Driver Fall Time as a Function of Temperature
DRIVER PROPAGATION DELAY (tPLHD) (ns)
VOD - DRIVER OUTPUT AMPLITUDE (mV)
900
25
30
TEMPERATURE (°C)
Figure 16. Driver Rise Time as a Function of Temperature
0
VCC = 3.0 V
2.5
180
150
120
150
90
f = 125 MHz
VCC = 3.3V
60
TA = 25°C
RL = 50: On all CH)
30
DE0,1,2,3 = H
RE*0,1,2,3 = H
0
0
TEMPERATURE (°C)
25
50
75
100
125
FREQUENCY (MHz)
Figure 20. Driver Propagation Delay (tPHLD) as a Function
of Temperature
Figure 21. Driver Power Supply Current as a Function of
Frequency
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Product Folder Links: DS91M040
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DS91M040
SNLS283M – FEBRUARY 2008 – REVISED APRIL 2013
www.ti.com
RECEIVER PROPAGATION DELAY (tPLHD) (ns)
RECEIVER POWER SUPPLY CURRENT (mA)
Typical Performance Characteristics (continued)
90
75
60
45
f = 125 MHz
VCC = 3.3V
30
TA = 25°C
15
DE0,1,2,3 = L
RE*0,1,2,3 = L
0
0
25
50
75
100
125
3.8
f = 125 MHz
3.2
TYPE 2
TA = 25°C
VID = 200 mV
2.9
2.6
TYPE 1
2.3
2.0
-4.0
FREQUENCY (MHz)
-2.4
-0.8
0.8
2.4
4.0
INPUT COMMON MODE VOLTAGE (V)
Figure 22. Receiver Power Supply Current as a Function of
Frequency
RECEIVER PROPAGATION DELAY (tPHLD) (ns)
VCC = 3.3V
3.5
Figure 23. Receiver Propagation Delay (tPLHD) as a
Function of Input Common Mode Voltage
3.8
f = 125 MHz
3.5
VCC = 3.3V
3.2
VID = 200 mV
TA = 25°C
TYPE 2
2.9
2.6
2.3
TYPE 1
2.0
-4.0
-2.4
-0.8
0.8
2.4
4.0
INPUT COMMON MODE VOLTAGE (V)
Figure 24. Receiver Propagation Delay (tPHLD) as a Function of Input Common Mode Voltage
14
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS91M040
DS91M040
www.ti.com
SNLS283M – FEBRUARY 2008 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision L (April 2013) to Revision M
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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Product Folder Links: DS91M040
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS91M040TSQ/NOPB
ACTIVE
WQFN
RTV
32
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M040TS
DS91M040TSQE/NOPB
ACTIVE
WQFN
RTV
32
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M040TS
DS91M040TSQX/NOPB
ACTIVE
WQFN
RTV
32
4500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
M040TS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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