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ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020
ISO1500 3-kVRMS Basic Isolated RS-485/RS-422 Transceiver in Ultra-Small Package
1 Features
3 Description
•
•
•
•
The ISO1500 device is a galvanically-isolated
differential line transceiver for TIA/EIA RS-485 and
RS-422 applications. This device has a 3-channel
digital isolator and an RS-485 transceiver in an ultrasmall 16-pin SSOP package. The bus pins of this
transceiver are protected against IEC ESD contact
discharge and IEC EFT events. The receiver output
has a failsafe for bus open, short, and idle conditions.
The small solution size of ISO1500 greatly reduces
the board space required compared to other
integrated isolated RS-485 solutions or discrete
implementation with optocouplers and non-isolated
RS-485 transceiver.
1
•
•
•
•
•
•
•
•
Meets or exceeds requirements of TIA/EIA-485-A
Half-duplex transceiver
Low-EMI 1-Mbps data rate
Bus I/O protection
– ± 16 kV HBM ESD
1.71-V to 5.5-V Logic-side supply (VCC1), 4.5-V to
5.5-V Bus-side supply (VCC2)
1/8 Unit load: up to 256 nodes on bus
Failsafe receiver for bus open, short, and idle
100-kV/µs (typical) High common-mode transient
immunity
Extended temperature range from –40°C to
+125°C
Glitch-free power-up and power-down for hot plugin
Ultra-small SSOP (DBQ-16) package
Safety-related certifications:
– 4242-VPK VIOTM and 566-VPK VIORM per DIN
VDE V 0884-11:2017-01
– 3000-VRMS Isolation for 1 minute per UL 1577
– IEC 60950-1, IEC 62368-1 and IEC 61010-1
certifications
– CQC, TUV, and CSA certifications
2 Applications
•
•
•
•
•
Electricity meters
Protection relay
Factory automation & control
HVAC systems and building automation
Motor drives
The device is used for long distance communications.
Isolation breaks the ground loop between the
communicating nodes, allowing for a much larger
common mode voltage range. The symmetrical
isolation barrier of each device is tested to provide
3000 VRMS of isolation for 1 minute per UL 1577
between the bus-line transceiver and the logic-level
interface.
The ISO1500 device can operate from 1.71 V to 5.5
V on side 1 which lets the devices interface with lowvoltage FPGAs and ASICs. The supply voltage on
side 2 is from 4.5 V to 5.5 V. This device supports a
wide operating ambient temperature range from
–40°C to +125°C.
Device Information(1)
PART NUMBER
ISO1500
PACKAGE
BODY SIZE (NOM)
SSOP (16)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Logic Supply
VCC2
VCC1
Bus-Side Supply
VDD
DE
MCU
ISO1500
A
D
B
RS485 Bus
R
DGND
RE
GND1
GND2
Isolated Ground
Logic Ground
Galvanic Isolation
Barrier
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1500
SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics: Driver ............................... 8
Electrical Characteristics: Receiver ........................ 8
Supply Current Characteristics: Side 1(ICC1) .......... 9
Supply Current Characteristics: Side 2(ICC2) .......... 9
Switching Characteristics: Driver .......................... 10
Switching Characteristics: Receiver...................... 10
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 11
7
8
Parameter Measurement Information ................ 15
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
18
20
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 23
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2019) to Revision D
•
Page
Added updated certification information in Safety-Related Certifications .............................................................................. 7
Changes from Revision B (May 2019) to Revision C
Page
•
Changed certificate related info in Features section .............................................................................................................. 1
•
Added footnote to Pin function table for NC pin ..................................................................................................................... 3
Changes from Revision A (December 2018) to Revision B
•
Added HBM ESD to feature list ............................................................................................................................................. 1
Changes from Original (September 2018) to Revision A
•
2
Page
Page
Changed device status from Advanced Information to Production Data................................................................................ 1
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SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020
5 Pin Configuration and Functions
DBQ Package
16-Pin SSOP
Top View
1
16
VCC2
GND1
2
15
GND2
R
3
14
NC
RE
4
13
B
DE
5
12
A
D
6
11
NC
NC
7
10
VCC2
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
12
I/O
Transceiver noninverting input or output (I/O) on the bus side
B
13
I/O
Transceiver inverting input or output (I/O) on the bus side
D
6
I
Driver input
DE
5
I
Driver enable. This pin enables the driver output when high and disables the driver output when low
or open.
GND1
GND2
2
8
9
15
—
Ground connection for VCC1
—
Ground connection for VCC2
—
No internal connection
7
NC (1)
11
14
R
3
O
Receiver output
RE
4
I
Receiver enable. This pin disables the receiver output when high or open and enables the receiver
output when low.
VCC1
1
—
Logic-side power supply
—
Transceiver-side power supply. These pins are not connected internally and must be shorted
externally on PCB.
VCC2
(1)
10
16
Device functionality is not affected if NC pins are connected to supply or ground on PCB
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SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VCC1
Supply voltage, side 1
-0.5
6
V
VCC2
Supply voltage, side 2
-0.5
6
V
VIO
Logic voltage level (D, DE, RE, R)
-0.5
VCC1+0.5 (3)
IO
Output current on R pin
-15
15
VBUS
Voltage on bus pins (A, B, Y, Z w.r.t GND2)
-18
18
V
TJ
Junction temperature
-40
150
℃
TSTG
Storage temperature
-65
150
℃
(1)
(2)
(3)
UNIT
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
6.2 ESD Ratings
V(ESD)
(1)
(2)
VALUE
UNIT
±4000
V
All pins except bus pins (1)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
Bus terminals to GND2
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
(1)
±16000
V
All pins (2)
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC1
MIN
MAX
UNIT
Supply Voltage, Side 1, 1.8-V operation
1.71
1.89
V
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation
2.25
5.5
V
4.5
5.5
V
-7
12
V
VCC2
Supply Voltage, Side 2
VI
Common mode voltage at any bus terminal: A or B
VIH
High-level input voltage (D, DE, RE inputs)
0.7*VCC1
VCC1
V
VIL
Low-level input voltage (D, DE, RE inputs)
0
0.3*VCC1
V
VID
Differential input voltage
-12
12
V
IO
Output current, Driver
-60
60
mA
IOR
Output current, Receiver
-4
4
mA
RL
Differential load resistance
54
1/tUI
Signaling rate
TA
Operating ambient temperature
Ω
1
-40
125
Mbps
°C
6.4 Thermal Information
ISO1500
THERMAL METRIC (1)
DBQ (SSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
112.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020
Thermal Information (continued)
ISO1500
THERMAL METRIC (1)
DBQ (SSOP)
UNIT
16 PINS
RθJB
Junction-to-board thermal resistance
64.0
°C/W
ΨJT
Junction-to-top characterization parameter
32.1
°C/W
ΨJB
Junction-to-board characterization parameter
63.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
--
°C/W
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
TEST CONDITIONS
VCC1 = VCC2 = 5.5 V, TA=125°C, TJ =
150°C, A-B load = 54 Ω ||50pF, Load on
R=15pF
Input a 500kHz 50% duty cycle square
wave to D pin with
VDE=VCC1, VRE=GND1
MIN
TYP
MAX
UNIT
278
mW
28
mW
250
mW
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SLLSF21D – SEPTEMBER 2018 – REVISED FEBRUARY 2020
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6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
SPECIFICATIONS
DBQ-16
UNIT
IEC 60664-1
External clearance
(1)
Side 1 to side 2 distance through air
>3.7
mm
CPG
External creepage
(1)
Side 1 to side 2 distance across package surface >3.7
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
µm
CTI
Comparative tracking index
IEC 60112; UL 746A
>600
V
Material Group
According to IEC 60664-1
I
Overvoltage category
Rated mains voltage ≤ 300 VRMS
I-III
CLR
DIN VDE V 0884-11:2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage AC voltage (bipolar)
VIOWM
Maximum isolation working voltage
566
VPK
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test;
400
VRMS
DC voltage
566
VDC
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST =
1.2 × VIOTM, t = 1 s (100% production)
4242
VPK
VIOSM
Maximum surge isolation voltage
ISO1500 (3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 10000 VPK (qualification)
4000
VPK
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10
s
≤5
qpd
Apparent charge
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM , tm = 10 s
(4)
≤5
pC
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM, tini =
1 s;
≤5
Vpd(m) = 1.875 × VIORM , tm = 1 s
CIO
Barrier capacitance, input to output
RIO
(5)
Insulation resistance, input to output
(5)
VIO = 0.4 × sin (2 πft), f = 1 MHz
~1
pF
12
VIO = 500 V, TA = 25°C
> 10
VIO = 500 V, 100°C ≤ TA ≤ 150°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO , t = 60 s (qualification); VTEST = 1.2
3000
× VISO , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
ISO1500 is suitable for safe electrical insulation within the safety ratings. Compliance with the safety ratings shall be ensured by means
of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
Certified according to DIN
VDE V 0884-11:2017- 01
Maximum transient
isolation voltage,
4242 VPK;
Maximum repetitive peak
isolation voltage,
566 VPK;
Maximum surge isolation
voltage,
4000 VPK
Certificate number:
40040142
Certified according to IEC
60950-1, IEC 62368-1
UL
Recognized under UL
1577 Component
Recognition Program
CQC
TUV
Certified according to
GB4943.1-2011
Certified according to EN
61010-1:2010/A1:2019,
EN 609501:2006/A2:2013 and EN
62368-1:2014
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2, CSA 623681-14, and IEC 62368-1
Single protection,
2nd Ed., for pollution
3000 VRMS
degree 2, material group I:
370 VRMS
EN 610101:2010/A1:2019,
Basic insulation, Altitude ≤ 300 VRMS basic isolation
5000 m, Tropical Climate, ---------------400 VRMS maximum
EN 60950working voltage
1:2006/A2:2013 and EN
62368-1:2014, 400 VRMS
basic isolation
Master contract number:
220991
Certificate number:
CQC18001199097
File number: E181974
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DBQ-16 PACKAGE
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
RθJA = 67.9°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C, see Figure 1
201
RθJA = 67.9°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C, see Figure 1
308
RθJA = 67.9°C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C, see Figure 1
403
RθJA = 67.9°C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C, see Figure 1
586
RθJA = 67.9°C/W, TJ = 150°C, TA = 25°C,
see Figure 2
mA
1105
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics: Driver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
|VOD|
Driver differential-output voltage
magnitude
MIN
TYP
MAX
UNIT
Open circuit voltage, unloaded bus,
4.5 V ≤ VCC2 ≤ 5.5 V
TEST CONDITIONS
1.5
4.3
VCC2
V
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V,
4.5 V < VCC2 < 5.5 V (see Figure 19)
1.5
2.5
V
RL = 100 Ω (see Figure 20), RS-422 load
2
2.9
V
RL = 54 Ω (see Figure 20), RS-485 load,
4.5 V < VCC2 < 5.5 V
1.5
2.5
V
–50
Δ|VOD|
Change in differential output voltage
between two states
RL = 54 Ω or RL = 100 Ω, see Figure 20
VOC
Common-mode output voltage
RL = 54 Ω or RL = 100 Ω, see Figure 20
ΔVOC(SS)
change in steady-state common-mode
RL = 54 Ω or RL = 100 Ω, see Figure 20
output voltage between two states
VOC(PP)
Peak-to-peak common-mode output
voltage
RL = 54 Ω or RL = 100 Ω, see Figure 20
IOS
Short-circuit output current
VD = VCC1 or VD = VGND1, VDE = VCC1,
–7 V ≤ VO ≤ 12 V, see Figure 28
Ii
Input current
VD and VDE = 0 V or VD and VDE = VCC1
CMTI
Common-mode transient immunity
VD= VCC1 or GND1, VCM = 1200V, See Figure 22
0.5 × VCC2
–50
50
mV
3
V
50
mV
300
–175
mV
175
–10
85
10
100
mA
µA
kV/µs
6.10 Electrical Characteristics: Receiver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max are over recommended operating conditions unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Ii1
Bus input current
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, One bus
input at –7 V or 12 V, other input at 0 V
VTH+
Positive-going input threshold voltage
–7 V ≤ Common mode voltage on bus terminals ≤
12 V
VTH–
Negative-going input threshold
voltage
Vhys
Input hysteresis (VTH+ – VTH–)
VOH
Output high voltage on the R pin
VOL
Output low voltage on the R pin
–100
–100
–7 V ≤ Common mode voltage on bus terminals ≤
12 V
–200
–145
–7 V ≤ Common mode voltage on bus terminals ≤
12 V
20
45
See
MAX
UNIT
100
µA
–50
mV
(1)
mV
See
mV
VCC1=5V+/-10%, IOH = –4 mA, VID = 200 mV
VCC1 – 0.4
V
VCC1=3.3V+/-10%, IOH = –2 mA, VID = 200 mV
VCC1 – 0.3
V
VCC1=2.5V+/-10%, 1.8V+/-5%, IOH = –1 mA, VID =
200 mV
VCC1 – 0.2
V
VCC1=5V+/-10%, IOL = 4 mA, VID = –200 mV
0.4
V
VCC1=3.3V+/-10%, IOL = 2 mA, VID = –200 mV
0.3
V
VCC1=2.5V+/-10%, 1.8V+/-5%, IOL = 1 mA, VID =
–200 mV
0.2
V
1
µA
Output high-impedance current on
the R pin
VR = 0 V or VR = VCC1, VRE = VCC1
Ii
Input current on the RE pin
VRE = 0 V or VRE = VCC1
CMTI
Common-mode transient immunity
VID = 1.5 V or -1.5 V, VCM= 1200 V , See Figure 22
8
TYP
(1)
IOZ
(1)
MIN
–1
–10
85
10
100
µA
kV/µs
Under any specific conditions, VTH+ is ensured to be at least Vhys higher than VTH–.
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6.11 Supply Current Characteristics: Side 1(ICC1)
Bus loaded or unloaded (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER ENABLED, RECEIVER DISABLED
Logic-side
supply current
VD = VCC1, VCC1 = 5 V ± 10%
2.6
4.4
mA
Logic-side
supply current
VD = VCC1, VCC1 = 3.3 V ± 10%
2.6
4.4
mA
Logic-side
supply current
D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
3.2
5.1
mA
Logic-side
supply current
D = 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
3.2
5.1
mA
DRIVER ENABLED, RECEIVER ENABLED
Logic-side
supply current
VRE = VGND1, VD = VCC1, VCC1 = 5 V ± 10%
2.6
4.4
mA
Logic-side
supply current
VRE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10%
2.6
4.4
mA
Logic-side
supply current
VRE = VGND1, D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%, CL(R) (1) = 15 pF
3.4
5.2
mA
Logic-side
supply current
VRE = VGND1, D= 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%, CL(R) (1) = 15 pF
3.2
5.2
mA
DRIVER DISABLED, RECEIVER ENABLED
Logic-side
supply current
V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 5 V ± 10%
1.5
3.1
mA
Logic-side
supply current
V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 3.3 V ± 10%
1.5
3.1
mA
Logic-side
supply current
(A-B) =1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R) (1) = 15 pF
1.7
3.2
mA
Logic-side
supply current
(A-B) = 1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R) (1) = 15 pF
1.7
3.2
mA
DRIVER DISABLED, RECEIVER DISABLED
Logic-side
supply current
VDE = VGND1, VD = VCC1, VCC1 = 5 V ± 10%
1.5
3.1
mA
Logic-side
supply current
VDE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10%
1.5
3.1
mA
TYP
MAX
2.5
4.4
mA
(1)
CL(R) is the load capacitance on the R pin.
6.12 Supply Current Characteristics: Side 2(ICC2)
VRE = VGND1 or VRE = VCC1 (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
DRIVER ENABLED, BUS UNLOADED
Bus-side supply
current
VD = VCC1, VCC2 = 5 V ± 10%
DRIVER ENABLED, BUS LOADED
Bus-side supply
current
VD = VCC1, RL = 54 Ω, VCC2 = 5 V ± 10%
52
70
mA
Bus-side supply
current
D =1Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
60
80
mA
2.4
3.9
mA
DRIVER DISABLED, BUS LOADED OR UNLOADED
Bus-side supply
current
VD = VCC1, VCC2 = 5 V ± 10%
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6.13 Switching Characteristics: Driver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs over recommended operating conditions unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 54 Ω, CL = 50 pF, see Figure 21
210
300
ns
RL = 54 Ω, CL = 50 pF, see Figure 21
210
300
ns
RL = 54 Ω, CL = 50 pF, see Figure 21
3
30
ns
1Mbps DEVICE
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
Pulse width distortion (1), |tPHL – tPLH|
PWD
tPHZ, tPLZ Disable time
See Figure 23, and Figure 24
160
250
ns
tPZH, tPZL Enable time
See Figure 23, and Figure 24
200
400
ns
(1)
Also known as pulse skew.
6.14 Switching Characteristics: Receiver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max are over recommended operating conditions unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CL = 15 pF, see Figure 25
2.4
4
ns
CL = 15 pF, see Figure 25
120
180
ns
CL = 15 pF, see Figure 25
5
20
ns
1Mbps DEVICE
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
Pulse width distortion (1), |tPHL – tPLH|
PWD
tPHZ, tPLZ Disable time
See Figure 26 and Figure 27
11
30
ns
tPZH, tPZL Enable time
See Figure 26 and Figure 27
7
20
ns
(1)
Also known as pulse skew.
6.15 Insulation Characteristics Curves
700
1200
Safety Limiting Current (mA)
600
500
Safety Limiting Power (mW)
VCC = 1.89 V
VCC = 2.75 V
VCC = 3.6 V
VCC = 5.5 V
400
300
200
100
0
800
600
400
200
0
0
50
100
150
Ambient Temperature (qC)
200
0
D001
Figure 1. Thermal Derating Curve for Limiting Current per
VDE
10
1000
50
100
150
Ambient Temperature (qC)
200
D002
Figure 2. Thermal Derating Curve for Limiting Power per
VDE
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6.16 Typical Characteristics
35
80
ICC1 (VCC1 = 3.3V)
ICC2 (VCC2 = 5V)
ICC1 (VCC1=3.3V)
ICC2 (VCC2=5V)
70
25
Supply current (mA)
Supply Current (mA)
30
20
15
10
5
60
50
40
30
20
10
0
0
0
100
200
300
TA = 25°C
400 500 600 700
Data Rate (kbps)
800
900 1000
0
100
200
D001
DE = VCC1
RE = GND1
Figure 3. Supply Current Vs Data Rate- No Load
TA = 25°C
Driver load = 54
ohm || 50 pF
300
400 500 600
Data rate (kbps)
700
800
900 1000
D002
DE = VCC1
Load on R = 15 pF
RE = GND1
Figure 4. Supply Current Vs Data Rate- with 54 Ω || 50 pf
Load
60
4.5
Supply Current (mA)
50
Driver Differential Output Voltage (V)
ICC1 (VCC1=3.3V)
ICC2 (VCC2=5V)
40
30
20
10
0
4
3.5
3
2.5
2
1.5
1
0.5
0
100
200
TA = 25°C
Driver load = 120
ohm || 50 pF
300
400 500 600
Data rate (kbps)
700
DE = VCC1
Load on R = 15 pF
800
900 1000
0
10
20
D003
RE = GND1
Figure 5. Supply Current Vs Data Rate - with 120 Ω || 50 pf
Load
DE = VCC1
VCC2 = 5 V
30
40
50
60
70
Driver output current (mA)
D = GND1
TA = 25°C
80
90
100
D005
VCC1 = 3.3 V
Figure 6. Driver Differential Output Voltage Vs Driver Output
Current
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Typical Characteristics (continued)
4
5
Driver Output Voltage (V)
Driver Differential Output Voltage (V)
VOH
VOL
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
Driver output current (mA)
DE = VCC1
VCC2 = 5 V
80
90
VOD (5V, 120 :)
VOD (5V, 54 :)
3.5
3
2.5
2
1.5
1
-40
100
-20
0
D004
D = GND1
TA = 25°C
20
40
60
80
Ambient temp (°C)
100
120
140
D006
VCC1 = 3.3 V
Figure 7. Driver Output Voltage Vs Driver Output Current
Figure 8. Driver Differential Output Voltage Vs Temperature
230
55
225
45
Driver rise/fall time (ns)
Driver Output Current (mA)
50
40
35
30
25
20
15
10
220
215
210
205
200
5
0
0
0.5
1
TA = 25°C
1.5
2 2.5
3 3.5
4
Supply Voltage VCC2 (V)
RL = 54 ohm
4.5
5
5.5
-20
0
D007
DE = D = VCC1
Figure 9. Driver Output Current Vs Supply Voltage (VCC2)
12
195
-40
VCC1 = 3.3 V
20
40
60
80
100
Ambient Temperature (°C )
120
140
D008
VCC2 = 5 V
Figure 10. Driver rise/fall time vs Temperature
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Typical Characteristics (continued)
7
High Level Output Voltage (V)
Driver Propoagation Delay (ns)
215
210
205
200
195
190
-40
-20
VCC1 = 3.3 V
0
20
40
60
80
100
Ambient Temperature (°C )
120
5
4
3
2
1
0
-15
140
-10
-5
High Level Output Current (mA)
D009
VCC2 = 5 V
0
D010
TA = 25°C
Figure 11. Driver Propagation Delay vs Temperature
Figure 12. Receiver Buffer High Level Output Voltage Vs
High Level Output Current
0.9
140
Reveiver Propagation Delay (ns)
0.8
Low Level Output Voltage (V)
VOH (1.8V)
VOH (3.3V)
VOH (5V)
6
0.7
0.6
0.5
0.4
0.3
0.2
Vol (1.8V)
Vol (3.3V)
Vol (5V)
0.1
0
0
5
10
Low Level Output Current (mA)
15
135
130
125
120
115
110
105
-40
-20
D013
TA = 25°C
VCC1 = 3.3 V
Figure 13. Receiver Buffer Low Level Output Voltage Vs
Low Level Output Current
0
20
40
60
Temperature (qC)
80
100
120
D014
VCC2 = 5 V
Figure 14. Receiver Propagation Delay Vs Temperature
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Typical Characteristics (continued)
VCC1 = 3.3 V
TA = 25°C
VCC2 = 5 V
DE = VCC1
VCC1 = 3.3 V
DE = GND1
VCC2 = 5 V
RE = GND1
TA = 25°C,
Figure 16. Receiver Propagation Delay
Figure 15. Driver Propagation delay
Figure 18. VCC2 Power Up / Power down- Glitch Free
Behavior
Figure 17. VCC1 Power Up / Power down- Glitch Free
Behavior
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7 Parameter Measurement Information
VCC2
375
DE = VCC1
A
B VOD
D = 0 or
VCC1
RL
VTEST
375
+
±
GND2
Figure 19. Driver Voltages
RL(1) / 2
A
A
VA
B
VB
VOC
VOD
RL(1) / 2
B
VOC
GND2
ûVOC(SS)
VOC(PP)
(1)
0 V or D
VCC1
RL = 100 Ω for RS422, RL = 54 Ω for RS-485
Figure 20. Driver Voltages
VCC1
DE = VCC1
RL
54
D
Input
Generator
50
VI
VI
VOD
A
CL(1)
50 pF ± 20%
± 1%
50%
tPHL
tPLH
90%
B
VOD
0V
10%
GND1
(1)
90%
tr
tf
VOD (H)
0V
10%
VOD (L)
CL includes fixture and instrumentation capacitance.
Figure 21. Driver Switching Specifications
VCC1
VCC1
VCC2
10 µF
0.1 µF
GND1
DE
0.1 µF
10 µF
A
D
B
54
+
VOH or VOL
±
GND1
R
+
VOH or VOL
±
1k
CL
15 pF(1)
RE
GND1
GND2
+ VCM ±
(1)
Includes probe and fixture capacitance.
Figure 22. Common Mode Transient Immunity (CMTI)—Half Duplex
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Parameter Measurement Information (continued)
A
S1
D
Input
Generator
VI
50 %
VI
B
DE
VCC1
VO
CL(1)
50 pF
50 %
0V
RL
110
tPZH
90%
50
VOH
50%
VO
§0V
tPHZ
GND2
GND1
(1)
CL includes fixture and instrumentation capacitance
Figure 23. Driver Enable and Disable Times
VCC2
RL
110
A
VCC1
50 %
VI
D
0V
S1
Input
Generator
VI
tPLZ
tPZL
(1)
B
DE
50 %
CL
50 pF
VO
VCC2
50%
10%
50
VOL
GND2
GND1
Figure 24. Driver Enable and Disable Times
3V
50 %
A
R
Input
Generator
VI
50
1.5 V
B
RE
CL(1)
15 pF
0V
tPHL
tPLH
90%
50%
10%
50%
VO
tr
(1)
50 %
VI
VO
tf
VOH
VOL
CL includes fixture and instrumentation capacitance.
Figure 25. Receiver Switching Specifications
VCC1
50%
VI
0V
tPHZ
tPZH
VO
90%
50%
VOH
§0V
tPZL
tPLZ
VO
50%
VCC1
10%
VOL
Figure 26. Receiver Enable and Disable Times
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Parameter Measurement Information (continued)
VCC1
VCC1
VI
A
0 V or 1.5 V
R
B
1.5 V or 0 V
RE
Input
Generator
VI
VO
50%
0V
1k
S1
CL
15 pF
tPZH
VOH
VO
A at 1.5 V
B at 0 V
§ 0 V S1 to GND
50%
tPZL
50
VCC1
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to
VCC1
Figure 27. Receiver Enable and Disable Times
Steady-State
Logic Input
(1 or 0)
A
G
B
G
±7 9 ” 9 ” 12 V
I(1)
B
V
C
C
GND
(1)
A
Steady State
Logic Input
(1 or 0)
GND
The driver should not sustain any damage with this configuration.
Figure 28. Short-Circuit Current Limiting
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8 Detailed Description
8.1 Overview
The ISO1500 device is an isolated RS-485/RS-422 transceiver designed to operate in harsh industrial
environments. This device supports data transmissions up to 1 Mbps. The ISO1500 device has a 3-channel
digital isolator and an RS-485 transceiver in an ultra-small SSOP package. The silicon-dioxide based capacitive
isolation barrier supports an isolation withstand voltage of 3 kVRMS and an isolation working voltage of 566 VPK.
Isolation breaks the ground loop between the communicating nodes and lets data transfer in the presence of
large ground potential differences. The wide logic supply of the device (VCC1) supports interfacing with 1.8-V, 2.5V, 3.3-V. and 5-V control logic. Functional Block Diagram shows the functional block diagram of the the halfduplex device.
8.2 Functional Block Diagram
VCC1
VCC2
VCC2
VCC
DE
Tx
Rx
D
Tx
Rx
R
Rx
Tx
A
D
Half duplex
B
R
RE
GND1
GND2
GND2
8.3 Feature Description
Table 1 shows an overview of the device features.
Table 1. Device Features
PART NUMBER
ISOLATION
DUPLEX
DATA RATE
PACKAGE
ISO1500
Basic
Half
1 Mbps
16-pin SSOP
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO1500
device has dedicated circuitry to help protect the transceiver from Contact ESD per IEC61000-4-2.
8.3.2 Failsafe Receiver
The differential receiver of the ISO1500 device has failsafe protection from invalid bus states caused by:
• Open bus conditions such as a broken cable or a disconnected connector
• Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair
• Idle bus conditions that occur when no driver on the bus is actively driving
The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line.
The receiver outputs a failsafe logic-high state so that the output of the receiver is not indeterminate.
18
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The receiver thresholds are offset in the receiver failsafe protection so that the indeterminate range of the input
does not include a 0 V differential. The receiver output must generate a logic high when the differential input (VID)
is greater than 200 mV to comply with the RS-485 standard. The receiver output must also generate a output a
logic low when VID is less than –200 mV to comply with the RS-485 standard. The receiver parameters that
determine the failsafe performance are VTH+, VTH–, and VHYS. Differential signals less than –200 mV always
cause a low receiver output as shown in the Electrical Characteristics table. Differential signals greater than 200
mV always cause a high receiver output. A differential input signal that is near zero is still greater than the VTH+
threshold which makes the receiver output logic high. The receiver output goes to a low state only when the
differential input decreases by VHYS to less than VTH+.
The internal failsafe biasing feature removes the need for the two external resistors that are typically required
with traditional isolated RS-485 transceivers as shown in Figure 29.
Traditional
transceiver
ISO1500
(R1 and R2 not needed)
VCC2
VCC2
VCC1
VCC1
VCC2
VCC2
R1
A
A
RT
RS-485
Bus
RT
B
RS-485
Bus
B
R2
GND1
GND2
Galvanic
Isolation Barrier
GND1
ISO
Ground
GND2
Galvanic
Isolation Barrier
ISO
Ground
Figure 29. Failsafe Transceiver
8.3.3 Thermal Shutdown
The ISO1500 device has a thermal shutdown circuit to protect against damage when a fault condition occurs. A
driver output short circuit or bus contention condition can cause the driver current to increase significantly which
increases the power dissipation inside the device. An increase in the die temperature is monitored and the device
is disabled when the die temperature becomes 170℃ (typical) which lets the device decrease the temperature.
The device is enabled when the junction temperature becomes 163℃ (typical).
8.3.4 Glitch-Free Power Up and Power Down
Communication on the bus that already exist between a master node and slave node in an RS485 network must
not be disturbed when a new node is swapped in or out of the network. No glitches on the bus occur when the
device is:
• Hot plugged into the network in an unpowered state
• Hot plugged into the network in a powered state and disabled state
• Powered up or powered down in a disabled state when already connected to the bus
The ISO1500 device does not cause any false data toggling on the bus when powered up or powered down in a
disabled state with supply ramp rates from 100 µs to 10 ms.
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8.4 Device Functional Modes
Table 2 shows the driver functional modes.
Table 2. Driver Functional Table (1)
VCC1
PU
(1)
(2)
VCC2
OUTPUTS
INPUT D
DRIVER ENABLE
DE
A
B
H
H
H
L
PU
L
H
L
H
X
L
Hi-Z
Hi-Z
X
Open
Hi-Z
Hi-Z
Open
H
H
L
PD (2)
PU
X
X
Hi-Z
Hi-Z
X
PD
X
X
Hi-Z
Hi-Z
PU = Powered Up; PD = Powered Down; H = High Level; L = Low level; X = Irrelevant, Hi-Z = High impedance state
A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data
input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the
differential output voltage defined by Equation 1 is positive.
VOD = VA – VB
(1)
A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential
output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the
high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin
has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when
the DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes
low when the D pin is left open while the driver enabled.
Table 3 shows the receiver functional modes.
Table 3. Receiver Functional Table (1)
VCC1
VCC2
DIFFERENTIAL INPUT
RECEIVER ENABLE RE
OUTPUT R
VID = VA – VB
PU
(1)
(2)
20
PU
–0.02 V ≤ VID
L
H
–0.2 V < VID < 0.02 V
L
Indeterminate
VID≤ –0.2 V
L
L
X
H
Hi-Z
X
Open
Hi-Z
Open, Short, Idle
L
H
PD (2)
PU
X
X
Hi-Z
PU
PD
X
L
H
PD (2)
PD
X
X
Hi-Z
PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
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The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when
the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+.
VID = VA – VB
(2)
The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the
negative input threshold, VTH–. If the VID voltage is between the VTH+ and VTH– thresholds, the output is
indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when
the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a
failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one
another (short-circuit), or the bus is not actively driven (idle bus).
8.4.1 Device I/O Schematics
D and RE Inputs
VCC1
VCC1
DE Input
VCC1
VCC1
VCC1
VCC1
VCC1
1.5 M
985
985
Input
Input
1.5 M
R Output
VCC1
~20
R
Figure 30. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO1500 device is designed for bidirectional data transfer on multipoint RS-485 networks. The design of
each RS-485 node in the network requires an ISO1500 device and an isolated power supply as shown in
Figure 32.
An RS-485 bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated
with a termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance,
Z0, of the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable
length.
In half-duplex implementation, as shown in Figure 31, the driver and receiver enable pins let any node at any
given moment be configured in either transmit or receive mode which decreases cable requirements.
Integrated isolation barrier allows for communication between
nodes with large ground potential differences
R
A
RT
RT
B
ISO1500
RE
DE
D
B
A
B
R
RE
D
DE
R
RE
ISO1500
A
D
B
ISO1500
ISO1500
R
A
DE
RE
DE
D
Figure 31. Half-Duplex Network Circuit
22
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9.2 Typical Application
Figure 32 shows the application circuit of the ISO1500 device.
GND
4
D2
EN
1
3
SN6505
3.3 V
8
VCC
3
2
7
6
1
5
2
CLK
D1
1
0.1 …F
2
VDD
GPIO1
4
MCU
GPIO2
L1
3.3V
N PSU
PE
GPIO3
DGND
5
6
VCC2
OUT
5
EN
TPS76350
GND
NC
4
10, 16
0.1 …F × 2
GND1
NC 14
R
B
RE
ISO1500
A
DE
13
12
NC 11
D
Optional bus
protection
7 NC
0V
Protective Chasis
Earth
Ground
3
VCC1
IN
8
Digital
Ground
GND1
GND2
Galvanic
Isolation Barrier
9,15
ISO
Ground
Figure 32. Typical Application
9.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1500 device only requires external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface
can be used in a wide range of applications with varying requirements of distance of communication, data rate,
and number of nodes.
9.2.2.1 Data Rate and Bus Length
The RS-485 standard has typical curves similar to those shown in Figure 33. These curves show the inverse
relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower,
the cable length between the nodes can be longer.
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Typical Application (continued)
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10 k
100 k
1M
10 M
100 M
Data Rate (bps)
Figure 33. Cable Length vs Data Rate Characteristics
Applications can increase the cable length at slower data rates compared to what is shown in Figure 33 by
allowing for jitter of 5% or higher. Use Figure 33 as a guideline for cable selection, data rate, cable length and
subsequent jitter budgeting.
9.2.2.2 Stub Length
In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The
stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of
bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length,
or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline.
Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in Equation 3.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver.
c is the speed of light (3 × 108 m/s).
v is the signal velocity of the cable or trace as a factor of c.
(3)
9.2.2.3 Bus Loading
The current supplied by the driver must supply into a load because the output of the driver depends on this
current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a
hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents
a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs.
The ISO1500 device has 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus.
10 Power Supply Recommendations
To make sure device operation is reliable at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the logic and transceiver supply pins (VCC1 and VCC2). The capacitors should be placed as near
to the supply pins as possible. Side 2 requires one VCC2 decoupling capacitor on each VCC2 pin. If only one
primary-side power supply is available in an application, isolated power can be generated for the secondary-side
with the help of a transformer driver such as TI's SN6505B device. For such applications, detailed power supply
design and transformer selection recommendations are available in the SN6505 Low-Noise 1-A Transformer
Drivers for Isolated Power Supplies data sheet.
24
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Figure 35 shows the recommended placement and routing of the device bypass capacitors and optional TVS
diodes. Put the two VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not
use vias to complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal
layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the
stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system
can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this space
free from planes,
traces, pads, and
vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 34. Recommended Layer Stack
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Layout Example (continued)
Minimize
distance to
supply pins
GND1
R
MCU
VCC2
VCC1
RE
x
DE
D
NC
GND1
Isolation Capacitor
0.1 µF C
VCC2
Optional bus
protection
C 0.1 µF
GND2
NC
B
D1
R
VCC1
A
RS-485
NC
VCC2
GND2
C 0.1 µF
GND1
Plane
GND2
Plane
Figure 35. Layout Example
26
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, ISO1500 Isolated RS-485 Half-Duplex Evaluation Module use's guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO1500DBQ
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1500
ISO1500DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1500
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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