Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
ISO7142CC-Q1 4242-VPK Small-Footprint and Low-Power Quad Channel Digital Isolator
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM Classification Level 3A
– Device CDM Classification Level C6
Maximum Signaling Rate: 50 Mbps (with 5-V
Supplies)
Robust Design With Integrated Noise Filter
Low-Power Consumption, Typical ICC per Channel
(With 3.3-V Supplies):
– 1.3 mA at 1 Mbps, 2.5 mA at 25 Mbps
50 kV/µs Transient Immunity, Typical
Long Life with SiO2 Isolation Barrier
Operates From 2.7-V, 3.3-V and 5-V Supply
2.7-V to 5.5-V Level Translation
Small QSOP-16 Package
Safety and Regulatory Approvals
– 2500-VRMS Isolation for 1 Minute per UL 1577
– 4242-VPK Isolation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 End Equipment
Standards
– Planned CQC Certification per GB4943.1-2011
General Purpose Isolation
Industrial Automation
Motor Control
Solar Inverters
3 Description
The ISO7142CC-Q1 device provides galvanic
isolation up to 2500 VRMS for 1 minute per UL 1577
and 4242-VPK per VDE V 0884-10. The
ISO7142CC-Q1 is a quad-channel isolator with two
forward and two reverse-direction channels. This
device is capable of maximum data rate of 50 Mbps
with 5-V supplies and 40 Mbps with 3.3-V or 2.7-V
supplies. The ISO7142CC-Q1 device has integrated
filters on the inputs to support noise-prone
applications.
Each isolation channel has a logic input and output
buffer separated by a silicon dioxide (SiO2) insulation
barrier. Used in conjunction with isolated power
supplies, this device prevents noise currents on a
data bus or other circuits from entering the local
ground and interfering with or damaging sensitive
circuitry. This device has TTL input thresholds and
can operate from 2.7-V, 3.3-V, and 5-V supplies.
Device Information(1)
PART NUMBER
ISO7142CC-Q1
PACKAGE
SSOP (16)
BODY SIZE (NOM)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCO
VCCI
Isolation
Capacitor
INx
OUTx
ENx
GNDI
GNDO
VCCI and GNDI are supply and ground connections respectively for the input channels.
VCCO and GNDO are supply and ground connections respectively for the output channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
4
4
4
4
5
5
5
6
6
6
6
7
7
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics—5-V Supply .....................
Supply Current Characteristics—5-V Supply ............
Electrical Characteristics—3.3-V Supply ..................
Supply Current Characteristics—3.3-V Supply .........
Electrical Characteristics—2.7-V Supply ..................
Supply Current Characteristics—2.7-V Supply .......
Power Dissipation Characteristics ..........................
Switching Characteristics—5-V Supply...................
Switching Characteristics—3.3-V Supply................
Switching Characteristics—2.7-V Supply................
Typical Characteristics ............................................
7
8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2015
*
Initial release.
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
5 Pin Configuration and Functions
DBQ Package
16-Pin SSOP
Top View
VCC1
1
16
VCC2
GND1
2
15
GND2
INA
INB
3
14
OUTA
4
13
OUTB
OUTC
5
12
INC
OUTD
6
11
IND
EN1
7
10
EN2
GND1
8
9
GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN1
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in highimpedance state when EN1 is low.
EN2
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in highimpedance state when EN2 is low.
GND1
GND2
2
8
9
15
—
Ground connection for VCC1
—
Ground connection for VCC2
INA
3
I
Input, channel A
INB
4
I
Input, channel B
INC
12
I
Input, channel C
IND
11
I
Input, channel D
OUTA
14
O
Output, channel A
OUTB
13
O
Output, channel B
OUTC
5
O
Output, channel C
OUTD
6
O
Output, channel D
VCC1
1
—
Power supply, VCC1
VCC2
16
—
Power supply, VCC2
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
3
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage (2)
VCC1, VCC2
Voltage
INx, OUTx, ENx
IO
Output current
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
MIN
MAX
–0.5
6
–0.5
V
VCC + 0.5
–15
–65
UNIT
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
VCC1, VCC2
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
tui
Input pulse duration
1 / tui
Signaling rate
TJ
Junction temperature
TA
Ambient temperature
NOM
MAX
2.7
VCC ≥ 3 V
–4
VCC < 3 V
–2
5.5
UNIT
V
mA
4
mA
2
5.5
V
0
0.8
V
VCC ≥ 4.5 V
20
VCC < 4.5 V
25
VCC ≥ 4.5 V
0
50
VCC < 4.5 V
0
40
–55
ns
25
Mbps
136
°C
125
°C
6.4 Thermal Information
ISO7142CC-Q1
THERMAL METRIC
(1)
DBQ (SSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
104.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
57.8
°C/W
RθJB
Junction-to-board thermal resistance
46.8
°C/W
ψJT
Junction-to-top characterization parameter
18.3
°C/W
ψJB
Junction-to-board characterization parameter
46.4
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
6.5 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage
hysteresis
TEST CONDITIONS
IOH = –4 mA; see Figure 8
IOH = –20 μA; see Figure 8
VCCO
TYP
MAX
– 0.5
0.4
IOL = 20 μA; see Figure 8
0.1
480
(1)
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V; see Figure 11
V
mV
10
at INx or ENx
–10
25
UNIT
V
VCCO – 0.1
IOL = 4 mA; see Figure 8
IIH
(1)
MIN
(1)
70
μA
kV/μs
VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
6.6 Supply Current Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
Disable
EN1 = EN2 = 0 V
DC signal: VI = VCCI or 0 V,
DC to 1 Mbps AC signal: All channels switching with
square wave clock input; CL = 15 pF
Supply current for VCC1 and VCC2
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1, ICC2
0.8
1.6
ICC1 , ICC2
3.3
5
10 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
4.9
7
25 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
7.3
10
50 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
11.1
14.5
UNIT
mA
6.7 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 8
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V; see Figure 11
(1)
IOH = –20 μA; see Figure 8
MIN
VCCO
(1)
TYP
MAX
– 0.5
V
VCCO – 0.1
IOL = 4 mA; see Figure 8
0.4
IOL = 20 μA; see Figure 8
0.1
460
V
mV
10
–10
25
UNIT
50
μA
kV/μs
VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
5
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
6.8 Supply Current Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
Disable
EN1 = EN2 = 0 V
DC signal: VI = VCCI or 0 V
DC to 1 Mbps AC signal: All channels switching with
square-wave clock input; CL = 15 pF
Supply current for VCC1 and VCC2
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1, ICC2
0.5
1
ICC1, ICC2
2.5
4
10 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
3.5
5
25 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
5
7
40 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
6.5
10
UNIT
mA
6.9 Electrical Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –2 mA; see Figure 8
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage
hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V; see Figure 11
(1)
MIN
VCCO
IOH = –20 μA; see Figure 8
(1)
TYP
MAX
– 0.3
V
VCCO – 0.1
IOL = 4 mA; see Figure 8
0.4
IOL = 20 μA; see Figure 8
0.1
360
V
mV
10
–10
25
UNIT
45
μA
kV/μs
VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
6.10 Supply Current Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
Disable
EN1 = EN2 = 0 V
DC signal: VI = VCCI or 0 V
DC to 1 Mbps AC signal: All channels switching with
square-wave clock input; CL = 15 pF
Supply current for VCC1 and VCC2
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1, ICC2
0.4
0.8
ICC1, ICC2
2.2
3.5
10 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
3
4.2
25 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
4.2
5.5
40 Mbps
All channels switching with square
wave clock input; CL = 15 pF
ICC1, ICC2
5.4
7.5
UNIT
mA
6.11 Power Dissipation Characteristics
PARAMETER
PD
6
Device power dissipation
TEST CONDITIONS
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF
Input a 25-MHz, 50% duty cycle square wave
Submit Documentation Feedback
MIN
TYP
MAX
UNIT
170
mW
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
6.12 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH| See Figure 8
tsk(o)
(2)
tsk(pp)
(3)
Channel-to-channel output skew
time
MIN
TYP
15
21
See Figure 8
MAX UNIT
38
ns
3.5
ns
Same-direction channels
1.5
Opposite-direction channels
6.5
Part-to-part skew time
ns
14
ns
tr
Output signal rise time
See Figure 8
2.5
ns
tf
Output signal fall time
See Figure 8
2.1
ns
tPHZ, tPLZ
Disable propagation delay,
high/low-to-high impedance
output
See Figure 9
7
12
ns
tPZH
Enable propagation delay, high
impedance-to-high output
See Figure 9
6
12
ns
tPZL
Enable propagation delay, high
impedance-to-low output
See Figure 9
12
23
us
tfs
Fail-safe output delay time from
input data or power loss
See Figure 10
8
μs
tGR
Input glitch rejection time
9.5
ns
(1)
(2)
(3)
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
6.13 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay time
See Figure 8
(1)
Pulse width distortion |tPHL –
tPLH|
See Figure 8
(2)
Channel-to-channel output
skew time
PWD
tsk(o)
TEST CONDITIONS
tsk(pp)
(3)
MIN
TYP
MAX
16
25
46
ns
3
ns
Same-direction Channels
2
Opposite-direction Channels
6.5
Part-to-part skew time
21
UNIT
ns
ns
tr
Output signal rise time
See Figure 8
3
ns
tf
Output signal fall time
See Figure 8
2.5
ns
tPHZ, tPLZ
Disable propagation delay, from
high/low to high-impedance
See Figure 9
output
9
14
ns
tPZH
Enable propagation delay, from
high-impedance to high output
See Figure 9
9
17
ns
tPZL
Enable propagation delay, from
high-impedance to low output
See Figure 9
12
24
us
tfs
Fail-safe output delay time from
See Figure 10
input data or power loss
tGR
Input glitch rejection time
(1)
(2)
(3)
7
μs
11
ns
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
7
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
6.14 Switching Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay time
See Figure 8
(1)
Pulse width distortion |tPHL –
tPLH|
(2)
Channel-to-channel output
skew time
PWD
tsk(o)
TEST CONDITIONS
tsk(pp)
(3)
MIN
TYP
18
28
MAX UNIT
50
ns
See Figure 8
3
ns
Same-direction Channels
3
ns
8.5
ns
24
ns
Opposite-direction Channels
Part-to-part skew time
tr
Output signal rise time
See Figure 8
3.5
ns
tf
Output signal fall time
See Figure 8
2.8
ns
tPHZ, tPLZ
Disable propagation delay, from
high/low to high-impedance
See Figure 9
output
10
15
ns
tPZH
Enable propagation delay, from
high-impedance to high output
See Figure 9
10
19
ns
tPZL
Enable propagation delay, from
high-impedance to low output
See Figure 9
12
23
us
tfs
Fail-safe output delay time from
input data or power loss
See Figure 10
7
μs
tGR
Input glitch rejection time
12
ns
(1)
(2)
(3)
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
6.15 Typical Characteristics
12
High-Level Output Voltage (V)
10
Supply Current (mA)
6
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
6
4
2
5
4
3
2
1
ICC_3.3V
VCC
at 3.3 V
0
VCC
at 5 V
ICC_5V
0
±1
0
10
20
30
40
Data Rate (Mbps)
TA = 25°C
50
60
±15
CL = 15 pF
±5
0
C002
TA = 25°C
Figure 1. ISO7142CC-Q1 Supply Current for All Channels vs
Data Rate
8
±10
High-Level Output Current (mA)
C001
Submit Documentation Feedback
Figure 2. High-Level Output Voltage
vs High-Level Output Current
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
Typical Characteristics (continued)
Low-Level Output Voltage (V)
VCC3.3V
VCC
at 3.3 V
VCC
at 5 V
VCC_5V
0.8
0.4
0.0
0
5
10
15
C003
Low-Level Output Current (mA)
Power Supply Undervoltage Threshold (V)
1.2
2.50
2.48
2.46
2.44
VCCVCC_rise
Rising
2.42
VCCVCC_fall
Falling
2.40
2.38
2.36
2.34
±55
5
±25
TA = 25°C
30
14
25
12
20
15
tpLHPLH_3.3
at 3.3 V
tpHLPHL_3.3
at 3.3 V
tpLHPLH_5V
at 5 V
tpHLPHL_5V
at 5 V
5
0
±55
±25
5
35
65
95
95
125
C004
10
8
6
4
tGRtgr_3.3v
at 3.3 V
tGRtgr_2.7v
at 2.7 V
tGRtgr_5v
at 5 V
2
0
125
±55
5
±25
C005
Free-Air Temperature (oC)
65
Figure 4. VCC Undervoltage Threshold
vs Free-Air Temperature
Input Glitch Rejection Time (ns)
Propagation Delay Time (ns)
Figure 3. Low-Level Output Voltage
vs Low-Level Output Current
10
35
Free-Air Temperature (oC)
35
65
95
Free-Air Temperature (oC)
Figure 5. Propagation Delay Time
vs Free-Air Temperature
125
C006
Figure 6. Input Glitch Rejection Time
vs Free-Air Temperature
Peak-Peak Output Jitter (ns)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Output jitter at 2.7 V
0.4
Output jitter at 3.3 V
0.2
Output Jitter at 5 V
0.0
0
20
40
Data Rate (Mbps)
60
C007
TA = 25°C
Figure 7. Peak-Peak Output Jitter vs Data Rate
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
9
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
Isolation Barrier
7 Parameter Measurement Information
IN
Input
Generator
Note A
50 W
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
VO
CL
Note B
tPHL
90%
10%
50%
VO
VOH
50%
VOL
tr
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the input-generator signal. It is not
needed in an actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Switching-Characteristics Test Circuit and Voltage Waveforms
V CC
VCC
RL = 1 kΩ ±1%
Isolation Barrier
IN
0V
EN
VCC / 2
VI
OUT
VCC
VO
CL
0V
tPLZ
tPZL
VO
0.5 V
50%
V OL
See Note B
Input
Generator
VCC / 2
VI
50 Ω
See Note A
Isolation Barrier
VCC
IN
3V
OUT
EN
CL
See Note B
VI
VCC / 2
VI
VCC / 2
0V
Input
Generator
VO
tPZH
VOH
RL = 1 kΩ ±1%
VO
50 W
50%
0.5 V
tPHZ
See Note A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
0V
Figure 9. Enable/Disable Propagation Delay-Time Test Circuit and Waveform
10
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
Parameter Measurement Information (continued)
VI
VCC
VCC
Isolation Barrier
IN
VIN = 0 V
2.7 V
VI
0V
OUT
t fs
VO
VO
CL
VOH
50%
See Note A
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Failsafe Delay-Time Test Circuit and Voltage Waveforms
S1
C = 0.1 μ F ±1%
Isolation Barrier
VCCI
IN
GNDI
VCCO
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
Note A
GNDO
VOH or VOL
–
+ VCM –
A.
CL = 15pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
11
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
50 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a singleended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input.
The following capacitor-resistor networks differentiate the signal into transients, which then are converted into
differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an
output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between
signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case
of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency
channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
Isolation Barrier
OSC
LPF
LowtFrequency
Channel
(DC...100 kbps)
PWM
VREF
0
OUT
1 S
IN
DCL
HightFrequency
Channel
(100 kbps...50 Mbps)
VREF
Figure 12. Conceptual Block Diagram of a Digital Capacitive Isolator
12
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
8.3 Feature Description
8.3.1 Insulation and Safety-Related Specifications
PARAMETER
DTI
CI
(1)
TEST CONDITIONS
Distance through the insulation
Minimum internal gap (internal clearance)
Input capacitance
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
MIN
TYP
MAX
0.014
UNIT
mm
2
pF
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIOTM
Maximum transient isolation voltage
VIORM
Maximum working isolation voltage
VPR
Input-to-output test voltage
4242
VPK
566
VPK
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
679
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial discharge < 5 pC
906
Method b1, 100% production test,
VPR = VIORM x 1.875, t = 1 s,
Partial discharge < 5 pC
VPK
1061
L(I01)
Minimum air gap (clearance)
Shortest terminal to terminal distance through air
3.7
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal to terminal distance across the
package surface
3.7
mm
Pollution degree
2
Tracking resistance (comparative
tracking index)
CTI
DIN EN 60112 (VDE 0303-11); IEC 60112
o
RIO
(2)
Isolation resistance, input to output
>10
VIO = 500 V, 100oC ≤ TA ≤ 125oC
>1011
VIO = 500 V, TS = 150 C
(2)
Barrier capacitance, input to output
V
12
VIO = 500 V, TA = 25 C
o
CIO
≥400
VI = 0.4 sin (2πft), f = 1 MHz
Ω
9
>10
2.4
pF
UL 1577
Withstanding Isolation voltage
VTEST = VISO= 2500 VRMS, 60 sec (qualification);
VTEST = 1.2 * VISO= 3000 VRMS, 1 sec (100%
production)
VISO
(1)
(2)
2500
VRMS
Measured from input data pin to ground.
All pins on each side of the barrier tied together creating a two-terminal device.
spacer
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Material Group
Installation classification / Overvoltage
Category for Basic Insulation
SPECIFICATION
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
13
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
8.3.2 Regulatory Information
VDE
UL
Certified according to DIN V
VDE V 0884-10 (VDE V 088410):2006-12 and DIN EN
61010-1 (VDE 0411-1):2011-07
CSA
Certified under UL 1577
Component Recognition
Program
Basic Insulation;
Maximum transient Isolation
IsolatiIsolationvoltage, 4242 VPK Single protection, 2500 VRMS
Maximum working isolation
voltage, 566 VPK
File number: 40016131
(1)
File number: E181974
(1)
CQC
Approved under CSA Component
Acceptance Notice 5A, IEC 60950-1
and IEC 61010-1
Plan to certify according to GB
4943.1-2011
3000 VRMS Isolation rating;
185 VRMS Reinforced Insulation and
370 VRMS Basic Insulation per CSA
60950-1-07+A1+A2 and IEC 60950-1
2nd Ed.+A1+A2;
150 VRMS Reinforced Insulation and
300 VRMS Basic Insulation per CSA
61010-1-12 and IEC 61010-1 3rd Ed.
Basic Insulation, Altitude ≤
5000m, Tropical climate, 250
VRMS maximum working
voltage.
Master contract number: 220991
Certification Planned
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
8.3.3 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output
circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting,
dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary
system failures.
PARAMETER
IS
TS
TEST CONDITIONS
Safety input, output, or supply
current
DBQ-16
MIN
TYP MAX
θJA = 104.5°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
217
θJA = 104.5°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
332
θJA = 104.5°C/W, VI = 2.7 V, TJ = 150°C, TA = 25°C
443
Maximum safety temperature
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the
ambient temperature plus the power times the junction-to-air thermal resistance.
500
VCC1 = VCC2 = 2.7 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Safety Limiting Current (mA)
450
400
350
300
250
200
150
100
50
0
0
50
100
150
Ambient Temperature (qC)
200
D001
Figure 13. Thermal Derating Curve for Safety Limiting Current per VDE
14
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7142CC-Q1.
Table 2. Function Table (1)
VCCI
VCCO
PU
(1)
PU
INPUT
(INx)
OUTPUT ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
X
L
Z
Open
H or open
H
H
PD
PU
X
H or open
PD
PU
X
L
Z
X
PD
X
X
Undetermined
VCCI = Input-side Supply Voltage; VCCO = Output-side Supply Voltage; PU = Powered Up (VCC ≥ 2.7
V); PD = Powered Down (VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L = Low Level; Z = High
Impedance
8.4.1 Device I/O Schematics
Output
Input
VCCI
VCCI
VCCO
VCCI
VCCI
5 mA
500 W
40 W
INx
OUTx
Enable
VCCO
VCCO VCCO
VCCO
5 mA
500 W
ENx
Figure 14. Device I/O Schematics
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
15
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7142CC-Q1 device uses single-ended TTL-logic switching technology. The supply voltage range is from
2.7 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because
of the single-ended design structure the single-ended design structure, digital isolators do not conform to any
specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The
isolator is typically placed between the data controller (that is, µC or UART), and a data converter or a line
transceiver, regardless of the interface type or standard.
9.2 Typical Application
Figure 15 shows the typical isolated CAN interface implementation.
VS
3.3 V
10 F
2
Vcc
D2
1:1.33
3
MBR0520L
1
GND
4
OUT
ISO 3.3V
5
TPS76333-Q1
SN6501-Q1
D1
IN
10 F 0.1 F
3
1
EN
GND
10 F
2
MBR0520L
GND
5
ISO Barrier
0.1 F
0.1 F
0.1 F
0.1 F 29,57
VDDIO
TMS320F28
035PAGQ
CANRXA
CANTXA
26
1
5
25
3
VSS
6,28
VCC1
VCC2
OUTC
INC
INA
OUTA
16
12
14
3
VCC
RS
CANH
4 R SN65HVD231Q
D
CANL
1
Vref
GND
8
10
(optional)
7
6
10
(optional)
5
2
ISO7142CC-Q1
SM712
0.1 F
0.1 F 29,57
6
VDDIO
TMS320F28
035PAGQ
CANRXA
26
4
2,8
CANTXA
OUTD
IND
INB
OUTB
GND1
GND2
11
13
9,15
25
3
VCC
4.7 nF / 2 kV
RS 8 10
4 R SN65HVD231QCANH 7 10
6
CANL
1 D
Vref 5
GND
2
(optional)
(optional)
SM712
VSS
6,28
4.7 nF / 2 kV
Figure 15. Typical Isolated CAN Application Circuit for ISO7142CC-Q1
9.2.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7142CC-Q1 device only requires two external bypass capacitors to operate.
16
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
Typical Application (continued)
9.2.2 Detailed Design Procedure
Figure 16 shows the hookup of a typical ISO7142CC-Q1 circuit. The only external components are two bypass
capacitors.
VCC2
VCC1
ISO7142CC
0.1 µF
VCC1
0.1 µF
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
OUTD
6
11
IND
7
10
GND1
GND2
EN2
EN1
9
8
GND2
GND1
Figure 16. Typical ISO7142CC-Q1 Circuit Hook-up
9.2.3 Application Curves
Figure 17. Typical Eye Diagram at 40 Mbps,
PRBS 216 - 1, 2.7-V Operation
Figure 18. Typical Eye Diagram at 40 Mbps,
PRBS 216 - 1, 3.3-V Operation
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
17
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
Typical Application (continued)
Figure 19. Typical Eye Diagram at 50 Mbps,
PRBS 216 - 1, 5-V Operation
10 Power Supply Recommendations
To help ensure reliable operation supply voltages, a 0.1-µF bypass capacitor is recommended at the input and
output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If
only a single primary-side power supply is available in an application, isolated power can be generated for the
secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501Q1 datasheet (SLLSEF3).
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide, SLLA284.
18
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
ISO7142CC-Q1
www.ti.com
SLLSER5 – DECEMBER 2015
Layout Guidelines (continued)
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL 94 V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 20. Recommended Layer Stack
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
19
ISO7142CC-Q1
SLLSER5 – DECEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Digital Isolator Design Guide, SLLA284
• Isolation Glossary, SLLA353
• ISO71xx EVM User’s Guide, SLLU179
• SN6501-Q1 Transformer Driver for Isolated Power Supplies, SLLSEF3
• SN65HVD231Q-Q1 3.3-V CAN Transceivers, SGLS398
• TMS320F28035 Piccolo™ Microcontrollers, SPRS584
• TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators, SGLS247
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7142CC-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7142CCQDBQQ1
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7142Q
ISO7142CCQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7142Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
