ISO7421EQDWRQ1

ISO7421E-Q1 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 Low-power dual digital isolators 1 Features 3 Description • • The ISO7421E-Q1 provides double galvanic isolation of up to 2.5 KVrms for 1 minute per UL. This digital isolator has two isolation channels in a bi-directional configuration. Each isolation channel has a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. 1 • • • • • Qualified for automotive applications AEC-Q100 Qualified with the following results: – Device temperature grade 1: -40°C to +125°C ambient operating temperature range – Device HBM ESD classification level H3A – Device CDM ESD classification level C4 Propagation delay less than 20 ns Low power consumption Safety and regulatory approvals – 4242 VPK Isolation per VDE, 2.5 kVrms isolation per UL 1577, CSA approved per IEC 60950-1 and IEC 61010-1 End Equipment Standards 50 kV/µs Transient immunity typical Operates from 3.3 V or 5 V Supply and logic levels 2 Applications • Opto-coupler replacement in: – Servo control interface – Motor control – Power supply – Battery packs The devices have TTL input thresholds and require two supply voltages, 3.3 V or 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply. Note: The ISO7421E-Q1 is specified for signaling rates up to 50 Mbps. Due to their fast response time, under most cases, these devices will also transmit data with much shorter pulse widths. Designers should add external filtering to remove spurious signals with input pulse duration < 20 ns if desired. Simplified Schematic VCCI VCCO Isolation Capacitor INx OUTx GNDI GNDO (1) VCCI and GNDI are supply and ground connections respectively for the input channels. (2) VCCO and GNDO are supply and ground connections respectively for the output channels. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7421E-Q1 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 www.ti.com 4 Pin Configuration and Functions 16-Pin SSOP Top View ISO7421E-Q1 GND1 NC VCC1 OUTA INB NC GND1 NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND2 NC VCC2 INA OUTB NC NC GND2 NC = No Internal Connection Table 1. Pin Functions PIN NAME I/O ISO7421E-Q1 DESCRIPTION INA 13 I Input, channel A INB 5 – Input, channel B GND1 1, 7 – Ground connection for VCC1 GND2 9, 16 O Ground connection for VCC2 OUTA 4 O Output, channel A OUTB 12 – Output, channel B VCC1 14 – Power supply, VCC1 VCC2 14 - Power supply, VCC2 NC 2, 6, 8, 10, 11, 15 No Connect Pin 4.1 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 4.1 Device Function Table INPUT SIDE VCC (VCCI) (1) OUTPUT SIDE VCC (VCCO) (1) PU PU PD PU (1) INPUT (IN) (1) OUTPUT (OUT) (1) H H L L Open H X H PU = Powered Up (VCC ≥ 3.15V); PD = Powered Down (VCC ≤ 2.4V); X = Irrelevant; H = High Level; L = Low Level 4.2 Available Options PRODUCT RATED TA MARKED AS ORDERING NUMBER ISO7421E-Q1 –40°C to 125°C ISO7421EQ ISO7421EQDWRQ1 Absolute Maximum Ratings (1) 5 VALUE MIN UNIT MAX VCC Supply voltage (2), VCC1, VCC2 –0.5 6 V VI Voltage at IN, OUT –0.5 VCC + 0.5 (3) V IO Output Current ±15 mA 4 kV 1 kV 150 °C Human Body Model AEC-Q100 Classification Level H3A Charged Device Model AEC-Q100 Classification Level C4 ESD Electrostatic discharge TJ Maximum junction temperature (1) (2) (3) All pins (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Maximum voltage must not exceed 6 V. A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output. 6 Thermal Information ISO7421E-Q1 THERMAL METRIC (1) DW (16 Pins) θJA Junction-to-ambient thermal resistance 79.9 θJCtop Junction-to-case (top) thermal resistance 44.6 θJB Junction-to-board thermal resistance 51.2 ψJT Junction-to-top characterization parameter 18.0 ψJB Junction-to-board characterization parameter 42.2 θJCbot Junction-to-case (bottom) thermal resistance n/a PD Device power dissipation, Vcc1 = Vcc2 = 5.25 V, TJ = 150°C, CL = 15 pF, Input a 0.5 MHz 50% duty cycle square wave 42 (1) UNITS °C/W mW For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). spacer Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 3 ISO7421E-Q1 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 7 www.ti.com Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC1, VCC2 MIN TYP MAX UNIT Supply voltage - 3.3V Operation 3.15 3.3 3.45 V Supply voltage - 5V Operation 4.75 5 5.25 IOH High-level output current IOL Low-level output current VIH High-level output voltage 2 VCC V VIL Low-level output voltage 0 0.8 V TA Ambient Temperature -40 125 °C TJ (1) Junction temperature –40 136 °C 1/tui Signaling rate 0 50 Mbps tui Input pulse duration 1 (1) 4 –4 mA 4 mA µs To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table and the Icc Equations section of this data sheet Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 ISO7421E-Q1 www.ti.com 8 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 Electrical Characteristics VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP IOH = –4 mA; See Figure 1 VCC –0.8 4.6 IOH = –20 µA; See Figure 1 VCC –0.1 5 MAX UNIT V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 V 400 mV 10 INx at 0 V or VCC µA –10 VI = VCC or 0 V; See Figure 3 25 µA 50 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement) ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 2.3 3.6 AC Input: CL = 15 pF 2.3 3.6 2.9 4.5 2.9 4.5 4.3 6 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 9 4.3 6 6 9.1 6 9.1 TYP MAX mA Switching Characteristics VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) See Figure 1 See Figure 1 See Figure 2 MIN UNIT 9 14 ns 0.3 3.7 ns 4.9 ns 3.6 ns 1 ns 1 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 5 ISO7421E-Q1 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 10 www.ti.com Electrical Characteristics VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP 5-V side VCC –0.8 4.6 3.3-V side VCC –0.4 3 IOH = –20 µA; See Figure 1 VCC –0.1 VCC IOH = –4 mA; See Figure 1 MAX V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 400 –10 VI = VCC or 0 V; See Figure 3 25 V mV 10 INx at 0 V or VCC UNIT µA µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement) ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 2.3 3.6 AC Input: CL = 15 pF 1.8 2.8 2.9 4.5 2.2 3.2 4.3 6 2.8 4.1 6 9.1 3.8 5.8 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 11 mA Switching Characteristics VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 6 See Figure 1 See Figure 1 See Figure 2 MIN TYP MAX 10 17 UNIT ns 0.5 5.6 ns 6.3 ns 4 ns 2 ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 ISO7421E-Q1 www.ti.com 12 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 Electrical Characteristics VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP 5-V side VCC –0.8 4.6 3.3-V side VCC –0.4 3 IOH = –20 µA; See Figure 1 VCC –0.1 VCC IOH = –4 mA; See Figure 1 MAX UNIT V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 V 400 mV 10 INx at 0 V or VCC µA –10 VI = VCC or 0 V; See Figure 3 25 µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement) ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 1.8 2.8 AC Input: CL = 15 pF 2.3 3.6 2.2 3.2 2.9 4.5 2.8 4.1 4.3 6 3.8 5.8 6 9.1 TYP MAX 10 17 ns 0.5 4 ns 8.5 ns 4 ns 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 13 mA Switching Characteristics VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) See Figure 1 See Figure 1 See Figure 2 MIN UNIT 2 ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 7 ISO7421E-Q1 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 14 www.ti.com Electrical Characteristics VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP IOH = –4 mA; See Figure 1 VCC –0.4 3 IOH = –20 µA; See Figure 1 VCC –0.1 3.3 MAX UNIT V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 400 V mV µA INx at 0 V or VCC –10 VI = VCC or 0 V; See Figure 3 25 µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement) ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 1.8 2.8 AC Input: CL = 15 pF 1.8 2.8 2.2 3.2 2.2 3.2 2.8 4.1 2.8 4.1 3.8 5.8 3.8 5.8 TYP MAX 12 20 ns 1 5 ns 6.8 ns 5.5 ns 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 15 mA Switching Characteristics VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 8 See Figure 1 See Figure 1 See Figure 2 MIN 2 UNIT ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 Isolation Barrier 16 Parameter Measurement Information IN Input Generator 50 W VI (1) VCCI VI OUT 1.4 V 1.4 V 0V VO CL tPLH (2) tPHL 90% 10% 50% VO 50% VOH VOL tr tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3ns, tf ≤ 3ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI VCCI VCCI A. Isolation Barrier IN = 0 V VI 2.7 V 0V OUT tfs VO VOH CL 50% VO (1) Fail-Safe HIGH VOL CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms S1 IN C = 0.1 μ F ±1% Isolation Barrier VCCI VCCO C = 0.1 μ F ±1% Pass-fail criteria – output must remain stable. OUT + CL (1) GNDI GNDO VOH or VOL – + VCM – A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: ISO7421E-Q1 9 ISO7421E-Q1 SLLSEA5C – MARCH 2012 – REVISED MARCH 2019 www.ti.com 17 Device Information 17.1 Package Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER L(I01) TEST CONDITIONS MIN TYP MAX UNIT Minimum air gap (Clearance) Shortest terminal to terminal distance through air 7.6 mm L(I02) Minimum external tracking (Creepage) Shortest terminal to terminal distance across the package surface 7.6 mm CTI Tracking resistance (Comparative Tracking DIN EN 60112 (VDE 0303-11) Index) ≥400 V Minimum internal gap (Internal Clearance) Distance through the insulation 0.014 mm RIO Isolation resistance, input to output (1) Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device CIO Barrier capacitance input to output (1) CI Input capacitance to ground (2) (1) (2) >1012 Ω VIO = 0.4 sin(2πft), f = 1 MHz 2 pF VI = VCC/2 + 0.4 sin(2πft), f = 1 MHz, VCC = 5 V 2 pF All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. empty para for space above the NOTE NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 17.2 IEC 60664-1 Ratings Table PARAMETER Basic Isolation Group Installation Classification 10 TEST CONDITIONS Material Group SPECIFICATION II Rated mains voltages