ISO7421MDREP

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software ISO7421-EP SLLSEN3 – DECEMBER 2015 ISO7421-EP Low-Power Dual Digital Isolators 1 Features 3 Description • • The ISO7421-EP device provides galvanic isolation up to 2500 VRMS for 1 minute per UL. The ISO7421EP device has two isolated channels. Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, the device prevents noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. 1 • • • • • • • • • Highest Signaling Rate: 1 Mbps Low Power Consumption, Typical ICC per Channel (3.3-V Operation): 1.5 mA Low Propagation Delay – 9 ns Typical Low Skew – 300 ps Typical Wide TJ Range: –55°C to 136°C 50-kV/μs Transient Immunity, Typical Over 25-Year Isolation Integrity at Rated Voltage Operates From 3.3-V and 5-V Supply and Logic Levels 3.3-V and 5-V Level Translation Narrow Body SOIC-8 Package Safety and Regulatory Approvals: – 4242 VPK Isolation per DIN V VDE V 0884-10 and DIN EN 61010-1 – 2500 VRMS Isolation for 1 minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 Standards – CQC Certification per GB4943.1-2011 2 Applications • Optocoupler Replacement in: – Industrial Fieldbus – Profibus – Modbus – DeviceNet™ Data Buses – Servo Control Interface – Motor Control – Power Supplies – Battery Packs This device have TTL input thresholds and require two supply voltages, 3.3 or 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply. The ISO7421-EP device is specified for signaling rates up to 1 Mbps. Due to its fast response time, under most cases, this device will also transmit data with much shorter pulse widths. Designers should add external filtering to remove spurious signals with input pulse duration 109 Ω Pollution degree 2 UL 1577 VISO (1) VTEST = VISO = 2500 VRMS, t = 60 s (qualification) VTEST = 1.2 x VISO = 3000 VRMS, t = 1 s (100% production) Isolation voltage per UL 2500 VRMS Climatic Classification 40/125/21 Table 1. IEC 60664-1 Ratings Table PARAMETER TEST CONDITIONS SPECIFICATION Material group II Installation classification Rated mains voltage ≤ 150 VRMS I–IV Rated mains voltage ≤ 300 VRMS I–III 8.3.2 Package Characteristics Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4 mm CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112 >400 DTI Distance through the insulation Minimum internal gap (internal clearance) 0.014 V mm VIO = 500 V, TA = 25°C 12 >10 Ω VIO = 500 V, 100°C ≤ TA ≤ max >1011 Ω RIO Isolation resistance, input to output (1) CIO Barrier capacitance, input to output (1) VIO = 0.4 sin (2πft), f = 1 MHz 1 pF CI Input capacitance (2) VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 1 pF (1) (2) All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP 11 ISO7421-EP SLLSEN3 – DECEMBER 2015 www.ti.com SPACER NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 8.3.3 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum safety temperature MIN TYP MAX RθJA = 212°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C 112 RθJA = 212°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C 171 150 UNIT mA °C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Safety Limiting Current − mA 180 VCC1, VCC2 at 3.45 V 160 140 120 100 VCC1, VCC2 at 5.25 V 80 60 40 20 0 0 50 100 150 200 Case Temperature − °C G002 Figure 10. RθJC Thermal Derating Curve per VDE 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP ISO7421-EP www.ti.com SLLSEN3 – DECEMBER 2015 8.3.4 Regulatory Information VDE CSA UL Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1): 2011-07 Approved under CSA Component Acceptance Notice #5A Basic Insulation Maximum Transient Overvoltage, 4242 VPK Maximum Working Voltage, 566 VPK Certificate number: 40016131 (1) CQC Recognized under UL1577 Component Recognition Program (1) Certified according to GB4943.1-2011 Basic insulation per CSA 60950-107 and IEC 60950-1 (2nd Ed), 390 VRMS maximum working voltage Single Protection, 2500 VRMS Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Master contract number: 220991 File number: E181974 Certificate number: CQC14001109540 Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. 8.4 Device Functional Modes Table 2 shows the device functions. Table 2. Function Table (1) VCCI VCCO PU (1) (2) PU INPUT INA, INB OUTPUT OUTA, OUTB H H L L Open H (2) PD PU X H (2) X PD X Undetermined VCCI = Input-side power supply; VCCO = Output-side power supply; PU = Powered up (VCC ≥ 3.15 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level In fail-safe condition, output defaults to high level. Input VCC1 VCC1 VCC1 Output VCC2 1 MW 8W 500 W IN OUT 13 W Figure 11. Device I/O Schematics Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP 13 ISO7421-EP SLLSEN3 – DECEMBER 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ISO7421-EP device uses a single-ended TTL-logic switching technology. Its supply voltage range is from 3.15 V to 5.25 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 Typical Application ISO7421-EP can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter, transformer driver, and voltage regulator to create an isolated 4-20 mA current loop. VS 3.3 V 0.1 F 2 VCC D2 3 1:1.33 MBR0520L 1 SN6501 10 F GND D1 0.1 F IN OUT 3.3VISO 5 10 F TPS76333 3 1 EN GND 2 10 F MBR0520L 4, 5 0.1 F ISO-BARRIER 0.1 F 20 LOOP+ 0.1 F 0.1 F 15 0.1 F 10 1 5 6 VCC1 DVCC XOUT XIN MSP430 G2132 8 8 2 VCC2 2 OUTA P3.0 11 12 P3.1 INA ISO7421 3 INB GND1 DVSS 4 4 OUTB GND2 5 7 5 6 4 3 VA VD LOW BASE ERRLVL 16 0.1 F 22 DBACK DIN C1 14 3 × 22 nF 1 F DAC161P997 C3 COMA C2 13 12 1 OUT COMD 9 LOOP± 2 Figure 12. Isolated 4- to 20-mA Current Loop 9.2.1 Design Requirements For applications that require isolation in place of using x-fmr to provide isolation, ISO7421-EP meets the system needs with small size. Unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the ISO7421-EP device only requires two external bypass capacitors to operate. 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP ISO7421-EP www.ti.com SLLSEN3 – DECEMBER 2015 Typical Application (continued) 9.2.2 Detailed Design Procedure ISO7421 digital isolator containing two channels has logic input and output buffer isolated by silicon dioxide (SiO2) isolation barrier. When using ISO7421 in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. ISO7421 are specified for signaling rate up to 1Mbps. These devices also transmit data with much shorter pulse widths, in most cases, because of their fast response time. Designer must add external filtering to remove spurious signals with input pulse duration < 20 ns. VCC1 8 1 VCC2 0.1 µF 0.1 µF OUTA 2 7 INA INB 3 6 OUTB GND1 4 5 GND2 Figure 13. Typical ISO7421-EP Circuit Hookup 9.2.3 Application Curve Life Expectancy – Years 100 VIORM at 566 V 28 Years 10 0 120 250 500 750 880 1000 VIORM – Working Voltage – V G001 Figure 14. Life Expectancy vs Working Voltage Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP 15 ISO7421-EP SLLSEN3 – DECEMBER 2015 www.ti.com 10 Power Supply Recommendations Install high quality X7R capacitors typically 0.1 µF close to the device. To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 datasheet (SLLSEA0). 11 Layout 11.1 Layout Guidelines There are several signals that conduct fast charging current or voltages that can interact with stray inductance or parasitic capacitors to generate noise. Thus to eliminate these problems Vin ins of ISO7421 should be bypass to gnd with low esr ceramic bypass capacitor with X7R dielectric. A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 15). Layer stacking should be in the following order (top-tobottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see Application Note Digital Isolator Design Guide, SLLA284. 11.1.1 PCB Material For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics. 11.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces , pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 15. Recommended Layer Stack 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP ISO7421-EP www.ti.com SLLSEN3 – DECEMBER 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • SN6501 Transformer Driver for Isolated Power Supplies, SLLSEA0 • Isolation Glossary, SLLA353 • Digital Isolator Design Guide, SLLA284 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks DeviceNet, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7421-EP 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ISO7421MDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 7421EP V62/16605-01XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 7421EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of