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LM25066
SNVS654J – FEBRUARY 2010 – REVISED DECEMBER 2015
LM25066 System Power Management and Protection IC With PMBus™
1 Features
2 Applications
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Input Voltage Range: 2.9 V to 17 V
I2C/SMBus Interface and PMBus™ Compliant
Command Structure
Programmable 25-mV or 46-mV Current Limit
Threshold
Configurable Circuit Breaker Protection for Hard
Shorts
Configurable Undervoltage and Overvoltage
Lockouts With Hysteresis
Remote Temperature Sensing With
Programmable Warning and Shutdown
Thresholds
Detection and Notification of Damaged MOSFET
Condition
Real-Time Monitoring of VIN, VOUT, IIN, PIN, VAUX
With 12-bit Resolution and 1-kHz Sampling Rate
Current Measurement Accuracy: ±2.4% Over
Temperature
Power Measurement Accuracy: ±3% Over
Temperature
True Input Power Measurement Using
Simultaneous Sampling of VIN and IIN Accurately
Averages Dynamic Power Readings
Averaging of VIN, IIN, PIN, and VOUT Over
Programmable Interval Ranging from 0.001 to
4 Seconds
Programmable WARN and FAULT Thresholds
With SMBA Notification
Blackbox Capture of Telemetry Measurements
and Device Status Triggered by WARN or FAULT
Condition
Full-Featured Application Design and
Development GUI
24-Lead WQFN Package
Server Backplane Systems
Basestation Power Distribution Systems
Solid-State Circuit Breaker
3 Description
The LM25066 combines a high-performance hotswap controller with a PMBus™ compliant SMBus/I2C
interface to accurately measure, protect and control
the electrical operating conditions of computing and
storage blades connected to a backplane power bus.
The LM25066 continuously supplies real-time power,
voltage, current, temperature and fault data to the
system management host via the SMBus interface.
The LM25066 control block includes a unique hotswap architecture that provides current and power
limiting to protect sensitive circuitry during insertion of
boards into a live system backplane, or any other hot
power source. A fast acting circuit breaker prevents
damage in the event of a short circuit on the output.
The input undervoltage and overvoltage levels and
hysteresis are configurable, as well as the insertion
delay time and fault detection time. A temperature
monitoring block on the LM25066 interfaces with a
low-cost external diode for monitoring the
temperature of the external MOSFET or other
thermally sensitive components. The POWER GOOD
output provides a fast indicator when the input and/or
output voltages are outside their programmed range.
LM25066 current measurement accuracy is ±2.4%
over temperature.
Device Information(1)
PART NUMBER
PACKAGE
LN25066
WQFN (24)
BODY SIZE (NOM)
5.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Only required when FET
Vgs rating is < +/-20V
Q2
VIN
VOUT
RSNS
Q1
CIN
D3
Z1
GATE
SENSE
R1
VIN
COUT
Only required when
using dv/dt start-up
RFB1
OUT DIODE
FB
R3
D2
D1
VDD
RFB2
UVLO/EN
10kŸ
1kŸ
OVLO
R2
PGD
LM25066/I
R4
Cdv/dt
ADR2
ADR1
ADR0
GND
Q3
CL
SMBus
Interface
SMBA
SDA
SCL
VDD
1 PF
RETRY
VAUX
VREF
1 PF
PWR
Auxillary ADC Input
(0V " 1.16V)
TIMER
RPWR
CTIMER
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25066
SNVS654J – FEBRUARY 2010 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ............................................... 8
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 18
8.5 Register Maps ........................................................ 22
9
Application and Implementation ........................ 41
9.1 Application Information............................................ 41
9.2 Typical Application ................................................. 41
10 Power Supply Recommendations ..................... 55
11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
11.2 Layout Example .................................................... 56
12 Device and Documentation Support ................. 57
12.1
12.2
12.3
12.4
12.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
57
57
57
57
57
13 Mechanical, Packaging, and Orderable
Information ........................................................... 57
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (February 2013) to Revision J
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information................................................................................................................................... 1
Changes from Revision H (February 2013) to Revision I
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 40
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SNVS654J – FEBRUARY 2010 – REVISED DECEMBER 2015
5 Description (continued)
The LM25066 monitoring block computes both the real-time and average values of subsystem operating
parameters (VIN, IIN, PIN, VOUT) as well as the peak power. Accurate power averaging is accomplished by
averaging the product of the input voltage and current. A black box (Telemetry/Fault Snapshot) function captures
and stores telemetry data and device status in the event of a warning or a fault.
6 Pin Configuration and Functions
GATE
SENSE
VIN
UVLO/EN
OVLO
GND
SDA
NHZ Package
24-Pin WQFN
Top View
OUT
SCL
SMBA
PGD
Exposed
Pad
VREF
FB
CB
CL
RETRY
VDD
VAUX
ADR0
TIMER
ADR1
DIODE
ADR2
24
PWR
5x4 mm WQFN 24L
1
NOTE: Solder exposed pad to ground.
Pin Functions
PIN
TYPE
DESCRIPTION
ADR2
SMBUS address line 2
3 - state address line. Should be left floating, or else direct connection (either trace or 0-Ω
resistor) to VDD or GND.
2
ADR1
SMBUS address line 1
3 - state address line. Should be left floating, or else direct connection (either trace or 0-Ω
resistor) to VDD or GND.
3
ADR0
SMBUS address line 0
3 - state address line. Should be left floating, or else direct connection (either trace or 0-Ω
resistor) to VDD or GND.
4
VDD
Internal sub-regulator
output
Internally sub-regulated 4.5 V bias supply. Connect a 1 µF capacitor on this pin to ground
for bypassing.
5
CL
Current limit range
Connect this pin to GND to set the nominal overcurrent threshold at 25 mV. Connecting
CL to VDD will set the overcurrent threshold to be 46 mV.
Circuit breaker range
This pin sets the circuit breaker protection point in relation to the overcurrent trip point.
When connected to GND, this pin will set the circuit breaker point to be 1.8 times the
overcurrent threshold. Connecting this pin to VDD sets the circuit breaker trip point to be
3.6 times the overcurrent threshold.
NO.
NAME
1
6
CB
7
FB
8
RETRY
An external resistor divider from OUT sets the output voltage at which the PGD pin
POWER GOOD feedback switches. The threshold at the pin is 1.167 V. An internal 24 µA current source provides
hysteresis.
Fault retry input
This pin configures the power up fault retry behavior. When this pin is grounded, the
device will continually try to engage power during a fault. If the pin is connected to VDD,
the device will latch off during a fault.
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
9
TIMER
Timing capacitor
10
PWR
Power limit set
11
PGD
POWER GOOD indicator
12
OUT
Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine the
MOSFET VDS voltage for power limiting, and to monitor the output voltage.
13
GATE
Gate drive output
Connect to the external MOSFET's gate.
14
SENSE
Current sense input
The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the
voltage across RS reaches overcurrent threshold, the load current is limited and the fault
timer activates.
15
VIN
Positive supply input
A small ceramic bypass capacitor close to this pin is recommended to suppress transients
which occur when the load current is switched off.
16
UVLO/EN
Undervoltage lockout
An external resistor divider from the system input voltage sets the undervoltage turnon
threshold. An internal 23-µA current source provides hysteresis. The enable threshold at
the pin is 1.16 V. This pin can also be used for remote shutdown control.
17
OVLO
Overvoltage lockout
An external resistor divider from the system input voltage sets the overvoltage turnoff
threshold. An internal 23-µA current source provides hysteresis. The disable threshold at
the pin is 1.16 V.
18
GND
Circuit ground
19
SDA
SMBus data pin
Data pin for SMBus. Open-drain output, requires external pullup resistor to Vdd or other
voltage source.
20
SCL
SMBus clock
Clock pin for SMBus. Open-drain output, requires external pullup resistor to Vdd or other
voltage source.
21
SMBA
SMBus alert line
Alert pin for SMBus; active low. Open-drain output, requires external pullup resistor to Vdd
or other voltage source.
22
VREF
Internal reference
Internally generated precision 2.73-V reference used for analog to digital conversion.
Connect a 1-µF capacitor on this pin to ground for bypassing.
23
DIODE
External diode
Connect this to a diode-configured NPN transistor for temperature monitoring. Connect to
ground if unused.
An external capacitor connected to this pin sets the insertion time delay, fault timeout
period and restart timing.
An external resistor connected to this pin, in conjunction with the current sense resistor
(RS), sets the maximum power dissipation allowed in the external series pass MOSFET.
An open drain output. This output is high when the voltage at the FB pin is above 1.167 V
and the input supply is within its undervoltage and overvoltage thresholds. Connect via a
pullup resistor to the output rail (external MOSFET source) or any other voltage to be
monitored.
–
24
VAUX
Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full scale input of 1.16 V.
–
Exposed
Pad
Exposed pad of WQFN
package
No internal electrical connections. Solder to the ground plane to reduce thermal
resistance.
4
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SNVS654J – FEBRUARY 2010 – REVISED DECEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
24
V
–0.3
20
V
–1
20
V
SCL, SDA, SMBA, CL, CB, ADR0, ADR1, ADR2, VDD, VAUX,
DIODE, RETRY to GND
–0.3
6
V
VIN to SENSE
–0.3
VIN, SENSE to GND (2)
GATE, FB, UVLO/EN, OVLO, PGD to GND
(2)
OUT to GND
Input voltage
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
0.3
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The GATE pin voltage is typically 7.5 V above VIN when the LM25066 is enabled. Therefore, the Absolute Maximum Rating of 24 V for
VIN and SENSE apply only when the LM25066 is disabled or for a momentary surge to that voltage since the Absolute Maximum Rating
for the GATE pin is 20 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN, SENSE, OUT voltage
2.9
17
V
VDD
2.9
5.5
V
Junction temperature, TJ
–40
125
°C
7.4 Thermal Information
LM25066
THERMAL METRIC
(1)
NHZ (WQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
34.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.9
°C/W
RθJB
Junction-to-board thermal resistance
13.4
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
13.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to 85°C unless otherwise stated. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12 V (see (1) and (2)).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (VIN PIN)
IIN-EN
Input current, enabled
UVLO = 2 V and OVLO = 0.7 V
5.8
8
POR
Power on reset threshold at VIN
VIN increasing
2.6
2.8
PORHYS
POREN hysteresis
VIN decreasing
150
mA
V
mV
VDD REGULATOR (VDD PIN)
VDD
VDDILIM
IVDD = 5 mA, VIN = 12 V
4.3
4.5
4.7
IVDD = 5 mA, VIN = 4.5 V
3.5
3.9
4.3
25
45
1.147
1.16
1.173
V
18
23
28
µA
VDD current limit
V
V
mA
UVLO/EN, OVLO PINS
UVLOTH
UVLO threshold
VUVLO Falling
UVLOHYS
UVLO hysteresis current
UVLO = 1 V
Delay to GATE high
8
Delay to GATE low
20
UVLODEL
UVLO delay
µs
UVLOBIAS
UVLO bias current
UVLO = 3 V
OVLOTH
OVLO threshold
VOVLO rising
1.141
1.16
1.185
V
OVLOHYS
OVLO hysteresis current
OVLO = 1 V
–28
–23
–18
µA
OVLODEL
OVLO delay
OVLOBIAS
OVLO bias current
1
Delay to GATE high
19
Delay to GATE low
9
OVLO = 1 V
µA
µs
1
µA
60
mV
1
µA
POWER GOOD (PGD PIN)
PGDVOL
Output low voltage
ISINK = 2 mA
PGDIOH
Off leakage current
VPGD = 17 V
PGDDELAY
Power Good delay
VFB to VPG
FBTH
FB threshold
VFB rising
FBHYS
FB hysteresis current
FBLEAK
Off leakage current
25
115
ns
FB PIN
1.141
1.167
1.19
V
–31
–24
–18
µA
1
µA
15
mV
VFB = 1 V
POWER LIMIT (PWR PIN)
PWRLIM
Power limit sense voltage (VIN-SENSE)
SENSE-OUT = 12 V, RPWR = 25 kΩ
IPWR
PWR pin current
VPWR = 2.5 V
9
12.5
–10
µA
RSAT(PWR)
PWR pin impedance when disabled
UVLO = 0.7 V
180
Ω
GATE CONTROL (GATE PIN)
Source current
Normal operation
–28
–22
–16
µA
Fault sink current
UVLO = 1 V
1.5
2
2.5
mA
POR circuit breaker sink current
VIN - SENSE = 150 mV or VIN < RPOR,
VGATE = 5 V
105
190
275
mA
Gate output voltage in normal operation
GATE voltage with respect to ground
17
18.8
20.3
V
IOUT-EN
OUT bias current, enabled
OUT = VIN, normal operation
IOUT-DIS
OUT bias current, disabled (3)
Disabled, OUT = 0 V, SENSE = VIN
IGATE
VGATE
OUT PIN
(1)
(2)
(3)
6
16
µA
–12
µA
Current out of a pin is indicated as a negative value.
All limits are specified. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and
cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process
control.
OUT bias current (disabled) due to leakage current through an internal 0.9 MΩ resistance from SENSE to VOUT.
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to 85°C unless otherwise stated. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12 V (see (1) and (2)).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
22.5
25
27
23
25
27
42.3
46
49.7
UNIT
CURRENT LIMIT
CL = GND
VCL
Threshold voltage
CL = GND, TJ = 10°C to 85°C
CL = VDD
ISENSE
SENSE input current
Enabled, SENSE = OUT
33
Disabled, OUT = 0 V
46
Enabled, OUT = 0 V
45
mV
µA
CIRCUIT BREAKER
VCB
VCB
Threshold voltage × 1.8
VIN - SENSE, CL = GND, CB = GND
35
45
55
mV
CB:CL ratio
CB = GND
1.6
1.8
2
Threshold voltage × 3.6
VIN - SENSE, CL = GND, CB = VDD
70
90
110
CB:CL ratio
CB = VDD
3.1
3.6
4
1.54
1.7
1.85
V
0.85
1.0
1.07
V
mV
TIMER (TIMER PIN)
VTMRH
Upper threshold
Restart cycles
VTMRL
Lower threshold
End of 8th cycle
0.3
Re-enable threshold
ITIMER
0.3
V
Insertion time current
–3
–5.5
–8
µA
Sink current, end of insertion time
1.4
1.9
2.4
mA
–120
–90
–60
µA
Fault detection current
TIMER pin = 2 V
Fault sink current
DCFAULT
V
2.8
Fault restart duty cycle
µA
0.67%
INTERNAL REFERENCE
VREF
Reference voltage
2.703
2.73
2.757
V
ADC AND MUX
Resolution
INL
Integral non-linearity
12
Bits
±1
LSB
CL = GND
30.2
mV
CL = VDD
60.4
mV
CL = GND
7.32
µV
CL = VDD
14.64
µV
1.16
V
283.2
µV
ADC only
TELEMETRY ACCURACY
IINFSR
Current input full scale range
IINLSB
Current input LSB
VAUXFSR
VAUX input full scale range
VAUXLSB
VAUX input LSB
VINFSR
Input voltage full scale range
18.7
V
VINLSB
Input voltage LSB
4.54
mV
IINACC
Input current accuracy
VACC
VAUX, VIN, VOUT accuracy
VIN – SENSE = 25 mV, CL = GND
–2.7
2.4
VIN – SENSE = 25 mV, CL = GND
TJ = 10°C to 85°C
–2.4%
2.4%
VIN, VOUT = 12 V
VAUX = 1 V
–1.6%
1.4%
VIN, VOUT = 12 V
VAUX = 1 V
TJ = 10°C to 85°C
–1.4%
1.4%
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to 85°C unless otherwise stated. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12 V (see (1) and (2)).
PARAMETER
PINACC
TEST CONDITIONS
VIN = 12 V, VIN – SENSE = 25 mV,
CL = GND
Input power accuracy
MIN
TYP
–3%
MAX
UNIT
3%
REMOTE DIODE TEMPERATURE SENSOR
Temperature accuracy using local diode
TACC
TA = 10°C to 85°C
2
Remote diode resolution
IDIODE
10
9
External diode current source
High level
250
Low level
9.4
Diode current ratio
°C
bits
300
µA
µA
26
PMBUS PIN THRESHOLDS (SMBA, SDA, SCL)
VIL
Data, clock input low voltage
VIH
Data, clock input high voltage
VOL
Data output low voltage
IPULLUP = 500 µA
ILEAK
Input leakage current
SDA, SMBA, SCL = 5 V
0.8
V
2.1
5.5
V
0
0.4
V
1
µA
1
mA
CONFIGURATION PIN THRESHOLDS (CB, CL, RETRY)
VIH
Threshold voltage
ILEAK
Input leakage current
3
V
CL, CB, RETRY = 5 V
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
400
kHz
FSMB
SMBus operating frequency
10
tBUF
Bus free time between stop and start condition
1.3
µs
tHD:STA
Hold time after (repeated) start condition. After this period, the first clock is
generated.
0.6
µs
tSU:STA
Repeated start condition setup time
0.6
µs
tSU:STO
Stop condition setup time
0.6
µs
tHD:DAT
Data hold time
300
ns
tSU:DAT
Data setup time
100
tTIMEOUT
Clock low time-out (1)
25
tLOW
Clock low period
1.5
µs
tHIGH
Clock high period (2)
0.6
µs
tLOW:SEXT
Cumulative clock low extend time (slave device)
tLOW:MEXT
Cumulative low extend time (master device) (4)
tF
Clock or data fall time (5)
tR
(1)
(2)
(3)
(4)
(5)
8
Clock or data rise time
(3)
(5)
ns
35
ms
25
ms
10
ms
20
300
ns
20
300
ns
Devices participating in a transfer will timeout when any clock low exceeds the value of TTIMEOUT,MIN of 25 ms. Devices that have
detected a timeout condition must reset the communication no later than TTIMEOUT,MAX of 35 ms. The maximum value must be adhered
to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).
THIGH MAX provides a simple method for devices to detect bus idle conditions.
TLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If
a slave exceeds this time, it is expected to release both its clock and data lines and reset itself.
TLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from
start-to-ack, ack-to-ack, or ack-to-stop.
Rise and fall time are defined with TR = ( VILMAX – 0.15) to (VIHMIN + 0.15) and TF = 0.9 VDD to (VILMAX – 0.15).
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7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
tCL
Response time
VIN-SENSE stepped from 0 mV to 80 mV
1.2
VIN - SENSE stepped from 0 mV to 150 mV,
time to GATE low, no load
0.6
Fault to GATE low delay
TIMER pin reaches the upper threshold
17
tAQUIRE
Acquisition + conversion time
Any channel
tRR
Acquisition round robin time
Cycle all channels
µs
CIRCUIT BREAKER
tCB
Response time
1.2
µs
TIMER (TIMER PIN)
tFAULT_DELAY
µs
ADC AND MUX
tR
SCL
100
µs
1
ms
tF
tLOW
VIH
VIL
tHIGH
tHD;DAT
tHD;STA
tSU;STA
tSU;STO
tSU;DAT
SDA
VIH
VIL
tBUF
P
S
S
P
Figure 1. SMBus Timing Diagram
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7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12 V. All graphs show junction temperature.
5.5
VIN = 17V
5.0
VIN = 12V
4.5
4.0
VIN = 3V
3.5
3.0
-40 -20
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
SENSE PIN CURRENT (ENABLED) ( A)
VIN INPUT CURRENT (mA)
6.0
54
50
VIN = 17V
46
VIN = 12V
42
38
VIN = 2.9V
34
30
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
Figure 3. SENSE Pin Current (Enabled)
OUTPUT PIN CURRENT (ENABLED) ( A)
SENSE PIN CURRENT (DISABLED) ( A)
Figure 2. VIN Pin Current
52
50
VIN = 17V
48
46
44
VIN = 12V
42
40
38
VIN = 2.9V
36
34
-40 -20
28
24
16
VIN = 12V
12
8
VIN = 2.9V
4
0 20 40 60 80 100 120
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 5. OUT Pin Current (Enabled)
-2
20
VIN = 17V
-4
18
VIN = 17V
GATE PIN VOLTAGE (V)
OUTPUT PIN CURRNET (DISABLED) ( A)
Figure 4. SENSE Pin Current (Disabled)
-6
-8
VIN = 12V
-10
-12
-14
-16
VIN = 12V
16
VIN = 9V
14
12
VIN = 5V
10
8
VIN = 2.9V
-18
VIN = 2.9V
6
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 6. OUT Pin Current (Disabled)
10
VIN = 17V
20
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-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 7. GATE Pin Voltage
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12 V. All graphs show junction temperature.
24
22
21
20
VIN = 5V TO 17V
19
18
17
VIN = 2.9V
16
15
POWER LIMIT THRESHOLD (mV)
GATE PIN SOURCE CURRENT ( A)
23
20
RPWR
16
12
8
RPWR
0
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
-40 -20
Figure 8. GATE Pin Source Current
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 9. Power Limit Threshold
42
1.17
38
UVLO THRESHOLD (V)
PGD LOW VOLTAGE (mV)
=25K; CL = GND
4
14
-40 -20
34
30
26
VIN = 2.9 to 12V
1.16
VIN = 17V
22
PGD Sink Current = 2mA
18
-60 -40 -20 0 20 40 60 80 100120140
1.15
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. PGD Low Voltage
Figure 11. UVLO Threshold
24.0
1.172
1.171
23.8
1.170
FB THRESHOLD (V)
UVLO HYSTERESIS CURRENT ( A)
=50K; CL = VDD
1.169
23.6
1.168
1.167
23.4
1.166
1.165
23.2
1.164
1.163
23.0
-60 -40 -20 0 20 40 60 80 100120140
1.162
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. UVLO Hysteresis Current
Figure 13. FB Threshold
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12 V. All graphs show junction temperature.
-16
OVLO HYSTERESIS CURRENT ( A)
1.167
OVLO THRESHOLD (V)
VIN = 2.9V
1.166
VIN = 12V
1.165
1.164
1.163
VIN = 17V
1.162
-18
-20
-22
VIN = 12V to 17V
-24
-26
-28
-30
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
Figure 15. OVLO Hysteresis
Figure 14. OVLO Threshold
27.0
CURRENT LIMIT THRESHOLD (mV)
-23.0
FB HYSTERESIS ( A)
-23.5
-24.0
-24.5
-25.0
-25.5
26.5
26.0
25.5
VIN = 5V to 17V
25.0
24.5
24.0
VIN = 2.9V
23.5
23.0
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
-26.0
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
Figure 17. Current Limit Threshold
CURRENT LIMIT THRESHOLD (mV)
50
49
48
47
VIN = 5V to 17V
46
45
44
VIN = 2.9V
43
42
41
40
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
CIRCUIT BREAKER THRESHOLD (mV)
Figure 16. FB Pin Hysteresis
200
180
160
CL = VDD, CB = VDD
140
120
100
CL = GND, CB = VDD
80
60
CL = GND, CB = GND
40
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
Figure 18. Current Limit Threshold
12
Figure 19. Circuit Breaker Threshold (CL = VDD)
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12 V. All graphs show junction temperature.
VREF (V)
2.75
INSERTION DELAY = 140 ms
2.74
TIMER
1V/DIV
2.73
VIN
10V/DIV
2.72
GATE
2.71
10V/DIV
VOUT
10V/DIV
2.70
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
Figure 20. Reference Voltage
100 ms/DIV
Figure 21. Start-up (Insertion Delay)
TIMER
1V/DIV
TIMER
VIN
1V/DIV
10V/DIV
RETRY PERIOD = 1.10s
GATE
10V/DIV
10V/DIV
GATE
10V/DIV
VOUT
VOUT
10V/DIV
2.5A/DIV
ILOAD
1 ms/DIV
400 ms/DIV
Figure 22. Start-up (Short Circuit VOUT)
Figure 23. Start-up (5-A Load)
PGOOD
5V/DIV
OVLO = 15.2V
GATE
hyst = 1.2V
VIN
5V/DIV
10.7V
10.25V
5V/DIV
VOUT
VIN
hyst = 0.2V
UVLO = 2.9V
40 ms/DIV
40 ms/DIV
Figure 24. Start-up (UVLO, OVLO)
Figure 25. Start-up (PGOOD)
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12 V. All graphs show junction temperature.
1V/DIV
TIMER
TIMER
TIMEOUT PERIOD
= 8.3 ms
GATE
1V/DIV
GATE
10V/DIV
VOUT
>50A
10V/DIV
VOUT
10V/DIV
10V/DIV
ILOAD
> 90A Triggers
Circuit Breaker
25A/DIV
ILOAD
50A/DIV
1 ms/DIV
4 ms/DIV
Figure 26. Current Limit Event (CL = GND)
Figure 27. Circuit Breaker Event (CL = CB = GND)
RETRY PERIOD = 1.1s
1V/DIV
TIMER
TIMER
1V/DIV
GATE
10V/DIV
VOUT
VOUT
10V/DIV
ILOAD
10V/DIV
ILOAD
25A/DIV
25A/DIV
100 ms/DIV
400 ms/DIV
Figure 29. Latch Off (Retry = VDD)
0.5
1.0
0.4
0.8
0.3
0.6
PIN ERROR (% OF FSR)
IIN ERROR ( % OF FSR)
Figure 28. Retry Event (Retry = GND)
0.2
0.1
0.0
-0.1
-0.2
-0.3
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.4
-0.8
-0.5
-1.0
-15 -5
5 15 25 35 45 55 65 75 85
TEMPERATURE ( °C)
Figure 30. IIN Measurement Accuracy
(VIN – SENSE = 25 mV)
14
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-15 -5
5 15 25 35 45 55 65 75 85
TEMPERATURE (°C)
Figure 31. PIN Measurement Accuracy
(VIN – SENSE = 25 mV)
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8 Detailed Description
8.1 Overview
The inline protection functionality of the LM25066 is designed to control the in-rush current to the load upon
insertion of a circuit card into a live backplane or other hot power source, thereby limiting the voltage sag on the
backplane's supply voltage and the dV/dt of the voltage applied to the load. Effects on other circuits in the
system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is
removed can also be implemented using the LM25066.
In addition to a programmable current limit, the LM25066 monitors and limits the maximum power dissipation in
the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting
or power limiting for an extended period of time results in the shutdown of the series pass device. In this event,
the LM25066 can latch off or repetitively retry based on the hardware setting of the RETRY pin. Once started,
the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function quickly switches off
the series pass device upon detection of a severe overcurrent condition. Programmable undervoltage lockout
(UVLO) and overvoltage lockout (OVLO) circuits shut down the LM25066 when the system input voltage is
outside the desired operating range.
The telemetry capability of the LM25066 provides intelligent monitoring of the input voltage, output voltage, input
current, input power, temperature, and an auxiliary input. The LM25066 also provides a peak capture of the input
power and programmable hardware averaging of the input voltage, current, power, and output voltage. Warning
thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power and
temperature via the PMBus interface. Additionally, the LM25066 is capable of detecting damage to the external
MOSFET, Q1.
24 PA
LM25066
VDD
REG
VDD
REF
GEN
1.167V
UV
OV
S/H
AMUX
1/16
ID
25 mV
22 PA
Current Limit
Threshold
Gain = 2.3V/V
VAUX
1 M:
MEASUREMENT/
AVERAGING
FAULT REGISTERS
SCL
SDA
SMBUS
INTERFACE
VDS
10 PA
Diode
Temp
Sense
Gate
Control
2 mA
190
mA
Power Limit
Threshold
GATE
18.8V
Current Limit/
Power Limit
Control
5.5 PA
Insertion
Timer
SnapShot
DIODE
Charge
Pump
1/16
12bit
ADC
VREF
PGD
FB
OUT
SENSE
VIN
8.2 Functional Block Diagram
90 PA
Fault
Timer
23 PA
TIMER
TELEMETRY
STATE
MACHINE
1.16V
TIMER AND GATE
LOGIC CONTROL
1.16V
SMBA
1.9 mA
End
Insertion
Time
2.8 PA
Fault
Discharge
1.72V
ADDRESS
DECODER
1.0V
23 PA
0.3V
2.5V
ADR0
VDD
ADR1
POR
RETRY
CL
GND
UVLO/EN
PWR
OVLO
CB
2.6V
VIN
ADR2
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8.3 Feature Description
8.3.1 Current Limit
The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) exceeds
the internal voltage limit of 25 mV or 46 mV depending on whether the CL pin is connected to GND or VDD,
respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1.
While the current limit circuit is active, the fault timer is active as described in Fault Timer and Restart. If the load
current falls below the current limit threshold before the end of the Fault Timeout Period, the LM25066 resumes
normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by the timer
capacitor, CT, the IIN OC FAULT bit in the MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) register, the
INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the register will be
toggled high and SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08:
ALERT_MASK (D8h) register. For proper operation, the RS resistor value should be less than 200 mΩ. Higher
values may create instability in the current limit control loop. The current limit threshold pin value may be
overridden by setting appropriate bits in the MFR_SPECIFIC_09: DEVICE_SETUP (D9h).
8.3.2 Circuit Breaker
If the load current increases rapidly (for example, the load is short circuited), the current in the sense resistor
(RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current
exceeds 1.8 or 3.6 times (user settable) the current limit threshold, Q1 is quickly switched off by the 190-mA
pulldown current at the GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below
the threshold the 190-mA pulldown current at the GATE pin is switched off and the gate voltage of Q1 is then
determined by the current limit or power limit functions. If the TIMER pin reaches 1.7 V before the current limiting
or power limiting condition ceases, Q1 is switched off by the 2-mA pulldown current at the GATE pin as described
in Fault Timer and Restart. A circuit breaker event will cause the CIRCUIT BREAKER FAULT bit in the
STATUS_MFR_SPECIFIC (80h) and MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) registers to be
toggled high and SMBA pin will be pulled low unless this feature is disabled using the MFR_SPECIFIC_08:
ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits
in the MFR_SPECIFIC_09: DEVICE_SETUP (D9h)) register.
8.3.3 Power Limit
An important feature of the LM25066 is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM25066 determines
the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current
through RS (VIN to SENSE). The product of the current and voltage is compared to the power limit threshold
programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE
voltage is controlled to regulate the current in Q1. While the power limiting circuit is active, the fault timer is active
as described in Fault Timer and Restart. If the power limit condition persists for longer than the Fault Timeout
Period set by the timer capacitor, CT, the IIN_OC_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT
bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in theMFR_SPECIFIC_17:
READ_DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be pulled low unless this
feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register.
8.3.4 Undervoltage Lockout (UVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range
defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. Typically the
UVLO level at VSYS is set with a resistor divider (R1-R3) as shown in Figure 35. Refering to the Block Diagram
when VSYS is below the UVLO level, the internal 23-µA current source at UVLO is enabled, the current source at
OVLO is off, and Q1 is held off by the 2-mA pulldown current at the GATE pin. As VSYS is increased, raising the
voltage at UVLO above its threshold the 23-µA current source at UVLO is switched off, increasing the voltage at
UVLO, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q1 is switched on by
the 22-µA current source at the GATE pin if the insertion time delay has expired.
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Feature Description (continued)
See Typical Application for a procedure to calculate the values of the threshold setting resistors (R1-R3). The
minimum possible UVLO level at VSYS can be set by connecting the UVLO/EN pin to VIN. In this case, Q1 is
enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power up, an UVLO
condition will toggle high the VIN UV FAULT bit in the STATUS_INPUT (7Ch), the INPUT bit in the
STATUS_WORD (79h) register, and the VIN_UNDERVOLTAGE_FAULT bit in the MFR_SPECIFIC_17:
READ_DIAGNOSTIC_WORD (E1h) register, and SMBA pin will be pulled low unless this feature is disabled
using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register.
8.3.5 Overvoltage Lockout (OVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range
defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. If VSYS raises
the OVLO pin voltage above its threshold, Q1 is switched off by the 2-mA pulldown current at the GATE pin,
denying power to the load. When the OVLO pin is above its threshold, the internal 23 µA current source at OVLO
is switched on, raising the voltage at OVLO to provide threshold hysteresis. When VSYS is reduced below the
OVLO level, Q1 is re-enabled. An OVLO condition will toggle high the VIN OV FAULT bit in the STATUS_INPUT
(7Ch), the INPUT bit in the STATUS_WORD (79h) register, and the VIN_OVERVOLTAGE_FAULT bit in the
MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) register, and the SMBA pin will be pulled low unless
this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h) register.
See Typical Application for a procedure to calculate the threshold setting resistor values.
8.3.6 Power Good
The Power Good indicator (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 17 V in the off-state, and transients up to 20 V. An external pullup resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds
the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as
long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Block Diagram, when the
voltage at the FB pin is below its threshold, the 24-µA current source at FB is disabled. As the output voltage
increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising
the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is
below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read via the PMBus
interface in either the STATUS_WORD (79h) or MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
registers.
8.3.7 VDD Sub-Regulator
The LM25066 contains an internal linear sub-regulator which steps down the input voltage to generate a 4.5 V
rail used for powering low voltage circuitry. When the input voltage is below 4.5 V, VDD will track VIN. For input
voltages 3.3 V and below, VDD should be tied directly to VIN to avoid the dropout of the sub-regulator. The VDD
sub-regulator should be used as the pullup supply for the CL, CB, RETRY, ADR2, ADR1, ADR0 pins if they are
to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, SMBA).
The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated
circuits. The VDD pin is current limited to 45 mA in order to protect the LM25066 in the event of a short. The subregulator requires a bypass capacitance having a value from 1 µF to 4.7 µF to be placed as close to the VDD pin
as the PCB layout allows.
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Feature Description (continued)
8.3.8 Remote Temperature Sensing
The LM25066 is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and
collector of the MMBT3904 is connected to the DIODE pin and the emitter is grounded. Place the MMBT3904
near the device whose temperature is to be monitored. If the temperature of the hot-swap pass MOSFET, Q1, is
to be measured, the MMBT3904 should be placed as close to Q1 as the layout allows. The temperature is
measured by means of a change in the diode voltage in response to a step in current supplied by the DIODE pin.
The DIODE pin sources a constant 9.4 µA but pulses 250 µA once every millisecond in order to measure the
diode temperature. Care must be taken in the PCB layout to keep the parasitic resistance between the DIODE
pin and the MMBT3904 low so as not to degrade the measurement. Additionally, a small 1000-pF bypass
capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The temperature can be
read using the READ_TEMPERATURE_1 (8Dh) PMBus command. The default limits of the LM25066 will cause
SMBA pin to be pulled low if the measured temperature exceeds 125°C and will disable the hot-swap pass
MOSFET if the temperature exceeds 150°C. These thresholds can be reprogrammed via the PMBus interface
using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and
protection capability of the LM25066 is not used, the DIODE pin should be grounded.
8.3.9 Damaged MOSFET Detection
The LM25066 is able to detect whether the external MOSFET, Q1, is damaged under certain conditions. If the
voltage across the sense resistor exceeds 4mV while the GATE voltage is low or the internal logic indicates that
the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and
MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) registers will be toggled high and the SMBA pin will be
pulled low unless this feature is disabled using the MFR_SPECIFIC_08: ALERT_MASK (D8h). This method
effectively determines whether Q1 is shorted because of damage present between the drain and gate and/or
drain and source of the external MOSFET.
8.4 Device Functional Modes
8.4.1 Power Up Sequence
The VIN operating range of the LM25066 is +2.9 V to +17 V, with transient capability to +24 V. Referring to
Figure 38 and Figure 32, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held
off by an internal 190-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin
prevents an inadvertent turnon as the MOSFET's gate-to-drain (Miller) capacitance is charged. Additionally, the
TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold, the insertion time begins.
During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5-µA current source and Q1 is
held off by a 2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay
allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin
voltage reaches 1.7 V. CT is then quickly discharged by an internal 1.9-mA pulldown current. The GATE pin then
switches on Q1 when VSYS, the input supply voltage, exceeds the UVLO threshold. If VSYS is above the UVLO
threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 22
µA to charge the gate capacitance of Q1. The maximum voltage at the GATE pin with respect to ground is limited
by an internal 18.8-V Zener diode.
As the voltage at the OUT pin increases, the LM25066 monitors the drain current and power dissipation of
MOSFET Q1. Inrush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the inrush limiting interval (t2 in Figure 32), an internal 90 -A fault timer current source charges CT. If
Q1's power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 1.7 V, the 90-µA current source is switched off and CT is discharged by the internal 2.8-µA current
sink (t3 in Figure 32). The PGD pin switches high when FB exceeds its rising threshold of 1.167 V.
If the TIMER pin voltage reaches 1.7 V before inrush current limiting or power limiting ceases during t2, a fault is
declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode.
The LM25066 will pull the SMBA pin low after the input voltage has exceeded its POR threshold to indicate that
the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
STATUS_MFR_SPECIFIC (80h) indicates default configuration of warning thresholds and device operation and
will remain set until a CLEAR_FAULTS command is received.
18
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LM25066
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Device Functional Modes (continued)
VSYS
UVLO
VIN
POR
1.7V
5.5 PA
90 PA
2.8 PA
TIMER
Pin
GATE
Pin
190 mA
pull-down
2 mA pull-down
22 PA source
ILIMIT
Load
Current
Output
Voltage
(OUT Pin)
PGD
t1
Insertion Time
t2
t3
In rush
Limiting
Normal Operation
Figure 32. Power Up Sequence (Current Limit Only)
8.4.2 Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET's gate. During normal
operating conditions (t3 in Figure 32) the gate of Q1 is held charged by an internal 22-µA current source. The
voltage at the GATE pin (with respect to ground) is limited by an internal 18.8-V Zener diode. See the graph
Figure 7 in Typical Characteristics. Since the gate-to-source voltage applied to Q1 could be as high as 18.8 V
during various conditions, a Zener diode with the appropriate voltage rating must be added between the GATE
and OUT pins if the maximum VGS rating of the selected MOSFET is less than 18.8 V. The external Zener diode
must have a forward current rating of at least 190 mA. When the system voltage is initially applied, the GATE pin
is held low by a 190-mA pulldown current. This helps prevent an inadvertent turnon of the MOSFET through its
drain-gate capacitance as the applied system voltage increases.
During the insertion time (t1 in Figure 32) the GATE pin is held low by a 2-mA pulldown current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time (t2 in
Figure 32), the gate voltage of Q1 is controlled to keep the current or power dissipation level from exceeding the
programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the
current and power limiting cease before the TIMER pin reaches 1.7 V, the TIMER pin capacitor then discharges,
and the circuit begins normal operation. If the inrush limiting condition persists such that the TIMER pin reached
1.7 V during t2, the GATE pin is then pulled low by the 190-mA pulldown current. The GATE pin is then held low
until either a power up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin
to GROUND). See Fault Timer and Restart. If the system input voltage falls below the UVLO threshold or rises
above the OVLO threshold, the GATE pin is pulled low by the 2-mA pulldown current to switch off Q1.
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LM25066
SNVS654J – FEBRUARY 2010 – REVISED DECEMBER 2015
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Device Functional Modes (continued)
8.4.3 Fault Timer and Restart
When the current limit or power limit threshold is reached during turnon, or as a result of a fault condition, the
gate-to-source voltage of Q1 is controlled to regulate the load current and power dissipation in Q1. When either
limiting function is active, a 90-µA fault timer current source charges the external capacitor (CT) at the TIMER pin
as shown in Figure 32 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period
before the TIMER pin reaches 1.7 V, the LM25066 returns to the normal operating mode and CT is discharged by
the 1.9-mA current sink. If the TIMER pin reaches 1.7 V during the Fault Timeout Period, Q1 is switched off by a
2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM25066 latches the GATE pin low at the end of the Fault Timeout Period. CT is
then discharged to ground by the 2.8-µA fault current sink. The GATE pin is held low by the 2-mA pulldown
current until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling
the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 33. The
voltage at the TIMER pin must be
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