LM48821, LM48821TLEVAL
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SNAS354A – JUNE 2007 – REVISED MAY 2013
LM48821
Direct Coupled, Ultra Low Noise, 52mW
Differential Input Stereo Headphone Amplifier with I2C Volume Control
Check for Samples: LM48821, LM48821TLEVAL
FEATURES
DESCRIPTION
•
•
•
•
•
•
With its directly-coupled output technology, the
LM48821 is a variable gain audio power amplifier
capable of delivering 52mWRMS per channel into a
16Ω single-ended load with less than 1% THD+N
from a 3V power supply. The I2C volume control has
a range of –76dB to 18dB.
1
2
•
•
•
Ground Referenced Outputs
Differential Inputs
I2C Volume and Mode Controls
Available in Space-Saving DSBGA Package
Ultra Low Current Shutdown Mode
Advanced Output Transient Suppression
Circuitry Eliminates Noises During Turn-On
and Turn-Off Transitions
2.0V to 4.0V Operation (PVDD and SVDD)
1.8 to 4.0V Operation (I2CVDD)
No Output Coupling Capacitors, Snubber
Networks, Bootstrap Capacitors, or GainSetting Resistors Required
APPLICATIONS
•
•
•
•
•
•
Notebook PCs
Desktop PCs
Mobile Phones
PDAs
Portable Electronic Devices
MP3 Players
The LM48821's Tru-GND technology utilizes
advanced charge pump technology to generate the
LM48821’s negative supply voltage. This eliminates
the need for output-coupling capacitors typically used
with single-ended loads.
Boomer audio power amplifiers were designed
specifically to provide high quality output power with a
minimal amount of external components. The
LM48821 does not require output coupling capacitors
or bootstrap capacitors, and therefore, is ideally
suited for mobile phone and other low voltage
applications where minimal power consumption is a
primary requirement.
The LM48821 incorporates selectable low-power
consumption shutdown and channel select modes.
The LM48821 contains advanced output transient
suppression circuitry that eliminates noises which
would otherwise occur during turn-on and turn-off
transitions.
KEY SPECIFICATIONS
•
•
•
•
Improved PSRR at 217Hz: 82dB (typ)
Stereo Output Power at VDD = 3V, RL = 16Ω,
THD+N = 1%: 52mW (typ)
Mono Output Power at VDD = 3V, RL = 16Ω,
THD+N = 1%: 93mW (typ)
Shutdown current: 0.1μA (typ)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LM48821, LM48821TLEVAL
SNAS354A – JUNE 2007 – REVISED MAY 2013
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Typical Application
0.1 PF
VDD
4.7 PF
0.1 PF
PVDD
0.47 PF
IN A-
0.47 PF
IN A+
-
VOA
+
0.47 PF
IN B+
0.47 PF
Digital
Control
System
SVDD
SGND
IN B-
SCL
SDA
2
I CVDD
2
I C Digitally
Controlled
Analog Volume
Control
Interface
+
Bias
Control
VOB
-
Charge
Pump
CCP-
VSS
CCP+
4.7 PF
PGND
4.7 PF
Figure 1. Typical Audio Amplifier Application Circuit
Connection Diagram
2
4
IN A-
IN B-
I CVDD
PVDD
3
IN A+
IN B+
SDA
CCP+
2
SGND
VOB
SCL
PGND
1
SVDD
VOA
VSS
CCP-
A
B
C
D
Figure 2. DSBGA - Top View
See YZR0016 Package
2
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PIN DESCRIPTIONS
Pin Designator
Pin Name
Pin Function
A1
SVDD
Signal power supply input
A2
SGND
Signal ground
A3
IN A+
Left non-inverting input
A4
IN A-
Left inverting input
B1
VOA
Left output
B2
VOB
Right output
B3
IN B+
Right non-inverting input
Right inverting input
B4
IN B-
C1
VSS
DC to DC converter output
C2
SCL
I2C serial clock input
SDA
I2C serial data input
C3
2
I2C supply voltage input
C4
I CVDD
D1
CCP-
D2
PGND
D3
CCP+
DC to DC converter flying capacitor non-inverting input
D4
PVDD
DC to DC converter power supply input
DC to DC converter flying capacitor inverting input
Power ground
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2) (3)
Supply Voltage
4.5V
−65°C to +150°C
Storage Temperature
−0.3V to VDD +0.3V
Input Voltage
Power Dissipation
(4)
Internally Limited
ESD Susceptibility
(5)
2000V
ESD Susceptibility
(6)
200V
Junction Temperature
150°C
Thermal Resistance
θJA (typ) - (DSBGA)
(1)
(2)
(4)
105°C/W
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not specify performance limits. Electrical Characteristics state DC and AC electrical specifications
under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings.
Specifications are for parameters where no limit is given, however, the typical value is a good indication of device performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM48821, see power derating currents for more information.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF - 240pF discharged through all pins.
(3)
(4)
(5)
(6)
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
Supply Voltage
2.0V ≤ VDD ≤ 4.0V
PVDD and SVDD
I2CVDD
1.8V ≤ I2CVDD ≤ 4.0V
Audio Amplifier Electrical Characteristics VDD = 3V
(1)
The following specifications apply for VDD = 3V, RL = 16Ω, AV = 0dB, unless otherwise specified. Limits apply for TA = 25°C.
LM48821
Symbol
IDD
Parameter
Quiescent Power Supply Current
Conditions
Typical
(2)
Limits
(3) (4)
Units
(Limits)
VIN = 0V, inputs terminated,
both channels enabled
3.0
4.5
mA (max)
VIN = 0V, inputs terminated,
one channel enabled
2.0
3.0
mA
ISD
Shutdown Current
Right and Left Enable bits set to 0
0.1
1.2
µA (max)
VOS
Output Offset Voltage
RL = 32Ω
0.5
2.5
mV (max)
AV
Volume Control Range
ΔAV
Channel-to-Channel Gain Match
AV-MUTE
Mute Gain
RIN
Input Resistance
(1)
(2)
(3)
(4)
4
[B0:B4] = 00000
–76
dB
[B0:B4] = 11111
+18
dB
±0.015
dB
–76
dB
Gain = 18dB
9
Gain = –76dB
81
5
15
kΩ (min)
kΩ (max)
kΩ
All voltages are measured with respect to the GND pin unless otherwise specified.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Data sheet min and /max specification limits are specified by design, test, or statistical analysis.
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Audio Amplifier Electrical Characteristics VDD = 3V (1) (continued)
The following specifications apply for VDD = 3V, RL = 16Ω, AV = 0dB, unless otherwise specified. Limits apply for TA = 25°C.
LM48821
Symbol
POUT
THD+N
Parameter
Output Power
Total Harmonic Distortion +
Noise
Conditions
Typical
(2)
Limits
(3) (4)
Units
(Limits)
THD+N = 1% (max); fIN = 1kHz,
RL = 16Ω, per channel
52
43
mW (min)
THD+N = 1% (max); fIN = 1kHz,
RL = 32Ω, per channel
53
45
mW (min)
THD+N = 1% (max); fIN = 1kHz,
RL = 16Ω, single channel driven
93
80
mW (min)
THD+N = 1% (max); fIN = 1kHz,
RL = 32Ω, single channel driven
79
mW
POUT = 50mW, f = 1kHz
RL = 16Ω, single channel
0.022
%
POUT = 50mW, f = 1kHz
RL = 32Ω, single channel
0.011
%
VRIPPLE = 200mVP-P, input referred
f = 217Hz
f = 1kHz
f = 20kHz
82
80
55
Common Mode Rejection Ratio
VRIPPLE = 200mVp-p, Input referred
f = 2kHz
65
dB
SNR
Signal-to-Noise-Ratio
RL = 32Ω, POUT = 20mW,
f = 1kHz, BW = 20Hz to 22kHz
100
dB
TWU
Charge Pump Wake-Up Time
PSRR
Power Supply Rejection Ratio
CMRR
XTALK
Crosstalk
RL = 16Ω, POUT = 1.6mW,
f = 1kHz, A-weighted filter
ZOUT
Output Impedance
Right and Left Enable bits set to 0
Control Interface Electrical Characteristics
65
dB (min)
dB
dB
400
μs
82
dB
41
kΩ
(1)
The following specifications apply for 1.8V ≤ I2CVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA = 25°C. See
Figure 56.
Symbol
Parameter
Conditions
LM48821
Typical
(2)
Limits
(3) (4)
Units
(Limits)
t1
SCL period
2.5
μs (min)
t2
SDA Setup Time
100
ns (min)
t3
SDA Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
VIH
Logic High Input Threshold
0.7 x I2CVDD
V (min)
VIL
Logic Low Input Threshold
0.3 x I2CVDD
V (max)
(1)
(2)
(3)
(4)
All voltages are measured with respect to the GND pin unless otherwise specified.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Data sheet min and /max specification limits are specified by design, test, or statistical analysis.
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 2V, PO = 6mW,
RL = 16Ω, Stereo
THD+N vs Frequency
VDD = 2V, PO = 10mW,
RL = 32Ω, Stereo
1
0.1
0.1
THD+N (%)
THD+N (%)
1
0.01
0.01
0.001
20
100 200
1k 2k
0.001
10k 20k
20
1k 2k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3.
Figure 4.
THD+N vs Frequency
VDD = 2V, PO = 16mW,
RL = 16Ω, Mono Left
THD+N vs Frequency
VDD = 2V, PO = 16mW,
RL = 16Ω, Mono Right
1
0.1
0.1
THD+N (%)
THD+N (%)
1
0.01
0.01
0.001
20
100 200
1k 2k
0.001
20
10k 20k
100 200
1k 2k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5.
Figure 6.
THD+N vs Frequency
VDD = 2V, PO = 18mW,
RL = 32Ω, Mono Left
THD+N vs Frequency
VDD = 2V, PO = 18mW,
RL = 32Ω, Mono Right
1
0.1
0.1
THD+N (%)
THD+N (%)
1
0.01
0.001
0.01
20
100 200
1k 2k
10k 20k
0.001
20
FREQUENCY (Hz)
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100 200
1k 2k
10k 20k
FREQUENCY (Hz)
Figure 7.
6
100 200
Figure 8.
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Typical Performance Characteristics (continued)
THD+N vs Frequency
VDD = 3V, PO = 35mW,
RL = 16Ω, Stereo
THD+N vs Frequency
VDD = 4V, PO = 50mW,
RL = 16Ω, Stereo
1
0.1
0.1
THD+N (%)
THD+N (%)
1
0.01
0.01
0.001
20
100 200
1k 2k
0.001
20
10k 20k
FREQUENCY (Hz)
Figure 10.
THD+N vs Frequency
VDD = 3V, PO = 70mW,
RL = 16Ω, Mono Left
THD+N vs Frequency
VDD = 3V, PO = 70mW,
RL = 16Ω, Mono Right
0.1
THD+N (%)
THD+N (%)
0.1
0.01
0.01
100 200
1k 2k
0.001
20
10k 20k
FREQUENCY (Hz)
100 200
1k 2k
10k 20k
FREQUENCY (Hz)
Figure 11.
Figure 12.
THD+N vs Frequency
VDD = 4V, PO = 160mW,
RL = 16Ω, Mono Left
THD+N vs Frequency
VDD = 4V, PO = 160mW,
RL = 16Ω, Mono Right
1
1
0.1
0.1
THD+N (%)
THD+N (%)
10k 20k
FREQUENCY (Hz)
1
0.01
0.001
20
1k 2k
Figure 9.
1
0.001
20
100 200
0.01
100 200
1k 2k
10k 20k
0.001
20
FREQUENCY (Hz)
Figure 13.
100 200
1k 2k
10k 20k
FREQUENCY (Hz)
Figure 14.
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Typical Performance Characteristics (continued)
THD+N vs Frequency
VDD = 3V, PO = 40mW,
RL = 32Ω, Stereo
THD+N vs Frequency
VDD = 3V, PO = 60mW,
RL = 32Ω, Mono Left
1
0.1
0.1
THD+N (%)
THD+N (%)
1
0.01
0.001
20
0.01
100 200
1k 2k
0.001
20
10k 20k
Figure 16.
THD+N vs Frequency
VDD = 3V, PO = 60mW,
RL = 32Ω, Mono Right
THD+N vs Frequency
VDD = 4V, PO = 90mW,
RL = 32Ω, Stereo
1
0.1
0.1
0.01
100 200
1k 2k
0.001
20
10k 20k
100 200
1k 2k
10k 20k
FREQUENCY (Hz)
Figure 17.
Figure 18.
THD+N vs Frequency
VDD = 4V, PO = 120mW,
RL = 32Ω, Mono Left
THD+N vs Frequency
VDD = 4V, PO = 120mW,
RL = 32Ω, Mono Right
1
1
0.1
0.1
THD+N (%)
THD+N (%)
10k 20k
0.01
FREQUENCY (Hz)
0.01
0.001
20
0.01
100 200
1k 2k
10k 20k
0.001
20
FREQUENCY (Hz)
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100 200
1k 2k
10k 20k
FREQUENCY (Hz)
Figure 19.
8
1k 2k
Figure 15.
1
0.001
20
100 200
FREQUENCY (Hz)
THD+N (%)
THD+N (%)
FREQUENCY (Hz)
Figure 20.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 2V, RL = 16Ω,
f = 1kHz, Mono Left
THD+N vs Output Power
VDD = 2V, RL = 16Ω,
f = 1kHz, Mono Right
Figure 21.
Figure 22.
THD+N vs Output Power
VDD = 2V, RL = 16Ω,
f = 1kHz, Stereo
THD+N vs Output Power
VDD = 3V, RL = 16Ω,
f = 1kHz, Mono Left
1
THD + N (%)
0.5
0.1
0.05
0.01
0.005
0.001
0.01
0.1
1
10
100
500
OUTPUT POWER (mW)
Figure 23.
Figure 24.
THD+N vs Output Power
VDD = 3V, RL = 16Ω,
f = 1kHz, Mono Right
THD+N vs Output Power
VDD = 3V, RL = 16Ω,
f = 1kHz, Stereo
1
THD + N (%)
0.5
0.1
0.05
0.01
0.005
0.001
0.01
0.1
1
10
100
500
OUTPUT POWER (mW)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 4V, RL = 16Ω,
f = 1kHz, Mono Left
THD+N vs Output Power
VDD = 4V, RL = 16Ω,
f = 1kHz, Mono Right
Figure 27.
Figure 28.
THD+N vs Output Power
VDD = 4V, RL = 16Ω,
f = 1kHz, Stereo
THD+N vs Output Power
VDD = 2V, RL = 32Ω,
f = 1kHz, Mono Left
1
THD + N (%)
0.5
0.1
0.05
0.01
0.005
0.001
0.01
0.1
1
10
100
500
OUTPUT POWER (mW)
Figure 29.
Figure 30.
THD+N vs Output Power
VDD = 2V, RL = 32Ω,
f = 1kHz, Mono Right
THD+N vs Output Power
VDD = 2V, RL = 32Ω,
f = 1kHz, Stereo
1
THD + N (%)
0.5
0.1
0.05
0.01
0.005
0.001
0.01
0.1
1
10
100
500
OUTPUT POWER (mW)
Figure 31.
10
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Figure 32.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3V, RL = 32Ω,
f = 1kHz, Mono Left
THD+N vs Output Power
VDD = 3V, RL = 32Ω,
f = 1kHz, Mono Right
Figure 33.
Figure 34.
THD+N vs Output Power
VDD = 3V, RL = 32Ω,
f = 1kHz, Stereo
THD+N vs Output Power
VDD = 4V, RL = 32Ω,
f = 1kHz, Mono Left
1
THD + N (%)
0.5
0.1
0.05
0.01
0.005
0.001
0.01
0.1
1
10
100
500
OUTPUT POWER (mW)
Figure 35.
Figure 36.
THD+N vs Output Power
VDD = 4V, RL = 32Ω,
f = 1kHz, Mono Right
THD+N vs Output Power
VDD = 4V, RL = 32Ω,
f = 1kHz, Stereo
1
THD + N (%)
0.5
0.1
0.05
0.01
0.005
0.001
0.01
0.1
1
10
100
500
OUTPUT POWER (mW)
Figure 37.
Figure 38.
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Typical Performance Characteristics (continued)
CMRR vs Frequency
VDD = 3V, RL = 16Ω
PSRR vs Frequency
VDD = 2V, RL = 16Ω
+0
+0
-10
-10
-20
-20
-30
-40
PSRR (dB)
CMRR (dB)
-30
-40
-50
-60
-50
-60
-70
-80
-70
-90
-80
-100
-90
-110
-100
20
100 200
1k 2k
-120
20
10k 20k
PSRR vs Frequency
VDD = 2V, RL = 32Ω
PSRR vs Frequency
VDD = 3V, RL = 16Ω
+0
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
-50
-60
-70
-50
-70
-80
-90
-90
-100
-100
-110
-110
100 200
1k 2k
-120
20
10k 20k
100 200
1k 2k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41.
Figure 42.
PSRR vs Frequency
VDD = 3V, RL = 32Ω
PSRR vs Frequency
VDD = 4V, RL = 16Ω
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-60
-70
-50
-70
-80
-90
-90
-100
-100
-110
-110
1k 2k
10k 20k
-120
20
100 200
1k 2k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43.
Figure 44.
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10k 20k
-60
-80
100 200
10k 20k
-60
-80
PSRR (dB)
PSRR (dB)
PSRR (dB)
12
Figure 40.
+0
-120
20
1k 2k
Figure 39.
-10
-120
20
100 200
FREQUENCY (Hz)
FREQUENCY (Hz)
10k 20k
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDD = 4V, RL = 32Ω
300
+0
Output Power vs Voltage Supply
RL = 16Ω, Mono
MONO OUTPUT POWER (W)
-10
-20
-30
PSRR (dB)
-40
-50
-60
-70
-80
-90
-100
THD=10%
250
200
150
100
THD=1%
50
-110
-120
20
0
100 200
1k 2k
1.5
10k 20k
2
FREQUENCY (Hz)
3
3.5
4
4.5
POWER SUPPLY VOLTAGE (V)
Figure 45.
Figure 46.
Output Power vs Voltage Supply
RL = 32Ω, Mono
Output Power vs Voltage Supply
RL = 16Ω, Stereo
300
STEREO OUTPUT POWER (W)
MONO OUTPUT POWER (W)
300
2.5
250
THD=10%
200
150
100
THD=1%
50
250
200
150
THD=10%
100
50
THD=1%
0
1.5
2
2.5
3
3.5
4
0
1.5
4.5
2
POWER SUPPLY VOLTAGE (V)
AMPLLIFIER DISSIPATION (W)
STEREO OUTPUT POWER (W)
THD=10%
100
50
0
3
3.5
4
POWER SUPPLY VOLTAGE (V)
0.40
0.35
0.30
0.25
THD=1%
0.20
4.5
THD=10%
VDD=4V
0.15
VDD=3V
0.10
0.05
THD=1%
2.5
4.5
Output Power vs Power Dissipation
VDD = 2V, 3V, 4V, RL = 16Ω, Mono
200
2
4
0.45
250
1.5
3.5
Figure 48.
Output Power vs Voltage Supply
RL = 32Ω, Stereo
150
3
POWER SUPPLY VOLTAGE (V)
Figure 47.
300
2.5
VDD=2V
0.00
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
MONOPHONIC OUTPUT POWER (W)
Figure 49.
Figure 50.
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Typical Performance Characteristics (continued)
Output Power vs Power Dissipation
VDD = 2V, 3V, 4V, RL = 16Ω, Stereo
0.45
0.45
0.40
0.40
AMPLLIFIER DISSIPATION (W)
AMPLLIFIER DISSIPATION (W)
Output Power vs Power Dissipation
VDD = 2V, 3V, 4V, RL = 32Ω, Mono
0.35
0.30
0.25
0.20
0.15
THD=1%
THD=10%
0.10
0.05
VDD=4V
THD=1%
0.35
0.30
0.25
VDD=3V
0.20
0.15
0.10
VDD=2V
0.05
VDD=3V
VDD=2V
0.00
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
0.00
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
TOTAL STEREO OUTPUT POWER (W)
MONOPHONIC OUTPUT POWER (W)
Figure 51.
Figure 52.
Output Power vs Power Dissipation
VDD = 2V, 3V, 4V, RL = 32Ω, Stereo
Supply Current vs Supply Voltage
Mono
0.45
4.0
0.40
POWER SUPPLY CURRENT (mA)
AMPLLIFIER DISSIPATION (W)
THD=10%
VDD=4V
0.35
0.30
0.25
THD=1%
0.20
THD=10%
VDD=4V
0.15
0.10
VDD=3V
0.05
VDD=2V
0.00
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
POWER SUPPLY VOLTAGE (V)
TOTAL STEREO OUTPUT POWER (W)
Figure 53.
Figure 54.
Supply Current vs Supply Voltage
Stereo
POWER SUPPLY CURRENT (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
POWER SUPPLY VOLTAGE (V)
Figure 55.
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APPLICATION INFORMATION
Figure 56. I2C Timing Diagram
Figure 57. I2C Bus Format
Table 1. Chip Address
Chip Address
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
1
0
0
Table 2. Control Registers
Volume Control
D7
D6
D5
D4
D3
D2
D1
D0
VD4
VD3
VD2
VD1
VD0
MUTE
LF
ENABLE
RT
ENABLE
I2C VOLUME CONTROL
The LM48821 can be configured in 32 different gain steps by forcing I2C volume control bits to a desired gain
according to Table 3.
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Table 3. Volume Control
VD4
VD3
VD2
VD1
VD0
Gain (dB)
0
0
0
0
0
–76
0
0
0
0
1
–62
0
0
0
1
0
–52
0
0
0
1
1
–44
0
0
1
0
0
–38
0
0
1
0
1
–34
0
0
1
1
0
–30
0
0
1
1
1
–27
0
1
0
0
0
–24
0
1
0
0
1
–21
0
1
0
1
0
–18
0
1
0
1
1
–16
0
1
1
0
0
–14
0
1
1
0
1
–12
0
1
1
1
0
–10
0
1
1
1
1
–8
1
0
0
0
0
–6
1
0
0
0
1
–4
1
0
0
1
0
–2
1
0
0
1
1
0
1
0
1
0
0
2
1
0
1
0
1
4
1
0
1
1
0
6
1
0
1
1
1
8
1
1
0
0
0
10
1
1
0
0
1
12
1
1
0
1
0
13
1
1
0
1
1
14
1
1
1
0
0
15
1
1
1
0
1
16
1
1
1
1
0
17
1
1
1
1
1
18
I2C COMPATIBLE INTERFACE
The LM48821 uses a serial data bus that conforms to the I2C protocol. Controlling the chip’s functions is
accomplished with two wires: serial clock (SCL) and serial data (SDA). The clock line is uni-directional. The data
line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In
this discussion, the master is the controlling microcontroller and the slave is the LM48821.
The bus format for the I2C interface is shown in Figure 57. The bus format diagram is broken up into six major
sections: The Start Signal, the I2C Address, an Acknowledge bit, the I2C data, second Acknowledge bit, and the
Stop Signal.
The start signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
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After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM48821 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM48821. The 8 bits of data are sent next, most
significant bit first. Each data bit should be valid while the clock level is stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM48821 received the
data.
If the master has more data bytes to send to the LM48821, then the master can repeat the previous two steps
until all data bytes have been sent.
The stop signal ends the transfer. To signal stop , the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
The LM48821's I2C address is shown in Table 1. The I2C data register and its control bit names are shown in
Table 2. The data values for the volume control are shown in Table 3.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM48821’s I2C interface is powered up through the I2CVDD pin. The LM48821’s I2C interface operates at a
voltage level set by the I2CVDD pin. This voltage can be independent from the main power supply pin (VDD). This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 3.3V voltage regulator typically use a 10μF in parallel with a 0.1μF filter
capacitors to stabilize the regulator’s output, reduce noise on the regulated supply lines, and improve the
regulator’s transient response. However, their presence does not eliminate the need for a local 1.0μF tantalum
bypass capacitance connected between the LM48821’s supply pins and ground. Keep the length of leads and
traces that connect capacitors between the LM48821’s power supply pins and ground as short as possible.
ELIMINATING THE OUTPUT COUPLING CAPACITOR
The LM48821 features a low noise inverting charge pump that generates an internal negative supply voltage.
This allows the LM48821 to reference its amplifier outputs to ground instead of a half-supply voltage, like
traditional capacitivel-coupled headphone amplifiers. Because there is no DC bias voltage associated with either
stereo output, the large DC blocking capacitors (typically 220μF) are not necessary. The coupling capacitors are
replaced by two, small ceramic charge pump capacitors, saving board space and cost.
Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone
amplifiers, the headphone impedance and the output capacitor form a high pass filter that not only blocks the DC
component of the output, but also attenuates low frequencies, impacting the bass response. Because the
LM48821 does not require the output coupling capacitors, the low frequency response of the device is not
degraded.
In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the output
voltage swing and available dynamic range of the LM48821 when compared to a traditional capacitively-coupled
output headphone amplifier operating from the same supply voltage.
OUTPUT TRANSIENT ELIMINATED
The LM48821 contains advanced circuitry that virtually eliminates output transients (’clicks' and 'pops’). This
circuitry attenuates output transients when the supply voltage is first applied or when the part resumes operation
after using the shutdown mode.
POWER DISSIPATION
Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to
ensure a successful design. Equation 1 states the maximum power dissipation point for a single-ended amplifier
operating at a given supply voltage and driving a specified output load.
PDMAX = (2VDD)2 / (2π2RL)
(1)
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Since the LM48821 has two power amplifiers in one package, the maximum internal power dissipation point is
twice that of the number which results from Equation 1. Even with large internal power dissipation, the LM48821
does not require heat sinking over a large range of ambient temperatures. The maximum power dissipation point
obtained must not be greater than the power dissipation that results from Equation 2:
PDMAX = (TJMAX - TA) / (θJA)
(2)
For the DSBGA package, θJA = 105°C/W. TJMAX = 150°C for the LM48821. Depending on the ambient
temperature, TA, of the system surroundings, Equation 2 can be used to find the maximum internal power
dissipation supported by the IC packaging. If the result of Equation 1 is greater than that of Equation 2, then
either the supply voltage must be decreased, the load impedance increased or TA reduced. Power dissipation is
a function of output power and thus, if typical operation is not around the maximum power dissipation point, the
ambient temperature may be increased accordingly.
SELECTING EXTERNAL COMPONENTS
Optimizing the LM48821’s performance requires properly selecting external components. Though the LM48821
operates well when using external components with wide tolerances, best performance is achieved by optimizing
component values.
Charge Pump Capacitor Selection
Use low ESR (equivalent series resistance) (
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