LM49100
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LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
Mono Class AB Audio Sub-System with a TrueGround Headphone Amplifier
Check for Samples: LM49100
FEATURES
APPLICATIONS
•
•
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•
•
•
•
•
•
•
•
•
•
•
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1
2
•
Mono and Stereo Inputs
Thermal Overload Protection
True-Ground Headphone Drivers
I2C Control Interface
Input Mute Attenuation
2nd Stage Headphone Attenuator
32-Step Digital Volume Control
10 Operating Modes
Minimum External Components
Click and Pop Suppression
Micro-Power Shutdown
Available in Space-Saving 3mm x 3mm
25-Bump csBGA Package
RF Suppression
KEY SPECIFICATIONS
•
•
Power Output at VDD = 5V:
– Loudspeaker (LS):
– RL = 8Ω, THD+N ≤: 1% 1.275W
– Headphone (VDDHP = 2.8V):
– RL = 32Ω, THD+N ≤ 1%: 50mW
Shutdown current 0.01μA
Mobile Phones
PDAs
Laptops
Portable Electronics
DESCRIPTION
The LM49100 is a fully integrated audio subsystem
capable of delivering 1.275W of continuous average
power into a mono 8Ω bridged-tied load (BTL) with
1% THD+N and with a 5V power supply. The
LM49100 also has a stereo true-ground headphone
amplifier capable of 50mW per channel of continuous
average power into a 32Ω single-ended (SE) loads
with 1% THD+N.
The LM49100 has three input channels. One pair of
SE inputs can be used with a stereo signal. The other
input channel is fully differential and may be used
with a mono input signal. The LM49100 features a
32-step digital volume control and ten distinct output
modes. The mixer, volume control, and device mode
select are controlled through an I2C compatible
interface.
Thermal overload protection prevent the device from
being damaged during fault conditions. Superior click
and pop suppression eliminates audible transients on
power-up/down and during shutdown.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
www.ti.com
Typical Application
VDDLS
+
VDDLS
Audio
Input
CIN
1 PF MIN+
CIN
1 PF MIN-
CS1
4.7 PF
VDDLS
LS+
Mono Input
-60 dB - +12 dB
Class AB
+6 dB
LS
GND
Audio
Input
CIN
LIN
Mixer
and
Mode Select
Left Input
-54 dB - +18 dB
0.22 PF
Audio
Input
CIN
RIN
0 dB
-12 dB
-18 dB
-24 dB
Right Input
-54 dB - +18 dB
0.22
PF
2
VDDI C
+
0 dB
-12 dB
-18 dB
-24 dB
Bias
Click/Pop
Suppresion
BYPASS
CB
4.7 PF
HPL
HPR
AGND
VDDHP
VDDCP
2
VDDI C
I2C
BUS
SDA
SCL
2
ADDR
GND
VSSHP
VSSCP
+
C1N
C1P
4.7 PF
0.1 PF
GNDCP
C1
VIH
VIL
VDDCP
Charge Pump
I C
Interface
CAVSS
2.2 PF
2.2 PF
Figure 1. Typical Audio Amplifier Application Circuit
2
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Connection Diagrams
1
2
A
VDDCP
GNDCP
B
C1N
C
3
4
5
MIN+
BYPASS
RIN
C1P
MIN-
LIN
LS-
VSSCP
VSSHP
GND
ADDR
VDDLS
D
HPL
VDDHP
VDDI2C
SDA
LS+
E
HPR
VDDLS
AGND
GND
SCL
Figure 2. Top View
25-Bump csBGA
3mm × 3mm × 1mm
See NYA0025A Package
BUMP DESCRIPTIONS
Bump
Name
Description
A1
VDDCP
Positive Charge Pump Power Supply
A2
GNDCP
Charge Pump Ground
A3
MIN+
Positive Mono Input
A4
BYPASS
Half-Supply Bypass
A5
RIN
Right Input
B1
C1N
Negative Terminal – Charge Pump Flying
Capacitor
B2
C1P
Positive Terminal – Charge Pump Flying
Capacitor
B3
MIN-
Negative Mono Input
B4
LIN
Left Input
Negative Loudspeaker Output
B5
LS−
C1
VSSCP
Negative Charge Pump Power Supply
C2
VSSHP
Negative Headphone Power Supply
C3
GND
C4
ADDR
I2C Address Identification
C5
VDDLS
Loudspeaker Power Supply
D1
HPL
Ground
Left Headphone Output
D2
VDDHP
Positive Headphone Power Supply
D3
VDDI2C
I2C Power Supply
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BUMP DESCRIPTIONS (continued)
4
Bump
Name
D4
SDA
I2C Data
D5
LS+
Loudspeaker Output Positive
E1
HPR
Right Headphone Output
E2
VDDLS
Loudspeaker Power Supply
E3
AGND
Headphone Signal Ground (See Application
Information section).
E4
GND
Ground
E5
SCL
I2C Clock
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Description
Copyright © 2007–2013, Texas Instruments Incorporated
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LM49100
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2) (3)
Supply Voltage (Loudspeaker)
6V
Supply Voltage (Headphone)
3V
−65°C to +150°C
Storage Temperature
−0.3V to VDD + 0.3V
Input Voltage
Power Dissipation
(4)
Internally Limited
ESD Susceptibility
(5)
2000V
ESD Susceptibility
(6)
200V
Junction Temperature
150°C
Thermal Resistance
θJA (GR)
(1)
(2)
(3)
(4)
(5)
(6)
50.2°C/W
All voltages are measured with respect to the GND pin unless other wise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM49100, see power derating currents for more information.
Human body model, 100 pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF - 240pF discharged through all pins.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
Supply Voltage VDDLS
2.7V ≤ VDDLS ≤ 5.5V
Supply Voltage VDDHP
2.4 V ≤ VDDHP ≤ 2.9V
I2C Voltage (VDDI2C )
1.7V ≤ VDDI2C ≤ 5.5V
VDDHP ≤ VDDLS
VDDI2C ≤ VDDLS
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Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V
(1) (2)
The following specifications apply for all programmable gain set to 0 dB, CB = 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz
unless otherwise specified. Limits apply for TA = 25°C.
LM49100
Symbol
Parameter
Conditions
VDDLS = 3.0V
VDDHP = 2.8V
IDD
Supply Current
VDDLS = 3.6V
VDDHP = 2.8V
VDDLS = 5.0V
VDDHP = 2.8V
ISD
Shutdown Supply Current
VOS
Output Offset Voltage
Typical
Modes 2, 4, 6
VIN = 0V, No Load
3.4
mA
Modes 7, 10, 14
VIN = 0V, No Load
4.8
mA
Modes 1, 3, 5
VIN = 0V, No Load
2.9
4.3
mA (max)
Modes 2, 4, 6
VIN = 0V, No Load
3.5
5.4
mA (max)
Modes 7, 10, 14
VIN = 0V, No Load
4.8
7.4
mA (max)
Modes 1, 3, 5
VIN = 0V, No Load
3.1
mA
Modes 2, 4, 6
VIN = 0V, No Load
3.6
mA
Modes 7, 10, 14
VIN = 0V, No Load
5.0
mA
Mode 0
0.01
1
µA (max)
VIN = 0V, Mode 7, Mono
6.0
25
mV (max)
VIN = 0V, Mode 7, Headphone Gain = –24dB
2.2
5.5
mV
VIN = 0V, Mode 7, Headphone Gain = –18dB
2.4
VIN = 0V, Mode 7, Headphone Gain = –12dB
3.2
VDDLS = 3.0V
LS
f = 1kHz
Output Power
VDDLS = 3.6V
HP
f = 1kHz
(1)
(2)
(3)
(4)
6
Units
(Limits)
mA
HP
f = 1kHz
POUT
(4)
2.9
LS
f = 1kHz
Output Power
Limit
Modes 1, 3, 5
VIN = 0V, No Load
VIN = 0V, Mode 7, Headphone Gain = 0dB
POUT
(3)
7
mV (max)
mV
15
mV (max)
RL = 8Ω
1%
10%
425
525
mW
mW
RL = 16Ω
1%
10%
49
69
mW
mW
RL = 32Ω
1%
10%
35
44
mW
mW
RL = 8Ω
1%
10%
640
790
RL = 16Ω
1%
10%
49
72
RL = 32Ω
1%
10%
50
62
600
mW (min)
mW
mW
mW
46
mW (min)
mW
All voltages are measured with respect to the GND pin unless other wise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
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Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (1)(2) (continued)
The following specifications apply for all programmable gain set to 0 dB, CB = 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz
unless otherwise specified. Limits apply for TA = 25°C.
LM49100
Symbol
Parameter
Conditions
Typical
Output Power
THD+N
THD+N
THD+N
Total Harmonic Distortion +
Noise
Total Harmonic Distortion +
Noise
VDDLS = 3.6V
VDDLS = 5.0V
f = 1kHz
f = 1kHz
f = 1kHz
Units
(Limits)
mW
mW
RL = 16Ω
1%
10%
49
72
mW
mW
RL = 32Ω
1%
10%
53
62
mW
mW
Loudspeaker;
Mode 1,
RL = 8Ω,
POUT = 215mW
0.05
%
Headphone;
Mode 4,
RL = 32Ω,
POUT = 25mW
0.02
%
Loudspeaker;
Mode 1,
RL = 8Ω,
POUT = 320mW
0.05
%
Headphone;
Mode 4,
RL = 32Ω,
POUT = 25mW
0.02
%
Loudspeaker;
Mode 1,
RL = 8Ω,
POUT = 630mW
0.035
%
Headphone;
Mode 4,
RL = 32Ω,
POUT = 25mW
0.02
%
VDDLS = 5.0V
VDDLS = 3.0V
(4)
1275
1575
HP
f = 1kHz
Total Harmonic Distortion +
Noise
Limit
RL = 8Ω
1%
10%
LS
f = 1kHz
POUT
(3)
Headphone
eN
Noise
A-weighted, 0 dB, inputs
terminated to GND, output
referred
Mode 2, 10
12
µV
Mode 4, 7
13
µV
Mode 6, 14
16
µV
Loudspeaker
Mode 1
14
µV
Mode 3, 7, 10,
14
23
µV
Mode 5
27
µV
TON
Turn-on Time
26
ms
TOFF
Turn-off Time
1
ms
ZIN
Maximum gain setting
12.5
10
15
kΩ (min)
kΩ (max)
Maximum attenuation setting
110
90
130
kΩ (min)
kΩ (max)
Input Impedance
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Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (1)(2) (continued)
The following specifications apply for all programmable gain set to 0 dB, CB = 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz
unless otherwise specified. Limits apply for TA = 25°C.
LM49100
Symbol
Parameter
Conditions
(4)
Units
(Limits)
–52
–56
dB (min)
dB (max)
Input referred maximum gain
18
17.5
18.5
dB (min)
dB (max)
Input referred maximum
attenuation
−60
–58
–62
dB (min)
dB (max)
Input referred maximum gain
12
11.5
12.5
dB (min)
dB (max)
Headphone Mode 2, f = 217 Hz, VCM = 1 VPP,
RL = 32Ω
64
dB
Loudspeaker Mode 1, f = 217 Hz, VCM = 1 VPP,
RL = 8Ω
58
dB
Mono
Common Mode Rejection Ratio
Limit
−54
Volume Control
CMRR
(3)
Input referred maximum
attenuation
Stereo (Left
and Right
Channels)
AV
Typical
VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz
PSRR
Power Supply Rejection Ratio
PSRR
Power Supply Rejection Ratio
LS, Mode 1
90
dB
LS, Mode 3, 7, 10, 14
78
dB
LS, Mode 5
77
dB
VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz
LS, Mode 7, 10, 14
83
dB
VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz
PSRR
Power Supply Rejection Ratio
HP, Mode 2, 10
90
dB
HP, Mode 4, 7
88
dB
HP, Mode 6, 14
87
dB
VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz
PSRR
I2C
Power Supply Rejection Ratio
HP, Mode 2, 10
83
dB
HP, Mode 4, 7
83
dB
HP, Mode 6, 14
80
dB
(1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ VDDI2C ≤ 5.5V, unless otherwise specified.
Symbol
Parameter
Conditions
(3)
LM49100
Typical
(4)
t1
I2C Clock Period
2
Limits
Units
(Limits)
(2)
2.5
µs (min)
t2
I C Data Setup Time
100
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
t6
I2C Data Hold Time
100
ns (min)
VIH
I2C Input Voltage High
VIL
(1)
(2)
(3)
(4)
8
0.7xVDDI2C
2
2
I C Input Voltage Low
0.3xVDDI C
V (min)
V (max)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
Limits are specified to AOQL (Average Outgoing Quality Level).
Please refer to Figure 32 (I2C Timing Diagram).
Typicals are measured at 25°C and represent the parametric norm.
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I2C
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(1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ VDDI2C ≤ 2.2V, unless otherwise specified.
Symbol
Parameter
Conditions
(3)
LM49100
Typical
(4)
2
Limits
Units
(Limits)
(2)
t1
I C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
250
ns (min)
2
t3
I C Data Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
250
ns (min)
2
t6
I C Data Hold Time
VIH
I2C Input Voltage High
0.7xVDDI2C
V (min)
VIL
I2C Input Voltage Low
0.3xVDDI2C
V (max)
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
Limits are specified to AOQL (Average Outgoing Quality Level).
Please refer to Figure 32 (I2C Timing Diagram).
Typicals are measured at 25°C and represent the parametric norm.
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.6V, RL = 8Ω, PO = 320mW
BW = 22kHz, LS, Mode 1
THD+N vs Frequency
VDD = 3.6V, RL = 32Ω, PO = 25mW
HP, BW = 22kHz, Mode 4,7
10
10
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
0.001
20
200
2k
0.001
20
20k
Figure 3.
Figure 4.
THD+N vs Frequency
VDD = 3V, RL = 8Ω, PO = 215mW
BW = 22kHz, LS, Mode 1
THD+N vs Frequency
VDD = 3V, RL = 32Ω, PO = 25mW
BW = 22kHz, HP, Mode 4, 7
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
0.001
20
20k
10
10
0.001
200
2k
20
20k
FREQUENCY (Hz)
200
2k
20k
FREQUENCY (Hz)
Figure 5.
Figure 6.
THD+N vs Frequency
VDD = 5V, RL = 8Ω, PO = 630mW
BW = 22kHz, Loudspeaker, Mode 1
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 25mW
BW = 22kHz, Headphone, Mode 4,7
10
10
1
1
THD+N (%)
THD+N (%)
2k
FREQUENCY (Hz)
FREQUENCY (Hz)
0.1
0.1
0.01
0.001
20
0.01
200
2k
20k
0.001
20
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7.
10
200
Figure 8.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
RL = 32Ω, f = 1kHz
BW = 22kHz, HP, Mode 4
THD+N vs Output Power
RL = 8Ω, f = 1kHz
BW = 22kHz, LS, Mode 1
10
10
+3.6V
+3V
+5V
+3V
+3.6V
1
THD+N (%)
THD+N (%)
1
+5V
0.1
0.1
0.01
2
1
5
10
20
50
0.01
10
100
1000
10000
OUTPUT POWER (mW)
Figure 9.
Figure 10.
Output Power vs Supply Voltage
VDDHP = 2.8V, RL = 8Ω,
f = 1kHz, LS
Output Power vs Supply Voltage
VDDHP = 2.8V, RL = 32Ω,
f = 1kHz, HP
80
2000
70
1800
OUTPUT POWER (mW)
1600
OUTPUT POWER (mW)
100
OUTPUT POWER (mW)
THD+N = 10%
1400
1200
1000
800
THD+N = 1%
600
THD+N = 10%
60
50
THD+N = 1%
40
30
20
400
10
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
2.0
6.0
LOUDSPEAKER VOLTAGE SUPPLY (V)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
LOUDSPEAKER VOLTAGE SUPPLY (V)
Figure 11.
Figure 12.
Power Dissipation vs Output Power
VDD = 3.6V, RL = 8Ω,
f = 1kHz, Mode 1
Power Dissipation vs Output Power
VDD = 3V, RL = 8Ω,
f = 1kHz, Mode 1
250
400
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
350
300
250
200
150
100
200
150
100
50
50
0
0
0
100 200 300 400 500 600 700 800
0
100
200
300
400
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 13.
Figure 14.
500
600
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Typical Performance Characteristics (continued)
Supply Current vs VDDLS
VDDHP = 2.8V, Mode 1, 3, 5, No Load
5.0
600
4.5
SUPPLY CURRENT (mA)
POWER DISSIPATION (mW)
700
Power Dissipation vs Output Power
VDD = 5V, RL = 8Ω,
f = 1kHz, Mode 1
500
400
300
200
3.5
3.0
2.5
100
0
4.0
0
2.0
2.0
200 400 600 800 1000 1200 1400 1600
2.5
OUTPUT POWER (mW)
3.0
5.0
4.5
4.5
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
5.0
5.5
6.0
Supply Current vs VDDLS
VDDHP = 2.8V, Mode 7,10, 14, No Load
5.0
4.0
3.5
3.0
4.0
3.5
3.0
2.5
2.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.0
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDLS (V)
VDDLS ( V)
Figure 17.
Figure 18.
PSRR vs Frequency
RL = 32Ω, VRIPPLE = 200mVPP on VDDHP
VDDHP = 2.8V, CB = 4.7μF, Mode 2, 10, HP
PSRR vs Frequency
RL = 32Ω, VRIPPLE = 200mVPP on VDDHP
VDDHP = 2.8V, CB = 4.7μF, Mode 4, 7, HP
0
0
-10
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
4.5
Figure 16.
Supply Current vs VDDLS
VDDHP = 2.8V, Mode 2, 4, 6, No Load
12
4.0
VOLTAGE SUPPLY (V)
Figure 15.
2.0
2.0
3.5
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
RL = 32Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB = 4.7μF, Mode 2, 10, HP
0
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
0
-10
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21.
Figure 22.
PSRR vs Frequency
RL = 32Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB = 4.7μF, Mode 4, 7, HP
PSRR vs Frequency
RL = 32Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB = 4.7μF, Mode 6, 14, HP
0
0
-10
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR vs Frequency
RL = 32Ω, VRIPPLE = 200mVPP on VDDHP
VDDHP = 2.8V, CB = 4.7μF, Mode 6, HP
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
20k
FREQUENCY (Hz)
Figure 23.
Figure 24.
PSRR vs Frequency
RL = 8Ω, VRIPPLE = 200mVPP on VDDHP
VDDHP = 2.8V, CB = 4.7μF, Mode 7, 10, 14, LS+HP
PSRR vs Frequency
RL = 8Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB = 4.7μF, Mode 1, LS
0
0
-10
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
FREQUENCY (Hz)
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25.
Figure 26.
20k
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Typical Performance Characteristics (continued)
14
PSRR vs Frequency
RL = 8Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB = 4.7μF, Mode 3, LS
0
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
0
-10
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27.
Figure 28.
PSRR vs Frequency
RL = 8Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB = 4.7μF, Mode 5, LS
Crosstalk vs Frequency
PO = 12mW, f = 1kHz, Mode 4, HP
0
0
-10
-10
-20
-20
-30
-30
CROSSTALK (dB)
PSRR (dB)
PSRR (dB)
PSRR vs Frequency
RL = 8Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB = 4.7μF, Mode 7, 10, 14, LS+HP
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29.
Figure 30.
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LM49100 Control Tables
Table 1. I2C Control Register Table (1)
Modes Control
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
MC3
MC2
MC1
MC0
0
0
HPR_SD
HPVC1
HPVC0
HP Volume (Gain)
Control
0
1
INPUT_MU
TE
Mono Volume Control
1
0
0
MV4
MV3
MV2
MV1
MV0
Left Volume (Gain)
Control
1
1
0
LV4
LV3
LV2
LV1
LV0
Right Volume (Gain)
Control
1
1
1
RV4
RV3
RV2
RV1
RV0
(1)
The LM49100 is controlled through an I2C compatible interface. The I2C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin = 1).
Table 2. Headphone Attenuation Control (1)
(1)
Gain Select
HPVC1
HPVC0
Gain, dB
0
0
0
0
1
0
1
−12
2
1
0
−18
3
1
1
−24
The following bits have added for extra headphone output attenuation:
Table 3. Output Mode Selection (1)
(1)
Output
Mode
Number
MC3
MC2
MC1
MC0
0
0
0
0
1
0
0
0
2
0
0
3
0
4
0
5
Handsfree Mono Output
Right HP Output
Left HP Output
0
SD
SD
SD
1
2 × GM × M
SD
SD
1
0
SD
GHP × (GM × M)
GHP × (GM × M)
0
1
1
2 × (GL × L + GR × R)
SD
SD
1
0
0
SD
GHP × (GR × R)
GHP × (GL × L)
0
1
0
1
2 × (GL × L + GR × R + GM ×
M)
SD
SD
6
0
1
1
0
SD
GHP × (GR × R + GM × M)
GHP × (GL × L + GM × M)
7
0
1
1
1
2 × (GL × L + GR × R)
GHP × (GR × R)
GHP × (GL × L)
10
1
0
1
0
2 × (GL × L + GR × R)
GHP × (GM × M)
GHP × (GM × M)
14
1
1
1
0
2 × (GL × L + GR × R)
GHP × (GR × R + GM × M)
GHP × (GL × L + GM × M)
GL — Left channel gain
GR — Right channel gain
GM — Mono channel gain
GHP — Headphone Amplifier gain
R — Right input signal
L — Left input signal
SD — Shutdown
M — Mono input signal
Table 4. Mono/Stereo Left/Stereo Right Input Gain Control
Volume Step
MV4/LV4/RV4
MV3/LV3/RV3
MV2/LV2/RV2
MV1/LV1/RV1
MV0/LV0/RV0
R/L Gain, dB
MonoGain, dB
1
0
0
0
0
0
−54
−60
2
0
0
0
0
1
−47
−53
3
0
0
0
1
0
−40.5
−46.5
4
0
0
0
1
1
−34.5
−40.5
5
0
0
1
0
0
−30.0
−36
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Table 4. Mono/Stereo Left/Stereo Right Input Gain Control (continued)
Volume Step
MV4/LV4/RV4
MV3/LV3/RV3
MV2/LV2/RV2
MV1/LV1/RV1
MV0/LV0/RV0
R/L Gain, dB
MonoGain, dB
6
0
0
1
0
1
−27
−33
7
0
0
1
1
0
−24
−30
8
0
0
1
1
1
−21
−27
9
0
1
0
0
0
−18
−24
10
0
1
0
0
1
−15
−21
11
0
1
0
1
0
−13.5
−19.5
12
0
1
0
1
1
−12
−18
13
0
1
1
0
0
−10.5
−16.5
14
0
1
1
0
1
−9
−15
15
0
1
1
1
0
−7.5
−13.5
16
0
1
1
1
1
−6
−12
17
1
0
0
0
0
−4.5
−10.5
18
1
0
0
0
1
−3
−9
19
1
0
0
1
0
−1.5
−7.5
20
1
0
0
1
1
0
−6
21
1
0
1
0
0
1.5
−4.5
22
1
0
1
0
1
3
−3
23
1
0
1
1
0
4.5
−1.5
24
1
0
1
1
1
6
0
25
1
1
0
0
0
7.5
1.5
26
1
1
0
0
1
9
3
27
1
1
0
1
0
10.5
4.5
28
1
1
0
1
1
12
6
29
1
1
1
0
0
13.5
7.5
30
1
1
1
0
1
15
9
31
1
1
1
1
0
16.5
10.5
32
1
1
1
1
1
18
12
APPLICATION INFORMATION
MINIMIZING CLICK AND POP
To minimize the audible click and pop heard through a headphone, maximize the input signal through the
corresponding volume (gain) control registers and adjust the output amplifier gain accordingly to achieve the
user’s desired signal gain. For example, setting the output of the headphone amplifier to -24dB and setting the
input volume control gain to 24dB will reduce the output offset from 7mV (typical) to 2.2mV (typical). This will
reduce the audible click and pop noise significantly while maintaining a 0dB signal gain.
SIGNAL GROUND NOISE
The LM49100 has proprietary suppression circuitry, which provides an additional -50dB (typical) attenuation of
the headphone ground noise and its incursion into the headphone. For optimum utilization of this feature the
headphone jack ground should connect to the AGND (E3) bump.
HPL
HPR
AGND
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I2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADDR: This is the address select input pin.
I2C COMPATIBLE INTERFACE
The LM49100 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
LM49100's I2C compatible interface supports standard (100kHz) and fast (400kHz) I2C modes. In this discussion,
the master is the controlling microcontroller and the slave is the LM49100.
The I2C address for the LM49100 is determined using the ADDR pin. The LM49100's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ADDR pin is logic LOW; and X1 = 1, if ADDR pin
is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM49100's chip address
can be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 31. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is HIGH.
After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM49100 has received the address correctly, then it
holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock
pulse, then the master should abort the rest of the data transfer to the LM49100.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
After the data byte is sent, the master must check for another acknowledge to see if the LM49100 received the
data.
If the master has more data bytes to send to the LM49100, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH.
The data line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (VDDI2C)
The LM49100's I2C interface is powered up through theVDD I2C pin. The LM49100's I2C interface operates at a
voltage level set by the VDD I2C pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Figure 31. I2C Bus Format
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Figure 32. I2C Timing Diagram
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8Ω LOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by an 8Ω load from 158.3mW to 156.4mW. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
The LM49100 drives a load, such as a loudspeaker, connected between outputs, LS+ and LS-.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between LS- and LS+ and driven differentially (commonly referred to as
”bridge mode”).
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing LS- and LS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a
single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation
and may permanently damage loads such as loudspeakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM49100 has a pair of bridged-tied amplifiers driving a handsfree loudspeaker, LS. The
maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From
Equation 1, assuming a 5V power supply and an 8Ω load, the maximum MONO power dissipation is 634mW.
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PDMAX-LS = 4(VDD)2/ (2π2 RL): Bridge Mode
(1)
The LM49100 also has a pair of single-ended amplifiers driving stereo headphones, HPR and HPL. The
maximum internal power dissipation for HPR and HPL is given by Equation 2. Assuming a 2.8V power supply
and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 49mW, or 99mW total.
PDMAX-HPL = 4(VDDHP)2 / (2π2 RL): Single-ended Mode
(2)
The maximum internal power dissipation of the LM49100 occurs when all three amplifiers pairs are
simultaneously on; and is given by Equation 3.
PDMAX-TOTAL = PDMAX-LS + PDMAX-HPL + PDMAX-HPR
(3)
The maximum power dissipation point given by Equation 3 must not exceed the power dissipation given by
Equation 4:
PDMAX = (TJMAX - TA) / θJA
(4)
The LM49100's TJMAX = 150°C. In the csBGA package, the LM49100's θJA is 50.2°C/W. At any given ambient
temperature TA, use Equation 4 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 4 and substituting PDMAX-TOTAL for PDMAX results in Equation 5. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the
LM49100's maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
(5)
For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows
maximum mono power dissipation without exceeding the maximum junction temperature is approximately 114°C
for the csBGA package.
TJMAX = PDMAX-TOTAL θJA + TA
(6)
Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM49100's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 3 is greater than that of Equation 4,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 4.7µF tantalum bypass capacitor and a parallel
0.1µF ceramic capacitor connected between the LM49100's supply pin and ground. Keep the length of leads and
traces that connect capacitors between the LM49100's power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (CIN in Figure 1). A high
value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases,
however, the loudspeakers used in portable systems, whether internal or external, have little ability to reproduce
signals below 150Hz. Applications using loudspeakers and headphones with this limited frequency response
reap little improvement by using large input capacitor.
The internal input resistor (Ri), typical 12.5kΩ, and the input capacitor (CIN) produce a high pass filter cutoff
frequency that is found using Equation 7.
fc = 1 / (2πRiCIN)
(7)
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Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how fast the LM49100 settles to quiescent operation, its
value is critical when minimizing turn-on pops. Choosing CB equal to 2.2µF along with a small value of Ci (in the
range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above, choosing
CIN no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in
the range of 4 to 5 times the value of CIN . This ensures that output transients are eliminated when power is first
applied or the LM49100 resumes operation after shutdown.
Demo Board Schematic
Figure 33. Demo Board Schematic
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Demonstration Board Layout
Figure 34. Signal 1 Layer
Figure 35. Signal 2 Layer
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Figure 36. Top Layer
Figure 37. Top Overlay
22
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Figure 38. Bottom Layer
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Figure 39. Bottom Overlay
REVISION HISTORY
24
Rev
Date
1.0
06/21/07
Initial release.
Description
1.1
06/28/07
Changed the mktg outline from TLA25XXX to GRA25A.
1.2
08/09/07
Replaced some curves.
1.3
08/13/07
Changed the f = 1kHz into f = 217Hz (PSRR) in the Electrical Characteristics
table.
1.4
08/14/07
Edited Table 1.
1.5
09/18/07
Edited the Schematic Diagram.
F
05/02/2013
Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM49100GR/NOPB
ACTIVE
csBGA
NYA
25
1000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GC9
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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