LM5145RGYR

LM5145 LM5145 SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 www.ti.com LM5145 75-V Synchronous Buck DC/DC Controller With Wide Duty Cycle Range 1 Features 2 Applications • • • • • • • • • • • Versatile synchronous buck DC/DC controller – Wide input voltage range of 6 V to 75 V – 0.8-V reference with ±1% feedback accuracy – Adjustable output voltage from 0.8 V to 60 V – 40-ns tON(min) for high VIN / VOUT ratio – 140-ns tOFF(min) for low dropout – Optimized for CISPR 32 requirements Switching frequency from 100 kHz to 1 MHz – SYNC In and SYNC Out capability – Selectable diode emulation or FPWM 7.5-V gate drivers for standard VTH MOSFETs – 14-ns adaptive dead-time control – 2.3-A source and 3.5-A sink capability – Low-side soft start for prebiased start-up Fast line and load transient response – Voltage-mode control with line feedforward – High gain-bandwidth error amplifier Inherent protection features for robust design – Adjustable output voltage soft start – Hiccup-mode overcurrent protection – Input UVLO with hysteresis – VCC and gate-drive UVLO protection – Precision enable input and open-drain PGOOD indicator for sequencing and control – Thermal shutdown protection with hysteresis 20-pin VQFN package with wettable flanks Create a custom design using the LM5145 with WEBENCH® Power Designer 3 Description The LM5145 75-V synchronous buck controller regulates from a high input voltage source or from an input rail subject to high voltage transients, minimizing the need for external surge suppression components. A high-side switch minimum on-time of 40 ns gives large step-down ratios, enabling the direct step-down conversion from a 48-V nominal input to low-voltage rails for reduced system complexity and solution cost. The LM5145 continues to operate during input voltage dips as low as 6 V, at nearly 100% duty cycle if needed, making it an excellent choice for highperformance industrial control, robotic, datacom, and RF power applications. Forced-PWM (FPWM) operation eliminates switching frequency variation to minimize EMI, while userselectable diode emulation lowers current consumption at light-load conditions. The adjustable switching frequency as high as 1 MHz can be synchronized to an external clock source to eliminate beat frequencies in noise-sensitive applications. Device Information PART NUMBER LM5145 (1) VIN Remote radio unit (RRU) and BTS Networking and computing power Non-isolated PoE and IP cameras Industrial motor drives PACKAGE(1) VQFN (20) BODY SIZE (NOM) 4.50 mm × 3.50 mm For all available packages, see the orderable addendum at the end of the data sheet. EN VIN VOUT VIN SYNC In RC2 RFB1 SYNC Out CC1 CC3 EN/UVLO SYNCIN Q1 HO SYNCOUT BST CBST COMP RC1 CC2 LM5145 FB Q2 LO RT CSS VOUT SW CIN RFB2 RRT LF COUT VCC SS/TRK CVCC AGND PGND PGOOD PG GND ILIM RILIM Typical Application Circuit and Efficiency Performance, VOUT = 5 V An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: LM5145 1 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Pin Configuration and Functions...................................4 6.1 Wettable Flanks.......................................................... 5 7 Specifications.................................................................. 6 7.1 Absolute Maximum Ratings........................................ 6 7.2 ESD Ratings............................................................... 6 7.3 Recommended Operating Conditions.........................7 7.4 Thermal Information....................................................7 7.5 Electrical Characteristics.............................................8 7.6 Switching Characteristics..........................................10 7.7 Typical Characteristics.............................................. 11 8 Detailed Description......................................................16 8.1 Overview................................................................... 16 8.2 Functional Block Diagram......................................... 16 8.3 Feature Description...................................................17 8.4 Device Functional Modes..........................................25 9 Application and Implementation.................................. 27 9.1 Application Information............................................. 27 9.2 Typical Applications.................................................. 37 10 Power Supply Recommendations..............................54 11 Layout........................................................................... 55 11.1 Layout Guidelines................................................... 55 11.2 Layout Example...................................................... 58 12 Device and Documentation Support..........................60 12.1 Device Support....................................................... 60 12.2 Documentation Support.......................................... 61 12.3 Receiving Notification of Documentation Updates..61 12.4 Support Resources................................................. 61 12.5 Trademarks............................................................. 62 12.6 Electrostatic Discharge Caution..............................62 12.7 Glossary..................................................................62 13 Mechanical, Packaging, and Orderable Information.................................................................... 63 4 Revision History Changes from Revision A (June 2020) to Revision B (November 2020) Page • Changed ILIM from 0 V to -1 V in the Absolute Maxmium Ratings ................................................................... 6 Changes from Revision * (June 2017) to Revision A (June 2020) Page • Updated list of bullets in the Features ............................................................................................................... 1 • Updated the numbering format for tables, figures and cross-references throughout the document...................1 • Corrected equation in Table 9-4 .......................................................................................................................31 • Added conducted EMI plots..............................................................................................................................40 • Updated Section 11.2 .......................................................................................................................................58 • Added Table 12-1 in Section 12 .......................................................................................................................60 • Added Table 12-1 in Section 12 .......................................................................................................................60 • Updated Section 12.2 ...................................................................................................................................... 61 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 5 Description (continued) Measuring the voltage drop across the low-side MOSFET or with an optional current sense resistor gives cycleby-cycle overcurrent protection. The LM5145 voltage-mode controller with line feedforward drives external highside and low-side N-channel power switches with robust 7.5-V gate drivers suitable for standard-threshold MOSFETs. Adaptively-timed gate drivers with 2.3-A source and 3.5-A sink capability minimize body diode conduction during switching transitions, reducing switching losses and improving thermal performance when driving MOSFETs at high input voltage and high frequency. The LM5145 can be powered from the output of the switching regulator or another available source, further improving efficiency. A 180° out-of-phase clock output relative to the internal oscillator at SYNCOUT works well for cascaded or multichannel power supplies to reduce input capacitor ripple current and EMI filter size. Additional features of the LM5145 include a configurable soft start, an open-drain power-good monitor for fault reporting and output monitoring, monotonic start-up into prebiased loads, integrated VCC bias supply regulator and bootstrap diode, external power supply tracking, precision enable input with hysteresis for adjustable line undervoltage lockout (UVLO), hiccup-mode overload protection, and thermal shutdown protection with automatic recovery. The LM5145 controller is offered in a 4.5-mm × 3.5-mm thermally enhanced, 20-pin VQFN package with additional spacing for high-voltage pins and wettable flanks for optical inspection of solder joint fillets. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 3 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 EN/UVLO VIN 1 20 6 Pin Configuration and Functions RT 2 19 SW SS/TRK 3 18 HO COMP 4 17 BST FB 5 16 NC AGND 6 15 EP SYNCOUT 7 14 VCC SYNCIN 8 13 LO NC 9 12 PGND 10 11 PGOOD ILIM Exposed Pad (EP) Connect Exposed Pad on bottom to AGND and PGND on the PCB. Figure 6-1. RGY Package 20-Pin VQFN With Wettable Flanks Top View Table 6-1. Pin Functions PIN NO. 4 NAME I/O(1) DESCRIPTION 1 EN/UVLO I Enable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the controller is in the shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V and less than 1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK voltage can ramp and pulse-width modulated gate-drive signals are delivered to the HO and LO pins. A 10μA current source is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO resistor divider to provide hysteresis. Hysteresis can be adjusted by varying the resistance of the external divider. 2 RT I Oscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and the AGND. TI recommends a maximum oscillator frequency of 1 MHz. An RT pin resistor is required even when using the SYNCIN pin to synchronize to an external clock. 3 SS/TRK I Soft-start and voltage-tracking pin. An external capacitor and an internal 10-μA current source set the ramp rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V, the amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby and fault conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB falls due to a load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery when the fault is removed. Voltage tracking can be implemented by connecting a low impedance reference between 0 V and 0.8 V to the SS/TRK pin. The 10-µA SS/TRK charging current flows into the reference and produces a voltage error if the impedance is not low. Connect a minimum capacitance from SS/TRK to AGND of 2.2 nF. 4 COMP O Low impedance output of the internal error amplifier. Connect the loop compensation network between the COMP pin and the FB pin. 5 FB I Feedback connection to the inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V. 6 AGND P Analog ground. Return for the internal 0.8-V voltage reference and analog circuits. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 Table 6-1. Pin Functions (continued) PIN NO. 7 NAME SYNCOUT I/O(1) DESCRIPTION O Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-side FET gate drive. Connect SYNCOUT of the master LM5145 to the SYNCIN pin of a second LM5145 to operate two controllers at the same frequency with 180° interleaved high-side FET switch turn-on transitions. Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating from an external clock that is different from the free-running frequency set by the RT resistor. Dual function pin for providing an optional clock input and for enabling diode emulation by the low-side MOSFET. Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode emulation by the low-side MOSFET is disabled when the controller is synchronized to an external clock, and negative inductor current can flow in the low-side MOSFET with light loads. A continuous logic low state at the SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode emulation results in discontinuous mode operation (DCM) at light loads, which improves efficiency. A logic high state at the SYNCIN pin disables diode emulation producing forced-PWM (FPWM) operation. During soft-start when SYNCIN is high or a clock signal is present, the LM5145 operates in diode emulation mode until the output is in regulation, then gradually increases the SW zero-cross threshold, resulting in a gradual transition from DCM to FPWM. 8 SYNCIN I 9 NC — No electrical connection. 10 PGOOD O Power Good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin is within a specified tolerance window centered at 0.8 V. 11 ILIM I Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an external resistor programs the threshold voltage for valley current limiting. The opposite end of the threshold adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing or to a current sense resistor connected to the source of the low-side FET. 12 PGND P Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-side MOSFET or the ground side of a shunt resistor. 13 LO P Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through a short, low inductance path. O Output of the 7.5-V bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close as possible to the controller. Controller bias can be supplied from an external supply that is greater than the internal VCC regulation voltage. Use caution when applying external bias to ensure that the applied voltage is not greater than the minimum VIN voltage and does not exceed the VCC pin maximum operating rating, see Section 7.3. 14 VCC 15 EP — Pin internally connected to exposed pad of the package. Electrically isolated. 16 NC — No electrical connection. 17 BST O Bootstrap supply for the high-side gate driver. Connect to the bootstrap (boot) capacitor. The bootstrap capacitor supplies current to the high-side FET gate and must be placed as close as possible to controller. If an external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the cathode of the diode to the BST pin and anode to VCC. 18 HO P High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low inductance path. 19 SW P Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the highside MOSFET and the drain terminal of the low-side MOSFET using short, low inductance paths. 20 VIN P Supply voltage input for the VCC LDO regulator. — EP — Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal resistance. (1) P = Power, G = Ground, I = Input, O = Output. 6.1 Wettable Flanks 100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins and terminals that are easily viewed. It is therefore difficult to visually determine whether or not the package is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM5145 is assembled using a 20-pin VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 5 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 7 Specifications 7.1 Absolute Maximum Ratings Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted).(1) Input voltages MIN MAX UNIT VIN –0.3 105 V SW –1 105 SW (20-ns transient) –5 105 ILIM –1 105 EN/UVLO –0.3 105 VCC –0.3 14 FB, COMP, SS/TRK, RT –0.3 6 SYNCIN –0.3 14 BST –0.3 115 BST to VCC Output voltages BST to SW –0.3 VCC to BST (20-ns transient) 14 7 LO (20-ns transient) –3 PGOOD –0.3 14 150 °C –55 150 °C Operating junction temperature, TJ Storage temperature, Tstg (1) V 105 Stresses beyond those listed under Section 7.1 may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 7.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 7.3 Recommended Operating Conditions Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted).(1) MIN VI Input voltages VO Output voltages NOM MAX VIN 6 75 SW –1 75 ILIM 0 75 External VCC bias rail 8 13 EN/UVLO –0.3 75 BST –0.3 88 BST to VCC 75 BST to SW 5 13 PGOOD Sink/source currents TJ Operating junction temperature (1) V V 13 SYNCOUT ISINK, ISRC UNIT –1 1 PGOOD 2 –40 125 mA °C Section 7.3 are conditions under which the device is intended to be functional. For specifications and test conditions, see Section 7.5. 7.4 Thermal Information LM5145 THERMAL METRIC(1) RGY (VQFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT ψJB RθJC(bot) (1) 36.8 °C/W 28 °C/W 11.8 °C/W Junction-to-top characterization parameter 0.4 °C/W Junction-to-board characterization parameter 11.7 °C/W Junction-to-case (bottom) thermal resistance 2.1 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 7 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 7.5 Electrical Characteristics Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. VIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 75 V 1.8 2.1 mA INPUT SUPPLY VIN Operating input voltage range IQ-RUN Operating input current, not switching VEN/UVLO = 1.5 V, VSS/TRK = 0 V 6 IQ-STBY Standby input current VEN/UVLO = 1 V 1.75 2 mA IQ-SDN Shutdown input current VEN/UVLO = 0 V, VVCC < 1 V 13.5 16 µA 7.5 7.7 V 0.25 0.63 V VCC REGULATOR VVCC VCC regulation voltage VSS/TRK = 0 V, 9 V ≤ VVIN ≤ 75 V, 0 mA < IVCC ≤ 20 mA VVCC-LDO VIN to VCC dropout voltage VVIN = 6 V, VSS/TRK = 0 V, IVCC = 20 mA 7.3 ISC-LDO VCC short-circuit current VSS/TRK = 0 V, VVCC = 0 V 40 50 70 mA VVCC-UV VCC undervoltage threshold VVCC rising 4.8 4.93 5.2 V VVCC-UVH VCC undervoltage hysteresis Rising threshold – falling threshold VVCC-EXT Minimum external bias supply voltage Voltage required to disable VCC regulator IVCC External VCC input current, not switching 0.26 V 8 V VSS/TRK = 0 V, VVCC = 13 V 2.1 mA ENABLE AND INPUT UVLO V SDN Shutdown to standby threshold VEN/UVLO rising V SDN-HYS Shutdown threshold hysteresis EN/UVLO rising – falling threshold V EN Standby to operating threshold VEN/UVLO rising IEN-HYS Standby to operating hysteresis VEN/UVLO = 1.5 V 0.42 V 50 mV 1.164 1.2 1.236 V 9 10 11 µA 800 808 mV 0.1 µA ERROR AMPLIFIER VREF FB reference voltage FB connected to COMP 792 IFB-BIAS FB input bias current VFB = 0.8 V –0.1 VCOMP-OH COMP output high voltage VFB = 0 V, COMP sourcing 1 mA VCOMP-OL COMP output low voltage COMP sinking 1 mA AVOL DC gain 94 dB GBW Unity gain bandwidth 6.5 MHz 5 V 0.3 V SOFT-START AND VOLTAGE TRACKING ISS SS/TRK capacitor charging current VSS/TRK = 0 V RSS SS/TRK discharge FET resistance VEN/UVLO = 1 V, VSS/TRK = 0.1 V VSS-FB SS/TRK to FB offset VSS-CLAMP SS/TRK clamp voltage 8.5 10 12 11 –15 VSS/TRK – VFB, VFB = 0.8 V µA Ω 15 115 mV mV POWER GOOD INDICATOR 8 PGUTH FB upper threshold for PGOOD high to low % of VREF, VFB rising 106% 108% 110% PGLTH FB lower threshold for PGOOD high to low % of VREF, VFB falling 90% 92% 94% PGHYS_U PGOOD upper threshold hysteresis % of VREF 3% PGHYS_L PGOOD lower threshold hysteresis % of VREF 2% TPG-RISE PGOOD rising filter FB to PGOOD rising edge 25 µs TPG-FALL PGOOD falling filter FB to PGOOD falling edge 25 µs VPG- OL PGOOD low state output voltage VFB = 0.9 V, IPGOOD = 2 mA 150 mV IPG-OH PGOOD high state leakage current VFB = 0.8 V, VPGOOD = 13 V 100 nA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. VIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCILLATOR FSW1 Oscillator Frequency – 1 RRT = 100 kΩ FSW2 Oscillator Frequency – 2 RRT = 25 kΩ FSW3 Oscillator Frequency – 3 RRT = 12.5 kΩ 100 380 400 kHz 420 780 kHz kHz SYNCHRONIZATION INPUT AND OUTPUT FSYNC SYNCIN external clock frequency range VSYNC-IH Minimum SYNCIN input logic high VSYNC-IL Maximum SYNCIN input logic low RSYNCIN SYNCIN input resistance tSYNCI-PW SYNCIN input minimum pulsewidth VSYNCO-OH SYNCOUT high state output voltage VSYNCO-OL SYNCOUT low state output voltage % of nominal frequency set by RRT –20% +50% 2 V 0.8 VSYNCIN = 3 V Minimum high state or low state duration ISYNCOUT = –1 mA (sourcing) 20 50 ns 3 V ISYNCOUT = 1 mA (sinking) tSYNCOUT Delay from HO rising to SYNCOUT leading edge VSYNCIN = 0 V, TS = 1/FSW, FSW set by RRT tSYNCIN Delay from SYNCIN leading edge to HO rising 50% to 50% V kΩ 0.4 V TS/2 – 140 ns 150 ns BOOTSTRAP DIODE AND UNDERVOLTAGE THRESHOLD VBST-FWD Diode forward voltage, VCC to BST VCC to BST, BST pin sourcing 20 mA IQ-BST BST to SW quiescent current, not switching VSS/TRK = 0 V, VSW = 48 V, VBST = 54 V VBST-UV BST to SW undervoltage detection VBST-HYS BST to SW undervoltage hysteresis 0.75 0.9 V 80 µA VBST – VSW falling 3.4 V VBST – VSW rising 0.42 V PWM CONTROL tON(MIN) Minimum controllable on-time VBST – VSW = 7 V, HO 50% to 50% tOFF(MIN) Minimum off-time VBST – VSW = 7 V, HO 50% to 50% DC100kHz DC400kHz Maximum duty cycle VRAMP(min) Ramp valley voltage (COMP at 0% duty cycle) kFF PWM feedforward gain (VIN / VRAMP) 40 60 ns 140 200 ns FSW = 100 kHz, 6 V ≤ VVIN ≤ 60 V 98% 99% FSW = 400 kHz, 6 V ≤ VVIN ≤ 60 V 90% 94% 6 V ≤ VVIN ≤ 75 V 300 mV 15 V/V OVERCURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING IRS ILIM source current, RSENSE mode Low voltage detected at ILIM IRDSON ILIM source current, RDS(on) mode SW voltage detected at ILIM, TJ = 25°C 90 100 110 µA 180 200 220 µA IRDSONTC ILIM current tempco RDS-ON mode 4500 ppm/°C IRSTC ILIM current tempco RSENSE mode 0 ppm/°C VILIM-TH ILIM comparator threshold at ILIM –8 –2 3.5 mV SHORT-CIRCUIT PROTECT (SCP) – DUTY CYCLE CLAMP VCLAMP-OS Clamp offset voltage – no current limiting VCLAMP-MIN Minimum clamp voltage CLAMP to COMP steady state offset voltage 0.2 + VVIN/75 V CLAMP voltage with continuous current limiting 0.3 + VVIN/150 V HICCUP MODE FAULT PROTECTION CHICC-DEL Hiccup mode activation delay Clock cycles with current limiting before hiccup off-time activated CHICCUP Hiccup mode off-time after activation Clock cycles with no switching followed by SS/TRK release 128 cycles 8192 cycles Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 9 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. VIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIODE EMULATION VZCD-SS Zero-cross detect (ZCD) soft-start ramp ZCD threshold measured at SW pin 50 clock cycles after first HO pulse VZCD- DIS Zero-cross detect disable threshold (CCM) ZCD threshold measured at SW pin 1000 clock cycles after first HO pulse VDEM-TH Diode emulation zero-cross threshold Measured at SW with VSW rising –5 0 mV 200 mV 0 5 mV GATE DRIVERS RHO-UP HO high-state resistance, HO to BST VBST – VSW = 7 V, IHO = –100 mA 1.5 Ω RHO-DOWN HO low-state resistance, HO to SW VBST – VSW = 7 V, IHO = 100 mA 0.9 Ω RLO-UP LO high-state resistance, LO to VCC VBST – VSW = 7 V, ILO = –100 mA 1.5 Ω RLO-DOWN LO low-state resistance, LO to PGND VBST – VSW = 7 V, ILO = 100 mA 0.9 Ω IHOH, ILOH HO, LO source current VBST – VSW = 7 V, HO = SW, LO = AGND 2.3 A IHOL, ILOL HO, LO sink current VBST – VSW = 7 V, HO = BST, LO = VCC 3.5 A TJ rising 175 °C 20 °C THERMAL SHUTDOWN TSD Thermal shutdown threshold TSD-HYS Thermal shutdown hysteresis (1) (2) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in Section 7.4. 7.6 Switching Characteristics Typical values correspond to TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THO-TR TLO-TR HO, LO rise times VBST – VSW = 7 V, CLOAD = 1 nF, 20% to 80% 7 ns THO-TF TLO-TF HO, LO fall times VBST – VSW = 7 V, CLOAD = 1 nF, 80% to 20% 4 ns THO-DT HO turn-on dead time VBST – VSW = 7 V, LO off to HO on, 50% to 50% 14 ns TLO-DT LO turn-on dead time VBST – VSW = 7 V, HO off to LO on, 50% to 50% 14 ns 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 7.7 Typical Characteristics VVIN = 48 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted). 100 100 95 90 80 85 80 VIN = 12V VIN = 24V VIN = 36V VIN = 48V VIN = 60V VIN = 75V 75 70 Efficiency (%) Efficiency (%) 90 5 VOUT = 5 V 10 Output Current (A) VSYNCIN = VVCC See Figure 9-5 15 RRT = 43.2 kΩ VIN = 12V VIN = 24V VIN = 36V VIN = 48V VIN = 60V VIN = 75V 20 0.1 0.5 VOUT = 5 V 1 Output Current (A) VSYNCIN = 0 V See Figure 9-5 5 10 20 FSW = 230 kHz RRT = 43.2 kΩ Figure 7-2. Efficiency vs Load, DCM Figure 7-1. Efficiency vs Load, CCM 100 100 95 Efficiency (%) 95 Efficiency (%) 50 30 20 FSW = 230 kHz 60 40 65 0 70 90 85 VIN = 14V VIN = 18V VIN = 24V VIN = 36V VIN = 48V 80 90 85 80 VIN = 36V VIN = 48V VIN = 60V VIN = 75V 75 70 75 0 2 4 6 Output Current (A) VOUT = 12 V 8 FSW = 400 kHz See Figure 9-20 0 10 RRT = 24.9 kΩ 1 2 3 Output Current (A) VOUT = 24 V 4 5 FSW = 440 kHz See Figure 9-33 RRT = 22.6 kΩ Figure 7-4. Efficiency vs Load, CCM Figure 7-3. Efficiency vs Load, CCM 0.808 100 0.806 60 40 VIN = 6V VIN = 12V VIN = 24V VIN = 36V VIN = 48V 20 0 0 2 4 6 Output Current (A) VOUT = 1.1 V See Figure 9-46 8 10 Feedback Voltage (V) Efficiency (%) 80 0.804 0.802 0.8 0.798 0.796 0.794 0.792 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 FSW = 300 kHz RRT = 33.2 kΩ Figure 7-6. FB Voltage vs Junction Temperature Figure 7-5. Efficiency vs Load, CCM Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 11 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 40 140 120 100 80 60 40 20 TOFF(min) 0 -40 TON(min) VIN Shutdown Quiescent Current (PA) Min On-Time, Min Off-Time (ns) 160 30 20 10 40°C -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 0 110 125 20 40 60 Input Voltage (V) VSW = 0 V Figure 7-7. tON(min) and tOFF(min) vs Junction Temperature VIN Operating Quiescent Current (mA) VIN Standby Quiescent Current (mA) 2 1.8 1.6 40°C 100 VEN/UVLO = 0 V 25°C 125°C 2 1.8 1.6 40°C 25°C 125°C 1.4 0 20 40 60 Input Voltage (V) VSW = 0 V 80 0 100 VEN/UVLO = 1 V 20 VSW = 0 V 40 60 Input Voltage (V) VEN/UVLO = VVIN 80 100 VSS/TRK = 0 V Figure 7-10. IQ-OPERATING (Non-switching) vs Input Voltage Figure 7-9. IQ-STANDBY vs Input Voltage 4 0.6 3.75 3.5 3.25 3 2.75 40°C 25°C 125°C VIN Operating Quiescent Current (mA) Switching (mA) 80 2.2 1.4 VIN Operating Current 125°C Figure 7-8. IQ-SHD vs Input Voltage 2.2 0.5 0.4 0.3 0.2 0.1 VCC = 8V 0 2.5 0 20 40 60 Input Voltage (V) VSW = 0 V 80 0 100 HO, LO Open Figure 7-11. IQ-OPERATING (Switching) vs Input Voltage 12 25°C 0 VSW = 0 V 20 40 60 Input Voltage (V) VVCC = VBST = VILIM 80 100 VFB = 0 V Figure 7-12. VIN Quiescent Current With External VCC Applied Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 25 350 20 250 Deadtime (ns) ILIM Current Source (PA) 300 200 150 15 10 100 5 50 0 -40 HO to LO LO to HO RDS-ON Mode RSENSE Mode -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 0 -40 110 125 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 VSW = 0 V Figure 7-14. Deadtime vs Junction Temperature 5.2 4 5 3.8 BST UVLO Threshold (V) VCC UVLO Threshold (V) Figure 7-13. ILIM Current Source vs Junction Temperature 4.8 4.6 4.4 3.6 3.4 3.2 Rising Falling 4.2 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 Rising Falling 3 -40 110 125 Figure 7-15. VCC UVLO Thresholds vs Junction Temperature -10 5 20 35 50 65 80 Junction Temperature (°C) 95 PGOOD OVP Thresholds (V) 110 96 94 92 90 108 106 104 102 Rising Falling 88 -40 110 125 Figure 7-16. BST UVLO Thresholds vs Junction Temperature 98 PGOOD UVP Thresholds (V) -25 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 7-17. PGOOD UVP Thresholds vs Junction Temperature Rising Falling 100 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 7-18. PGOOD OVP Thresholds vs Junction Temperature Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 13 LM5145 www.ti.com 1.3 0.5 1.25 0.45 EN Standby Threshold (V) EN Threshold (V) SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 1.2 1.15 1.1 0.4 0.35 0.3 Rising Falling 1.05 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 0.25 -40 110 125 Figure 7-19. EN/UVLO Threshold vs Junction Temperature -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 7-20. EN Standby Thresholds vs Junction Temperature 420 1000 Switching Frequency (kHz) 800 Switching Frequency (kHz) -25 600 400 200 0 0 10 20 30 40 50 60 70 RT Resistance (k:) 80 90 410 400 390 VIN = 6V VIN = 48V VIN = 100V 380 -40 100 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 VSW = 0 V Figure 7-21. Oscillator Frequency vs RT Resistance Figure 7-22. Oscillator Frequency vs Junction Temperature 4 0.9 0.8 0.7 0.6 VCC = 8V 0.5 3.5 3 2.5 2 1.5 Source Sink 1 0 10 20 30 40 BST Diode Forward Current (mA) 50 Figure 7-23. BST Diode Forward Voltage vs Current 14 LO, HO Gate Driver Peak Current (A) BST Diode Forward Voltage (V) 1 6 7 8 9 10 VCC Voltage (V) 11 12 13 Figure 7-24. Gate Driver Peak Current vs VCC Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 1.6 1.6 1.4 1.4 LO Gate Driver RDS(on) (:) HO Gate Driver RDS(on) (:) www.ti.com 1.2 1 0.8 1.2 1 0.8 High State Low State High State Low State 0.6 0.6 6 7 8 9 10 VCC Voltage (V) 11 12 13 Figure 7-25. HO Driver Resistance vs VCC Voltage 6 7 7.5 6 VCC Voltage (V) VCC Voltage (V) 7.25 6.75 6.5 8 9 10 VCC Voltage (V) 11 12 13 Figure 7-26. LO Driver Resistance vs VCC Voltage 7.75 7 7 5 4 3 2 6.25 1 6 40°C 25°C 125°C 25°C 40°C 5.75 125°C 0 0 20 40 60 Input Voltage (V) 80 100 VSS/TRK = 0 V 0 10 20 30 40 VCC Current (mA) 50 60 VIN = 6 V Figure 7-27. VCC Voltage vs Input Voltage Figure 7-28. VCC vs ICC Characteristic 8 11 7 10.8 10.6 Soft-Start Current (PA) VCC Voltage (V) 6 5 4 3 2 10.4 10.2 10 9.8 9.6 9.4 1 40°C 25°C 9.2 125°C 0 0 10 20 30 40 VCC Current (mA) 50 60 9 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 VIN = 12 V Figure 7-29. VCC vs ICC Characteristic Figure 7-30. SS/TRK Current Source vs Junction Temperature Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 15 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 8 Detailed Description 8.1 Overview The LM5145 is a 75-V synchronous buck controller with all of the functions necessary to implement a high efficiency step-down power supply. The output voltage range is from 0.8 V to 60 V. The voltage-mode control architecture uses input feedforward for excellent line transient response over a wide V IN range. Voltage-mode control supports the wide duty cycle range for high input voltage and low dropout applications as well as when a high voltage conversion ratio (for example, 10-to-1) is required. Current sensing for cycle-by-cycle current limit can be implemented with either the low-side FET R DS(on) or a current sense resistor. The operating frequency is programmable from 100 kHz to 1 MHz. The LM5145 drives external high-side and low-side NMOS power switches with robust 7.5-V gate drivers suitable for standard threshold MOSFETs. Adaptive dead-time control between the high-side and low-side drivers minimizes body diode conduction during switching transitions. An external bias supply can be connected to the VCC pin to improve efficiency in high-voltage applications. A userselectable diode emulation feature enables DCM operation for improved efficiency and lower dissipation at lightload conditions. 8.2 Functional Block Diagram VIN VCC 7.5 V LDO REGULATOR + ± VCC UVLO 7.5 V VCC ENABLE 0.4 V EN/UVLO 1.2 V BST ± + SHUTDOWN + ± VVCC-UV ENABLE LOGIC + ± 5 µs FILTER BST_UV ³1´ STANDBY D R ± + VSW + VBST-UV CL Q kFF*VIN RT OSCILLATOR & FEEDFORWARD RAMP GENERATOR SYNCOUT THERMAL SHUTDOWN HYSTERESIS LEVEL SHIFT CLK SYNCIN RAMP FPWM PWM COMPARATOR PWM LOGIC VCC 0.3 V DRIVER + COMP HO SW ADAPTIVE DEADTIME DELAY kFF*VIN + 0.3 V PEAK DETECT FILTER DRIVER ± LO PGND ERROR AMP FB ± ± 115 mV 0.8 V + + + + ± + ± ZERO CROSS DETECTION CLAMP SS/TRK COMP CLAMP MODULATOR STANDBY HICCUP COUNTERS SUPERVISORY COMPARATORS ± 0.8 V + 8% ILIM LO + PGOOD 25 µs delay FB OCP LO ± + 16 CLK RDS(on) or Shunt Sensing 0.8 V - 8% Submit Document Feedback CURRENT LIMIT COMPARATOR ± ILIM + AGND Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 8.3 Feature Description 8.3.1 Input Range (VIN) The LM5145 operational input voltage range is from 6 V to 75 V. The device is intended for step-down conversions from 12-V, 24-V, 48-V, 60-V, and 72-V unregulated, semiregulated, and fully-regulated supply rails. The application circuit in Figure 8-1 shows all the necessary components to implement an LM5145-based wideV IN step-down regulator using a single supply. The LM5145 uses an internal LDO subregulator to provide a 7.5V VCC bias rail for the gate drive and control circuits (assuming the input voltage is higher than 7.5 V plus the necessary subregulator dropout specification). RUV2 RUV1 VOUT VIN RC2 RRT RFB1 CC3 RC1 CC1 CSS CC2 RFB2 SYNC out SYNC optional 1 20 EN/UVLO VIN CBST 2 RT 3 SS/TRK HO 18 4 COMP SW 19 5 FB BST 17 Q1 LF VOUT NC 16 LM5145 6 AGND 7 SYNCOUT 8 SYNCIN 9 NC EP 15 Q2 CIN VCC 14 COUT LO 13 PGOOD 10 ILIM PGND 12 GND 11 CVCC RPG PG RILIM CILIM Copyright © 2017, Texas Instruments Incorporated Figure 8-1. Schematic Diagram for VIN Operating Range of 6 V to 75 V In high voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum voltage rating of 105 V during line or load transient events. Voltage ringing on the VIN pin that exceeds the Section 7.1 can damage the IC. Use high-quality ceramic input capacitors to minimize ringing. An RC filter from the input rail to the VIN pin (for example, 4.7 Ω and 0.1 µF) provides supplementary filtering at the VIN pin. 8.3.2 Output Voltage Setpoint and Accuracy (FB) The reference voltage at the FB pin is set at 0.8 V with a feedback system accuracy over the full junction temperature range of ±1%. Junction temperature range for the device is –40°C to +125°C. While dependent on switching frequency and load current levels, the LM5145 is generally capable of providing output voltages in the range of 0.8 V to a maximum of 60 V or slightly less than V IN , whichever is lower. The DC output voltage setpoint during normal operation is set by the feedback resistor network, R FB1 and R FB2, connected to the output. 8.3.3 High-Voltage Bias Supply Regulator (VCC) The LM5145 contains an internal high-voltage VCC regulator that provides a bias supply for the PWM controller and its gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an input voltage source up to 75 V. The output of the VCC regulator is set to 7.5 V. However, when the input voltage is below the VCC setpoint level, the VCC output tracks V IN with a small voltage drop. Connect a ceramic decoupling capacitor between 1 µF and 5 µF from VCC to AGND for stability. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 17 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 The VCC regulator output has a current limit of 40 mA (minimum). At power up, the regulator sources current into the capacitor connected to the VCC pin. When the VCC voltage exceeds its rising UVLO threshold of 4.93 V, the output is enabled (if EN/UVLO is above 1.2 V), and the soft-start sequence begins. The output remains active until the VCC voltage falls below its falling UVLO threshold of 4.67 V (typical) or if EN/UVLO goes to a standby or shutdown state. Internal power dissipation of the VCC regulator can be minimized by connecting the output voltage or an auxiliary bias supply rail (up to 13 V) to VCC using a diode D VCC as shown in Figure 8-2. A diode in series with the input prevents reverse current flow from VCC to VIN if the input voltage falls below the external VCC rail. LM5145 Required if VIN < VCC(EXT) DVCC DVIN VIN 20 VIN 6 V to 75 V VCC 14 CVIN VCC-EXT CVCC 0.1 PF 8 V to 13 V 2.2 PF AGND 6 Copyright © 2017, Texas Instruments Incorporated Figure 8-2. VCC Bias Supply Connection From VOUT or Auxiliary Supply Note that a finite bias supply regulator dropout voltage exists and is manifested to a larger extent when driving high gate charge (Q G) power MOSFETs at elevated switching frequencies. For example, at V VIN = 6 V, the VCC voltage is 5.8 V with a DC operating current, IVCC, of 20 mA. Such a low gate drive voltage may be insufficient to fully enhance the power MOSFETs. At the very least, MOSFET on-state resistance, R DS(ON), can increase at such low gate drive voltage. Here are the main considerations when operating at input voltages below 7.5 V: • • • Increased MOSFET RDS(on) at lower VGS, leading to Increased conduction losses and reduced OCP setpoint. Increased switching losses given the slower switching times when operating at lower gate voltages. Restricted range of suitable power MOSFETs to choose from (MOSFETs with RDS(on) rated at VGS = 4.5 V become mandatory). 8.3.4 Precision Enable (EN/UVLO) The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by the resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way to enable the operation of the LM5145 is to connect EN/UVLO directly to VIN. This allows self start-up of the LM5145 when V CC is within its valid operating range. However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in Figure 8-3 to establish a precision UVLO level. Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turnon and turnoff voltages. RUV1 RUV2 18 VIN(on) VIN(off) IHYS RUV1 ˜ (1) VEN VIN(on) VEN (2) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 vcc LM5145 VIN 10 A RUV1 EN/UVLO 1 RUV2 1.2V Remote Shutdown Enable Comparator Copyright © 2017, Texas Instruments Incorporated Figure 8-3. Programmable Input Voltage UVLO Turnon and Turnoff The LM5145 enters a low I Q shutdown mode when EN/UVLO is pulled below approximately 0.4 V. The internal LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the LM5145. The LM5145 operates in standby mode when the EN/UVLO voltage is between the hard shutdown and precision enable (standby) thresholds. 8.3.5 Power Good Monitor (PGOOD) The LM5145 provides a PGOOD flag pin to indicate when the output voltage is within a regulation window. Use the PGOOD signal as shown in Figure 8-4 for start-up sequencing of downstream converters, fault protection, and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 13 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail. VIN(on) = 15 V VIN(off) = 10 V VOUT(MASTER) = 5 V LM5145 RUV1 499 k PGOOD 10 1 EN/UVLO RUV2 43.2 k FB 5 RFB1 20 k VOUT(SLAVE) = 3.3 V LM5145 RPG 20 k 0.8 V PGOOD 10 1 EN/UVLO FB 5 0.8 V RFB4 6.34 k RFB2 3.83 k Regulator #1 Start-up based on Input Voltage UVLO RFB3 20 k Regulator #2 Sequential Start-up based on PGOOD Copyright © 2017, Texas Instruments Incorporated Figure 8-4. Master-Slave Sequencing Implementation Using PGOOD and EN/UVLO When the FB voltage exceeds 94% of the internal reference V REF, the internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 92% of V REF, the internal PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. Similarly, when the FB voltage exceeds 108% of VREF, the internal PGOOD switch turns on, pulling PGOOD low. If the FB voltage subsequently falls below 105% of V REF, the PGOOD switch is turned off and PGOOD is pulled high. PGOOD has a built-in deglitch delay of 25 µs. 8.3.6 Switching Frequency (RT, SYNCIN) There are two options for setting the switching frequency, F SW, of the LM5145, thus providing a power supply designer with a level of flexibility when choosing external components for various applications. To adjust the Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 19 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 frequency, use a resistor from the RT pin to AGND, or synchronize the LM5145 to an external clock signal through the SYNCIN pin. 8.3.6.1 Frequency Adjust Adjust the LM5145 free-running switching frequency by using a resistor from the RT pin to AGND. The switching frequency range is from 100 kHz to 1 MHz. The frequency set resistance, R RT, is governed by Equation 3. E96 standard-value resistors for common switching frequencies are given in Table 8-1. 4 RRT ¬ªk: ¼º 10 FSW ¬ªkHz ¼º (3) Table 8-1. Frequency Set Resistors SWITCHING FREQUENCY (kHz) FREQUENCY SET RESISTANCE (kΩ) 100 100 200 49.9 250 40.2 300 33.2 400 24.9 500 20 750 13.3 1000 10 8.3.6.2 Clock Synchronization Apply an external clock synchronization signal to the LM5145 to synchronize switching in both frequency and phase. Requirements for the external clock SYNC signal are: • • • • Clock frequency range: 100 kHz to 1 MHz Clock frequency: –20% to +50% of the free-running frequency set by RRT Clock maximum voltage amplitude: 13 V Clock minimum pulse width: 50 ns Figure 8-5 shows a clock signal at 400 kHz and the corresponding SW node waveform (V IN = 48 V, V OUT = 5 V, free-running frequency = 280 kHz). The SW voltage waveform is synchronized with respect to the rising edge of SYNCIN. The rising edge of the SW voltage is phase delayed relative to SYNCIN by approximately 100 ns. VSW 10 V/DIV VSYNCIN 2 V/DIV 1 Ps/DIV Figure 8-5. Typical 400-kHz SYNCIN and SW Voltage Waveforms 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 8.3.7 Configurable Soft Start (SS/TRK) After the EN/UVLO pin exceeds its rising threshold of 1.2 V, the LM5145 begins charging the output to the DC level dictated by the feedback resistor network. The LM5145 features an adjustable soft start (set by a capacitor from the SS/TRK pin to GND) that determines the charging time of the output. A 10-µA current source charges this soft-start capacitor. Soft start limits inrush current as a result of high output capacitance to avoid an overcurrent condition. Stress on the input supply rail is also reduced. The soft-start time, t SS, for the output voltage to ramp to its nominal level is set by Equation 4. t SS CSS ˜ VREF ISS (4) where • • • CSS is the soft-start capacitance VREF is the 0.8-V reference ISS is the 10-µA current sourced from the SS/TRK pin More simply, calculate CSS using Equation 5. CSS ª¬nF º¼ 12.5 ˜ t SS ª¬ms º¼ (5) The SS/TRK pin is internally clamped to VFB + 115 mV to allow a soft-start recovery from an overload event. The clamp circuit requires a soft-start capacitance greater than 2 nF for stability and has a current limit of approximately 2 mA. 8.3.7.1 Tracking The SS/TRK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This tracking is achieved by simply dividing down the output voltage of the master with a simple resistor network. Coincident, ratiometric, and offset tracking modes are possible. If an external voltage source is connected to the SS/TRK pin, the external soft-start capability of the LM5145 is effectively disabled. The regulated output voltage level is reached when the SS/TRACK pin reaches the 0.8-V reference voltage level. It is the responsibility of the system designer to determine if an external soft-start capacitor is required to keep the device from entering current limit during a start-up event. Likewise, the system designer must also be aware of how fast the input supply ramps if the tracking feature is enabled. SS/TRK 160mV/DIV 94% VOUT 92% VOUT VOUT 1V/DIV PGOOD 2V/DIV 10 ms/DIV Figure 8-6. Typical Output Voltage Tracking and PGOOD Waveforms Figure 8-6 shows a triangular voltage signal directly driving SS/TRK and the corresponding output voltage tracking response. Nominal output voltage here is 5 V, with oscilloscope channel scaling chosen such that the Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 21 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 waveforms overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 94% (rising) and 92% (falling) of the nominal output voltage setpoint. Two practical tracking configurations, ratiometric and coincident, are shown in Figure 8-7. The most common application is coincident tracking, used in core versus I/O voltage tracking in DSP and FPGA implementations. Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the output voltage of the slave to a fraction of the output voltage of the master during start-up. VOUTMASTER = 3.3 V Slave Regulator #1 Ratiometric Tracking Slave Regulator #2 Coincident Tracking VOUTSLAVE1 = 1.8 V LM5145 LM5145 RTRK1 26.7 k RFB1 12.5 k 3 SS/TRK RTRK2 10 k VOUTSLAVE2 = 1.2 V FB 5 CSS1 RFB3 10 k 3 0.8 V RFB2 10 k 2.2 nF RTRK3 10 k RTRK4 20 k SS/TRK FB 5 CSS2 0.8 V RFB4 20 k 2.2 nF SYNCIN SYNCIN 8 8 SYNCOUT from Master Copyright © 2017, Texas Instruments Incorporated Figure 8-7. Tracking Implementation With Master, Ratiometric Slave, and Coincident Slave Rails For coincident tracking, connect the SS/TRK input of the slave regulator to a resistor divider from the output voltage of the master that is the same as the divider used on the FB pin of the slave. In other words, simply select R TRK3 = R FB3 and R TRK4 = R FB4 as shown in Figure 8-7. As the master voltage rises, the slave voltage rises identically (aside from the 80-mV offset from SS/TRK to FB when VFB is below 0.8 V). Eventually, the slave voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the SS/TRK input continues to 115 mV above FB, and no longer controls the output voltage. In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRK voltage being too close to the 0.8-V reference voltage, the final value of the SS/TRK voltage of the slave should be at least 100 mV above FB. 8.3.8 Voltage-Mode Control (COMP) The LM5145 incorporates a voltage-mode control loop implementation with input voltage feedforward to eliminate the input voltage dependence of the PWM modulator gain. This configuration allows the controller to maintain stability throughout the entire input voltage operating range and provides for optimal response to input voltage transient disturbances. The constant gain provided by the controller greatly simplifies loop compensation design because the loop characteristics remain constant as the input voltage changes, unlike a buck converter without voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage amplitude to maintain constant modulator gain. The input voltage feedforward gain, k FF, is 15, equivalent to the input voltage divided by the ramp amplitude, VIN/VRAMP. See Section 9.1.3 for more detail. 8.3.9 Gate Drivers (LO, HO) The LM5145 gate driver impedances are low enough to perform effectively in high output current applications where large die-size or paralleled MOSFETs with correspondingly large gate charge, QG, are used. Measured at V VCC = 7.5 V, the low-side driver of the LM5145 has a low impedance pulldown path of 0.9 Ω to minimize the effect of dv/dt induced turn-on, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 driver has 1.5-Ω and 0.9-Ω pullup and pulldown impedances, respectively, for faster switching transition times, lower switching loss, and greater efficiency. The high-side gate driver works in conjunction with an integrated bootstrap diode and external bootstrap capacitor, C BST. When the low-side MOSFET conducts, the SW voltage is approximately at 0 V and C BST is charged from VCC through the integrated boot diode. Connect a 0.1-μF or larger ceramic capacitor close to the BST and SW pins. Furthermore, there is a proprietary adaptive dead-time control on both switching edges to prevent shoot-through and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery losses. 8.3.10 Current Sensing and Overcurrent Protection (ILIM) The LM5145 implements a lossless current sense scheme designed to limit the inductor current during an overload or short-circuit condition. Figure 8-8 portrays the popular current sense method using the on-state resistance of the low-side MOSFET. Meanwhile, Figure 8-9 shows an alternative implementation with current shunt resistor, RS. The LM5145 senses the inductor current during the PWM off-time (when LO is high). VIN VIN Q1 HO Q1 LF HO LF VOUT VOUT SW SW RILIM Q2 LO ILIM COUT COUT ILIM Q2 RILIM LO GND GND Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated Figure 8-8. MOSFET RDS(on) Current Sensing RS Figure 8-9. Shunt Resistor Current Sensing The ILIM pin of the LM5145 sources a reference current that flows in an external resistor, designated R ILIM, to program of the current limit threshold. A current limit comparator on the ILIM pin prevents further SW pulses if the ILIM pin voltage goes below GND. Figure 8-10 shows the implementation. Resistor R ILIM is tied to SW to use the R DS(on) of the low-side MOSFET as a sensing element (termed R DS(on) mode). Alternatively, R ILIM is tied to a shunt resistor connected at the source of the low-side MOSFET (termed RSENSE mode). The LM5145 detects the appropriate mode at start-up and sets the source current amplitude and temperature coefficient (TC) accordingly. The ILIM current with R DS-ON sensing is 200 µA at 27°C junction temperature and incorporates a TC of +4500 ppm/°C to generally track the R DS(on) temperature variation of the low-side MOSFET. Conversely, the ILIM current is a constant 100 µA in R SENSE mode. This controls the valley of the inductor current during a steadystate overload at the output. Depending on the chosen mode, select the resistance of RILIM using Equation 6. RILIM - IOUT 'IL 2 ˜ RDS(on)Q2 , RDS(on) sensing ° I ° RDSON ® ° IOUT 'IL 2 ˜ RS , shunt sensing ° IRS ¯ (6) where • ΔIL is the peak-to-peak inductor ripple current Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 23 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 • • • • RDS(on)Q2 is the on-state resistance of the low-side MOSFET IRDSON is the ILIM pin current in RDS-ON mode RS is the resistance of the current-sensing shunt element, and IRS is the ILIM pin current in RSENSE mode. Given the large voltage swings of ILIM in R DS(on) sensing mode, a capacitor designated C ILIM connected from ILIM to PGND is essential to the operation of the valley current limit circuit. Choose this capacitance such that the time constant RILIM · CILIM is approximately 6 ns. VIN CLK COMP S Q R Q ValleyPWM PWML Error Amp IRAMP FB PWM Comp VREF Q1 HO S Q R Q Gate Driver + + PWM Latch VRAMP VOUT Q2 LO ILIM + ± LF SW RILIM COUT IRDSON(TJ) 300 mV CILIM PWM Aux COMP Clamp Modulator + VCLAMP ILIM comparator + PGND GND Figure 8-10. OCP Setpoint Defined by Current Source IRDSON and Resistor RILIM in RDS-ON Mode Note that current sensing with a shunt component is typically implemented at lower output current levels to provide accurate overcurrent protection. Burdened by the unavoidable efficiency penalty, PCB layout, and additional cost implications, this configuration is not usually implemented in high-current applications (except where OCP setpoint accuracy and stability over the operating temperature range are critical specifications). 24 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 8.3.11 OCP Duty Cycle Limiter Short Applied CLAMP COMP Many cycles RAMP 300 mV ILIM Threshold Inductor Current CLK PWML ValleyPWM PWML terminated by VRAMP > VCOMP PWML terminated by VRAMP > VCLAMP Figure 8-11. OCP Duty Cycle Limiting Waveforms In addition to valley current limiting, the LM5145 uses a proprietary duty-cycle limiter circuit to reduce the PWM on-time during an overcurrent condition. As shown in Figure 8-10, an auxiliary PWM comparator along with a modulated CLAMP voltage limits how quickly the on-time increases in response to a large step in the COMP voltage that typically occurs with a voltage-mode control loop architecture. As depicted in Figure 8-11, the CLAMP voltage, V CLAMP, is normally regulated above the COMP voltage to provide adequate headroom during a response to a load-on transient. If the COMP voltage rises quickly during an overloaded or shorted output condition, the on-time pulse terminates thereby limiting the on-time and peak inductor current. Moreover, the CLAMP voltage is reduced if additional valley current limit events occur, further reducing the average output current. If the overcurrent condition exists for 128 continuous clock cycles, a hiccup event is triggered and SS is pulled low for 8192 clock cycles before a soft-start sequence is initiated. 8.4 Device Functional Modes 8.4.1 Shutdown Mode The EN/UVLO pin provides ON / OFF control for the LM5145. When the EN/UVLO voltage is below 0.37 V (typical), the device is in shutdown mode. Both the internal bias supply LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 13.5 μA (typical) at V IN = 48 V. The LM5145 also includes undervoltage protection of the internal bias LDO. If the internal bias supply voltage is below its UVLO threshold level, the switching regulator remains off. 8.4.2 Standby Mode The internal bias supply LDO has a lower enable threshold than the switching regulator. When the EN/UVLO voltage exceeds 0.42 V (typical) and is below the precision enable threshold (1.2 V typically), the internal LDO is on and regulating. Switching action and output voltage regulation are disabled in standby mode. 8.4.3 Active Mode The LM5145 is in active mode when the VCC voltage is above its rising UVLO threshold of 5 V and the EN/ UVLO voltage is above the precision EN threshold of 1.2 V. The simplest way to enable the LM5145 is to tie EN/ UVLO to VIN. This allows self start-up of the LM5145 when the input voltage exceeds the VCC threshold plus the LDO dropout voltage from VIN to VCC. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 25 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 8.4.4 Diode Emulation Mode The LM5145 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation, the low-side MOSFET is switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss at no-load and light-load conditions, the disadvantage being slower light-load transient response. The diode emulation feature is configured with the SYNCIN pin. To enable diode emulation and thus achieve discontinuous conduction mode (DCM) operation at light loads, connect the SYNCIN pin to AGND or leave SYNCIN floating. If forced PWM (FPWM) continuous conduction mode (CCM) operation is desired, tie SYNCIN to VCC either directly or using a pullup resistor. Note that diode emulation mode is automatically engaged to prevent reverse current flow during a prebias start-up. A gradual change from DCM to CCM operation provides monotonic start-up performance. 8.4.5 Thermal Shutdown The LM5145 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical), thermal shutdown occurs. When entering thermal shutdown, the device: 1. Turns off the high-side and low-side MOSFETs. 2. Pulls SS/TRK and PGOOD low. 3. Turns off the VCC regulator. 4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of 20°C (typical). This is a non-latching protection, and the device will cycle into and out of thermal shutdown if the fault persists. 26 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Design and Implementation To expedite the process of designing of a LM5145-based regulator for a given application, use the LM5145 Quickstart Calculator available as a free download, as well as numerous LM5145 reference designs populated in TI Designs™ reference design library, or the designs provided in Section 9.2. The LM5145 is also WEBENCH® Designer enabled. 9.1.2 Power Train Components Comprehensive knowledge and understanding of the power train components are key to successfully completing a synchronous buck regulator design. 9.1.2.1 Inductor For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 40% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 7 based on a peak inductor current given by Equation 8. LF VOUT § VIN VOUT · ˜¨ ¸ VIN © 'IL ˜ FSW ¹ IL(peak) IOUT (7) 'IL 2 (8) Check the inductor data sheet to ensure that the saturation current of the inductor is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation. 9.1.2.2 Output Capacitors Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient response of the regulator as the load step amplitude and slew rate increase. The output capacitor, C OUT, filters the inductor ripple current and provides a reservoir of charge for step-load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 27 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 Based on the static specification of peak-to-peak output voltage ripple denoted by ΔV OUT, choose an output capacitance that is larger than that given by Equation 9. 'IL COUT t 8 ˜ FSW 'VOUT 2 RESR ˜ 'IL 2 (9) Figure 9-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load stepup transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible. IOUT1 diL dt 'IOUT VOUT LF inductor current, iL(t) 'QC IOUT2 diOUT dt load current, iOUT(t) 'IOUT tramp inductor current, iL(t) IOUT2 'QC diL dt 'IOUT VIN VOUT LF load current, iOUT(t) IOUT1 tramp Figure 9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit In a typical regulator application of 48-V input to low output voltage (for example, 5 V), the load-off transient represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the steady-state duty cycle is approximately 10% and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –V OUT/L. Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and limit the voltage overshoot. To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger than LF ˜ 'IOUT COUT t VOUT 2 'VOVERSHOOT 2 VOUT 2 (10) The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 ESL contributions at the switching frequency, and the capacitive impedance component dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied DC voltage and operating temperature. Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. One to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification. A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance provides low-frequency energy storage to cope with load transient demands. 9.1.2.3 Input Capacitors Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switchingfrequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET. The input capacitor RMS current is given by Equation 11. ICIN,rms § 2 D ˜ ¨ IOUT ˜ 1 D ¨ © 2 'IL · ¸ 12 ¸ ¹ (11) The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the capacitors should be greater than half the output current. Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT − IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak ripple voltage amplitude is given by Equation 12. 'VIN IOUT ˜ D ˜ 1 D FSW ˜ CIN IOUT ˜ RESR (12) The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔVIN, is given by Equation 13. CIN t D ˜ 1 D ˜ IOUT FSW ˜ 'VIN RESR ˜ IOUT (13) Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2-μF 100-V X7R ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current rating and operating temperature. 9.1.2.4 Power MOSFETs The choice of power MOSFETs has significant impact on DC-DC regulator performance. A MOSFET with low on-state resistance, R DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 29 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 transition times and reduced switching loss. Normally, the lower the R DS(on) of a MOSFET, the higher the gate charge and output charge (Q G and Q OSS respectively), and vice versa. As a result, the product R DS(on) × Q G is commonly specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature. The main parameters affecting power MOSFET selection in a LM5145 application are as follows: • • • • • • RDS(on) at VGS = 7.5 V Drain-source voltage rating, BVDSS, typically 60 V, 80 V or 100 V, depending on maximum input voltage Gate charge parameters at VGS = 7.5 V Output charge, QOSS, at the relevant input voltage Body diode reverse recovery charge, QRR Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG vs. VGS plot in the MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 5 V, the 7.5-V gate drive amplitude of the LM5145 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt shoot-through when off. The MOSFET-related power losses are summarized by the equations presented in Table 9-1, where suffixes 1 and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Consult the LM5145 Quickstart Calculator to assist with power loss calculations. Table 9-1. Buck Regulator MOSFET Power Losses POWER LOSS MODE MOSFET conduction(2) (3) MOSFET switching HIGH-SIDE MOSFET Pcond1 Psw1 MOSFET gate drive(1) § 2 D ˜ ¨ IOUT ¨ © VIN ˜ FSW ª§ «¨ IOUT 2 ¬© PGate1 'IL 2 Body diode reverse recovery(5) (1) (2) (3) (4) (5) · ¸ ˜ RDS(on)1 12 ¸ ¹ · ¸ ˜ tR ¹ 'IL 2 § ¨ IOUT © Pcond2 PCoss § 2 Dc ˜ ¨ IOUT ¨ © · º ¸ ˜ tF » ¹ ¼ PGate2 FSW ˜ VIN ˜ Qoss2 N/A VCC ˜ FSW ˜ QG2 Eoss1 Eoss2 PcondBD PRR 2 'IL · ¸ ˜ RDS(on)2 12 ¸ ¹ Negligible VCC ˜ FSW ˜ QG1 MOSFET output charge(4) Body diode conduction LOW-SIDE MOSFET 2 'IL ª§ VF ˜ FSW «¨ IOUT ¬© 'IL 2 · § ¸ ˜ t dt1 ¨ IOUT ¹ © 'IL 2 º · ¸ ˜ t dt2 » ¹ ¼ VIN ˜ FSW ˜ QRR2 Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally-added series gate resistance and the relevant driver resistance of the LM5145. MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or near minimum input voltage, ensure that the MOSFET RDS(on) is rated at VGS = 4.5 V. D' = 1–D is the duty cycle complement. MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this is offset by the stored energy Eoss2 on Coss2. MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition speed and temperature. The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery. 30 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just commutates from the channel to the body diode or vice versa during the transition deadtimes. The LM5145, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency. In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases where the conduction loss is too high or the target R DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery. The LM5145 is well suited to drive TI's portfolio of NexFET™ power MOSFETs. 9.1.3 Control Loop Compensation The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue dashed rings in the schematic embedded in Table 9-2. Table 9-2. Buck Regulator Poles and Zeros VIN Power Stage Q1 &L D Adaptive Gate Driver &o LF RDAMP VOUT &ESR IOUT RESR Q2 Modulator COUT RL PWM Ramp VRAMP GND Compensator + PWM Comparator COMP Error Amp + VREF CC3 &p2 RC2 FB CC1 &z1 RC1 &z2 RFB1 RFB2 CC2 POWER STAGE POLES 1 Zo # § 1 RESR RL · LF ˜ COUT ¨ ¸ © 1 RESR RDAMP ¹ 1 LF ˜ COUT &p1 POWER STAGE ZEROS ZESR ZL 1 RESR ˜ COUT LF RDAMP COMPENSATOR POLES Zp1 COMPENSATOR ZEROS 1 1 # RC1 ˜ (CC1 CC2 ) RC1 ˜ CC2 Zp2 1 RC2 ˜ CC3 Zz1 Zz2 1 RC1 ˜ CC1 1 (RFB1 RC2 ) ˜ CC3 The compensation network typically employed with voltage-mode control is a Type-III circuit with three poles and two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation strategy uses two compensator zeros to counteract the LC double pole, one compensator pole located to nullify the output capacitor ESR zero, with the remaining compensator pole located at one-half switching frequency to attenuate high frequency noise. The resistor divider network to FB determines the desired output voltage. Note that the lower feedback resistor, RFB2, has no impact on the control loop from an AC standpoint because the FB node is the input to an error amplifier and is effectively at AC ground. Hence, the control loop is designed irrespective of output voltage level. The proviso here is the necessary output capacitance derating with bias voltage and temperature. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 31 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 The small-signal open-loop response of a buck regulator is the product of modulator, power train and compensator transfer functions. The power stage transfer function can be represented as a complex pole pair associated with the output LC filter and a zero related to the ESR of the output capacitor. The DC (and low frequency) gain of the modulator and power stage is V IN/V RAMP. The gain from COMP to the average voltage at the input of the LC filter is held essentially constant by the PWM line feedforward feature of the LM5145 (15 V/V or 23.5 dB). Complete expressions for small-signal frequency analysis are presented in Table 9-3. The transfer functions are denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio susceptibility. Table 9-3. Buck Regulator Small-Signal Analysis TRANSFER FUNCTION EXPRESSION Open-loop transfer function Tv (s) Duty-cycle-to-output transfer function Ö vÖ comp (s) vÖ o (s) d(s) ˜ ˜ Ö vÖ o (s) d(s) vÖ comp (s) Gvd (s) Compensator transfer function(1) Gc (s) Modulator transfer function FM (1) 1 vÖ o (s) Ö vÖ in (s) d(s) 0 Öi (s) 0 o vÖ comp (s) vÖ o (s) Ö d(s) vÖ comp (s) K mid VIN 1 Gc (s) ˜ Gvd (s) ˜ FM s ZESR 2 s s QoZo Zo 2 s § Zz1 · § ¨1 s ¸ ¨1 Z © ¹© z2 § ·§ s s ¨1 ¸¨ 1 ¨ Zp1 ¸¨ Zp2 © ¹© · ¸ ¹ · ¸ ¸ ¹ 1 VRAMP Kmid = RC1/RFB1 is the mid-band gain of the compensator. By expressing one of the compensator zeros in inverted zero format, the mid-band gain is denoted explicitly. Figure 9-2 shows the open-loop response gain and phase. The poles and zeros of the system are marked with x and o symbols, respectively, and a + symbol indicates the crossover frequency. When plotted on a log (dB) scale, the open-loop gain is effectively the sum of the individual gain components from the modulator, power stage, and compensator (see Figure 9-3). The open-loop response of the system is measured experimentally by breaking the loop, injecting a variable-frequency oscillator signal, and recording the ensuing frequency response using a network analyzer setup. 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 40 0 Loop Gain Complex LC Double Pole Crossover Frequency, fc 20 Loop Gain (dB) Compensator Poles Compensator Zeros 0 -45 Loop Phase Loop Phase -90 (°) NM -135 -20 Output Capacitor ESR Zero -40 1 10 100 -180 1000 Frequency (kHz) Figure 9-2. Typical Buck Regulator Loop Gain and Phase With Voltage-Mode Control If the pole located at ω p1 cancels the zero located at ω ESR and the pole at ω p2 is located well above crossover, the expression for the loop gain, Tv(s) in Table 9-3, can be manipulated to yield the simplified expression given in Equation 14. Tv (s) RC1 ˜ CC3 ˜ 2 VIN ˜ Zo VRAMP s (14) Essentially, a multi-order system is reduced to a single-order approximation by judicious choice of compensator components. A simple solution for the crossover frequency (denoted as f c in Figure 9-2) with Type-III voltagemode compensation is derived as shown in Equation 15 and Equation 16. Zc K mid 2 S ˜ fc Zo ˜ K mid ˜ fc 1 ˜ fo kFF VIN VRAMP (15) RC1 RFB1 (16) 40 Modulator Gain Loop Gain Compensator Gain 20 Gain (dB) 0 -20 Filter Gain -40 1 10 fc 100 1000 Frequency (kHz) Figure 9-3. Buck Regulator Constituent Gain Components Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 33 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 The loop crossover frequency is usually selected between one-tenth to one-fifth of switching frequency. Inserting an appropriate crossover frequency into Equation 16 gives a target for the mid-band gain of the compensator, K mid. Given an initial value for R FB1, R FB2 is then selected based on the desired output voltage. Values for R C1, R C2, C C1, C C2, and C C3 are calculated from the design expressions listed in Table 9-4, with the premise that the compensator poles and zeros are set as follows: ωz1 = 0.5·ωo, ωz2 = ωo, ωp1 = ωSW/2, and ωp2 = ωESR. Table 9-4. Compensation Component Selection RESISTORS RFB2 RC1 RC2 RFB1 VOUT VREF CAPACITORS 1 K mid ˜ RFB1 1 CC1 2 Zz1 ˜ RC1 CC2 1 Zp1 ˜ RC1 CC3 Zp2 ˜ CC3 1 Zz2 ˜ RFB1 Referring to the bode plot in Figure 9-2, the phase margin, indicated as φ M, is the difference between the loop phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole (hence why C C1 is scaled by a factor of 2 above). This helps mitigate the phase dip associated with the LC filter, particularly at light loads when the Q-factor is higher and the phase dip becomes especially prominent. The ramification of low phase in the frequency domain is an under-damped transient response in the time domain. The power supply designer now has all the necessary expressions to optimally position the loop crossover frequency while maintaining adequate phase margin over the required line, load and temperature operating ranges. The LM5145 Quickstart Calculator is available to expedite these calculations and to adjust the bode plot as needed. 9.1.4 EMI Filter Design Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance. ZIN VIN(min) 2 PIN (17) The EMI filter design steps are as follows: • • • 34 Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the existing capacitance at the input of the switching converter. Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a high current design. Calculate input filter capacitor CF full stop. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 LIN Q1 VIN LF CD VOUT CIN CF Q2 RD COUT GND GND Figure 9-4. Buck Regulator With π-Stage EMI Filter By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it by the input impedance (the impedance is defined by the existing input capacitor C IN), a formula is derived to obtain the required attenuation as shown by Equation 18. Attn § IL(PEAK) 1 · ¸ VMAX 20log ¨ 2 ˜ sin S ˜ DMAX ˜ ¨ S ˜F ˜ C ¸ 1 9 SW IN © ¹ (18) where • • • • VMAX is the noise specification in dBμV from the applicable EMI standard, for example CISPR 32 Class B. CIN is the existing input capacitance of the buck regulator. DMAX is the maximum duty cycle. IPEAK is the peak inductor current. For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI filter capacitance CF from Equation 19. CF Attn § 1 ¨ 10 40 ¨ LIN ¨ 2S ˜ FSW ¨ © · ¸ ¸ ¸ ¸ ¹ 2 (19) Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the filter is given by Equation 20. fres 1 2S ˜ LIN ˜ CF (20) The purpose of R D is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor C D blocks the DC component of the input voltage to avoid excessive power dissipation in R D. Capacitor C D must have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input capacitor C IN. This prevents C IN from interfering with the cutoff frequency of the main filter. Added damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by L IN and CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 21. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 35 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 CD t 4 ˜ CIN (21) Select the damping resistor RD using Equation 22. RD 36 LIN CIN (22) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2 Typical Applications For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of an LM5145-powered implementation, see TI Designs reference design library. 9.2.1 Design 1 – 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications Figure 9-5 shows the schematic diagram of a 5-V, 20-A buck regulator with a switching frequency of 230 kHz. In this example, the target half-load and full-load efficiencies are 93.5% and 92.5%, respectively, based on a nominal input voltage of 48 V that ranges from 7 V to 72 V. The switching frequency is set by means of a synchronization input signal at 230 kHz, and the free-running switching frequency (in the event that the synchronization signal is removed) is set at 200 kHz by resistor R RT. In terms of control loop performance, the target loop crossover frequency is 35 kHz with a phase margin greater than 50°. The output voltage soft-start time is 4 ms. RUV2 RUV1 11.3 k 49.9 k VIN = 7 V to 72 V CVIN 0.1 F VOUT U1 RFB1 1k CC3 1.8 nF RC1 CC1 CSS 11 k 4.7 nF 47 nF CC2 150 pF RFB2 4.42 k 0.1 F 49.9 k 23.2 k SYNC Out SYNC In 230 kHz CBST 20 1 RRT RC2 EN/UVLO VIN 2 RT 3 SS/TRK HO 18 4 COMP SW 19 5 FB BST 17 Q1 LF 3.3 H VOUT = 5 V NC 16 LM5145 6 AGND 7 SYNCOUT EP 15 8 SYNCIN 9 NC Q2 CIN VCC 14 7 u 4.7 F COUT CBULK 7 u 47 F 220 F LO 13 ILIM PGND PGOOD 10 12 GND 11 CVCC 2.2 F RPG PGOOD 20 k CILIM RILIM 422 15 pF Copyright © 2017, Texas Instruments Incorporated Figure 9-5. Application Circuit 1 With LM5145 48-V to 5-V, 20-A Buck Regulator at 230 kHz Note This and subsequent design examples are provided herein to showcase the LM5145 controller in several different applications. Depending on the source impedance of the input supply bus, an electrolytic capacitor may be required at the input to ensure stability, particularly at low input voltage and high output current operating conditions. See Section 10 for more detail. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 37 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.1.1 Design Requirements The intended input, output, and performance-related parameters pertinent to this design example are shown in Table 9-5. Table 9-5. Design Parameters DESIGN PARAMETER VALUE Input voltage range (steady state) 7 V to 72 V Input transient voltage (peak) 80 V Output voltage and current 5 V, 20 A Input voltage UVLO thresholds 6.5 V on, 6 V off Switching frequency (SYNC in) 230 kHz Output voltage regulation ±0.5% Load transient peak voltage deviation < 100 mV 9.2.1.2 Detailed Design Procedure The design procedure for an LM5145-based regulator for a given application is streamlined by using the LM5145 Quickstart Calculator available as a free download, or by availing of TI's WEBENCH® Power Designer. Such tools are complemented by the availability of an LM5145 evaluation module (EVM) design, numerous PSPICE models, as well as several LM5145 reference designs populated in the TI Designs reference design library. The selected buck converter powertrain components are cited in Table 9-6, and many of the components are available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching power loss, as discussed in detail in Section 9.1.2.4. The current limit setpoint in this design is set at 25 A based on the resistor RILIM and the 4-mΩ RDS(on) of the lowside MOSFET (typical at T J = 25°C and V GS = 7.5 V). This design uses a low-DCR, metal-powder inductor, and composite ceramic–polymer electrolytic output capacitor implementation. Table 9-6. List of Materials for Application Circuit 1 REFERENCE DESIGNATOR CIN COUT COUT(BULK) QTY 7 7 1 SPECIFICATION MANUFACTURER PART NUMBER TDK C3225X7R2A225M230AB Murata GRM32ER72A225KA35L Kemet C1210C225K1RACTU Murata GRM32ER71A476KE15L Taiyo Yuden LMK325B7476MM-TR 2.2 µF, 100 V, X7R, 1210, ceramic 47 µF, 10 V, X7R, 1210, ceramic AVX 1210ZC476KAT2A Kemet C1210C476M8RAC7800 220 µF, 6.3 V, 10 mΩ, polymer electrolytic Murata ECASD60J227M010K00 3.3 µH, 3.75 mΩ, 40 A, 13.45 × 12.6 × 6.3 mm Cyntec CMLS136E-3R3MS LF 1 3.3 µH, 5.7 mΩ, 32 A, 12.5 × 12.5 × 6.2 mm Würth Electronik 744373965033 Q1 1 80 V, 12 mΩ, high-side MOSFET, SON 5 × 6 Infineon BSC117N08NS5 Q2 1 80 V, 4 mΩ, low-side MOSFET, SON 5 × 6 Infineon BSC037N08NS5 U1 1 Wide VIN synchronous buck controller Texas Instruments LM5145RGYR 9.2.1.3 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM5145 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. 38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 39 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.1.4 Application Curves 100 95 SW 10V/DIV SYNCOUT 1V/DIV Efficiency (%) 90 85 80 VIN = 12V VIN = 24V VIN = 36V VIN = 48V VIN = 60V VIN = 75V 75 70 65 0 5 10 Output Current (A) 15 2 Ps/DIV 20 Figure 9-6. Efficiency and Power Loss vs IOUT and VIN VIN = 48 V IOUT = 5 A Figure 9-7. SYNCOUT and SW Node Voltages VIN 10V/DIV VOUT 1V/DIV VIN 2V/DIV VOUT 1V/DIV PGOOD 2V/DIV PGOOD 2V/DIV IOUT 5A/DIV IOUT 5A/DIV 400 Ps/DIV 1 ms/DIV VIN step to 48 V 0.25-Ω Load Figure 9-8. Start-Up, 20-A Resistive Load VIN 48 V to 6 V 0.25-Ω Load Figure 9-9. Shutdown Through Input UVLO, 20-A Resistive Load VOUT 1V/DIV VOUT 1V/DIV IOUT 5A/DIV IOUT 5A/DIV ENABLE 1V/DIV ENABLE 1V/DIV PGOOD 2V/DIV PGOOD 2V/DIV 1 ms/DIV VIN = 48 V 40 Ps/DIV 0.25-Ω Load Figure 9-10. ENABLE ON, 20-A Resistive Load 40 VIN = 48 V 0.25-Ω Load Figure 9-11. ENABLE OFF, 20-A Resistive Load Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 VOUT 200m/DIV VOUT 500m/DIV IOUT 5A/DIV IOUT 5A/DIV 40 Ps/DIV 40 Ps/DIV VIN = 48 V VIN = 48 V Figure 9-12. Load Transient Response, 10 A to 20 A to 10 A Figure 9-13. Load Transient Response, 0 A to 20 A to 0 A VOUT 50mV/DIV VOUT 50mV/DIV VIN 20V/DIV IOUT 5A/DIV IOUT 5A/DIV VIN 20V/DIV 20 ms/DIV 20 ms/DIV IOUT = 10 A IOUT = 10 A Figure 9-14. Line Transient Response, 12 V to 72 V Figure 9-15. Line Transient Response, 72 V to 12 V SW 10V/DIV VOUT 1V/DIV VOUT 50mV/DIV PGOOD 2V/DIV VIN 10V/DIV 2 ms/DIV VIN = 48 V 2 Ps/DIV IOUT = 0 A Figure 9-16. Pre-Biased Start-Up VIN = 48 V IOUT = 0 A Figure 9-17. SW Node and Output Ripple Voltages Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 41 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 Margin Margin Start 150 kHz VIN = 48 V Stop 30 MHz VOUT = 5 V 10-A load Figure 9-18. CISPR 25 Class 5 Conducted EMI, 150 kHz to 30 MHz 42 Start 30 MHz VIN = 48 V Stop 108 MHz VOUT = 12 V 10-A load Figure 9-19. CISPR 25 Class 5 Conducted EMI, 30 MHz to 108 MHz Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.2 Design 2 – High Density, 12-V, 10-A Rail With LDO Low-Noise Auxiliary Output for RF Power Applications Figure 9-20 shows the schematic diagram of a 400-kHz, 12-V output, 10-A synchronous buck regulator intended for RF power applications. An auxiliary 10-V, 800-mA rail to power noise-sensitive circuits is available using the LP38798 ultra-low noise LDO as a post-regulator. The internal pull-up of the EN pin of the LP38798 facilitates direct connection to the PGOOD of the LM5145 for sequential start-up control. RUV2 RUV1 7.5 k 80.6 k VIN = 14.4 V to 48 V CVIN VOUT 0.1 F U1 1 20 EN/UVLO VIN RRT RC2 RFB1 100 24.9 k 33.2 k CC3 680 pF RC1 CC1 15 k 3.3 nF CC2 CSS 33 nF 56 pF RFB2 2.37 k SYNC Out SYNC In RBST 2.2 2 RT 3 SS/TRK HO 18 4 COMP SW 19 5 FB BST 17 Q1 LF CBST 4.7 H 0.1 F VOUT1 = 12 V NC 16 LM5145 6 AGND 7 SYNCOUT EP 15 8 SYNCIN 9 NC Q2 CIN VCC 14 COUT 5 u 4.7 F 5 u 47 F LO 13 12 ILIM PGND PGOOD 10 GND 11 D1 CVCC 2.2 F RILIM CILIM 402 10 pF U2 VOUT1 OUT 18 2 IN OUT 17 3 IN(CP) CLDO_IN 1 F 1 IN CCP OUT(FB) 16 4 CP SET 15 5 EN FB 14 VOUT2 = 10V RT CV2 1 F 73.5 k 10 nF 6 GND(CP) GND 13 RB 10 k LP38798SD-ADJ Copyright © 2017, Texas Instruments Incorporated Figure 9-20. Application Circuit 2 With LM5145 48-V to 12-V Synchronous Buck Regulator at 400 kHz Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 43 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.2.1 Design Requirements The required input, output, and performance parameters for this application example are shown in Table 9-7. Table 9-7. Design Parameters DESIGN PARAMETER VALUE Input voltage range (steady state) 14.4 V to 48 V Input transient voltage (peak) 56 V Output voltage and current 12 V, 10 A Input UVLO thresholds 14 V on, 13.2 V off Switching frequency 400 kHz Output voltage regulation ±1% Load transient peak voltage deviation, 5-A load step < 120 mV 9.2.2.2 Detailed Design Procedure A high power density, high-efficiency regulator solution uses TI NexFET™ Power MOSFETs, such as CSD18563Q5A (60-V, 6-mΩ MOSFET in a SON 5-mm × 6-mm package), together with a low-DCR inductor and all-ceramic capacitor design. The design occupies 30 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is set at 14 A based on the resistor R ILIM and the 6-mΩ R DS(on) of the low-side MOSFET (typical at T J = 25°C and V GS = 7.5 V). The 12-V output is connected to VCC through a diode, D1, to reduce IC bias power dissipation. The selected buck converter powertrain components are cited in Table 9-8, including power MOSFETs, buck inductor, input and output capacitors, and ICs. Use the LM5145 Quickstart Calculator to find compensation components that are selected based on a target loop crossover frequency of 40 kHz and phase margin greater than 55°. The output voltage soft-start time is 4 ms based on the selected soft-start capacitance, CSS, of 33 nF. Table 9-8. List of Materials for Application Circuit 2 REFERENCE DESIGNATOR QTY CIN 5 5 SPECIFICATION MANUFACTURER 4.7 µF, 100 V, X7S, 1210, ceramic 47 µF, 16 V, X5R, 1210, ceramic COUT 7 22 µF, 25 V, X7R, 1210, ceramic PART NUMBER TDK C3225X7S2A475M Murata GRM32DC72A475KE01L Taiyo Yuden HMK325C7475MN-TE Murata GRM32ER61C476KE15K Würth Electronik 885012109011 Murata GRM32ER71E226KE15L Taiyo Yuden TMK325B7226MM-TR TDK C3225X7R1E226M 4.7 µH, 7.8 mΩ, 25 A, 13.45 × 12.6 × 6.3 mm Cyntec CMLS136E-4R7MS 4.7 µH, 6.5 mΩ, 27 A, 12.5 × 12.5 × 6.2 mm Würth Electronik WE-LHMI 744373965047 Coilcraft XAL1060-472ME Texas Instruments CSD18563Q5A LF 1 Q1, Q2 2 60 V, 6 mΩ, MOSFET, SON 5 × 6 U1 1 Wide VIN synchronous buck controller Texas Instruments LM5145RGYR U2 1 Ultra-low noise and high-PSRR LDO Texas Instruments LP38798SD-ADJ 4.7 µH, 9.75 mΩ, 25 A, 11.3 × 10 × 6 mm As shown in Figure 9-20, a 2.2-Ω resistor in series with C BST is used to slow the turn-on transition of the highside MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics for more detail. 44 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.2.3 Application Curves 100 VSW 10 V/DIV VSYNCOUT 1 V/DIV Efficiency (%) 95 90 85 VIN = 14V VIN = 18V VIN = 24V VIN = 36V VIN = 48V 80 1 Ps/DIV 75 0 2 4 6 Output Current (A) 8 10 Figure 9-21. Efficiency vs IOUT and VIN VIN 10V/DIV VIN = 48 V IOUT = 10 A Figure 9-22. SYNCOUT and SW Node Voltages VOUT 2V/DIV VOUT 2V/DIV IOUT 2A/DIV IOUT 2A/DIV VIN 10V/DIV PGOOD 2V/DIV PGOOD 2V/DIV 1 ms/DIV 400 Ps/DIV VIN step to 48 V 1.2-Ω Load Figure 9-23. Start-Up, 10-A Resistive Load 1.2-Ω Load Figure 9-24. Shutdown Through Input UVLO, 10-A Resistive Load VOUT 2V/DIV VOUT 2V/DIV IOUT 2A/DIV IOUT 2A/DIV ENABLE 1V/DIV PGOOD 2V/DIV ENABLE 1V/DIV 1 ms/DIV VIN = 48 V 100 Ps/DIV 1.2-Ω Load Figure 9-25. ENABLE ON, 10-A Resistive Load VIN = 48 V PGOOD 2V/DIV 1.2-Ω Load Figure 9-26. ENABLE OFF, 10-A Resistive Load Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 45 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 VOUT 200m/DIV VOUT 100m/DIV IOUT 5A/DIV IOUT 2A/DIV 100 Ps/DIV 100 Ps/DIV VIN = 48 V VIN = 48 V Figure 9-27. Load Transient Response, 5 A to 10 A to 5 A Figure 9-28. Load Transient Response, 0 A to 10 A to 0 A VOUT 50mV/DIV VOUT 50mV/DIV IOUT 2A/DIV IOUT 2A/DIV VIN 10V/DIV VIN 10V/DIV 2 ms/DIV 2 ms/DIV IOUT = 10 A IOUT = 10 A Figure 9-29. Line Transient Response, 24 V to 48 V Figure 9-30. Line Transient Response, 48 V to 24 V VSW 10 V/DIV VOUT 2V/DIV VSYNCIN 1 V/DIV ENABLE 1V/DIV PGOOD 2V/DIV 1 ms/DIV VIN = 48 V 400 ns/DIV IOUT = 0 A Figure 9-31. Pre-Biased Start-Up 46 VIN = 48 V IOUT = 0 A Figure 9-32. SW Node and SYNCIN Voltages Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.3 Design 3 – 150-W, Regulated 24-V Rail for Commercial Drone Applications With Output Voltage Tracking Feature Figure 9-33 shows the schematic diagram of a 150-W, regulated 24-V buck regulator for commercial drone applications with output voltage tracking feature. VTRACK RUV2 RUV1 8.87 k 200 k VIN = 28 V to 75 V RTRK1 13.3 k VOUT CVIN 0.1 F RTRK2 2.49 k U1 RFB1 1k CC3 390 pF RC1 CC1 41.2 k 1 nF CC2 18 pF EN/UVLO VIN 2 RT 3 SS/TRK HO 18 4 COMP SW 19 5 FB BST 17 SYNC Out SYNC In Q1 LF 15 H VOUT = 24 V NC 16 LM5145 RFB2 2.49 k 0.1 F 22.6 k 72.3 k CBST 20 1 RRT RC2 6 AGND 7 SYNCOUT EP 15 8 SYNCIN 9 NC Q2 CIN VCC 14 5 u 2.2 F COUT 7 u 10 F LO 13 ILIM PGND PGOOD 10 12 GND 11 CVCC 2.2 F RPG PGOOD 20 k CILIM RILIM 499 10 pF Copyright © 2017, Texas Instruments Incorporated Figure 9-33. Application Circuit 3 With LM5145 48-V to 24-V Buck Regulator at 440 kHz 9.2.3.1 Design Requirements The intended input, output, and performance parameters are shown in Table 9-9 for this implementation example that derives power from large battery packs common to commercial drone and electric forklift applications. Table 9-9. Design Parameters DESIGN PARAMETER VALUE Input voltage range (steady state) 28 V to 75 V Input transient voltage (peak) 85 V Output voltage and current 24 V, 5 A Switching frequency 440 kHz Output voltage regulation ±1% Load transient peak voltage deviation, 2.5-A load step < 100 mV 9.2.3.2 Detailed Design Procedure Resistors R TRK1 and R TRK2 connected to the SS/TRK pin of the LM5145 define a ratiometric tracking start-up sequence from a master power supply, V TRACK. The output voltage ramps from 0 V to its nominal 24-V setpoint as the master supply ramps from 0 V to 5 V. See Section 8.3.7.1 for more detail. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 47 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 The selected buck converter power stage components are cited in Table 9-10. Note that additional input or output capacitance can be included in this design as needed, but you can view the LM5145 Quickstart Calculator to adjust the compensation circuit components if COUT changes. Table 9-10. List of Materials for Application Circuit 3 REFERENCE DESIGNATOR CIN COUT LF QTY 5 7 1 SPECIFICATION MANUFACTURER PART NUMBER TDK C3225X7S2A475M Murata GRM32DC72A475KE01L AVX 12101C225KAT2A 2.2 µF, 100 V, X7R, 1210, ceramic TDK C3225X7R1H106M 10 µF, 50 V, X7R, 1210, ceramic Murata GRM32ER71H106KA12L AVX 12105C106KAT2A 15 µH, 24 mΩ, 10 A, 13.45 × 12.6 × 5.8 mm Cyntec CMLB136T-150MS 15 µH, 24.4 mΩ, 10 A, 13.5 × 12.5 × 6.2 mm Würth Electronik WE LHMI 744373965150 Coilcraft XAL1010-153ME 15 µH, 18.6 mΩ, 15.5 A, 10.5 × 11.8 × 10.2 mm 48 Q1, Q2 2 100 V, 13 mΩ, MOSFET, SON 5 × 6 Texas Instruments CSD19534Q5A U1 1 Wide VIN synchronous buck controller Texas Instruments LM5145RGYR Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.3.3 Application Curves 100 Efficiency (%) 95 VSYNCOUT 1 V/DIV VSW 10 V/DIV 90 85 80 VIN = 36V VIN = 48V VIN = 60V VIN = 75V 75 70 0 1 2 3 Output Current (A) 4 5 1 Ps/DIV VIN = 48 V Figure 9-34. Efficiency vs IOUT and VIN IOUT = 5 A Figure 9-35. SW Node and SYNCOUT Voltages VOUT 5V/DIV VIN 10V/DIV VOUT 5V/DIV VIN 20V/DIV IOUT 2A/DIV IOUT 2A/DIV PGOOD 2V/DIV PGOOD 2V/DIV 2 ms/DIV 200 Ps/DIV VIN ramped to 60 V 5-Ω Load Figure 9-36. Start-Up, 5-A Resistive Load VIN 85 V to 48 V 5-Ω Load Figure 9-37. Shutdown Through Input UVLO, 5-A Resistive Load VOUT 5V/DIV VOUT 5V/DIV IOUT 2A/DIV ENABLE 1V/DIV IOUT 2A/DIV PGOOD 2V/DIV ENABLE 1V/DIV 1 ms/DIV VIN = 60 V 100 Ps/DIV 5-Ω Load Figure 9-38. ENABLE ON, 5-A Resistive Load VIN = 60 V PGOOD 2V/DIV 5-Ω Load Figure 9-39. ENABLE OFF, 10-A Resistive Load Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 49 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 VOUT 200m/DIV VOUT 100m/DIV IOUT 2A/DIV IOUT 2A/DIV 100 Ps/DIV 100 Ps/DIV VIN = 48 V VIN = 48 V Figure 9-40. Load Transient Response, 2.5 A to 5 A to 2.5 A Figure 9-41. Load Transient Response, 0 A to 5 A to 0 A VOUT 100mV/DIV VOUT 100mV/DIV VIN 20V/DIV VIN 20V/DIV IOUT 2A/DIV IOUT 2A/DIV 10 ms/DIV 1 ms/DIV IOUT = 5 A IOUT = 5 A Figure 9-42. Line Transient Response, 48 V to 85 V Figure 9-43. Line Transient Response, 85 V to 48 V VSW 10 V/DIV VOUT 5V/DIV VSYNCIN 1 V/DIV ENABLE 1V/DIV 1 ms/DIV VIN = 60 V PGOOD 2V/DIV IOUT 2A/DIV IOUT = 0 A Figure 9-44. Pre-Biased Start-Up 50 400 ns/DIV VIN = 48 V IOUT = 0 A Figure 9-45. SW Node and SYNCIN Voltages at 600 kHz Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.4 Design 4 – Powering a Multicore DSP From a 24-V or 48-V Rail For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power House blog series. Figure 9-46 shows the schematic diagram of a 10-A synchronous buck regulator for a DSP core voltage supply. CVIN D1 0.1 F VIN = 6 V to 48 V VOUT U1 100 RFB1 33.2 k 6.81 k CC3 2.7 nF 1 20 EN/UVLO VIN RRT RC2 RC1 CC1 2.32 k 10 nF CC2 RFB2 18.2 k CSS 47 nF 470 pF CBST 0.1 F 2 RT 3 SS/TRK HO 18 4 COMP SW 19 5 FB BST 17 Q1 LF 1 H NC 16 LM5145 6 AGND SYNC Out 7 SYNCOUT SYNC In 8 SYNCIN 9 NC Core voltage 0.9 V ± 1.1 V EP 15 Q2 VCC 14 CIN Step resolution 6.4 mV 5 u 2.2 F LO 13 ILIM PGND PGOOD 10 12 11 CILIM 22 pF VAUX = 8 V to 13 V COUT RILIM 4 x 100 F CVCC 249 2.2 F U3 RPU1:4 DVDD18 CVDD U2 VIDS 10 VCNTL[3] 2 IDAC_OUT VIDC 9 VCNTL[2] 3 VIDB 8 VCNTL[1] VIDA 7 VCNTL[0] 1 3.3 V GND VDD 4 EN 5 MODE TMS320C667x KeyStone¥ Multicore DSP SET 6 RSET LM10011SD GND 182 k Copyright © 2017, Texas Instruments Incorporated Figure 9-46. Application Circuit 4 With LM5145 DSP Core Voltage Supply Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 51 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.4.1 Design Requirements For this application example, the intended input, output, and performance parameters are listed in Table 9-11. Table 9-11. Design Parameters DESIGN PARAMETER VALUE Input voltage range (steady-state) 6 V to 48 V Input transient voltage (peak) 55 V Output voltage and current 0.9 V to 1.1 V, 10 A Output voltage regulation ±1% Load transient peak voltage deviation, 10-A step < 120 mV Switching frequency 300 kHz 9.2.4.2 Detailed Design Procedure The schematic diagram of a 300-kHz, 24-V nominal input, 10-A regulator powering a KeyStone™ DSP is given in Figure 9-46. This high step-down ratio design leverages the low 40-ns minimum controllable on-time of the LM5145 controller to achieve stable, efficient operation at very low duty cycles. 60-V power MOSFETs, such as TI's CSD18543Q3A and CSD18531Q5A NexFET devices, are used together with a low-DCR, metal-powder inductor, and ceramic output capacitor implementation. An external rail between 8 V and 13 V powers VCC to minimize bias power dissipation, and a blocking diode connected to the VIN pin is used as recommended in Figure 8-2. The important components for this design are listed in Table 9-12. Table 9-12. List of Materials for Application Circuit 4 REFERENCE DESIGNATOR CIN QTY SPECIFICATION 5 2.2 µF, 100 V, X7R, 1206, ceramic 3 4.7 µF, 80 V, X7R, 1210, ceramic MANUFACTURER PART NUMBER Murata GRM31CR72A225MA73L 100 µF, 6.3V, X7S, 1210, ceramic COUT 4 100 µF, 6.3V, X5R, 1206, ceramic CL31B225KCHSNNE Murata GRM32ER71K475KE14L Murata GRM32EC70J107ME15L Taiyo Yuden JMK325AC7107MM-P Murata GRM31CR60J107ME39K TDK C3216X5R0J107M Würth Electronik 885012108005 1 µH, 5.6 mΩ, 16 A, 6.95 × 6.6 × 2.8 mm Cyntec CMLE063T-1R0MS 1 µH, 5.5 mΩ, 12 A, 6.65 × 6.45 × 3.0 mm Würth Electronik WE XHMI 74439344010 Panasonic ETQP3M1R0YFN LF 1 Coilcraft XEL6030-102ME Q1 1 60 V, 8.5 mΩ, high-side MOSFET, SON 3 × 3 Texas Instruments CSD18543Q3 A Q2 1 60 V, 4 mΩ, low-side MOSFET, SON 5 × 6 Texas Instruments CSD18531Q5A U1 1 Wide VIN synchronous buck controller Texas Instruments LM5145RGYR U2 1 6- or 4-bit VID voltage programmer, WSON-10 Texas Instruments LM10011SD U3 1 KeyStone™ DSP Texas Instruments TMS320C667x 1 µH, 7.9 mΩ, 16 A, 6.5 × 6.0 × 3.0 mm 1 µH, 6.95 mΩ, 18 A, 6.76 × 6.56 × 3.1 mm (1) Samsung Refer to Hardware Design Guide for Keystone I Devices (SPRAB12) and How to Optimize Your DSP Power Budget for further detail. The regulator output current requirements are dependent upon the baseline and activity power consumption of the DSP in a real-use case. While baseline power is highly dependent on voltage, temperature and DSP frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To this end, the IDAC_OUT pin of the LM10011 connects to the LM5145 FB pin to allow continuous optimization of the core voltage. The SmartReflex-enabled DSP provides 6-bit information using the VCNTL open-drain I/Os to command the output voltage setpoint with 6.4-mV step resolution. (1) 52 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 9.2.4.3 Application Curves 100 VOUT 0.2V/DIV Efficiency (%) 80 VIN 5V/DIV 60 40 IOUT 5A/DIV VIN = 6V VIN = 12V VIN = 24V VIN = 36V VIN = 48V 20 PGOOD 2V/DIV 0 0 2 4 6 Output Current (A) VOUT = 1.1 V 8 10 VAUX = 8 V Figure 9-47. Efficiency vs IOUT and VIN 1 ms/DIV VIN step to 24 V 0.11-Ω Load Figure 9-48. Start-Up, 10-A Resistive Load VOUT 0.2V/DIV VOUT 100m/DIV ENABLE 1V/DIV IOUT 5A/DIV IOUT 2A/DIV PGOOD 2V/DIV 40 Ps/DIV 1 ms/DIV VIN = 24 V 0.11-Ω Load Figure 9-49. ENABLE ON and OFF, 10-A Resistive Load VIN = 24 V Figure 9-50. Load Transient Response, 0 A to 10 A to 0 A Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 53 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 10 Power Supply Recommendations The LM5145 buck controller is designed to operate from a wide input voltage range from 6 V to 75 V. The characteristics of the input supply must be compatible with the Section 7.1 and Section 7.3 tables. In addition, the input supply must be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input current with Equation 23. IIN VOUT ˜ IOUT VIN ˜ K (23) where • η is the efficiency If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables may have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps to hold the input voltage steady during large load transients. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching regulator. 54 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 11 Layout 11.1 Layout Guidelines Proper PCB design and layout is important in a high-current, fast-switching circuits (with high current and voltage slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must be considered before designing a PCB layout using the LM5145. The high-frequency power loop of the buck converter power stage is denoted by #1 in the shaded area of Figure 11-1. The topological architecture of a buck converter means that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important is the gate drive loops of the low-side and high-side MOSFETs, denoted by 2 and 3, respectively, in Figure 11-1. VIN LM5145 VCC 14 17 BST CIN CBST High-side gate driver 18 19 14 #1 High frequency power loop HO SW 13 LF #2 VOUT VCC CVCC Low-side gate driver Q1 LO PGND Q2 COUT #3 12 GND Copyright © 2017, Texas Instruments Incorporated Figure 11-1. DC-DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops 11.1.1 Power Stage Layout 1. Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout, small-signal components are typically placed on the bottom side (component side). insert at least one inner plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines. 2. The DC/DC converter has several high-current loops. Minimize the area of these loops in order to suppress generated switching noise and parasitic loop inductance and optimize switching performance. • Loop #1: The most important loop to minimize the area of is the path from the input capacitor or capacitors through the high- and low-side MOSFETs, and back to the capacitor(s) through the ground connection. Connect the input capacitor or capacitors negative terminal close to the source of the low-side MOSFET (at ground). Similarly, connect the input capacitor or capacitors positive terminal close to the drain of the high-side MOSFET (at VIN). Refer to loop #1 of Figure 11-1. • Another loop, not as critical though as loop #1, is the path from the low-side MOSFET through the inductor and output capacitor(s), and back to source of the low-side MOSFET through ground. Connect the source of the low-side MOSFET and negative terminal of the output capacitor(s) at ground as close as possible. 3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and wide. However, the SW connection is a source of injected EMI and thus must not be too large. 4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including pad geometry and solder paste stencil design. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 55 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the high-side gate driver. The parasitic inductance inherent to loop #1 in Figure 11-1 and the output capacitance (COSS) of both power MOSFETs form a resonant circuit that induces high frequency (>100 MHz) ringing on the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then include snubber components as needed. 11.1.2 Gate Drive Layout The LM5145 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time control and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important: • Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turn-on, high current flows from the bootstrap (boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side MOSFET through the SW trace. Refer to loop #2 of Figure 11-1. • Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turn-on, high current flows from the VCC decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET through ground. Refer to loop #3 of Figure 11-1. TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits. 1. Connections from gate driver outputs, HO and LO, to the respective gate of the high-side or low-side MOSFET must be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or wider traces. Use a via or vias, if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from the LM5145 to the high-side MOSFET, taking advantage of flux cancellation. 2. Minimize the current loop path from the VCC and BST pins through their respective capacitors as these provide the high instantaneous current, up to 3.5 A, to charge the MOSFET gate capacitances. Specifically, locate the bootstrap capacitor, CBST, close to the BST and SW pins of the LM5145 to minimize the area of loop #2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and PGND pins of the LM5145 to minimize the area of loop #3 associated with the low-side driver. 3. Placing a 2-Ω to 10-Ω resistor in series with the boot capacitor, as shown in Figure 9-20, slows down the high-side MOSFET turn-on transition, serving to reduce the voltage ringing and peak amplitude at the SW node at the expense of increased MOSFET turn-on power loss. 11.1.3 PWM Controller Layout With the proviso to locate the controller as close as possible to the MOSFETs to minimize gate driver trace runs, the components related to the analog and feedback signals, current limit setting, and temperature sense are considered in the following: 1. Separate power and signal traces, and use a ground plane to provide noise shielding. 2. Place all sensitive analog traces and components such as COMP, FB, RT, ILIM and SS/TRK away from highvoltage switching nodes such as SW, HO, LO or BST to avoid mutual coupling. Use an internal layer or layers 56 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 as a ground plane or ground planes. Pay particular attention to shielding the feedback (FB) trace from power traces and components. 3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or the bulk capacitor at the converter side. 4. Connect the ILIM setting resistor from the drain of the low-side MOSFET to ILIM and make the connections as close as possible to the LM5145. The trace from the ILIM pin to the resistor must avoid coupling to a highvoltage switching net. 5. Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the GND pin. Locate these capacitors as close as possible to the LM5145. 11.1.4 Thermal Design and Layout The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO regulator is greatly affected by: • average gate drive current requirements of the power MOSFETs; • switching frequency; • operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation); • thermal characteristics of the package and operating environment. For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM5145 controller is available in a small 3.5-mm × 4.5-mm 20-pin VQFN (RGY) PowerPAD™ package to cover a range of application requirements. The thermal metrics of this package are summarized in Section 7.4. The application report Semiconductor and IC Package Thermal Metrics provides detailed information regarding the thermal information table. The 20-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any leads of the package, it is thermally connected to the substrate of the LM5145 device (ground). This allows a significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM5145 is soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the thermal resistance to a very low value. Wide traces of the copper tying in the no-connect pins of the LM5145 (pins 9 and 16) and connection to this thermal land helps to dissipate heat. Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow but it also represents a thermally conductive path away from the heat generating devices. The thermal characteristics of the MOSFETs also are significant. The drain pad of the high-side MOSFET is normally connected to a VIN plane for heat sinking. The drain pad of the low-side MOSFET is tied to the SW plane, but the SW plane area is purposely kept relatively small to mitigate EMI concerns. 11.1.5 Ground Plane Design As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended. A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control circuitry. Connect the PGND pin to the system ground plane using an array of vias under the exposed pad. Also connect the PGND directly to the return terminals of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce because of load current variations. The power traces for PGND, VIN and SW can be restricted to one side of the ground plane. The other side of the ground plane contains much less noise and is ideal for sensitive analog trace routes. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 57 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 11.2 Layout Example Figure 11-2 shows an example PCB layout based on the LM5145EVM-HD-20A design. The power component connections are made on the top layer with wide, copper-filled areas. A power ground plane is placed on layer 2 with 6 mil (0.15 mm) spacing to the top layer. The small area of the buck regulator hot loop is denoted by the white border in Figure 11-2. This is critical to minimize EMI as well as switch-node voltage overshoot and ringing. The LM5145 is located on the bottom side with a surrounding analog ground plane for sensitive analog components as shown in Figure 11-3. The analog ground plane (AGND) and power ground plane (PGND) are connected at a single point directly under the IC (at the die attach pad or DAP). Refer to the LM5145EVMHD-20A High Density Evaluation Module User's Guide and LM5146-Q1-EVM12V Evaluation Module User's Guide for more detail. LF Inductor Output Capacitors Low-side MOSFET G SW Copper D Cout4 Cout3 Cout2 Cout1 VOUT S Q2 GND Input Capacitors High-side MOSFET Cin3 Q1 D Cin1 Power Loop Cin2 G S VIN Legend Top Layer Copper Layer 2 GND Plane Top Solder Figure 11-2. LM5145 Power Stage PCB Layout 58 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 CILIM To VOUT To D O O PG 10 RFB1 RFB2 CC3 RTRIM RC1 11 9 12 AGND RUV2 CC1 RRT To Gate of Low-side MOSFET 19 1 CSS To SW RBOOT 2 CC2 PGND LM5145 RC2 RILIM CVCC RBODE 20 CVIN CBOOT RVIN To Gate of High-side MOSFET To Source of High-side MOSFET RUV1 To VIN Legend Bottom Layer Copper Layer 3 GND Plane Bottom Solder Figure 11-3. LM5145 Controller PCB Layout (Viewed From Top) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 59 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.1.2 Development Support With an input operating voltage as low as 3.5 V and up to 100 V as specified in Table 12-1, the LM(2)514x family of synchronous buck controllers from TI provides flexibility, scalability and optimized solution size for a range of applications. These controllers enable DC/DC solutions with high density, low EMI and increased flexibility. Table 12-1. Synchronous Buck DC/DC Controller Family DC/DC CONTROLLER SINGLE or DUAL VIN RANGE CONTROL METHOD GATE DRIVE VOLTAGE SYNC OUTPUT PRGRAMMABLE DITHER LM5140-Q1 Dual 3.8 V to 65 V Peak current mode 5V 180° phase shift N/A LM25141 Single 3.8 V to 42 V Peak current mode 5V N/A Yes LM5141 Single 3.8 V to 65 V Peak current mode 5V N/A Yes LM5143-Q1 Dual 3.5 V to 65 V Peak current mode 5V 90° phase shift Yes LM25145 Single 6 V to 42 V Voltage mode 7.5 V 180° phase shift N/A LM5145 Single 6 V to 75 V Voltage mode 7.5 V 180° phase shift N/A LM5146-Q1 Single 5.5 V to 100 V Voltage mode 7.5 V 180° phase shift N/A For development support see the following: • • • • • • LM5145 Quickstart Calculator LM5145 Simulation Models For TI's reference design library, visit TI Designs For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center TI Reference Designs: – 57W Output Synchronous Buck Converter for Telecom Reference Design – 20-A Automotive Pre-regulator Reference Design With Extended Input Voltage Range for Trucks – 20-A Automotive Pre-regulator Reference Design – 10-A Automotive Pre-regulator Reference Design With Extended Input Voltage Range for Trucks – 10-A Automotive Pre-regulator Reference Design Technical Articles: – High-Density PCB Layout of DC/DC Converters – Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility – How to Use Slew Rate for EMI Control 12.1.3 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM5145 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: 60 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com • • • • SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 Run electrical simulations to see important waveforms and circuit performance Run thermal simulations to understand board thermal performance Export customized schematic and layout into popular CAD formats Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: • • • • • • • LM5146-Q1 EVM User's Guide LM5145 EVM User's Guide LM5143-Q1 Synchronous Buck Controller EVM LM5143-Q1 Synchronous Buck Controller High-Density 4-Phase Design Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics AN-2162 Simple Success with Conducted EMI from DC-DC Converters White Papers: – Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications – An Overview of Conducted EMI Specifications for Power Supplies – An Overview of Radiated EMI Specifications for Power Supplies 12.2.1.1 PCB Layout Resources • • • • Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout AN-1149 Layout Guidelines for Switching Power Supplies Constructing Your Power Supply – Layout Considerations Technical Articles: – High-Density PCB Layout of DC-DC Converters 12.2.1.2 Thermal Design Resources • • • • • • • AN-2020 Thermal Design by Insight, Not Hindsight AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Semiconductor and IC Package Thermal Metrics Thermal Design Made Simple with LM43603 and LM43602 PowerPAD™Thermally Enhanced Package PowerPAD Made Easy Using New Thermal Metrics 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 61 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 12.5 Trademarks NexFET™ and TI E2E™ are trademarks of Texas Instruments. KeyStone™ is a trademark of TI. PowerPAD™ is a trademark of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. are registered trademarks of Texas Instruments. is a registered trademark of TI. All trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary TI Glossary 62 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 63 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 PACKAGE OUTLINE RGY0020B VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD 3.6 3.4 A B PIN 1 INDEX AREA 4.6 4.4 0.1 MIN (0.05) SECTION A-A SECTION A-A SCALE 30.000 TYPICAL C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 1.7 0.1 (0.2) TYP 2X 1.5 10 14X 0.5 9 2X 3.5 EXPOSED THERMAL PAD 11 12 21 SYMM 2.7 0.1 A A 2 PIN 1 ID (OPTIONAL) 19 1 SYMM 20X 20 0.3 0.2 0.1 0.05 0.5 20X 0.3 C A B 4222860/B 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com 64 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 EXAMPLE BOARD LAYOUT RGY0020B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (1.7) SYMM 1 20 20X (0.6) 2 19 20X (0.25) (1.1) (4.3) 21 SYMM (2.7) 14X (0.5) (0.6) 9 12 (R0.05) TYP 11 10 (0.75) TYP (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4222860/B 06/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 65 LM5145 www.ti.com SNVSAI4B – NOVEMBER 2017 – REVISED NOVEMBER 2020 EXAMPLE STENCIL DESIGN RGY0020B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X (0.75) (R0.05) TYP 1 20 20X (0.6) 2 19 21 20X (0.25) 4X (1.21) SYMM (4.3) (0.71) TYP 14X (0.5) 12 9 METAL TYP 11 10 4X (0.75) (0.475) TYP SYMM (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4222860/B 06/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com 66 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM5145 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM5145RGYR ACTIVE VQFN RGY 20 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM5145 LM5145RGYT ACTIVE VQFN RGY 20 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM5145 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of