LM8323
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SNLS273A – JULY 2010 – REVISED MARCH 2013
LM8323 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and
ACCESS.bus Host Interface
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FEATURES
1
•
2
•
Key Features
– Supports Keypad Matrices of up to 8 × 12
Keys Plus 8 Special-function (SF) Keys for
a Total of 104 Keys. SF Keys Pull Keypad
Scan Inputs Directly to Ground, Rather than
Connecting to a Keypad Scan Output.
– Supports I2C-compatible ACCESS.bus
Interface in Slave Mode up to 400 kHz
(Fast-mode).
– Three Host-programmable PWM Outputs
Useful for Smooth LED Brightness
Modulation.
– Supports General-purpose I/O Expansion
on Pins Not Otherwise Used for Keypad or
Rotary Encoder Interface.
– Key-scan Event Storage in a FIFO Buffer for
up to 15 Events.
– Key Events, Errors, and Dedicated
Hardware Interrupts Request Host Service
by Asserting the IRQ Output.
– The Correct Reception of a Command May
be Assumed, if No Error is Reported from
the LM8323 After Receiving it.
– Wake-up from Halt Mode on any Matrix
Key-scan Event, any Use of the SF Keys, or
Any Activity on the ACCESS.bus Interface,
or Any Change in the Rotary Encoder
Counter Value (if Enabled).
Host-Controlled Functions
– Three PWM Outputs
– Period of Inactivity that Triggers Entry into
Halt Mode
– Debounce Time for Reliable Key Event
•
Polling
– Configuration of General-purpose I/O Ports
– Various Initialization Options (Keypad Size,
etc.)
Key Device Characteristics
– 1.8V ± 180 mV Single-supply Operation
– On-chip Power-on Reset (POR)
– Watchdog Timer
– Dedicated Slow Clock Input for 32 kHz
– -40°C to +85°C Industrial Temperature
Range
– 36-pin csBGA Package
APPLICATIONS
•
•
Cordless Phones
Smart Handheld Devices
DESCRIPTION
The LM8323 key-scan controller is a dedicated
device to unburden a host from scanning a matrixaddressed keypad. In addition, the LM8323 provides
general-purpose I/O expansion, a rotary encoder
interface and PWM outputs useful for dynamic LED
brightness modulation.
It communicates with the host through an I2Ccompatible ACCESS.bus interface. An interrupt
output is available for signaling key-press and keyrelease events. Communication frequencies up to
400 kHz (Fast-mode) bus speed are supported. The
LM8323 supports a predefined set of commands.
These commands enable a host device to keep
control over all functions.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM8323
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BLOCK DIAGRAM
2
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PIN ASSIGNMENTS
Figure 1. Top View
36-Pin csBGA Package
See Package Number NYB0036A
SIGNAL DESCRIPTIONS
Pin
Function
I/O
A6
KP-X0
Input
Wake-up input/Keyboard scanning input 0
A5
KP-X1
Input
Wake-up input/Keyboard scanning input 1
F1
KP-X2
Input
Wake-up input/Keyboard scanning input 2
KP-X3
Input
Wake-up input/Keyboard scanning input 3
GPIO_13
I/O
F2
A2
B3
A3
B4
KP-X4
Input
GPIO_12
I/O
KP-X5
Input
Description
General-purpose I/O port 13
Wake-up input/Keyboard scanning input 4
General-purpose I/O port 12
Wake-up input/Keyboard scanning input 5
GPIO_11
I/O
KP-X6
Input
General-purpose I/O port 11
GPIO_10
I/O
KP-X7
Input
Wake-up input/Keyboard scanning input 7
Wake-up input/Keyboard scanning input 6
General-purpose I/O port 10
GPIO_09
Input
General-purpose I/O port 9
C6
KP_Y0
Output
Keyboard scanning output 0
C5
KP-Y1
Output
Keyboard scanning output 1
B6
KP-Y2
Output
Keyboard scanning output 2
KP-Y3
Output
Keyboard scanning output 3
GPIO_08
I/O
General-purpose I/O port 8
B5
B2
A1
B1
C2
KP-Y4
Output
Keyboard scanning output 4
GPIO_07
I/O
General-purpose I/O port 7
KP-Y5
Output
Keyboard scanning output 5
GPIO_06
I/O
General-purpose I/O port 6
KP-Y6
Output
Keyboard scanning output 6
GPIO_05
I/O
General-purpose I/O port 5
KP-Y7
Output
Keyboard scanning output 7
GPIO_04
I/O
General-purpose I/O port 4
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SIGNAL DESCRIPTIONS (continued)
Pin
Function
I/O
KP-Y8
Output
Keyboard scanning output 8
SLOWCLKOUT
Output
32.768 kHz clock output
GPIO_03
I/O
General-purpose I/O port 3
KP-Y9
Output
Keyboard scanning output 9
MUX2_IN1
Input
GPIO_02
I/O
KP-Y10
Output
MUX2_IN2
Input
GPIO_01
I/O
KP-Y11
Output
Keyboard scanning output 11
F6
MUX2_OUT
Output
Multiplexer 2 output
GPIO_00
I/O
General-purpose I/O port 0
E2
ACB_SDA
I/O
ACCESS.bus data signal
E1
ACB_SCL
I/O
ACCESS.bus clock signal
E3
D5
E6
E4
F5
E5
D6
D1
D2
4
PWM_0
Output
MUX_IN1
Input
PWM_1
Output
Description
Multiplexer 2 input 1
General-purpose I/O port 2
Keyboard scanning output 10
Multiplexer 2 input 2
General-purpose I/O port 1
Pulse-width modulated output 0
Multiplexer 1 input 1
Pulse-width modulated output 1
MUX_IN2
Input
PWM_2
Output
Multiplexer 1 input 2
Pulse-width modulated output 2
MUX1_OUT
Output
Multiplexer 1 output
CONFIG_2
Input
Slave address select input 2
GPIO_15
I/O
General-purpose I/O port 15
CONFIG_1
Input
Slave address select input 1
GPIO_14
I/O
General-purpose I/O port 14
XTAL_OUT
Output
SLOWCLK
Input
32.768 kHz clock
XTAL_IN
Input
32.768 kHz crystal input
Interrupt request output
32.768 kHz crystal output
F3
IRQ
Output
C1
RESET
Input
Reset Input
A4, F4
VCC
N/A
VCC
C3, C4,
D3, D4
GND
N/A
Ground
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TERMINATION OF UNUSED SIGNALS
TERMINATION OF UNUSED SIGNALS
Signal
RESET
CONFIG_1
XTAL_IN
XTAL_OUT
KP-X[2:0]
Termination
Connect to VCC if not driven from an external Supervisory circuit.
Connect to VCC or GND through a pullup or pulldown resistor because the slave address is selected by the
level on this pin. This pin cannot be left unconnected.
This pin is a high-impedance input and must be connected to VCC or GND if it is unused.
This pin has a weak pullup and can be left open-circuit if it is unused.
These pins are dedicated keypad pins. In the minimum configuration, these pins are keypad inputs with weak
pullups.
These pins are in high-impedance mode after power-on initialization. There are two ways to handle these pins
if unused:
KP-X[7:3]
•
Connect to VCC or GND.
•
Program as inputs with weak pullups or outputs.
Care must be taken when connecting to VCC or GND. Erroneous parameters sent with the
WRITE_PORT_SEL or WRITE_PORT_STATE commands could cause excessive current consumption. A
better approach is to leave unused keyboard inputs open-circuit and use the WRITE_PORT_SEL and
WRITE_PORT_STATE commands to configure the pins as inputs with weak pullups or outputs.
KP-X7 can only be an input. This pin should be programmed as an input with a weak pullup.
KP-Y[2:0]
These pins are dedicated keypad pins. In the minimum configuration, these pins are keypad outputs driven low.
These pins are in high-impedance mode after power-on initialization. There are two ways to handle these pins
if unused:
KP-Y[11:3]
•
Connect to VCC or GND.
•
Program as inputs with weak pullups or outputs
Care must be taken when connecting to VCC or GND. Erroneous parameters sent with the
WRITE_PORT_SEL or WRITE_PORT_STATE commands could cause excessive current consumption. A
better approach is to leave unused keyboard inputs open-circuit and use the WRITE_PORT_SEL and
WRITE_PORT_STATE commands to configure the pins as inputs with weak pullups or outputs.
PWM_0,
PWM_1
These pins must be connected to VCC or GND if they are not used for any optional function described in the
datasheet.
PWM_2/
CONFIG_2
Connect to VCC or GND through a pullup or pulldown resistor because the slave address is selected by the
level on this pin. This pin cannot be left unconnected.
IRQ
This pin must be connected.
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APPLICATION EXAMPLE
VCC
VCC RESET
SDA
Host
Processor
SCL
IRQ
XTAL_IN
KP-Y0
KP-Y1
KP-Y2
KP-Y3
KP-Y4
KP-Y5
KP-Y6
KP-Y7
KP-Y8
XTAL_OUT
LM8323
Keypad
I/O Controller
GPIO_14
CONFIG_1
GPIO_15
CONFIG_2
SF Keys
KP-X0
KP-X1
KP-X2
KP-X3
PWM_1
KP-X4
PWM_0
KP-X5
ROT_IN_1
KP-X6
ROT_IN_2
ROT_IN_3
KP-X7
GND
Figure 2. Typical Application
FEATURES
The application example shown in Figure 2 supports the following features:
• 8 x 9 standard keys.
• 8 special function keys (SF keys) with wake-up capability by forcing a WAKE_INx pin to ground. Pressing a
SF key overrides any other key in the same row.
• ACCESS.bus (I2C-compatible) interface for communication with the host.
• Hardware IRQ interrupt to host to signal keypad, rotary encoder, error, and status events. By default, this is
an open-drain output, so an external pullup resistor may be required to avoid false assertion. The host can
program this output for push-pull mode, in which case the pullup might not be required, if the host can ignore
a false assertion before the LM8323 has been programmed.
• Two LEDs driven by PWM outputs with programmable ramp-up and ramp-down. PWM_2 (shared with
GPIO_15 and CONFIG_2) could be used as an additional PWM driver port to control a third external LED.
• Rotary encoder interface shares pins with KP-Y9, KP-Y10, and KP-Y11. For larger keyboard configurations
(such as QWERTY layouts), the rotary encoder interface is not available.
• ACCESS.bus address is selected by the CONFIG_1 and CONFIG_2 inputs. These pins may also be used as
GPIO pins after reset initialization has occurred. If extra GPIO pins are not needed, CONFIG_1 and
CONFIG_2 may be tied directly to VCC and GND.
• Crystal pins XTAL_IN and XTAL_OUT may be used to connect to an external 32.768 kHz crystal or receive
an external 32.768 kHz clock input for running the PWM peripheral. By default, the PWM is clocked by an onchip clock source.
CLOCKS
•
•
6
System Clock (mclk) — The system clock is in the range of about 21 MHz (±7%) typical. This clock is used
to drive the I2C-compatible serial ACCESS bus and is the input clock for other function blocks.
Processing and Command Execution Clock (tC) — The internal processing is based on a 2MHz clock. This
clock is derived from the System Clock.
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•
•
•
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Internal PWM Clock — The internal PWM clock is a fixed scaled down clock (÷ 64) of the Processing and
Command Execution Clock. This clock is close to 32 kHz which is in a good range to source the PWM
function block as an alternative to an external clock source.
External 32.768 kHz Clock — driven into the SLOWCLK input. May be used internally as the timebase for
the PWM and driven on the SLOWCLKOUT output.
External 32.768 kHz Crystal — connected across the XTAL_IN and XTAL_OUT pins (XTAL_IN is an
alternate function of the SLOWCLK pin). May be used internally as the timebase for the PWM and driven on
the SLOWCLKOUT output.
Figure 3. Clock Architecture
INTERNAL EXECUTION CYCLE
The Processing - and Command - execution clock is about 2MHz. This clock is stopped in Halt mode, which only
occurs under control of the LM8323. However, the host can set the period of inactivity which causes the device
to enter Halt mode.
Exit from Halt mode can be triggered by any of these events:
• Occurrence of a key-press or key-release event.
• A Start condition driven by the host on the ACCESS.bus interface.
• Any change to the rotary encoder counter value (if the interface is enabled).
• Assertion of the RESET input.
After reset, the default timebase for the PWM outputs is the internal execution clock divided by 64.
BUFFERED CLOCK
The timebase for the PWM comes from any of three sources:
• Prescaled internal Execution clock.
• External 32.768 kHz clock received on the SLOWCLK input.
• On-chip oscillator with an external crystal connected across XTAL_IN and XTAL_OUT.
Any of these sources may be buffered and driven on the SLOWCLKOUT output. The clock buffer is enabled with
the WRITE_CLOCK command.
If XTAL_IN is not used it must be terminated to VCC or GND.
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CLOCK CONFIGURATION
Table 1 shows the clock configurations available by loading the clock configuration register with the
WRITE_CLOCK command. The WRITE_CLOCK command must be issued only once during system initialization.
This command is used to override the default settings.
Table 1. Clock Configuration Register
7
0
6
SLOWCLKOUT
Bit
SLOWCLKOUT
SLOWCLKEN
RCPWM
5
0
4
0
Value
3
SLOWCLKEN
2
0
1
0
RCPWM
Description
0
Disable SLOWCLKOUT buffer.
1
Enable SLOWCLKOUT buffer.
0
External 32.768 kHz crystal is installed between the XTAL_IN and XTAL_OUT pins.
1
External 32.768 kHz clock is received on the SLOWCLK pin, or no 32.768 kHz clock is required.
00
On-chip RC clock divided by 64 drives the PWM and clock buffer.
01
Reserved
10
Reserved
11
External 32.768 kHz clock or crystal drives the PWM and clock buffer.
The SLOWCLKOUT signal is an alternate function of the pin used for the KP-Y8 scanning output and the
GPIO_03 port. If the SLOWCLKOUT function is enabled, these other functions of the pin are unavailable.
RESET
The LM8323 may be reset by either an external reset, RESET command, or an internally generated power-on
reset (POR) signal. The RESET input must not be allowed to float. If the external RESET input is not used, it
must be connected to VCC, either directly or through a pull-up resistor.
EXTERNAL RESET
The device enters a reset state immediately when the RESET input is driven low. RESET must be held low for a
minimum of 700 ns to ensure a valid reset. If RESET is asserted at power-on, it must be held low until VCC rises
above the minimum operating voltage (1.62V). If an RC circuit is used to drive RESET, it must have a time
constant 5 times (5×) greater than the VCC rise time to this level.
When RESET goes low, the I/O ports are initialized immediately, any observed delay being only propagation
delay. When the RESET pin goes high, the LM8323 comes out of the reset state within about 1400 ns.
POWER-ON RESET (POR)
The POR circuit is always enabled. When VCC rises above the POR threshold voltage VPOR (about 1.2–1.5V), an
on-chip reset signal is asserted. The VCC rise time must be greater than 20 µs and less than 10 ms, otherwise
the on-chip reset signal may deassert before VCC reaches the minimum operating voltage. While VCC is below
VPOR, the LM8323 is held in reset and a timer clocked by the on-chip RC clock is preset with 0xFF (256 clock
cycles). When VCC reaches a value greater than VPOR, the timer starts counting down. When it underflows, the
on-chip reset signal is deasserted and the LM8323 begins operation.
PIN CONFIGURATION AFTER RESET
Table 2 shows the pin configuration after reset.
8
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Table 2. Pin Configuration After Reset
Pins
After Reset
After LM8323 Initialization
KP-X00
KP-X01
High-impedance mode.
Input mode with an on-chip pullup enabled.
High-impedance mode.
High-impedance mode, until host configures them as keypad inputs or GPIO.
High-impedance mode.
Active drive low.
High-impedance mode.
High-impedance mode, until host configures them as keypad outputs or GPIO.
High-impedance mode.
The ACCESS.bus slave address must be selected with external pullup or
pulldown resistors or direct connections to VCC or GND.
High-impedance mode.
Active drive low.
High-impedance mode.
High-impedance mode.
Open-drain mode.
Open-drain mode.
High-impedance mode.
High-impedance mode. Terminate to VCC or GND if not used.
Weak pullup device.
Weak pullup device.
High-impedance mode.
High-impedance mode.
KP-X02
KP-X03
KP-X04
KP-X05
KP-X06
KP-X07
KP-Y00
KP-Y01
KP-Y02
KP-Y03
KP-Y04
KP-Y05
KP-Y06
KP-Y07
KP-Y08
KP-Y09
KP-Y10
KP-Y11
CONFIG_1
CONFIG_2
IRQ
PWM_0
PWM_1
PWM_2
ACB_SDA
ACB_SCL
XTAL_IN
XTAL_OUT
RESET
DEVICE CONFIGURATION AFTER RESET
After the LM8323 has completed its reset initialization, it will have the following internal configuration:
• PWM Clock: The PWM clock source is the on-chip clock divided by 64. This remains in effect until changed
by a host command.
• Keypad Size: 3 × 3.
• Rotary Encoder Interface: disabled.
• Digital Multiplexers: disabled.
• IRQ: enabled, active low.
• NOINIT Bit : set.
• Debounce Time: 3 scan cycles (about 12 milliseconds).
• Active Time: 500 milliseconds.
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NOTE
When FW6 version devices receive a RESET command the IRQ line is set high and held
high for 60 ms and then pulled low to show the device was successfully reset and is ready
to be used.
CONFIGURATION INPUTS
The states sampled from the CONFIG_1 and CONFIG_2 inputs during reset select the ACCESS.bus address
used by the LM8323, as shown in Table 3. The address occupies the high seven bits of the first byte of a bus
transaction, with the LSB (shown as X below) indicating the direction of transfer.
Table 3. Bus Address Selection
CONFIG_1
CONFIG_2
Bus Address
0
0
1000 010X
0
1
1000 011X
1
0
1000 100X
1
1
1000 101X
When these pins are used as GPIO ports, the design must ensure that they have the desired states during reset.
For example, a 100-kΩ resistor to ground can impose a logic 0 during reset without interfering with normal
operation as a GPIO port.
INITIALIZATION
The LM8323 waits for a WRITE_CFG command from the host. During this time, IRQ is asserted to request
service from the host. Figure 4 describes the behavior of the LM8323 following reset.
Figure 4. LM8323 Initialization Behavior
Figure 5 shows the timing of IRQ relative to a RESET or POR event and the WRITE_CFG command. 100 µs
after a RESET or POR event, IRQ is asserted and any READ_INT command will return an interrupt code with
the NOINIT bit set. 90 µs after a WRITE_CFG command is received, IRQ is deasserted.
10
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Figure 5. IRQ Reset Timing
After sending the WRITE_CFG command, the host must send a series of commands to configure the LM8323,
as shown in Figure 6. (See left hand side.)
This Flow - diagram illustrates also the basic host communication steps which the host must execute upon an
IRQ request received from the LM8323 during operation. Such requests will be made from the LM8323 as a
result of key pressed events, the detection of an error, the termination of a PWM cycle and others.
Host Initialization
Yes
No
Is IRQ low?
Send any command.
READ_PORT_STATE
PWM_WRITE, etc.
Check interrupt code.
READ_INT
Yes
Is NOINIT
bit set?
No
Yes
Is ERROR
bit set?
Initialize configuration.
WRITE_CFG
No
Check error code.
READ_ERROR
Configure clocks.
WRITE_CLOCK
Service error condition.
If the error code reports a
FIFOOVR or KEYOVR error,
then the FIFO buffer must be
unloaded to clear the FIFO.
If this is not done, the LM8323
will not store any new events in
the FIFO. Any data unloaded
from the FIFO after the error
interrupt should be ignored.
Specify keypad size.
SET_KEY_SIZE
Initialize keypad scan timing.
SET_ACTIVE
SET_DEBOUNCE
Configure GPIO pins.
WRITE_PORT_STATE
WRITE_PORT_SEL
Is KEYPAD
bit set?
No
Check interrupt code.
READ_INT
Yes
Are NOINIT,ERROR,
and COMMAND
bits clear?
No
Is ROTATOR
bit set?
No
Is a PWMxEND
bit set?
Yes
Read keypad events.
READ_FIFO
Yes
Read rotation steps.
READ_ROTATOR
Yes
No
Service PWM channel.
Figure 6. Host-Side LM8323 Initialization
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INITIALIZATION EXAMPLE
In
•
•
•
•
•
•
•
•
the following example, the LM8323 is configured as:
Keypad matrix configuration is 8 × 4.
Rotary encoder interface enabled.
GPIO_03 through GPIO_07 are available to use as GPIO pins.
GPIO_03 is an output driven low.
GPIO_4 and GPIO_5 are outputs driven high.
GPIO_06 and GPIO_07 are inputs with weak pulldowns.
GPIO_14 and GPIO_15 are inputs with weak pullups.
The PWM clock source is the internal execution clock divided by 64 (about 32 kHz).
Most of these settings can be verified by executing commands such as READ_CONF, READ_PORT_SEL,
READ_CLOCK, etc.
ALL GPIO pin states can be read using the READ_PORT_STATE command, without regard to whether the pin is
an input or an output.
An open-drain signal can be created by alternating between input mode and driving the output low.
All GPIOs can sink and source 16 mA when configured as an output.
Command
Encoding
Parameter 1
Parameter 2
Description
WRITE_CFG
0x81
0x40
Selects 36-pin package and disables the two digital
multiplexers.
WRITE_CLK
0x93
0x08
SLOWCLKOUT disabled, no external 32.768 kHz clock
required, PWM clock source is internal.
SET_KEY_SIZE
0x90
0x84
Selects a keypad matrix size of 8 × 4.
SET_ACTIVE
0x8B
0x4B
Sets the active time to about 300 milliseconds (75 × 4
milliseconds).
SET_DEBOUNCE
0x8F
0x03
Sets the key debouncing time to about 12 milliseconds (3 × 4
ms). This is actually the default and would not have to be
performed.
WRITE_PORT_SEL
0x85
0x00
0x38
Configure GPIO_03, GPIO_04, and GPIO_05 as outputs.
Configure GPIO_06, GPIO_07, GPIO_14, and GPIO_15 as
inputs.
WRITE_PULL_DOWN
0x84
0x00
0x3F
Set the direction for the pullup/pulldown devices on GPIO_06
and GPIO_07 to pulldown. Set the direction for the
pullup/pulldown devices on GPIO_14 and GPIO_15 to pullup.
WRITE_PORT_STATE
0x86
0xC0
0xF0
Set GPIO_04 and GPIO_05 to drive high. Enable the pullups
on GPIO_06, GPIO_07, GPIO_14, and GPIO_15.
HALT MODE
The fully static architecture of the LM8323 allows stopping the internal RC clock in Halt mode, which reduces
power consumption to the minimum level. Figure 7 shows the current in Halt mode at the maximum VCC (1.98V)
from 25°C to +85°C.
12
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Figure 7. Halt Current vs. Temperature at 1.98V
Halt mode is entered when no key-press event, key-release event, change in the rotary encoder counter value or
ACCESS.bus activity is detected for a certain period of time (by default, 500 ms). The mechanism for entering
Halt mode is always enabled in hardware, but the host can program the period of inactivity which triggers entry
into Halt mode.
NOTE
When FW4 version devices enter the Halt mode there is approximately a 33% chance the
device may miss key events during the period of 3ms before entering Halt mode until 3ms
after entering Halt mode resulting in lost key events. This was corrected in FW6 devices
so that 100% of all key events are captured, even as the device is entering Halt mode.
ACCESS.bus ACTIVITY
When the LM8323 is in Halt mode, any activity on the ACCESS.bus interface will cause the LM8323 to exit from
Halt mode. However, the LM8323 will not be able to acknowledge the first bus cycle immediately following wakeup from Halt mode. It will respond with a negative acknowledgement, and the host should then repeat the cycle.
The LM8323 will be prevented from entering Halt mode if it shares the bus with peripherals that are continuously
active. For lowest power consumption, the LM8323 should only share the bus with peripherals that require little
or no bus activity after system initialization.
KEYPAD INTERFACE
EVENT CODE ASSIGNMENT
After power-on reset and host initialization, the LM8323 starts scanning the keypad. It stays active for a default
time of about 500 ms after the last key is released, after which it enters Halt mode to minimize power
consumption (typically 30 ms) command
sequences for SCL frequencies > 100 kHz.
DEVICE ADDRESS
The device address is controlled by states sampled on the CONFIG_1 and CONFIG_2 pins, as shown in
Table 12. In the first byte of a bus transaction, a 7-bit address plus a direction bit are broadcast by the bus
master to all bus slaves.
Table 12. Device Address Selection
CONFIG_1
CONFIG_2
Device Address
0
0
1000 010X
0
1
1000 011X
1
0
1000 100X
1
1
1000 101X
CONFIG_1 and CONFIG_2 pins should be connected to GND or VCC using pulldown or pullup resistors. The
pins cannot be left unconnected.
HOST WRITE COMMANDS
Some host commands include one or more data bytes written to the LM8323. Figure 18 shows a
SET_KEY_SIZE command, which consists of an address byte, a command byte, and one data byte.
The first byte is composed of a 7-bit slave address in bits 7:1 and a direction bit in bit 0. The state of the direction
bit is 0 on writes from the host to the slave and 1 on reads from the slave to the host.
The second byte sends the command. The SET_KEY_SIZE command is 0x90.
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The third byte sends the data, in this case specifying the number of rows and columns for the keypad.
Figure 18. Host Write Command
HOST READ COMMANDS
Some host commands include one or more data bytes read from the LM8323. Figure 19 shows a
READ_PORT_SEL command which consists of an address byte, a command byte, a second address byte, and
two data bytes.
The first address byte is sent with the direction bit driven low to indicate a write transaction of the command to
the LM8323. The second address byte is sent with the direction bit undriven (pulled high) to indicate a read
transaction of the data from the LM8323.
The Repeated Start condition must be repeated whenever the slave address or the direction bit is changed. In
this case, the direction bit is changed.
The bus master can send any number of Repeated Start conditions without releasing control of the bus. This
technique can be used to implement atomic transactions, in which the bus master sends a command and then
reads a register without allowing any other device to get control of the bus between these events.
The data is sent from the slave to the host in the fourth and fifth bytes. The fifth byte ends with a negative
acknowledgement (NACK) to indicate the end of the data.
Figure 19. Host Read Command
INTERRUPTS
The IRQ output may be asserted on these conditions:
• Any new key-event after the last interrupt was asserted but not yet acknowledged by reading the interrupt
code.
• Any change in the state of the rotary encoder inputs.
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•
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Termination of a PWM script (END command).
Any error condition, which is indicated by the error code.
INTERRUPT CODE
The interrupt code is read and acknowledged with the READ_INT command (0x82). This command clears the
code and deasserts the IRQ output. Table 13 shows the format of the interrupt code.
Table 13. Interrupt Code
7
PWM2END
6
PWM1END
5
PWM0END
4
NOINIT
3
ERROR
Bit
2
0
An END script command was executed by PWM channel 2.
PWM1END
An END script command was executed by PWM channel 1.
PWM0END
An END script command was executed by PWM channel 0.
NOINIT
The LM8323 is waiting for an initialization sequence.
ERROR
An error condition occurred.
KEYPAD
0
KEYPAD
Description
PWM2END
ROTATOR
1
ROTATOR
A state change was detected in the rotary encoder inputs.
A key-press or key-release event occurred.
ERROR CODE
If the LM8323 reports an error, the READ_ERROR command (0x8C) is used to read the error code. This
command clears the error code. Table 14 shows the format of the error code.
Table 14. Error Code
7
0
6
FIFOOVR
5
0
4
0
3
0
Bit
FIFOOVER
2
KEYOVR
1
CMDUNK
0
BADPAR
Description
Event occurred while the FIFO was full.
KEYOVR
More than two keys were pressed simultaneously.
CMDUNK
Not a valid command.
BADPAR
Bad command parameter.
WAKE-UP FROM HALT MODE
Any bus transaction initiated by the host may encounter the LM8323 device in Halt mode or busy with processing
data, such as controlling the FIFO buffer or executing interrupt service routines.
LM8323 shows the case in which the host sends a command while the LM8323 is in Halt mode (Internal
execution clock is stopped). Any activity on the ACCESS.bus wakes up the LM8323, but it cannot acknowledge
the first bus cycle immediately after wake-up.
The host drives a Start condition followed by seven address bits and a R/W bit. The host then releases SDA for
one clock period, so that it can be driven by the LM8323.
If the LM8323 does not drive SDA low during the high phase of the clock period immediately after the R/W bit,
the bus cycle terminates without being acknowledged (shown as NACK in Figure 20). The host then aborts the
transaction by sending a Stop condition. After aborting the bus cycle, the host may then retry the bus cycle. On
the second attempt, the LM8323 will be able to acknowledge the slave address, because it will be in Active
mode.
Alternatively, the I2C specification allows sending a START byte (00000001), which will not be acknowledged by
any device. This byte can be used to wake up the LM8323 from Halt mode.
The LM8323 may also stall the bus transaction by pulling the SCL low, which is a valid behavior defined by the
I2C specification.
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Figure 20. LM8323 Responds with NACK, Host Retries Command
HOST COMMANDS
Function
Cmd
Dir
READ_ID
0x80
R
WRITE_CFG
0x81
READ_INT
Data Bytes
nnnn nnnn
Description
pppp pppp
Read the manufacturer code (nnnn nnnn) and the device
revision number (pppp pppp).
W
nnnn nnnn
Write the hardware configuration register.
0x82
R
nnnn nnnn
Read the interrupt code, deassert the IRQ output, and clear
the code. (If the NOINIT bit is set, it remains set and IRQ
remains asserted until a WRITE_CFG command is received.)
RESET
0x83
W
nnnn nnnn
Reset the LM8323. Error if nnnn nnnn is not 0xAA.
WRITE_PULL_DOWN
0x84
W
nnnn nnnn
Select pullup (0) or pulldown (1) direction for the
corresponding general-purpose I/O (GPIO) port pins.
WRITE_PORT_SEL
0x85
W
WRITE_PORT_STATE
0x86
W
READ_PORT_SEL
0x87
R
READ_PORT_STATE
0x88
R
READ_FIFO
0x89
R
Up to 15 event
codes
Read an event from the FIFO.
Maximum of 14 event codes stored in the FIFO.
RPT_READ_FIFO
0x8A
R
Up to 15 event
codes
Repeats a FIFO read without advancing the FIFO pointer, for
example to retry a read after an error.
SET_ACTIVE
0x8B
W
nnnn nnnn
Set the time during which the LM8323 stays active before
entering Halt mode. The active time must be greater than the
debounce time. The default time is 500 milliseconds. The
valid range is 1255. Active time = n × 4 milliseconds.
pppp pppp
nnnn nnnn
pppp pppp
nnnn nnnn
pppp pppp
nnnn nnnn
pppp pppp
nnnn nnnn
pppp pppp
Select input (0) or output (1) for the corresponding generalpurpose I/O (GPIO) port pins.
For pins configured as inputs, 0 selects high-impedance
mode and 1 enables a weak pullup. For pins configured as
outputs, each bit specifies the logic level driven on the pin.
Read the direction of the corresponding GPIO port pins.
Read the state on the corresponding GPIO port pins.
READ_ERROR
0x8C
R
nnnn nnnn
Read and clear the error code.
READ_ROTATOR
0x8E
R
nnnn nnnn
Read accumulated rotation steps since previous read.
SET_DEBOUNCE
0x8F
W
nnnn nnnn
Set the time for rescanning the keypad after detecting a keypress or key-release event to verify the event. The default
time is 12 milliseconds. The valid range is 1255. Debounce
time = n × 4 milliseconds and must not exceed active time.
SET_KEY_SIZE
0x90
W
nnnn pppp
Set keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins
READ_KEY_SIZE
0x91
R
nnnn pppp
Read keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins
READ_CFG
0x92
R
nnnn nnnn
Read the hardware configuration register.
WRITE_CLOCK
0x93
W
nnnn nnnn
Write the clock configuration register.
READ_CLOCK
0x94
R
nnnn nnnn
Read the clock configuration register.
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Cmd
Dir
Data Bytes
Description
Write a command to the PWM script command file.
nn = PWM channel number (01, 10, or 11)
PWM_WRITE
0x95
W
aaaa aann
aaaaaa = address in script command file (0-59)
pppp pppp
pppp pppp = high byte of script command
qqqq qqqq
qqqq qqqq = low byte of script command
PWM_START
0x96
W
aaaa aann
Start script on channel nn (01, 10, or 11) at address aaaaaa.
PWM_STOP
0x97
W
0000 00nn
Stop script on channel nn (01, 10, or 11).
SPACER
NOTE
The data bytes which follow the command can be reads (toward the host) or writes
(toward the LM8323). In the case of the READ_FIFO and RPT_READ_FIFO commands,
the number of data bytes is variable, with the last transaction indicated by returning a
negative acknowledgement (NACK).
READ_ID COMMAND
The READ_ID command consists of a command byte (0x80) from the host and two data bytes from the LM8323.
The first data byte returns the manufacturer code, and the second byte returns the device revision level.
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
6
5
4
3
2
MANUFACTURER
1
0
7
6
5
4
3
2
REVISION
1
0
WRITE_CFG COMMAND
The WRITE_CFG command consists of a command byte (0x81) and a data byte from the host. The data byte is
loaded into the hardware configuration register. The default state of this register is 0x80.
7
1
6
0
5
0
Bit
IRQPST
ROTEN
MUX2EN
MUX2SEL
MUX1EN
MUX1SEL
32
4
0
3
0
2
0
1
0
0
1
7
IRQPST
6
ROTEN
5
0
Value
4
0
3
MUX2EN
2
MUX2SEL
1
MUX1EN
0
MUX1SEL
Description
0
IRQ is an open-drain output.
1
IRQ is a push-pull output.
0
Rotary encoder interface disabled.
1
Rotary encoder interface enabled. This selection enables the ROT_IN_x inputs which are alternate
functions of certain KP-Yx pins.
0
MUX2_OUT output disabled.
1
MUX2_OUT output enabled. This overrides any other function available on this pin.
0
If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output.
1
If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output.
0
MUX1_OUT output disabled.
1
MUX1_OUT output enabled. This overrides any other function available on this pin.
0
If the MUX1 EN bit is 1, the MUX1_IN1 input drives the MUX1_OUT output.
1
If the MUX1 EN bit is 1, the MUX1_IN2 input drives the MUX1_OUT output.
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READ_INT COMMAND
The READ_INT command consists of a command byte (0x82) from the host and a data byte from the LM8323.
The data byte is the interrupt code. Reading the interrupt code acknowledges the interrupt (which deasserts IRQ)
and clears the interrupt code. An exception to this behavior occurs if the NOINIT bit is set, in which case IRQ will
not be deasserted and the interrupt code will not be cleared until a WRITE_CFG command is received.
7
1
6
0
5
0
4
0
3
0
2
0
1
1
Bit
0
0
7
PWM2END
6
PWM1END
5
PWM0END
Value
PWM2END
PWM1END
PWM0END
NOINIT
ERROR
ROTATOR
KEYPAD
4
NOINIT
3
ERROR
2
0
1
ROTATOR
0
KEYPAD
Description
0
No interrupt from PWM channel 2.
1
An END script command was executed by PWM channel 2.
0
No interrupt from PWM channel 1.
1
An END script command was executed by PWM channel 1.
0
No interrupt from PWM channel 0.
1
An END script command was executed by PWM channel 0.
0
Normal operation.
1
LM8323 is waiting for the initialization sequence.
0
No error condition is indicated.
1
An error condition occurred.
0
No state change in the rotary encoder inputs is indicated.
1
A state change was detected in the rotary encoder inputs.
0
No key-press or key-release event is indicated.
1
A key-press or key-release event occurred.
RESET COMMAND
The RESET command consists of a command byte (0x83) and one data byte from the host. The command
causes a reset, identical to an external reset. The data byte must be 0xAA, otherwise no reset will occur and an
error condition will be signalled.
NOTE
When FW6 version devices receive a RESET command the IRQ line is set high and held
high for 60 ms, then pulled low to show the device was successfully reset and is ready to
be used.
7
1
6
0
5
0
4
0
3
0
2
0
1
1
0
1
7
1
6
0
5
1
4
0
3
1
2
0
1
1
0
0
WRITE_PULL_DOWN COMMAND
0
Bit
GPIO_xx
Value
0
7
6
5
4
3
2
1
0
GPIO_00
0
1
GPIO_01
1
2
GPIO_02
0
3
GPIO_03
0
4
GPIO_04
0
5
GPIO_05
0
6
GPIO_06
1
7
GPIO_07
0
GPIO_08
1
GPIO_09
2
GPIO_10
3
GPIO_11
4
GPIO_12
5
GPIO_13
6
GPIO_14
7
GPIO_15
The WRITE_PORT_SEL command consists of a command byte (0x84) and two data bytes from the host. The
data bytes configure the pullup/pulldown device (if enabled) for the corresponding general-purpose I/O ports as
pullups (0) or pulldowns (1). The first data byte controls ports GPIO_15 through GPIO_08, and the second byte
controls ports GPIO_07 through GPIO_00.
Description
0
GPIO port pin pullup/pulldown device is a pullup.
1
GPIO port pin pullup/pulldown device is a pulldown.
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WRITE_PORT_SEL COMMAND
6
5
4
3
2
1
1
0
0
0
0
1
0
1
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
0
Bit
Value
GPIO_xx
0
7
6
5
4
3
2
1
0
GPIO_00
7
GPIO_01
0
GPIO_02
1
GPIO_03
2
GPIO_04
3
GPIO_05
4
GPIO_06
5
GPIO_07
6
GPIO_08
7
GPIO_15
The WRITE_PORT_SEL command consists of a command byte (0x85) and two data bytes from the host. The
data bytes configure the corresponding general-purpose I/O ports as inputs (0) or outputs (1). The first data byte
controls ports GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07 through GPIO_00.
Description
0
GPIO port pin is an input.
1
GPIO port pin is an output.
The GPIO_09 port pin can only be configured as an input with weak pullup/pulldown device.
WRITE_PORT_STATE COMMAND
6
5
4
3
2
1
1
0
0
0
0
1
1
0
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_09
Bit
0
7
6
5
4
3
2
1
0
GPIO_00
7
GPIO_01
0
GPIO_02
1
GPIO_03
2
GPIO_04
3
GPIO_05
4
GPIO_06
5
GPIO_07
6
GPIO_08
7
GPIO_15
The WRITE_PORT_STATE command consists of a command byte (0x86) and two data bytes from the host. For
general-purpose I/O ports configured as inputs, the data bytes select whether the inputs are high-impedance (0)
or have a weak pullup (1). For ports configured as outputs, the data bytes control the state driven on the output.
The first data byte controls ports GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07
through GPIO_00.
Value
Description
0
If the GPIO port pin is an input, pullup device is disabled. If the GPIO port pin is an output, it is
driven low.
1
If the GPIO port pin is an input, pullup device is enabled. If the GPIO port pin is an output, it is
driven high.
GPIO_xx
READ_PORT_SEL COMMAND
6
5
4
3
2
1
1
0
0
0
0
1
1
1
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_09
Bit
GPIO_xx
34
Value
0
7
6
5
4
3
2
1
0
GPIO_00
7
GPIO_01
0
GPIO_02
1
GPIO_03
2
GPIO_04
3
GPIO_05
4
GPIO_06
5
GPIO_07
6
GPIO_08
7
GPIO_15
The READ_PORT_SEL command consists of a command byte (0x87) from the host and two data bytes from the
LM8323. The data bytes indicate the direction configured for the corresponding ports, either input (0) or output
(1). The first data byte controls ports GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07
through GPIO_00.
Description
0
GPIO port pin is an input.
1
GPIO port pin is an output.
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READ_PORT_STATE COMMAND
6
5
4
3
2
1
1
0
0
0
1
0
0
0
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_09
Bit
Value
0
7
6
5
4
3
2
1
0
GPIO_00
7
GPIO_01
0
GPIO_02
1
GPIO_03
2
GPIO_04
3
GPIO_05
4
GPIO_06
5
GPIO_07
6
GPIO_08
7
GPIO_15
The READ_PORT_STATE command consists of a command byte (0x88) from the host and two data bytes from
the LM8323. The data bytes indicate the states on the corresponding ports. The first data byte controls ports
GPIO_15 through GPIO_08, and the second byte controls ports GPIO_07 through GPIO_00.
Description
0
If the GPIO port pin is an input, pullup is disabled. If the GPIO port pin is an output, it is
driven low.
1
If the GPIO port pin is an input, pullup is enabled. If the GPIO port pin is an output, it is
driven high.
GPIO_xx
READ_FIFO COMMAND
The READ_FIFO command consists of a command byte (0x89) sent from the host and a variable number of data
bytes received from the LM8323. The LM8323 will provide data until the FIFO is empty. The last data byte is
indicated by its value (0x00) and a negative acknowledgement (NACK) on the ACCESS.bus interface. The data
bytes correspond to key-press and key-release events, as described in Table 4.
7
1
6
0
5
0
4
0
3
1
Field
2
0
1
0
0
1
7
6
5 4 3
2
FIFODATA
Value
FIFODATA
1
0
7
6
5
4
3
0x00
2
1
0
Description
0xxxxxxx
Key-release event.
1xxxxxxx
Key-press event.
RPT_READ_FIFO COMMAND
The RPT_READ_FIFO command consists of a command byte (0x8A) and from the host and a variable number
of data bytes from the LM8323. This command provides the same data as a previous READ_FIFO command,
but without advancing the FIFO pointer. It may be used to recover from an error encountered during a
READ_FIFO command.
7
1
6
0
5
0
Field
FIFODATA
4
0
3
1
2
0
1
1
0
0
7
6
5
4
3
2
FIFODATA
Value
1
0
7
6
5
4
3
0x00
2
1
0
Description
0xxxxxxx
Key-release event.
1xxxxxxx
Key-press event.
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SET_ACTIVE COMMAND
The SET_ACTIVE command consists of a command byte (0x8B) and a data byte from the host. This command
sets the time that the LM8323 stays active without detecting a key-press, key-release or rotary encoder event
before entering Halt mode. The default active time is 500 milliseconds. The host can program ACTIVETIME from
4–1020 milliseconds with a granularity of 4 milliseconds.
7
1
6
0
5
0
4
0
3
1
Field
2
0
1
1
0
1
7
6
5
4
Value
2
1
0
Description
0
ACTIVETIME
3
ACTIVETIME
Halt mode is disabled.
1–255
Active time = n × 4 milliseconds.
READ_ERROR COMMAND
The READ_ERROR command consists of a command byte (0x8C) from the host and a data byte from the
LM8323. After reading an interrupt code that indicates an error condition, this command is used to read an error
code that indicates the cause of the error condition.
7
1
6
0
5
0
4
0
3
1
Bit
2
1
1
0
0
0
7
0
6
FIFOOVR
5
0
4
0
Value
FIFOOVR
KEYOVR
CMDUNK
BADPAR
3
0
2
KEYOVR
1
CMDUNK
0
BADPAR
Description
0
No FIFO overrun occurred.
1
Event occurred while the FIFO was full.
0
No keypad overrun occurred.
1
More than two keys were pressed simultaneously.
0
No invalid command was encountered.
1
Not a valid command.
0
No bad parameter was encountered.
1
Bad command parameter.
READ_ROTATOR COMMAND
The READ_ROTATOR command consists of a command byte (0x8E) from the host and a data byte from the
LM8323. The data byte is a signed two's complement value which indicates the accumulated number of rotation
steps of an external rotary encoder since the last time the READ_ROTATOR command was executed.
7
1
6
0
5
0
4
0
3
1
2
1
1
1
0
0
7
Field
Value
ROTATION
−128 to +127
6
5
4
3
ROTATION
2
1
0
Description
Clockwise rotation is indicated by a positive value. Counterclockwise
movement is indicated by a negative value.
SET_DEBOUNCE COMMAND
The SET_DEBOUNCE command consists of a command byte (0x8F) and a data byte from the host. This
command sets the time that the LM8323 waits before rescanning the keypad to confirm a key-press or keyrelease event. The default debounce time is 12 milliseconds. The host can program DEBOUNCETIME from
4–1020 milliseconds with a granularity of 4 milliseconds. The DEBOUNCETIME must not exceed the active time
set with the SET_ACTIVE command.
7
1
36
6
0
5
0
4
0
3
1
2
1
1
1
0
1
7
6
5
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3
DEBOUNCETIME
2
1
0
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Field
Value
DEBOUNCETIME
1–255
Description
Active time = n × 4 milliseconds.
SET_KEY_SIZE COMMAND
The SET_KEY_SIZE command consists of a command byte (0x90) and a data byte from the host. This
command specifies the keypad size in terms of the number of KP-Xx inputs and KP-Yx outputs which are used.
Any unused KP-Xx and KP-Yx pins may be used for general-purpose I/O. The minimum value for either field is 3,
which corresponds to a keypad configuration that supports 3 × 3 + 3 SF keys (total of 12 keys).
The maximum number of KP-Xx inputs is 8, and the maximum number of KP-Yx outputs is 12. If the digital
multiplexer MUX2 or the rotary encoder interface is used, the maximum number of KP-Yx outputs is 9. If the
SLOWCLKOUT pin is used, the maximum number is 8.
7
1
6
0
5
0
4
1
Field
3
0
2
0
1
0
0
0
7
6
5
4
3
2
KP-X
Value
1
0
KP-Y
Description
KP-X
3–8
Number of KP-Xx inputs.
KP-Y
3–12
Number of KP-Yx outputs.
READ_KEY_SIZE COMMAND
The READ_KEY_SIZE command consists of a command byte (0x91) from the host and a data byte from the
LM8323. The host can issue the command at any time to read the configuration of the keypad.
7
1
6
0
5
0
4
1
3
0
Field
2
0
1
0
0
1
7
6
5
4
3
2
KP-X
Value
1
0
KP-Y
Description
KP-X
3–8
Number of KP-Xx inputs.
KP-Y
3–12
Number of KP-Yx outputs.
READ_CFG COMMAND
The READ_CFG command consists of a command byte (0x92) from the host and a data byte from the LM8323.
The data byte returns the settings in the hardware configuration register. The default state of this register is 0x80.
7
1
6
0
5
0
Bit
ROTEN
MUX2EN
MUX2SEL
MUX1EN
MUX1SEL
4
1
3
0
2
0
1
1
0
0
7
0
6
ROTEN
5
0
Value
4
0
3
MUX2EN
2
MUX2SEL
1
MUX1EN
0
MUX1SEL
Description
0
Rotary encoder interface disabled.
1
Rotary encoder interface enabled. This selection enables the ROT_IN_x inputs, which are
alternate functions of certain KP-Yx pins.
0
MUX2_OUT output disabled.
1
MUX2_OUT output enabled. This overrides any other function available on this pin.
0
If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output.
1
If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output.
0
MUX1_OUT output disabled.
1
MUX1_OUT output enabled. This overrides any other function available on this pin.
0
If the MUX1 EN bit is 1, the MUX1_IN1 input drives the MUX1_OUT output.
1
If the MUX1 EN bit is 1, the MUX1_IN2 input drives the MUX1_OUT output.
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LM8323
SNLS273A – JULY 2010 – REVISED MARCH 2013
www.ti.com
WRITE_CLOCK COMMAND
The WRITE_CLOCK command consists of a command byte (0x93) and a data byte from the host. This
command sets the clock configuration, as described in Table 1.
7
1
6
0
5
0
4
1
3
0
2
0
1
1
0
1
7
6
5
4
3
2
CONFIGURATION
1
0
READ_CLOCK COMMAND
The READ_CLOCK command consists of a command byte (0x94) from the host and a data byte from the
LM8323. This command reads bits 7:2 of the clock configuration, as described in Table 1.
7
1
6
0
5
0
4
1
3
0
2
1
1
0
0
0
7
6
5
4
CONFIGURATION
3
2
1
1
0
0
PWM_WRITE COMMAND
The PWM_WRITE command consists of a command byte (0x95) and three data bytes from the host. The
command writes a 16-bit script command into a specified address in the script command file of the specified
PWM channel.
7
1
6
0
5
0
4
1
3
0
2
1
1
0
0
1
7
6
5 4 3
ADDRESS
Bit
Value
ADDRESS
0–59
CH
2
1 0
CH
7
6
5
4 3
2
1
0
7
6
5
COMMAND
4
3
2
1
0
Description
Location in the PWM script command file.
01
PWM channel 0.
10
PWM channel 1.
11
PWM channel 2.
PWM_START COMMAND
The PWM_START command consists of a command byte (0x96) and a data byte from the host. This command
starts execution of the script command file at the specified address for the specified channel.
7
1
6
0
5
0
4
1
3
0
Bit
Value
ADDRESS
0–59
CH
2
1
1
1
0
0
7
6
5
4
ADDRESS
3
2
1
0
CH
Description
Start address in the PWM script command file.
01
PWM channel 0.
10
PWM channel 1.
11
PWM channel 2.
PWM_STOP COMMAND
The PWM_STOP command consists of a command byte (0x97) and a data byte from the host. This command
stops execution of the script command file for the specified channel.
7
1
6
0
Bit
CH
38
5
0
4
1
3
0
2
1
1
1
0
1
7
0
6
0
Value
5
0
4
0
3
0
2
0
1
0
CH
Description
01
PWM channel 0.
10
PWM channel 1.
11
PWM channel 2.
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LM8323
LM8323
www.ti.com
SNLS273A – JULY 2010 – REVISED MARCH 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Supply Voltage (VCC)
2V
Voltage at Any Pin
-0.3V to VCC +0.3V
Maximum Input Current Without Latchup
ESD Protection Level
±100 mA
(Human Body Model)
2 kV
(Machine Model)
200V
(Charge Device Model)
750V
Total Current into VCC Pin (Source)
100 mA
Total Current out of GND Pin (Sink)
100 mA
−65°C to +140°C
Storage Temperature Range
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions,
see the DC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS tables.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
DC ELECTRICAL CHARACTERISTICS
(Temperature: -40°C ≤ TA ≤ +85°C, unless otherwise specified)
Data sheet specification limits are specified by design, test, or statistical analysis.
Symbol
Parameter
VCC
Operating Voltage
IDD
Supply Current
Conditions
Min
(1)
VCC = 1.9V, TC = 0.5 µs
IHALT
Standby Mode Current
(3)
VIL
Logical 0 Input Voltage
(4)
Logical 1 Input Voltage
(4)
(1)
(2)
(3)
(4)
(5)
(6)
V
1.9
3.0
mA
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